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if_iwnreg.h (198429) if_iwnreg.h (201209)
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 198429 2009-10-23 22:04:18Z rpaulo $ */
2/* $OpenBSD: if_iwnreg.h,v 1.26 2009/05/29 08:25:45 damien Exp $ */
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 201209 2009-12-29 19:47:34Z rpaulo $ */
2/* $OpenBSD: if_iwnreg.h,v 1.34 2009/11/08 11:54:48 damien Exp $ */
3
4/*-
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
3
4/*-
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21#define EDCA_NUM_AC 4
22
23#define IWN_TX_RING_COUNT 256
24#define IWN_TX_RING_LOMARK 192
25#define IWN_TX_RING_HIMARK 224
26#define IWN_RX_RING_COUNT_LOG 6
27#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
28
29#define IWN4965_NTXQUEUES 16
30#define IWN5000_NTXQUEUES 20
31
32#define IWN4965_NDMACHNLS 7
33#define IWN5000_NDMACHNLS 8
34
35#define IWN_SRVC_DMACHNL 9
36
21#define IWN_TX_RING_COUNT 256
22#define IWN_TX_RING_LOMARK 192
23#define IWN_TX_RING_HIMARK 224
24#define IWN_RX_RING_COUNT_LOG 6
25#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
26
27#define IWN4965_NTXQUEUES 16
28#define IWN5000_NTXQUEUES 20
29
30#define IWN4965_NDMACHNLS 7
31#define IWN5000_NDMACHNLS 8
32
33#define IWN_SRVC_DMACHNL 9
34
35#define IWN_ICT_SIZE 4096
36#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))
37
37/* Maximum number of DMA segments for TX. */
38#define IWN_MAX_SCATTER 20
39
40/* RX buffers must be large enough to hold a full 4K A-MPDU. */
41#define IWN_RBUF_SIZE (4 * 1024)
42
43#if defined(__LP64__)
44/* HW supports 36-bit DMA addresses. */

--- 7 unchanged lines hidden (view full) ---

52/* Base Address Register. */
53#define IWN_PCI_BAR0 PCI_MAPREG_START
54
55/*
56 * Control and status registers.
57 */
58#define IWN_HW_IF_CONFIG 0x000
59#define IWN_INT_COALESCING 0x004
38/* Maximum number of DMA segments for TX. */
39#define IWN_MAX_SCATTER 20
40
41/* RX buffers must be large enough to hold a full 4K A-MPDU. */
42#define IWN_RBUF_SIZE (4 * 1024)
43
44#if defined(__LP64__)
45/* HW supports 36-bit DMA addresses. */

--- 7 unchanged lines hidden (view full) ---

53/* Base Address Register. */
54#define IWN_PCI_BAR0 PCI_MAPREG_START
55
56/*
57 * Control and status registers.
58 */
59#define IWN_HW_IF_CONFIG 0x000
60#define IWN_INT_COALESCING 0x004
61#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
60#define IWN_INT 0x008
62#define IWN_INT 0x008
61#define IWN_MASK 0x00c
63#define IWN_INT_MASK 0x00c
62#define IWN_FH_INT 0x010
63#define IWN_RESET 0x020
64#define IWN_GP_CNTRL 0x024
65#define IWN_HW_REV 0x028
66#define IWN_EEPROM 0x02c
67#define IWN_EEPROM_GP 0x030
68#define IWN_OTP_GP 0x034
69#define IWN_GIO 0x03c
64#define IWN_FH_INT 0x010
65#define IWN_RESET 0x020
66#define IWN_GP_CNTRL 0x024
67#define IWN_HW_REV 0x028
68#define IWN_EEPROM 0x02c
69#define IWN_EEPROM_GP 0x030
70#define IWN_OTP_GP 0x034
71#define IWN_GIO 0x03c
72#define IWN_GP_DRIVER 0x050
70#define IWN_UCODE_GP1_CLR 0x05c
71#define IWN_LED 0x094
73#define IWN_UCODE_GP1_CLR 0x05c
74#define IWN_LED 0x094
75#define IWN_DRAM_INT_TBL 0x0a0
72#define IWN_GIO_CHICKEN 0x100
73#define IWN_ANA_PLL 0x20c
76#define IWN_GIO_CHICKEN 0x100
77#define IWN_ANA_PLL 0x20c
78#define IWN_HW_REV_WA 0x22c
74#define IWN_DBG_HPET_MEM 0x240
79#define IWN_DBG_HPET_MEM 0x240
80#define IWN_DBG_LINK_PWR_MGMT 0x250
75#define IWN_MEM_RADDR 0x40c
76#define IWN_MEM_WADDR 0x410
77#define IWN_MEM_WDATA 0x418
78#define IWN_MEM_RDATA 0x41c
81#define IWN_MEM_RADDR 0x40c
82#define IWN_MEM_WADDR 0x410
83#define IWN_MEM_WDATA 0x418
84#define IWN_MEM_RDATA 0x41c
79#define IWN_PRPH_WADDR 0x444
80#define IWN_PRPH_RADDR 0x448
81#define IWN_PRPH_WDATA 0x44c
82#define IWN_PRPH_RDATA 0x450
85#define IWN_PRPH_WADDR 0x444
86#define IWN_PRPH_RADDR 0x448
87#define IWN_PRPH_WDATA 0x44c
88#define IWN_PRPH_RDATA 0x450
83#define IWN_HBUS_TARG_WRPTR 0x460
84
85/*
86 * Flow-Handler registers.
87 */
88#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
89#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
90#define IWN_FH_KW_ADDR 0x197c

--- 38 unchanged lines hidden (view full) ---

129#define IWN5000_SCHED_CTX_OFF 0x600
130#define IWN5000_SCHED_CTX_LEN 520
131#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
132#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
133
134/*
135 * NIC internal memory offsets.
136 */
89#define IWN_HBUS_TARG_WRPTR 0x460
90
91/*
92 * Flow-Handler registers.
93 */
94#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
95#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
96#define IWN_FH_KW_ADDR 0x197c

--- 38 unchanged lines hidden (view full) ---

135#define IWN5000_SCHED_CTX_OFF 0x600
136#define IWN5000_SCHED_CTX_LEN 520
137#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
138#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
139
140/*
141 * NIC internal memory offsets.
142 */
137#define IWN_CLOCK_CTL 0x3000
138#define IWN_APMG_CLK_CTRL 0x3004
143#define IWN_APMG_CLK_CTRL 0x3000
144#define IWN_APMG_CLK_EN 0x3004
139#define IWN_APMG_CLK_DIS 0x3008
140#define IWN_APMG_PS 0x300c
145#define IWN_APMG_CLK_DIS 0x3008
146#define IWN_APMG_PS 0x300c
147#define IWN_APMG_DIGITAL_SVR 0x3058
148#define IWN_APMG_ANALOG_SVR 0x306c
141#define IWN_APMG_PCI_STT 0x3010
142#define IWN_BSM_WR_CTRL 0x3400
143#define IWN_BSM_WR_MEM_SRC 0x3404
144#define IWN_BSM_WR_MEM_DST 0x3408
145#define IWN_BSM_WR_DWCOUNT 0x340c
146#define IWN_BSM_DRAM_TEXT_ADDR 0x3490
147#define IWN_BSM_DRAM_TEXT_SIZE 0x3494
148#define IWN_BSM_DRAM_DATA_ADDR 0x3498
149#define IWN_BSM_DRAM_DATA_SIZE 0x349c
150#define IWN_BSM_SRAM_BASE 0x3800
151
149#define IWN_APMG_PCI_STT 0x3010
150#define IWN_BSM_WR_CTRL 0x3400
151#define IWN_BSM_WR_MEM_SRC 0x3404
152#define IWN_BSM_WR_MEM_DST 0x3408
153#define IWN_BSM_WR_DWCOUNT 0x340c
154#define IWN_BSM_DRAM_TEXT_ADDR 0x3490
155#define IWN_BSM_DRAM_TEXT_SIZE 0x3494
156#define IWN_BSM_DRAM_DATA_ADDR 0x3498
157#define IWN_BSM_DRAM_DATA_SIZE 0x349c
158#define IWN_BSM_SRAM_BASE 0x3800
159
152/* Possible values for IWN_APMG_CLK_DIS. */
153#define IWN_APMG_CLK_DMA_RQT (1 << 9)
154
155/* Possible flags for register IWN_HW_IF_CONFIG. */
156#define IWN_HW_IF_CONFIG_4965_R (1 << 4)
157#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
158#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
159#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
160#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22)
161#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
162#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
163#define IWN_HW_IF_CONFIG_PREPARE (1 << 27)
164
160/* Possible flags for register IWN_HW_IF_CONFIG. */
161#define IWN_HW_IF_CONFIG_4965_R (1 << 4)
162#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
163#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
164#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
165#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22)
166#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
167#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
168#define IWN_HW_IF_CONFIG_PREPARE (1 << 27)
169
170/* Possible values for register IWN_INT_PERIODIC. */
171#define IWN_INT_PERIODIC_DIS 0x00
172#define IWN_INT_PERIODIC_ENA 0xff
173
165/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
166#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
167
168/* Possible values for IWN_BSM_WR_MEM_DST. */
169#define IWN_FW_TEXT_BASE 0x00000000
170#define IWN_FW_DATA_BASE 0x00800000
171
172/* Possible flags for register IWN_RESET. */
173#define IWN_RESET_NEVO (1 << 0)
174#define IWN_RESET_SW (1 << 7)
175#define IWN_RESET_MASTER_DISABLED (1 << 8)
176#define IWN_RESET_STOP_MASTER (1 << 9)
174/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
175#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
176
177/* Possible values for IWN_BSM_WR_MEM_DST. */
178#define IWN_FW_TEXT_BASE 0x00000000
179#define IWN_FW_DATA_BASE 0x00800000
180
181/* Possible flags for register IWN_RESET. */
182#define IWN_RESET_NEVO (1 << 0)
183#define IWN_RESET_SW (1 << 7)
184#define IWN_RESET_MASTER_DISABLED (1 << 8)
185#define IWN_RESET_STOP_MASTER (1 << 9)
186#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31)
177
178/* Possible flags for register IWN_GP_CNTRL. */
179#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
180#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
181#define IWN_GP_CNTRL_INIT_DONE (1 << 2)
182#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
183#define IWN_GP_CNTRL_SLEEP (1 << 4)
184#define IWN_GP_CNTRL_RFKILL (1 << 27)

--- 12 unchanged lines hidden (view full) ---

197
198/* Possible flags for register IWN_GIO_CHICKEN. */
199#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
200#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
201
202/* Possible flags for register IWN_GIO. */
203#define IWN_GIO_L0S_ENA (1 << 1)
204
187
188/* Possible flags for register IWN_GP_CNTRL. */
189#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
190#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
191#define IWN_GP_CNTRL_INIT_DONE (1 << 2)
192#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
193#define IWN_GP_CNTRL_SLEEP (1 << 4)
194#define IWN_GP_CNTRL_RFKILL (1 << 27)

--- 12 unchanged lines hidden (view full) ---

207
208/* Possible flags for register IWN_GIO_CHICKEN. */
209#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
210#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
211
212/* Possible flags for register IWN_GIO. */
213#define IWN_GIO_L0S_ENA (1 << 1)
214
215/* Possible flags for register IWN_GP_DRIVER. */
216#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0)
217#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0)
218#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0)
219
205/* Possible flags for register IWN_UCODE_GP1_CLR. */
206#define IWN_UCODE_GP1_RFKILL (1 << 1)
207#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
208#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
209
210/* Possible flags/values for register IWN_LED. */
211#define IWN_LED_BSM_CTRL (1 << 5)
212#define IWN_LED_OFF 0x00000038
213#define IWN_LED_ON 0x00000078
214
220/* Possible flags for register IWN_UCODE_GP1_CLR. */
221#define IWN_UCODE_GP1_RFKILL (1 << 1)
222#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
223#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
224
225/* Possible flags/values for register IWN_LED. */
226#define IWN_LED_BSM_CTRL (1 << 5)
227#define IWN_LED_OFF 0x00000038
228#define IWN_LED_ON 0x00000078
229
230/* Possible flags for register IWN_DRAM_INT_TBL. */
231#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27)
232#define IWN_DRAM_INT_TBL_ENABLE (1 << 31)
233
215/* Possible values for register IWN_ANA_PLL. */
216#define IWN_ANA_PLL_INIT 0x00880300
217
218/* Possible flags for register IWN_FH_RX_STATUS. */
219#define IWN_FH_RX_STATUS_IDLE (1 << 24)
220
221/* Possible flags for register IWN_BSM_WR_CTRL. */
222#define IWN_BSM_WR_CTRL_START_EN (1 << 30)
223#define IWN_BSM_WR_CTRL_START (1 << 31)
224
225/* Possible flags for register IWN_INT. */
226#define IWN_INT_ALIVE (1 << 0)
227#define IWN_INT_WAKEUP (1 << 1)
228#define IWN_INT_SW_RX (1 << 3)
229#define IWN_INT_CT_REACHED (1 << 6)
230#define IWN_INT_RF_TOGGLED (1 << 7)
231#define IWN_INT_SW_ERR (1 << 25)
234/* Possible values for register IWN_ANA_PLL. */
235#define IWN_ANA_PLL_INIT 0x00880300
236
237/* Possible flags for register IWN_FH_RX_STATUS. */
238#define IWN_FH_RX_STATUS_IDLE (1 << 24)
239
240/* Possible flags for register IWN_BSM_WR_CTRL. */
241#define IWN_BSM_WR_CTRL_START_EN (1 << 30)
242#define IWN_BSM_WR_CTRL_START (1 << 31)
243
244/* Possible flags for register IWN_INT. */
245#define IWN_INT_ALIVE (1 << 0)
246#define IWN_INT_WAKEUP (1 << 1)
247#define IWN_INT_SW_RX (1 << 3)
248#define IWN_INT_CT_REACHED (1 << 6)
249#define IWN_INT_RF_TOGGLED (1 << 7)
250#define IWN_INT_SW_ERR (1 << 25)
251#define IWN_INT_SCHED (1 << 26)
232#define IWN_INT_FH_TX (1 << 27)
252#define IWN_INT_FH_TX (1 << 27)
253#define IWN_INT_RX_PERIODIC (1 << 28)
233#define IWN_INT_HW_ERR (1 << 29)
234#define IWN_INT_FH_RX (1 << 31)
235
236/* Shortcut. */
254#define IWN_INT_HW_ERR (1 << 29)
255#define IWN_INT_FH_RX (1 << 31)
256
257/* Shortcut. */
237#define IWN_INT_MASK \
258#define IWN_INT_MASK_DEF \
238 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
239 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
240 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
241
242/* Possible flags for register IWN_FH_INT. */
243#define IWN_FH_INT_TX_CHNL(x) (1 << (x))
244#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
245#define IWN_FH_INT_HI_PRIOR (1 << 30)

--- 50 unchanged lines hidden (view full) ---

296#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
297#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
298#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
299#define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
300#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
301#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
302#define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
303
259 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
260 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
261 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
262
263/* Possible flags for register IWN_FH_INT. */
264#define IWN_FH_INT_TX_CHNL(x) (1 << (x))
265#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
266#define IWN_FH_INT_HI_PRIOR (1 << 30)

--- 50 unchanged lines hidden (view full) ---

317#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
318#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
319#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
320#define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
321#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
322#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
323#define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
324
304/* Possible flags for register IWN_APMG_CLK_CTRL. */
325/* Possible flags for registers IWN_APMG_CLK_*. */
305#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
306#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
307
308/* Possible flags for register IWN_APMG_PS. */
309#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
310#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
311#define IWN_APMG_PS_PWR_SRC_VMAIN 0
312#define IWN_APMG_PS_PWR_SRC_VAUX 2
313#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
314#define IWN_APMG_PS_RESET_REQ (1 << 26)
315
326#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
327#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
328
329/* Possible flags for register IWN_APMG_PS. */
330#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
331#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
332#define IWN_APMG_PS_PWR_SRC_VMAIN 0
333#define IWN_APMG_PS_PWR_SRC_VAUX 2
334#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
335#define IWN_APMG_PS_RESET_REQ (1 << 26)
336
337/* Possible flags for register IWN_APMG_DIGITAL_SVR. */
338#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
339#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \
340 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
341#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \
342 IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
343
316/* Possible flags for IWN_APMG_PCI_STT. */
317#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
318
319/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
320#define IWN_FW_UPDATED (1 << 31)
321
322#define IWN_SCHED_WINSZ 64
323#define IWN_SCHED_LIMIT 64

--- 33 unchanged lines hidden (view full) ---

357#define IWN_STOP_SCAN 132
358#define IWN_RX_STATISTICS 156
359#define IWN_BEACON_STATISTICS 157
360#define IWN_STATE_CHANGED 161
361#define IWN_BEACON_MISSED 162
362#define IWN_RX_PHY 192
363#define IWN_MPDU_RX_DONE 193
364#define IWN_RX_DONE 195
344/* Possible flags for IWN_APMG_PCI_STT. */
345#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
346
347/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
348#define IWN_FW_UPDATED (1 << 31)
349
350#define IWN_SCHED_WINSZ 64
351#define IWN_SCHED_LIMIT 64

--- 33 unchanged lines hidden (view full) ---

385#define IWN_STOP_SCAN 132
386#define IWN_RX_STATISTICS 156
387#define IWN_BEACON_STATISTICS 157
388#define IWN_STATE_CHANGED 161
389#define IWN_BEACON_MISSED 162
390#define IWN_RX_PHY 192
391#define IWN_MPDU_RX_DONE 193
392#define IWN_RX_DONE 195
393#define IWN_RX_COMPRESSED_BA 197
365
366 uint8_t flags;
367 uint8_t idx;
368 uint8_t qid;
369} __packed;
370
371/* Possible RX status flags. */
372#define IWN_RX_NO_CRC_ERR (1 << 0)

--- 4 unchanged lines hidden (view full) ---

377#define IWN_RX_CIPHER_MASK (7 << 8)
378#define IWN_RX_CIPHER_CCMP (2 << 8)
379#define IWN_RX_MPDU_DEC (1 << 11)
380#define IWN_RX_DECRYPT_MASK (3 << 11)
381#define IWN_RX_DECRYPT_OK (3 << 11)
382
383struct iwn_tx_cmd {
384 uint8_t code;
394
395 uint8_t flags;
396 uint8_t idx;
397 uint8_t qid;
398} __packed;
399
400/* Possible RX status flags. */
401#define IWN_RX_NO_CRC_ERR (1 << 0)

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406#define IWN_RX_CIPHER_MASK (7 << 8)
407#define IWN_RX_CIPHER_CCMP (2 << 8)
408#define IWN_RX_MPDU_DEC (1 << 11)
409#define IWN_RX_DECRYPT_MASK (3 << 11)
410#define IWN_RX_DECRYPT_OK (3 << 11)
411
412struct iwn_tx_cmd {
413 uint8_t code;
385#define IWN_CMD_CONFIGURE 16
386#define IWN_CMD_ASSOCIATE 17
414#define IWN_CMD_RXON 16
415#define IWN_CMD_RXON_ASSOC 17
387#define IWN_CMD_EDCA_PARAMS 19
388#define IWN_CMD_TIMING 20
389#define IWN_CMD_ADD_NODE 24
390#define IWN_CMD_TX_DATA 28
391#define IWN_CMD_LINK_QUALITY 78
392#define IWN_CMD_SET_LED 72
393#define IWN5000_CMD_WIMAX_COEX 90
394#define IWN5000_CMD_CALIB_CONFIG 101
395#define IWN_CMD_SET_POWER_MODE 119
396#define IWN_CMD_SCAN 128
416#define IWN_CMD_EDCA_PARAMS 19
417#define IWN_CMD_TIMING 20
418#define IWN_CMD_ADD_NODE 24
419#define IWN_CMD_TX_DATA 28
420#define IWN_CMD_LINK_QUALITY 78
421#define IWN_CMD_SET_LED 72
422#define IWN5000_CMD_WIMAX_COEX 90
423#define IWN5000_CMD_CALIB_CONFIG 101
424#define IWN_CMD_SET_POWER_MODE 119
425#define IWN_CMD_SCAN 128
426#define IWN_CMD_TXPOWER_DBM 149
397#define IWN_CMD_TXPOWER 151
427#define IWN_CMD_TXPOWER 151
398#define IWN_CMD_TXPOWER_DBM 152
428#define IWN5000_CMD_TX_ANT_CONFIG 152
399#define IWN_CMD_BT_COEX 155
400#define IWN_CMD_GET_STATISTICS 156
401#define IWN_CMD_SET_CRITICAL_TEMP 164
402#define IWN_CMD_SET_SENSITIVITY 168
403#define IWN_CMD_PHY_CALIB 176
404
405 uint8_t flags;
406 uint8_t idx;
407 uint8_t qid;
408 uint8_t data[136];
409} __packed;
410
411/* Antenna flags, used in various commands. */
412#define IWN_ANT_A (1 << 0)
413#define IWN_ANT_B (1 << 1)
414#define IWN_ANT_C (1 << 2)
429#define IWN_CMD_BT_COEX 155
430#define IWN_CMD_GET_STATISTICS 156
431#define IWN_CMD_SET_CRITICAL_TEMP 164
432#define IWN_CMD_SET_SENSITIVITY 168
433#define IWN_CMD_PHY_CALIB 176
434
435 uint8_t flags;
436 uint8_t idx;
437 uint8_t qid;
438 uint8_t data[136];
439} __packed;
440
441/* Antenna flags, used in various commands. */
442#define IWN_ANT_A (1 << 0)
443#define IWN_ANT_B (1 << 1)
444#define IWN_ANT_C (1 << 2)
415/* Shortcut. */
445/* Shortcuts. */
446#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B)
447#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C)
416#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
417
448#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
449
418/* Structure for command IWN_CMD_CONFIGURE. */
450/* Structure for command IWN_CMD_RXON. */
419struct iwn_rxon {
420 uint8_t myaddr[IEEE80211_ADDR_LEN];
421 uint16_t reserved1;
422 uint8_t bssid[IEEE80211_ADDR_LEN];
423 uint16_t reserved2;
424 uint8_t wlap[IEEE80211_ADDR_LEN];
425 uint16_t reserved3;
426 uint8_t mode;
427#define IWN_MODE_HOSTAP 1
428#define IWN_MODE_STA 3
429#define IWN_MODE_IBSS 4
430#define IWN_MODE_MONITOR 6
431
432 uint8_t air;
433 uint16_t rxchain;
451struct iwn_rxon {
452 uint8_t myaddr[IEEE80211_ADDR_LEN];
453 uint16_t reserved1;
454 uint8_t bssid[IEEE80211_ADDR_LEN];
455 uint16_t reserved2;
456 uint8_t wlap[IEEE80211_ADDR_LEN];
457 uint16_t reserved3;
458 uint8_t mode;
459#define IWN_MODE_HOSTAP 1
460#define IWN_MODE_STA 3
461#define IWN_MODE_IBSS 4
462#define IWN_MODE_MONITOR 6
463
464 uint8_t air;
465 uint16_t rxchain;
434#define IWN_RXCHAIN_FORCE (1 << 0)
435#define IWN_RXCHAIN_VALID(x) ((x) << 1)
436#define IWN_RXCHAIN_SEL(x) ((x) << 4)
437#define IWN_RXCHAIN_MIMO(x) ((x) << 7)
466#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0)
467#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1)
468#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4)
469#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7)
438#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
439#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
440#define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
441
442 uint8_t ofdm_mask;
443 uint8_t cck_mask;
444 uint16_t associd;
445 uint32_t flags;
470#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
471#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
472#define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
473
474 uint8_t ofdm_mask;
475 uint8_t cck_mask;
476 uint16_t associd;
477 uint32_t flags;
446#define IWN_RXON_24GHZ 0x00000001 /* band */
447#define IWN_RXON_CCK 0x00000002 /* modulation */
448#define IWN_RXON_AUTO 0x00000004 /* 2.4-only auto-detect */
449#define IWN_RXON_HTPROT 0x00000008 /* xmit with HT protection */
450#define IWN_RXON_SHSLOT 0x00000010 /* short slot time */
451#define IWN_RXON_SHPREAMBLE 0x00000020 /* short premable */
452#define IWN_RXON_NODIVERSITY 0x00000080 /* disable antenna diversity */
453#define IWN_RXON_ANTENNA_A 0x00000100
454#define IWN_RXON_ANTENNA_B 0x00000200
455#define IWN_RXON_RADAR 0x00001000 /* enable radar detect */
456#define IWN_RXON_NARROW 0x00002000 /* MKK narrow band select */
457#define IWN_RXON_TSF 0x00008000
458#define IWN_RXON_HT 0x06400000
459#define IWN_RXON_HT20 0x02000000
460#define IWN_RXON_HT40U 0x04000000
461#define IWN_RXON_HT40D 0x04400000
462#define IWN_RXON_CTS_TO_SELF 0x40000000
478#define IWN_RXON_24GHZ (1 << 0)
479#define IWN_RXON_CCK (1 << 1)
480#define IWN_RXON_AUTO (1 << 2)
481#define IWN_RXON_SHSLOT (1 << 4)
482#define IWN_RXON_SHPREAMBLE (1 << 5)
483#define IWN_RXON_NODIVERSITY (1 << 7)
484#define IWN_RXON_ANTENNA_A (1 << 8)
485#define IWN_RXON_ANTENNA_B (1 << 9)
486#define IWN_RXON_TSF (1 << 15)
487#define IWN_RXON_CTS_TO_SELF (1 << 30)
463
464 uint32_t filter;
465#define IWN_FILTER_PROMISC (1 << 0)
466#define IWN_FILTER_CTL (1 << 1)
467#define IWN_FILTER_MULTICAST (1 << 2)
468#define IWN_FILTER_NODECRYPT (1 << 3)
469#define IWN_FILTER_BSS (1 << 5)
470#define IWN_FILTER_BEACON (1 << 6)
471
472 uint8_t chan;
473 uint8_t reserved4;
474 uint8_t ht_single_mask;
475 uint8_t ht_dual_mask;
488
489 uint32_t filter;
490#define IWN_FILTER_PROMISC (1 << 0)
491#define IWN_FILTER_CTL (1 << 1)
492#define IWN_FILTER_MULTICAST (1 << 2)
493#define IWN_FILTER_NODECRYPT (1 << 3)
494#define IWN_FILTER_BSS (1 << 5)
495#define IWN_FILTER_BEACON (1 << 6)
496
497 uint8_t chan;
498 uint8_t reserved4;
499 uint8_t ht_single_mask;
500 uint8_t ht_dual_mask;
476 /* The following fields are for 5000 Series only. */
501 /* The following fields are for >=5000 Series only. */
477 uint8_t ht_triple_mask;
478 uint8_t reserved5;
479 uint16_t acquisition;
480 uint16_t reserved6;
481} __packed;
482
483#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
484#define IWN5000_RXONSZ (sizeof (struct iwn_rxon))

--- 14 unchanged lines hidden (view full) ---

499#define IWN_EDCA_TXOP (1 << 4)
500
501 struct {
502 uint16_t cwmin;
503 uint16_t cwmax;
504 uint8_t aifsn;
505 uint8_t reserved;
506 uint16_t txoplimit;
502 uint8_t ht_triple_mask;
503 uint8_t reserved5;
504 uint16_t acquisition;
505 uint16_t reserved6;
506} __packed;
507
508#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
509#define IWN5000_RXONSZ (sizeof (struct iwn_rxon))

--- 14 unchanged lines hidden (view full) ---

524#define IWN_EDCA_TXOP (1 << 4)
525
526 struct {
527 uint16_t cwmin;
528 uint16_t cwmax;
529 uint8_t aifsn;
530 uint8_t reserved;
531 uint16_t txoplimit;
507 } __packed ac[EDCA_NUM_AC];
532 } __packed ac[WME_NUM_AC];
508} __packed;
509
510/* Structure for command IWN_CMD_TIMING. */
511struct iwn_cmd_timing {
512 uint64_t tstamp;
513 uint16_t bintval;
514 uint16_t atim;
515 uint32_t binitval;

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590 uint16_t disable_tid;
591 uint16_t reserved6;
592 uint8_t addba_tid;
593 uint8_t delba_tid;
594 uint16_t addba_ssn;
595 uint32_t reserved7;
596} __packed;
597
533} __packed;
534
535/* Structure for command IWN_CMD_TIMING. */
536struct iwn_cmd_timing {
537 uint64_t tstamp;
538 uint16_t bintval;
539 uint16_t atim;
540 uint32_t binitval;

--- 74 unchanged lines hidden (view full) ---

615 uint16_t disable_tid;
616 uint16_t reserved6;
617 uint8_t addba_tid;
618 uint8_t delba_tid;
619 uint16_t addba_ssn;
620 uint32_t reserved7;
621} __packed;
622
598#define IWN_RFLAG_HT (1 << 0) /* use HT modulation */
599#define IWN_RFLAG_CCK (1 << 1) /* use CCK modulation */
600#define IWN_RFLAG_HT40 (1 << 3) /* use dual-stream */
601#define IWN_RFLAG_SGI (1 << 5) /* use short GI */
602#define IWN_RFLAG_ANT_A (1 << 6) /* start on antenna port A */
603#define IWN_RFLAG_ANT_B (1 << 7) /* start on antenna port B */
623#define IWN_RFLAG_CCK (1 << 1)
604#define IWN_RFLAG_ANT(x) ((x) << 6)
605
606/* Structure for command IWN_CMD_TX_DATA. */
607struct iwn_cmd_data {
608 uint16_t len;
609 uint16_t lnext;
610 uint32_t flags;
611#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */

--- 43 unchanged lines hidden (view full) ---

655struct iwn_cmd_link_quality {
656 uint8_t id;
657 uint8_t reserved1;
658 uint16_t ctl;
659 uint8_t flags;
660 uint8_t mimo;
661 uint8_t antmsk_1stream;
662 uint8_t antmsk_2stream;
624#define IWN_RFLAG_ANT(x) ((x) << 6)
625
626/* Structure for command IWN_CMD_TX_DATA. */
627struct iwn_cmd_data {
628 uint16_t len;
629 uint16_t lnext;
630 uint32_t flags;
631#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */

--- 43 unchanged lines hidden (view full) ---

675struct iwn_cmd_link_quality {
676 uint8_t id;
677 uint8_t reserved1;
678 uint16_t ctl;
679 uint8_t flags;
680 uint8_t mimo;
681 uint8_t antmsk_1stream;
682 uint8_t antmsk_2stream;
663 uint8_t ridx[EDCA_NUM_AC];
683 uint8_t ridx[WME_NUM_AC];
664 uint16_t ampdu_limit;
665 uint8_t ampdu_threshold;
666 uint8_t ampdu_max;
667 uint32_t reserved2;
668 struct {
669 uint8_t plcp;
670 uint8_t rflags;
671 uint16_t xrflags;

--- 11 unchanged lines hidden (view full) ---

683 uint8_t off;
684 uint8_t on;
685 uint8_t reserved;
686} __packed;
687
688/* Structure for command IWN5000_CMD_WIMAX_COEX. */
689struct iwn5000_wimax_coex {
690 uint32_t flags;
684 uint16_t ampdu_limit;
685 uint8_t ampdu_threshold;
686 uint8_t ampdu_max;
687 uint32_t reserved2;
688 struct {
689 uint8_t plcp;
690 uint8_t rflags;
691 uint16_t xrflags;

--- 11 unchanged lines hidden (view full) ---

703 uint8_t off;
704 uint8_t on;
705 uint8_t reserved;
706} __packed;
707
708/* Structure for command IWN5000_CMD_WIMAX_COEX. */
709struct iwn5000_wimax_coex {
710 uint32_t flags;
691 struct {
711#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
712#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2)
713#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3)
714#define IWN_WIMAX_COEX_ENABLE (1 << 7)
715
716 struct iwn5000_wimax_event {
692 uint8_t request;
693 uint8_t window;
694 uint8_t reserved;
695 uint8_t flags;
696 } __packed events[16];
697} __packed;
698
699/* Structures for command IWN5000_CMD_CALIB_CONFIG. */

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799
800 int8_t srv_limit; /* in half-dBm */
801 uint8_t reserved;
802} __packed;
803
804/* Structure for command IWN_CMD_BLUETOOTH. */
805struct iwn_bluetooth {
806 uint8_t flags;
717 uint8_t request;
718 uint8_t window;
719 uint8_t reserved;
720 uint8_t flags;
721 } __packed events[16];
722} __packed;
723
724/* Structures for command IWN5000_CMD_CALIB_CONFIG. */

--- 99 unchanged lines hidden (view full) ---

824
825 int8_t srv_limit; /* in half-dBm */
826 uint8_t reserved;
827} __packed;
828
829/* Structure for command IWN_CMD_BLUETOOTH. */
830struct iwn_bluetooth {
831 uint8_t flags;
807 uint8_t lead;
808 uint8_t kill;
832#define IWN_BT_COEX_DISABLE 0
833#define IWN_BT_COEX_MODE_2WIRE 1
834#define IWN_BT_COEX_MODE_3WIRE 2
835#define IWN_BT_COEX_MODE_4WIRE 3
836
837 uint8_t lead_time;
838#define IWN_BT_LEAD_TIME_DEF 30
839
840 uint8_t max_kill;
841#define IWN_BT_MAX_KILL_DEF 5
842
809 uint8_t reserved;
843 uint8_t reserved;
810 uint32_t ack;
811 uint32_t cts;
844 uint32_t kill_ack;
845 uint32_t kill_cts;
812} __packed;
813
814/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
815struct iwn_critical_temp {
816 uint32_t reserved;
817 uint32_t tempM;
818 uint32_t tempR;
819/* degK <-> degC conversion macros. */

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845struct iwn_phy_calib {
846 uint8_t code;
847#define IWN4965_PHY_CALIB_DIFF_GAIN 7
848#define IWN5000_PHY_CALIB_DC 8
849#define IWN5000_PHY_CALIB_LO 9
850#define IWN5000_PHY_CALIB_TX_IQ 11
851#define IWN5000_PHY_CALIB_CRYSTAL 15
852#define IWN5000_PHY_CALIB_BASE_BAND 16
846} __packed;
847
848/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
849struct iwn_critical_temp {
850 uint32_t reserved;
851 uint32_t tempM;
852 uint32_t tempR;
853/* degK <-> degC conversion macros. */

--- 25 unchanged lines hidden (view full) ---

879struct iwn_phy_calib {
880 uint8_t code;
881#define IWN4965_PHY_CALIB_DIFF_GAIN 7
882#define IWN5000_PHY_CALIB_DC 8
883#define IWN5000_PHY_CALIB_LO 9
884#define IWN5000_PHY_CALIB_TX_IQ 11
885#define IWN5000_PHY_CALIB_CRYSTAL 15
886#define IWN5000_PHY_CALIB_BASE_BAND 16
853#define IWN5000_PHY_CALIB_TX_IQ_PERD 17
887#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17
854#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
855#define IWN5000_PHY_CALIB_NOISE_GAIN 19
856
857 uint8_t group;
858 uint8_t ngroups;
859 uint8_t isvalid;
860} __packed;
861

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941#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
942#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
943#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
944#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
945#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
946
947struct iwn4965_tx_stat {
948 uint8_t nframes;
888#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
889#define IWN5000_PHY_CALIB_NOISE_GAIN 19
890
891 uint8_t group;
892 uint8_t ngroups;
893 uint8_t isvalid;
894} __packed;
895

--- 79 unchanged lines hidden (view full) ---

975#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
976#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
977#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
978#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
979#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
980
981struct iwn4965_tx_stat {
982 uint8_t nframes;
949 uint8_t killcnt;
950 uint8_t rtscnt;
951 uint8_t retrycnt;
983 uint8_t btkillcnt;
984 uint8_t rtsfailcnt;
985 uint8_t ackfailcnt;
952 uint8_t rate;
953 uint8_t rflags;
954 uint16_t xrflags;
955 uint16_t duration;
956 uint16_t reserved;
957 uint32_t power[2];
958 uint32_t status;
959} __packed;
960
961struct iwn5000_tx_stat {
962 uint8_t nframes;
986 uint8_t rate;
987 uint8_t rflags;
988 uint16_t xrflags;
989 uint16_t duration;
990 uint16_t reserved;
991 uint32_t power[2];
992 uint32_t status;
993} __packed;
994
995struct iwn5000_tx_stat {
996 uint8_t nframes;
963 uint8_t killcnt;
964 uint8_t rtscnt;
965 uint8_t retrycnt;
997 uint8_t btkillcnt;
998 uint8_t rtsfailcnt;
999 uint8_t ackfailcnt;
966 uint8_t rate;
967 uint8_t rflags;
968 uint16_t xrflags;
969 uint16_t duration;
970 uint16_t reserved;
971 uint32_t power[2];
972 uint32_t info;
973 uint16_t seq;
974 uint16_t len;
1000 uint8_t rate;
1001 uint8_t rflags;
1002 uint16_t xrflags;
1003 uint16_t duration;
1004 uint16_t reserved;
1005 uint32_t power[2];
1006 uint32_t info;
1007 uint16_t seq;
1008 uint16_t len;
975 uint32_t tlc;
1009 uint8_t tlc;
1010 uint8_t ratid;
1011 uint8_t fc[2];
976 uint16_t status;
977 uint16_t sequence;
978} __packed;
979
980/* Structure for IWN_BEACON_MISSED notification. */
981struct iwn_beacon_missed {
982 uint32_t consecutive;
983 uint32_t total;

--- 38 unchanged lines hidden (view full) ---

1022 uint8_t rflags;
1023 uint16_t xrflags;
1024 uint16_t len;
1025 uint16_t reserve3;
1026} __packed;
1027
1028#define IWN_RSSI_TO_DBM 44
1029
1012 uint16_t status;
1013 uint16_t sequence;
1014} __packed;
1015
1016/* Structure for IWN_BEACON_MISSED notification. */
1017struct iwn_beacon_missed {
1018 uint32_t consecutive;
1019 uint32_t total;

--- 38 unchanged lines hidden (view full) ---

1058 uint8_t rflags;
1059 uint16_t xrflags;
1060 uint16_t len;
1061 uint16_t reserve3;
1062} __packed;
1063
1064#define IWN_RSSI_TO_DBM 44
1065
1066/* Structure for IWN_RX_COMPRESSED_BA notification. */
1067struct iwn_compressed_ba {
1068 uint8_t macaddr[IEEE80211_ADDR_LEN];
1069 uint16_t reserved;
1070 uint8_t id;
1071 uint8_t tid;
1072 uint16_t seq;
1073 uint64_t bitmap;
1074 uint16_t qid;
1075 uint16_t ssn;
1076} __packed;
1077
1030/* Structure for IWN_START_SCAN notification. */
1031struct iwn_start_scan {
1032 uint64_t tstamp;
1033 uint32_t tbeacon;
1034 uint8_t chan;
1035 uint8_t band;
1036 uint16_t reserved;
1037 uint32_t status;

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1073#define IWN_MEASUREMENT_CONCURRENT 1
1074#define IWN_MEASUREMENT_CSA_CONFLICT 2
1075#define IWN_MEASUREMENT_TGH_CONFLICT 3
1076#define IWN_MEASUREMENT_STOPPED 6
1077#define IWN_MEASUREMENT_TIMEOUT 7
1078#define IWN_MEASUREMENT_FAILED 8
1079} __packed;
1080
1078/* Structure for IWN_START_SCAN notification. */
1079struct iwn_start_scan {
1080 uint64_t tstamp;
1081 uint32_t tbeacon;
1082 uint8_t chan;
1083 uint8_t band;
1084 uint16_t reserved;
1085 uint32_t status;

--- 35 unchanged lines hidden (view full) ---

1121#define IWN_MEASUREMENT_CONCURRENT 1
1122#define IWN_MEASUREMENT_CSA_CONFLICT 2
1123#define IWN_MEASUREMENT_TGH_CONFLICT 3
1124#define IWN_MEASUREMENT_STOPPED 6
1125#define IWN_MEASUREMENT_TIMEOUT 7
1126#define IWN_MEASUREMENT_FAILED 8
1127} __packed;
1128
1081/* Structure for IWN_{RX,BEACON}_STATISTICS notification. */
1129/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
1082struct iwn_rx_phy_stats {
1083 uint32_t ina;
1084 uint32_t fina;
1085 uint32_t bad_plcp;
1086 uint32_t bad_crc32;
1087 uint32_t overrun;
1088 uint32_t eoverrun;
1089 uint32_t good_crc32;

--- 113 unchanged lines hidden (view full) ---

1203 uint32_t branch_link[2];
1204 uint32_t interrupt_link[2];
1205 uint32_t error_data[2];
1206 uint32_t src_line;
1207 uint32_t tsf;
1208 uint32_t time[2];
1209} __packed;
1210
1130struct iwn_rx_phy_stats {
1131 uint32_t ina;
1132 uint32_t fina;
1133 uint32_t bad_plcp;
1134 uint32_t bad_crc32;
1135 uint32_t overrun;
1136 uint32_t eoverrun;
1137 uint32_t good_crc32;

--- 113 unchanged lines hidden (view full) ---

1251 uint32_t branch_link[2];
1252 uint32_t interrupt_link[2];
1253 uint32_t error_data[2];
1254 uint32_t src_line;
1255 uint32_t tsf;
1256 uint32_t time[2];
1257} __packed;
1258
1211/* Firmware image file header. */
1212struct iwn_firmware_hdr {
1213 uint32_t version;
1214 uint32_t main_textsz;
1215 uint32_t main_datasz;
1216 uint32_t init_textsz;
1217 uint32_t init_datasz;
1218 uint32_t boot_textsz;
1219} __packed;
1220
1221#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1222#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1223#define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1224#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1225#define IWN_FW_BOOT_TEXT_MAXSZ 1024
1226#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1227#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1228
1259#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1260#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1261#define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1262#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1263#define IWN_FW_BOOT_TEXT_MAXSZ 1024
1264#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1265#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1266
1267#define IWN_FW_API(x) (((x) >> 8) & 0xff)
1268
1229/*
1230 * Offsets into EEPROM.
1231 */
1232#define IWN_EEPROM_MAC 0x015
1233#define IWN_EEPROM_RFCFG 0x048
1234#define IWN4965_EEPROM_DOMAIN 0x060
1235#define IWN4965_EEPROM_BAND1 0x063
1236#define IWN5000_EEPROM_REG 0x066

--- 11 unchanged lines hidden (view full) ---

1248#define IWN5000_EEPROM_DOMAIN 0x001
1249#define IWN5000_EEPROM_BAND1 0x004
1250#define IWN5000_EEPROM_BAND2 0x013
1251#define IWN5000_EEPROM_BAND3 0x021
1252#define IWN5000_EEPROM_BAND4 0x02e
1253#define IWN5000_EEPROM_BAND5 0x03a
1254#define IWN5000_EEPROM_BAND6 0x041
1255#define IWN5000_EEPROM_BAND7 0x049
1269/*
1270 * Offsets into EEPROM.
1271 */
1272#define IWN_EEPROM_MAC 0x015
1273#define IWN_EEPROM_RFCFG 0x048
1274#define IWN4965_EEPROM_DOMAIN 0x060
1275#define IWN4965_EEPROM_BAND1 0x063
1276#define IWN5000_EEPROM_REG 0x066

--- 11 unchanged lines hidden (view full) ---

1288#define IWN5000_EEPROM_DOMAIN 0x001
1289#define IWN5000_EEPROM_BAND1 0x004
1290#define IWN5000_EEPROM_BAND2 0x013
1291#define IWN5000_EEPROM_BAND3 0x021
1292#define IWN5000_EEPROM_BAND4 0x02e
1293#define IWN5000_EEPROM_BAND5 0x03a
1294#define IWN5000_EEPROM_BAND6 0x041
1295#define IWN5000_EEPROM_BAND7 0x049
1296#define IWN6000_EEPROM_ENHINFO 0x054
1256#define IWN5000_EEPROM_CRYSTAL 0x128
1257#define IWN5000_EEPROM_TEMP 0x12a
1258#define IWN5000_EEPROM_VOLT 0x12b
1259
1260/* Possible flags for IWN_EEPROM_RFCFG. */
1261#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1262#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1263#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1264#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1265#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1266
1267struct iwn_eeprom_chan {
1268 uint8_t flags;
1269#define IWN_EEPROM_CHAN_VALID (1 << 0)
1270#define IWN_EEPROM_CHAN_IBSS (1 << 1)
1271#define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1272#define IWN_EEPROM_CHAN_RADAR (1 << 4)
1297#define IWN5000_EEPROM_CRYSTAL 0x128
1298#define IWN5000_EEPROM_TEMP 0x12a
1299#define IWN5000_EEPROM_VOLT 0x12b
1300
1301/* Possible flags for IWN_EEPROM_RFCFG. */
1302#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1303#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1304#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1305#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1306#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1307
1308struct iwn_eeprom_chan {
1309 uint8_t flags;
1310#define IWN_EEPROM_CHAN_VALID (1 << 0)
1311#define IWN_EEPROM_CHAN_IBSS (1 << 1)
1312#define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1313#define IWN_EEPROM_CHAN_RADAR (1 << 4)
1273#define IWN_EEPROM_CHAN_WIDE (1 << 5) /* HT40 */
1274#define IWN_EEPROM_CHAN_NARROW (1 << 6) /* HT20 */
1275
1276 int8_t maxpwr;
1277} __packed;
1278
1314
1315 int8_t maxpwr;
1316} __packed;
1317
1318struct iwn_eeprom_enhinfo {
1319 uint16_t chan;
1320 int8_t chain[3]; /* max power in half-dBm */
1321 uint8_t reserved;
1322 int8_t mimo2; /* max power in half-dBm */
1323 int8_t mimo3; /* max power in half-dBm */
1324} __packed;
1325
1279#define IWN_NSAMPLES 3
1280struct iwn4965_eeprom_chan_samples {
1281 uint8_t num;
1282 struct {
1283 uint8_t temp;
1284 uint8_t gain;
1285 uint8_t power;
1286 int8_t pa_det;

--- 44 unchanged lines hidden (view full) ---

1331 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1332 { 6, { 145, 149, 153, 157, 161, 165 } },
1333 /* 40MHz channels (primary channels), 2GHz band. */
1334 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1335 /* 40MHz channels (primary channels), 5GHz band. */
1336 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1337};
1338
1326#define IWN_NSAMPLES 3
1327struct iwn4965_eeprom_chan_samples {
1328 uint8_t num;
1329 struct {
1330 uint8_t temp;
1331 uint8_t gain;
1332 uint8_t power;
1333 int8_t pa_det;

--- 44 unchanged lines hidden (view full) ---

1378 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1379 { 6, { 145, 149, 153, 157, 161, 165 } },
1380 /* 40MHz channels (primary channels), 2GHz band. */
1381 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1382 /* 40MHz channels (primary channels), 5GHz band. */
1383 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1384};
1385
1339#define IWN_RIDX_MCS 0x08 /* or'd to indicate MCS */
1386#define IWN1000_OTP_NBLOCKS 3
1387#define IWN6000_OTP_NBLOCKS 4
1388#define IWN6050_OTP_NBLOCKS 7
1340
1341/* HW rate indices. */
1342#define IWN_RIDX_CCK1 0
1343#define IWN_RIDX_CCK11 3
1344#define IWN_RIDX_OFDM6 4
1345#define IWN_RIDX_OFDM54 11
1346
1347static const struct iwn_rate {

--- 136 unchanged lines hidden (view full) ---

1484 uint32_t energy_ofdm;
1485};
1486
1487/*
1488 * RX sensitivity limits (values obtained from the reference driver.)
1489 */
1490static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
1491 105, 140,
1389
1390/* HW rate indices. */
1391#define IWN_RIDX_CCK1 0
1392#define IWN_RIDX_CCK11 3
1393#define IWN_RIDX_OFDM6 4
1394#define IWN_RIDX_OFDM54 11
1395
1396static const struct iwn_rate {

--- 136 unchanged lines hidden (view full) ---

1533 uint32_t energy_ofdm;
1534};
1535
1536/*
1537 * RX sensitivity limits (values obtained from the reference driver.)
1538 */
1539static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
1540 105, 140,
1492 170, 210,
1541 220, 270,
1493 85, 120,
1494 170, 210,
1495 125, 200,
1496 200, 400,
1497 97,
1498 100,
1499 100
1500};

--- 5 unchanged lines hidden (view full) ---

1506 170, 210,
1507 125, 200,
1508 170, 400,
1509 95,
1510 95,
1511 95
1512};
1513
1542 85, 120,
1543 170, 210,
1544 125, 200,
1545 200, 400,
1546 97,
1547 100,
1548 100
1549};

--- 5 unchanged lines hidden (view full) ---

1555 170, 210,
1556 125, 200,
1557 170, 400,
1558 95,
1559 95,
1560 95
1561};
1562
1563static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
1564 105, 105, /* min = max for performance bug in DSP. */
1565 220, 220, /* min = max for performance bug in DSP. */
1566 90, 120,
1567 170, 210,
1568 125, 200,
1569 170, 400,
1570 95,
1571 95,
1572 95
1573};
1574
1575static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
1576 105, 145,
1577 192, 232,
1578 80, 145,
1579 128, 232,
1580 125, 175,
1581 160, 310,
1582 97,
1583 97,
1584 100
1585};
1586
1514/* Map TID to TX scheduler's FIFO. */
1515static const uint8_t iwn_tid2fifo[] = {
1516 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1517};
1518
1587/* Map TID to TX scheduler's FIFO. */
1588static const uint8_t iwn_tid2fifo[] = {
1589 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1590};
1591
1592/* WiFi/WiMAX coexist event priority table for 6050. */
1593static const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
1594 { 0x04, 0x03, 0x00, 0x00 },
1595 { 0x04, 0x03, 0x00, 0x03 },
1596 { 0x04, 0x03, 0x00, 0x03 },
1597 { 0x04, 0x03, 0x00, 0x03 },
1598 { 0x04, 0x03, 0x00, 0x00 },
1599 { 0x04, 0x03, 0x00, 0x07 },
1600 { 0x04, 0x03, 0x00, 0x00 },
1601 { 0x04, 0x03, 0x00, 0x03 },
1602 { 0x04, 0x03, 0x00, 0x03 },
1603 { 0x04, 0x03, 0x00, 0x00 },
1604 { 0x06, 0x03, 0x00, 0x07 },
1605 { 0x04, 0x03, 0x00, 0x00 },
1606 { 0x06, 0x06, 0x00, 0x03 },
1607 { 0x04, 0x03, 0x00, 0x07 },
1608 { 0x04, 0x03, 0x00, 0x00 },
1609 { 0x04, 0x03, 0x00, 0x00 }
1610};
1611
1519/* Firmware errors. */
1520static const char * const iwn_fw_errmsg[] = {
1521 "OK",
1522 "FAIL",
1523 "BAD_PARAM",
1524 "BAD_CHECKSUM",
1525 "NMI_INTERRUPT_WDG",
1526 "SYSASSERT",

--- 26 unchanged lines hidden (view full) ---

1553#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
1554
1555#define IWN_READ(sc, reg) \
1556 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
1557
1558#define IWN_WRITE(sc, reg, val) \
1559 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1560
1612/* Firmware errors. */
1613static const char * const iwn_fw_errmsg[] = {
1614 "OK",
1615 "FAIL",
1616 "BAD_PARAM",
1617 "BAD_CHECKSUM",
1618 "NMI_INTERRUPT_WDG",
1619 "SYSASSERT",

--- 26 unchanged lines hidden (view full) ---

1646#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
1647
1648#define IWN_READ(sc, reg) \
1649 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
1650
1651#define IWN_WRITE(sc, reg, val) \
1652 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1653
1654#define IWN_WRITE_1(sc, reg, val) \
1655 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1656
1561#define IWN_SETBITS(sc, reg, mask) \
1562 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
1563
1564#define IWN_CLRBITS(sc, reg, mask) \
1565 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
1657#define IWN_SETBITS(sc, reg, mask) \
1658 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
1659
1660#define IWN_CLRBITS(sc, reg, mask) \
1661 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
1662
1663#define IWN_BARRIER_WRITE(sc) \
1664 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1665 BUS_SPACE_BARRIER_WRITE)
1666
1667#define IWN_BARRIER_READ_WRITE(sc) \
1668 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1669 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)