3
4/******************************************************************************
5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * USA
26 *
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
29 *
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *
34 * BSD LICENSE
35 *
36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
66#ifndef __IF_IWM_REG_H__
67#define __IF_IWM_REG_H__
68
69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
71
72/*
73 * BEGIN iwl-csr.h
74 */
75
76/*
77 * CSR (control and status registers)
78 *
79 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * whenever platform supplies power to device, even when device is in
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
83 *
84 * Use iwl_write32() and iwl_read32() family to access these registers;
85 * these provide simple PCI bus access, without waking up the MAC.
86 * Do not use iwl_write_direct32() family for these registers;
87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
89 * the CSR registers.
90 *
91 * NOTE: Device does need to be awake in order to read this memory
92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
93 */
94#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96#define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101#define IWM_CSR_GP_CNTRL (0x024)
102
103/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
104#define IWM_CSR_INT_PERIODIC_REG (0x005)
105
106/*
107 * Hardware revision info
108 * Bit fields:
109 * 31-16: Reserved
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
113 */
114#define IWM_CSR_HW_REV (0x028)
115
116/*
117 * EEPROM and OTP (one-time-programmable) memory reads
118 *
119 * NOTE: Device must be awake, initialized via apm_ops.init(),
120 * in order to read.
121 */
122#define IWM_CSR_EEPROM_REG (0x02c)
123#define IWM_CSR_EEPROM_GP (0x030)
124#define IWM_CSR_OTP_GP_REG (0x034)
125
126#define IWM_CSR_GIO_REG (0x03C)
127#define IWM_CSR_GP_UCODE_REG (0x048)
128#define IWM_CSR_GP_DRIVER_REG (0x050)
129
130/*
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
132 * SET/CLR registers set/clear bit(s) if "1" is written.
133 */
134#define IWM_CSR_UCODE_DRV_GP1 (0x054)
135#define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137#define IWM_CSR_UCODE_DRV_GP2 (0x060)
138
139#define IWM_CSR_LED_REG (0x094)
140#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
141#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
142
143
144/* GIO Chicken Bits (PCI Express bus link power management) */
145#define IWM_CSR_GIO_CHICKEN_BITS (0x100)
146
147/* Analog phase-lock-loop configuration */
148#define IWM_CSR_ANA_PLL_CFG (0x20c)
149
150/*
151 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
152 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
153 * See also IWM_CSR_HW_REV register.
154 * Bit fields:
155 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
156 * 1-0: "Dash" (-) value, as in C-1, etc.
157 */
158#define IWM_CSR_HW_REV_WA_REG (0x22C)
159
160#define IWM_CSR_DBG_HPET_MEM_REG (0x240)
161#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
162
163/* Bits for IWM_CSR_HW_IF_CONFIG_REG */
164#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
165#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
166#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
167#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
168#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
170#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
171#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
172
173#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
174#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
175#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
176#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
177#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
178#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
179
180#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
181#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
182#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
183#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
184#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
185
186#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
187#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
188
189/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
190 * acknowledged (reset) by host writing "1" to flagged bits. */
191#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
192#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
193#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
194#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
195#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
196#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
197#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
198#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
199#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
200#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
201#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
202
203#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
204 IWM_CSR_INT_BIT_HW_ERR | \
205 IWM_CSR_INT_BIT_FH_TX | \
206 IWM_CSR_INT_BIT_SW_ERR | \
207 IWM_CSR_INT_BIT_RF_KILL | \
208 IWM_CSR_INT_BIT_SW_RX | \
209 IWM_CSR_INT_BIT_WAKEUP | \
210 IWM_CSR_INT_BIT_ALIVE | \
211 IWM_CSR_INT_BIT_RX_PERIODIC)
212
213/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
214#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
215#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
216#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
217#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
218#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
219#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
220
221#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
222 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL0)
224
225#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
226 IWM_CSR_FH_INT_BIT_TX_CHNL0)
227
228/* GPIO */
229#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
230#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
231#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
232
233/* RESET */
234#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
235#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
236#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
237#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
238#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
239#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
240
241/*
242 * GP (general purpose) CONTROL REGISTER
243 * Bit fields:
244 * 27: HW_RF_KILL_SW
245 * Indicates state of (platform's) hardware RF-Kill switch
246 * 26-24: POWER_SAVE_TYPE
247 * Indicates current power-saving mode:
248 * 000 -- No power saving
249 * 001 -- MAC power-down
250 * 010 -- PHY (radio) power-down
251 * 011 -- Error
252 * 9-6: SYS_CONFIG
253 * Indicates current system configuration, reflecting pins on chip
254 * as forced high/low by device circuit board.
255 * 4: GOING_TO_SLEEP
256 * Indicates MAC is entering a power-saving sleep power-down.
257 * Not a good time to access device-internal resources.
258 * 3: MAC_ACCESS_REQ
259 * Host sets this to request and maintain MAC wakeup, to allow host
260 * access to device-internal resources. Host must wait for
261 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
262 * device registers.
263 * 2: INIT_DONE
264 * Host sets this to put device into fully operational D0 power mode.
265 * Host resets this after SW_RESET to put device into low power mode.
266 * 0: MAC_CLOCK_READY
267 * Indicates MAC (ucode processor, etc.) is powered up and can run.
268 * Internal resources are accessible.
269 * NOTE: This does not indicate that the processor is actually running.
270 * NOTE: This does not indicate that device has completed
271 * init or post-power-down restore of internal SRAM memory.
272 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
273 * SRAM is restored and uCode is in normal operation mode.
274 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
275 * do not need to save/restore it.
276 * NOTE: After device reset, this bit remains "0" until host sets
277 * INIT_DONE
278 */
279#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
280#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
281#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
282#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
283
284#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
285
286#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
287#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
288#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
289
290
291/* HW REV */
292#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
293#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
294
295#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
296#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
297#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
298#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
299#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
300#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
301#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
302#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
303#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
304#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
305#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
306#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
307#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
308#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
309#define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
310#define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
311#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
312
313/* EEPROM REG */
314#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
315#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
316#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
317#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
318
319/* EEPROM GP */
320#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
321#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
322#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
323#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
324#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
325#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
326
327/* One-time-programmable memory general purpose reg */
328#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
329#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
330#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
331#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
332
333/* GP REG */
334#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
335#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
336#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
337#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
338#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
339
340
341/* CSR GIO */
342#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
343
344/*
345 * UCODE-DRIVER GP (general purpose) mailbox register 1
346 * Host driver and uCode write and/or read this register to communicate with
347 * each other.
348 * Bit fields:
349 * 4: UCODE_DISABLE
350 * Host sets this to request permanent halt of uCode, same as
351 * sending CARD_STATE command with "halt" bit set.
352 * 3: CT_KILL_EXIT
353 * Host sets this to request exit from CT_KILL state, i.e. host thinks
354 * device temperature is low enough to continue normal operation.
355 * 2: CMD_BLOCKED
356 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
357 * to release uCode to clear all Tx and command queues, enter
358 * unassociated mode, and power down.
359 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
360 * 1: SW_BIT_RFKILL
361 * Host sets this when issuing CARD_STATE command to request
362 * device sleep.
363 * 0: MAC_SLEEP
364 * uCode sets this when preparing a power-saving power-down.
365 * uCode resets this when power-up is complete and SRAM is sane.
366 * NOTE: device saves internal SRAM data to host when powering down,
367 * and must restore this data after powering back up.
368 * MAC_SLEEP is the best indication that restore is complete.
369 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
370 * do not need to save/restore it.
371 */
372#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
373#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
374#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
375#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
376#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
377
378/* GP Driver */
379#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
380#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
381#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
382#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
383#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
384#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
385
386#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
387
388/* GIO Chicken Bits (PCI Express bus link power management) */
389#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
390#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
391
392/* LED */
393#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
394#define IWM_CSR_LED_REG_TURN_ON (0x60)
395#define IWM_CSR_LED_REG_TURN_OFF (0x20)
396
397/* ANA_PLL */
398#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
399
400/* HPET MEM debug */
401#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
402
403/* DRAM INT TABLE */
404#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
405#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
406
407/* SECURE boot registers */
408#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
409enum iwm_secure_boot_config_reg {
410 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
411 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
412};
413
414#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
415#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
416enum iwm_secure_boot_status_reg {
417 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
418 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
419 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
420 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
421 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
422};
423
424#define IWM_CSR_UCODE_LOAD_STATUS_ADDR (0x100)
425enum iwm_secure_load_status_reg {
426 IWM_CSR_CPU_STATUS_LOADING_STARTED = 0x00000001,
427 IWM_CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002,
428 IWM_CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
429 IWM_CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
430};
431
432#define IWM_CSR_SECURE_INSPECTOR_CODE_ADDR (0x100)
433#define IWM_CSR_SECURE_INSPECTOR_DATA_ADDR (0x100)
434
435#define IWM_CSR_SECURE_TIME_OUT (100)
436
437#define IWM_FH_TCSR_0_REG0 (0x1D00)
438
439/*
440 * HBUS (Host-side Bus)
441 *
442 * HBUS registers are mapped directly into PCI bus space, but are used
443 * to indirectly access device's internal memory or registers that
444 * may be powered-down.
445 *
446 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
447 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
448 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
449 * internal resources.
450 *
451 * Do not use iwl_write32()/iwl_read32() family to access these registers;
452 * these provide only simple PCI bus access, without waking up the MAC.
453 */
454#define IWM_HBUS_BASE (0x400)
455
456/*
457 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
458 * structures, error log, event log, verifying uCode load).
459 * First write to address register, then read from or write to data register
460 * to complete the job. Once the address register is set up, accesses to
461 * data registers auto-increment the address by one dword.
462 * Bit usage for address registers (read or write):
463 * 0-31: memory address within device
464 */
465#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
466#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
467#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
468#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
469
470/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
471#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
472#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
473
474/*
475 * Registers for accessing device's internal peripheral registers
476 * (e.g. SCD, BSM, etc.). First write to address register,
477 * then read from or write to data register to complete the job.
478 * Bit usage for address registers (read or write):
479 * 0-15: register address (offset) within device
480 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
481 */
482#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
483#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
484#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
485#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
486
487/* Used to enable DBGM */
488#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
489
490/*
491 * Per-Tx-queue write pointer (index, really!)
492 * Indicates index to next TFD that driver will fill (1 past latest filled).
493 * Bit usage:
494 * 0-7: queue write index
495 * 11-8: queue selector
496 */
497#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
498
499/**********************************************************
500 * CSR values
501 **********************************************************/
502 /*
503 * host interrupt timeout value
504 * used with setting interrupt coalescing timer
505 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
506 *
507 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
508 */
509#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
510#define IWM_HOST_INT_TIMEOUT_DEF (0x40)
511#define IWM_HOST_INT_TIMEOUT_MIN (0x0)
512#define IWM_HOST_INT_OPER_MODE (1 << 31)
513
514/*****************************************************************************
515 * 7000/3000 series SHR DTS addresses *
516 *****************************************************************************/
517
518/* Diode Results Register Structure: */
519enum iwm_dtd_diode_reg {
520 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
521 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
522 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
523 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
524 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
525 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
526/* Those are the masks INSIDE the flags bit-field: */
527 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
528 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
529 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
530 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
531};
532
533/*
534 * END iwl-csr.h
535 */
536
537/*
538 * BEGIN iwl-fw.h
539 */
540
541/**
542 * enum iwl_ucode_tlv_flag - ucode API flags
543 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
544 * was a separate TLV but moved here to save space.
545 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
546 * treats good CRC threshold as a boolean
547 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
548 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
549 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
550 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
551 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
552 * offload profile config command.
553 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
554 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
555 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
556 * (rather than two) IPv6 addresses
557 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
558 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
559 * from the probe request template.
560 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
561 * connection when going back to D0
562 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
563 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
564 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
565 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
566 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
567 * containing CAM (Continuous Active Mode) indication.
568 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
569 * single bound interface).
570 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
571 */
572enum iwm_ucode_tlv_flag {
573 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
574 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
575 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
576 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
577 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
578 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
579 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
580 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
581 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
582 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
583 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
584 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
585 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
586 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
587 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
588 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
589 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
590 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
591 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
592 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
593 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
594 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
595};
596
597/* The default calibrate table size if not specified by firmware file */
598#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
599#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
600#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
601
602/* The default max probe length if not specified by the firmware file */
603#define IWM_DEFAULT_MAX_PROBE_LENGTH 200
604
605/*
606 * enumeration of ucode section.
607 * This enumeration is used directly for older firmware (before 16.0).
608 * For new firmware, there can be up to 4 sections (see below) but the
609 * first one packaged into the firmware file is the DATA section and
610 * some debugging code accesses that.
611 */
612enum iwm_ucode_sec {
613 IWM_UCODE_SECTION_DATA,
614 IWM_UCODE_SECTION_INST,
615};
616/*
617 * For 16.0 uCode and above, there is no differentiation between sections,
618 * just an offset to the HW address.
619 */
620#define IWM_UCODE_SECTION_MAX 6
621#define IWM_UCODE_FIRST_SECTION_OF_SECOND_CPU (IWM_UCODE_SECTION_MAX/2)
622
623/* uCode version contains 4 values: Major/Minor/API/Serial */
624#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
625#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
626#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
627#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
628
629/*
630 * Calibration control struct.
631 * Sent as part of the phy configuration command.
632 * @flow_trigger: bitmap for which calibrations to perform according to
633 * flow triggers.
634 * @event_trigger: bitmap for which calibrations to perform according to
635 * event triggers.
636 */
637struct iwm_tlv_calib_ctrl {
638 uint32_t flow_trigger;
639 uint32_t event_trigger;
640} __packed;
641
642enum iwm_fw_phy_cfg {
643 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
644 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
645 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
646 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
647 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
648 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
649 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
650 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
651 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
652 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
653};
654
655#define IWM_UCODE_MAX_CS 1
656
657/**
658 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
659 * @cipher: a cipher suite selector
660 * @flags: cipher scheme flags (currently reserved for a future use)
661 * @hdr_len: a size of MPDU security header
662 * @pn_len: a size of PN
663 * @pn_off: an offset of pn from the beginning of the security header
664 * @key_idx_off: an offset of key index byte in the security header
665 * @key_idx_mask: a bit mask of key_idx bits
666 * @key_idx_shift: bit shift needed to get key_idx
667 * @mic_len: mic length in bytes
668 * @hw_cipher: a HW cipher index used in host commands
669 */
670struct iwm_fw_cipher_scheme {
671 uint32_t cipher;
672 uint8_t flags;
673 uint8_t hdr_len;
674 uint8_t pn_len;
675 uint8_t pn_off;
676 uint8_t key_idx_off;
677 uint8_t key_idx_mask;
678 uint8_t key_idx_shift;
679 uint8_t mic_len;
680 uint8_t hw_cipher;
681} __packed;
682
683/**
684 * struct iwm_fw_cscheme_list - a cipher scheme list
685 * @size: a number of entries
686 * @cs: cipher scheme entries
687 */
688struct iwm_fw_cscheme_list {
689 uint8_t size;
690 struct iwm_fw_cipher_scheme cs[];
691} __packed;
692
693/*
694 * END iwl-fw.h
695 */
696
697/*
698 * BEGIN iwl-fw-file.h
699 */
700
701/* v1/v2 uCode file layout */
702struct iwm_ucode_header {
703 uint32_t ver; /* major/minor/API/serial */
704 union {
705 struct {
706 uint32_t inst_size; /* bytes of runtime code */
707 uint32_t data_size; /* bytes of runtime data */
708 uint32_t init_size; /* bytes of init code */
709 uint32_t init_data_size; /* bytes of init data */
710 uint32_t boot_size; /* bytes of bootstrap code */
711 uint8_t data[0]; /* in same order as sizes */
712 } v1;
713 struct {
714 uint32_t build; /* build number */
715 uint32_t inst_size; /* bytes of runtime code */
716 uint32_t data_size; /* bytes of runtime data */
717 uint32_t init_size; /* bytes of init code */
718 uint32_t init_data_size; /* bytes of init data */
719 uint32_t boot_size; /* bytes of bootstrap code */
720 uint8_t data[0]; /* in same order as sizes */
721 } v2;
722 } u;
723};
724
725/*
726 * new TLV uCode file layout
727 *
728 * The new TLV file format contains TLVs, that each specify
729 * some piece of data.
730 */
731
732enum iwm_ucode_tlv_type {
733 IWM_UCODE_TLV_INVALID = 0, /* unused */
734 IWM_UCODE_TLV_INST = 1,
735 IWM_UCODE_TLV_DATA = 2,
736 IWM_UCODE_TLV_INIT = 3,
737 IWM_UCODE_TLV_INIT_DATA = 4,
738 IWM_UCODE_TLV_BOOT = 5,
739 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
740 IWM_UCODE_TLV_PAN = 7,
741 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
742 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
743 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
744 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
745 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
746 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
747 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
748 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
749 IWM_UCODE_TLV_WOWLAN_INST = 16,
750 IWM_UCODE_TLV_WOWLAN_DATA = 17,
751 IWM_UCODE_TLV_FLAGS = 18,
752 IWM_UCODE_TLV_SEC_RT = 19,
753 IWM_UCODE_TLV_SEC_INIT = 20,
754 IWM_UCODE_TLV_SEC_WOWLAN = 21,
755 IWM_UCODE_TLV_DEF_CALIB = 22,
756 IWM_UCODE_TLV_PHY_SKU = 23,
757 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
758 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
759 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
760 IWM_UCODE_TLV_NUM_OF_CPU = 27,
761 IWM_UCODE_TLV_CSCHEME = 28,
762
763 /*
764 * Following two are not in our base tag, but allow
765 * handling ucode version 9.
766 */
767 IWM_UCODE_TLV_API_CHANGES_SET = 29,
768 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30
769};
770
771struct iwm_ucode_tlv {
772 uint32_t type; /* see above */
773 uint32_t length; /* not including type/length fields */
774 uint8_t data[0];
775};
776
777#define IWM_TLV_UCODE_MAGIC 0x0a4c5749
778
779struct iwm_tlv_ucode_header {
780 /*
781 * The TLV style ucode header is distinguished from
782 * the v1/v2 style header by first four bytes being
783 * zero, as such is an invalid combination of
784 * major/minor/API/serial versions.
785 */
786 uint32_t zero;
787 uint32_t magic;
788 uint8_t human_readable[64];
789 uint32_t ver; /* major/minor/API/serial */
790 uint32_t build;
791 uint64_t ignore;
792 /*
793 * The data contained herein has a TLV layout,
794 * see above for the TLV header and types.
795 * Note that each TLV is padded to a length
796 * that is a multiple of 4 for alignment.
797 */
798 uint8_t data[0];
799};
800
801/*
802 * END iwl-fw-file.h
803 */
804
805/*
806 * BEGIN iwl-prph.h
807 */
808
809/*
810 * Registers in this file are internal, not PCI bus memory mapped.
811 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
812 */
813#define IWM_PRPH_BASE (0x00000)
814#define IWM_PRPH_END (0xFFFFF)
815
816/* APMG (power management) constants */
817#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
818#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
819#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
820#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
821#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
822#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
823#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
824#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
825#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
826#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
827#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
828
829#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
830#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
831#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
832
833#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
834#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
835#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
836#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
837#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
838#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
839#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
840
841#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
842
843#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
844
845/* Device system time */
846#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
847
848/* Device NMI register */
849#define IWM_DEVICE_SET_NMI_REG 0x00a01c30
850
851/*****************************************************************************
852 * 7000/3000 series SHR DTS addresses *
853 *****************************************************************************/
854
855#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
856#define IWM_DTSC_CFG_MODE (0x00a10604)
857#define IWM_DTSC_VREF_AVG (0x00a10648)
858#define IWM_DTSC_VREF5_AVG (0x00a1064c)
859#define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
860#define IWM_DTSC_PTAT_AVG (0x00a10650)
861
862
863/**
864 * Tx Scheduler
865 *
866 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
867 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
868 * host DRAM. It steers each frame's Tx command (which contains the frame
869 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
870 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
871 * but one DMA channel may take input from several queues.
872 *
873 * Tx DMA FIFOs have dedicated purposes.
874 *
875 * For 5000 series and up, they are used differently
876 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
877 *
878 * 0 -- EDCA BK (background) frames, lowest priority
879 * 1 -- EDCA BE (best effort) frames, normal priority
880 * 2 -- EDCA VI (video) frames, higher priority
881 * 3 -- EDCA VO (voice) and management frames, highest priority
882 * 4 -- unused
883 * 5 -- unused
884 * 6 -- unused
885 * 7 -- Commands
886 *
887 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
888 * In addition, driver can map the remaining queues to Tx DMA/FIFO
889 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
890 *
891 * The driver sets up each queue to work in one of two modes:
892 *
893 * 1) Scheduler-Ack, in which the scheduler automatically supports a
894 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
895 * contains TFDs for a unique combination of Recipient Address (RA)
896 * and Traffic Identifier (TID), that is, traffic of a given
897 * Quality-Of-Service (QOS) priority, destined for a single station.
898 *
899 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
900 * each frame within the BA window, including whether it's been transmitted,
901 * and whether it's been acknowledged by the receiving station. The device
902 * automatically processes block-acks received from the receiving STA,
903 * and reschedules un-acked frames to be retransmitted (successful
904 * Tx completion may end up being out-of-order).
905 *
906 * The driver must maintain the queue's Byte Count table in host DRAM
907 * for this mode.
908 * This mode does not support fragmentation.
909 *
910 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
911 * The device may automatically retry Tx, but will retry only one frame
912 * at a time, until receiving ACK from receiving station, or reaching
913 * retry limit and giving up.
914 *
915 * The command queue (#4/#9) must use this mode!
916 * This mode does not require use of the Byte Count table in host DRAM.
917 *
918 * Driver controls scheduler operation via 3 means:
919 * 1) Scheduler registers
920 * 2) Shared scheduler data base in internal SRAM
921 * 3) Shared data in host DRAM
922 *
923 * Initialization:
924 *
925 * When loading, driver should allocate memory for:
926 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
927 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
928 * (1024 bytes for each queue).
929 *
930 * After receiving "Alive" response from uCode, driver must initialize
931 * the scheduler (especially for queue #4/#9, the command queue, otherwise
932 * the driver can't issue commands!):
933 */
934#define IWM_SCD_MEM_LOWER_BOUND (0x0000)
935
936/**
937 * Max Tx window size is the max number of contiguous TFDs that the scheduler
938 * can keep track of at one time when creating block-ack chains of frames.
939 * Note that "64" matches the number of ack bits in a block-ack packet.
940 */
941#define IWM_SCD_WIN_SIZE 64
942#define IWM_SCD_FRAME_LIMIT 64
943
944#define IWM_SCD_TXFIFO_POS_TID (0)
945#define IWM_SCD_TXFIFO_POS_RA (4)
946#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
947
948/* agn SCD */
949#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
950#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
951#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
952#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
953#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
954
955#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
956#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
957#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
958#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
959#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
960#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
961#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
962#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
963
964/* Context Data */
965#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
966#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
967
968/* Tx status */
969#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
970#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
971
972/* Translation Data */
973#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
974#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
975
976#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
977 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
978
979#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
980 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
981
982#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
983 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
984
985#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
986
987#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
988#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
989#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
990#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
991#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
992#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
993#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
994#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
995#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
996
997static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
998{
999 if (chnl < 20)
1000 return IWM_SCD_BASE + 0x18 + chnl * 4;
1001 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1002}
1003
1004static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1005{
1006 if (chnl < 20)
1007 return IWM_SCD_BASE + 0x68 + chnl * 4;
1008 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1009}
1010
1011static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1012{
1013 if (chnl < 20)
1014 return IWM_SCD_BASE + 0x10c + chnl * 4;
1015 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1016}
1017
1018/*********************** END TX SCHEDULER *************************************/
1019
1020/* Oscillator clock */
1021#define IWM_OSC_CLK (0xa04068)
1022#define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1023
1024/*
1025 * END iwl-prph.h
1026 */
1027
1028/*
1029 * BEGIN iwl-fh.h
1030 */
1031
1032/****************************/
1033/* Flow Handler Definitions */
1034/****************************/
1035
1036/**
1037 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1038 * Addresses are offsets from device's PCI hardware base address.
1039 */
1040#define IWM_FH_MEM_LOWER_BOUND (0x1000)
1041#define IWM_FH_MEM_UPPER_BOUND (0x2000)
1042
1043/**
1044 * Keep-Warm (KW) buffer base address.
1045 *
1046 * Driver must allocate a 4KByte buffer that is for keeping the
1047 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1048 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1049 * from going into a power-savings mode that would cause higher DRAM latency,
1050 * and possible data over/under-runs, before all Tx/Rx is complete.
1051 *
1052 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1053 * of the buffer, which must be 4K aligned. Once this is set up, the device
1054 * automatically invokes keep-warm accesses when normal accesses might not
1055 * be sufficient to maintain fast DRAM response.
1056 *
1057 * Bit fields:
1058 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1059 */
1060#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1061
1062
1063/**
1064 * TFD Circular Buffers Base (CBBC) addresses
1065 *
1066 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1067 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1068 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1069 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1070 * aligned (address bits 0-7 must be 0).
1071 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1072 * for them are in different places.
1073 *
1074 * Bit fields in each pointer register:
1075 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1076 */
1077#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1078#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1079#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1080#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1081#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1082#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1083
1084/* Find TFD CB base pointer for given queue */
1085static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1086{
1087 if (chnl < 16)
1088 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1089 if (chnl < 20)
1090 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1091 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1092}
1093
1094
1095/**
1096 * Rx SRAM Control and Status Registers (RSCSR)
1097 *
1098 * These registers provide handshake between driver and device for the Rx queue
1099 * (this queue handles *all* command responses, notifications, Rx data, etc.
1100 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1101 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1102 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1103 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1104 * mapping between RBDs and RBs.
1105 *
1106 * Driver must allocate host DRAM memory for the following, and set the
1107 * physical address of each into device registers:
1108 *
1109 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1110 * entries (although any power of 2, up to 4096, is selectable by driver).
1111 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1112 * (typically 4K, although 8K or 16K are also selectable by driver).
1113 * Driver sets up RB size and number of RBDs in the CB via Rx config
1114 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1115 *
1116 * Bit fields within one RBD:
1117 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1118 *
1119 * Driver sets physical address [35:8] of base of RBD circular buffer
1120 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1121 *
1122 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1123 * (RBs) have been filled, via a "write pointer", actually the index of
1124 * the RB's corresponding RBD within the circular buffer. Driver sets
1125 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1126 *
1127 * Bit fields in lower dword of Rx status buffer (upper dword not used
1128 * by driver:
1129 * 31-12: Not used by driver
1130 * 11- 0: Index of last filled Rx buffer descriptor
1131 * (device writes, driver reads this value)
1132 *
1133 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1134 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1135 * and update the device's "write" index register,
1136 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1137 *
1138 * This "write" index corresponds to the *next* RBD that the driver will make
1139 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1140 * the circular buffer. This value should initially be 0 (before preparing any
1141 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1142 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1143 * "read" index has advanced past 1! See below).
1144 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1145 *
1146 * As the device fills RBs (referenced from contiguous RBDs within the circular
1147 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1148 * to tell the driver the index of the latest filled RBD. The driver must
1149 * read this "read" index from DRAM after receiving an Rx interrupt from device
1150 *
1151 * The driver must also internally keep track of a third index, which is the
1152 * next RBD to process. When receiving an Rx interrupt, driver should process
1153 * all filled but unprocessed RBs up to, but not including, the RB
1154 * corresponding to the "read" index. For example, if "read" index becomes "1",
1155 * driver may process the RB pointed to by RBD 0. Depending on volume of
1156 * traffic, there may be many RBs to process.
1157 *
1158 * If read index == write index, device thinks there is no room to put new data.
1159 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1160 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1161 * and "read" indexes; that is, make sure that there are no more than 254
1162 * buffers waiting to be filled.
1163 */
1164#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1165#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1166#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1167
1168/**
1169 * Physical base address of 8-byte Rx Status buffer.
1170 * Bit fields:
1171 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1172 */
1173#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1174
1175/**
1176 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1177 * Bit fields:
1178 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1179 */
1180#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1181
1182/**
1183 * Rx write pointer (index, really!).
1184 * Bit fields:
1185 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1186 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1187 */
1188#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1189#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1190
1191#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1192#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1193
1194/**
1195 * Rx Config/Status Registers (RCSR)
1196 * Rx Config Reg for channel 0 (only channel used)
1197 *
1198 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1199 * normal operation (see bit fields).
1200 *
1201 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1202 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1203 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1204 *
1205 * Bit fields:
1206 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1207 * '10' operate normally
1208 * 29-24: reserved
1209 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1210 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1211 * 19-18: reserved
1212 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1213 * '10' 12K, '11' 16K.
1214 * 15-14: reserved
1215 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1216 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1217 * typical value 0x10 (about 1/2 msec)
1218 * 3- 0: reserved
1219 */
1220#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1221#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1222#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1223
1224#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1225#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1226#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1227
1228#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1229#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1230#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1231#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1232#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1233#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1234
1235#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1236#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1237#define IWM_RX_RB_TIMEOUT (0x11)
1238
1239#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1240#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1241#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1242
1243#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1244#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1245#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1246#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1247
1248#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1249#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1250#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1251
1252/**
1253 * Rx Shared Status Registers (RSSR)
1254 *
1255 * After stopping Rx DMA channel (writing 0 to
1256 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1257 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1258 *
1259 * Bit fields:
1260 * 24: 1 = Channel 0 is idle
1261 *
1262 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1263 * contain default values that should not be altered by the driver.
1264 */
1265#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1266#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1267
1268#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1269#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1270#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1271 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1272
1273#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1274
1275#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1276
1277/* TFDB Area - TFDs buffer table */
1278#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1279#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1280#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1281#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1282#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1283
1284/**
1285 * Transmit DMA Channel Control/Status Registers (TCSR)
1286 *
1287 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1288 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1289 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1290 *
1291 * To use a Tx DMA channel, driver must initialize its
1292 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1293 *
1294 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1295 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1296 *
1297 * All other bits should be 0.
1298 *
1299 * Bit fields:
1300 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1301 * '10' operate normally
1302 * 29- 4: Reserved, set to "0"
1303 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1304 * 2- 0: Reserved, set to "0"
1305 */
1306#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1307#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1308
1309/* Find Control/Status reg for given Tx DMA/FIFO channel */
1310#define IWM_FH_TCSR_CHNL_NUM (8)
1311
1312/* TCSR: tx_config register values */
1313#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1314 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1315#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1316 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1317#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1318 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1319
1320#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1321#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1322
1323#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1324#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1325
1326#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1327#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1328#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1329
1330#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1331#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1332#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1333
1334#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1335#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1336#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1337
1338#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1339#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1340#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1341
1342#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1343#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1344
1345/**
1346 * Tx Shared Status Registers (TSSR)
1347 *
1348 * After stopping Tx DMA channel (writing 0 to
1349 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1350 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1351 * (channel's buffers empty | no pending requests).
1352 *
1353 * Bit fields:
1354 * 31-24: 1 = Channel buffers empty (channel 7:0)
1355 * 23-16: 1 = No pending requests (channel 7:0)
1356 */
1357#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1358#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1359
1360#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1361
1362/**
1363 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1364 * 31: Indicates an address error when accessed to internal memory
1365 * uCode/driver must write "1" in order to clear this flag
1366 * 30: Indicates that Host did not send the expected number of dwords to FH
1367 * uCode/driver must write "1" in order to clear this flag
1368 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1369 * command was received from the scheduler while the TRB was already full
1370 * with previous command
1371 * uCode/driver must write "1" in order to clear this flag
1372 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1373 * bit is set, it indicates that the FH has received a full indication
1374 * from the RTC TxFIFO and the current value of the TxCredit counter was
1375 * not equal to zero. This mean that the credit mechanism was not
1376 * synchronized to the TxFIFO status
1377 * uCode/driver must write "1" in order to clear this flag
1378 */
1379#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1380#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1381
1382#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1383
1384/* Tx service channels */
1385#define IWM_FH_SRVC_CHNL (9)
1386#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1387#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1388#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1389 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1390
1391#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1392#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1393 (_chan) * 4)
1394
1395/* Instruct FH to increment the retry count of a packet when
1396 * it is brought from the memory to TX-FIFO
1397 */
1398#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1399
1400#define IWM_RX_QUEUE_SIZE 256
1401#define IWM_RX_QUEUE_MASK 255
1402#define IWM_RX_QUEUE_SIZE_LOG 8
1403
1404/*
1405 * RX related structures and functions
1406 */
1407#define IWM_RX_FREE_BUFFERS 64
1408#define IWM_RX_LOW_WATERMARK 8
1409
1410/**
1411 * struct iwm_rb_status - reseve buffer status
1412 * host memory mapped FH registers
1413 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1414 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1415 * @finished_rb_num [0:11] - Indicates the index of the current RB
1416 * in which the last frame was written to
1417 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1418 * which was transferred
1419 */
1420struct iwm_rb_status {
1421 uint16_t closed_rb_num;
1422 uint16_t closed_fr_num;
1423 uint16_t finished_rb_num;
1424 uint16_t finished_fr_nam;
1425 uint32_t unused;
1426} __packed;
1427
1428
1429#define IWM_TFD_QUEUE_SIZE_MAX (256)
1430#define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1431#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1432 IWM_TFD_QUEUE_SIZE_BC_DUP)
1433#define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1434#define IWM_NUM_OF_TBS 20
1435
1436static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1437{
1438 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1439}
1440/**
1441 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1442 *
1443 * This structure contains dma address and length of transmission address
1444 *
1445 * @lo: low [31:0] portion of the dma address of TX buffer
1446 * every even is unaligned on 16 bit boundary
1447 * @hi_n_len 0-3 [35:32] portion of dma
1448 * 4-15 length of the tx buffer
1449 */
1450struct iwm_tfd_tb {
1451 uint32_t lo;
1452 uint16_t hi_n_len;
1453} __packed;
1454
1455/**
1456 * struct iwm_tfd
1457 *
1458 * Transmit Frame Descriptor (TFD)
1459 *
1460 * @ __reserved1[3] reserved
1461 * @ num_tbs 0-4 number of active tbs
1462 * 5 reserved
1463 * 6-7 padding (not used)
1464 * @ tbs[20] transmit frame buffer descriptors
1465 * @ __pad padding
1466 *
1467 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1468 * Both driver and device share these circular buffers, each of which must be
1469 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1470 *
1471 * Driver must indicate the physical address of the base of each
1472 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1473 *
1474 * Each TFD contains pointer/size information for up to 20 data buffers
1475 * in host DRAM. These buffers collectively contain the (one) frame described
1476 * by the TFD. Each buffer must be a single contiguous block of memory within
1477 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1478 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1479 * Tx frame, up to 8 KBytes in size.
1480 *
1481 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1482 */
1483struct iwm_tfd {
1484 uint8_t __reserved1[3];
1485 uint8_t num_tbs;
1486 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1487 uint32_t __pad;
1488} __packed;
1489
1490/* Keep Warm Size */
1491#define IWM_KW_SIZE 0x1000 /* 4k */
1492
1493/* Fixed (non-configurable) rx data from phy */
1494
1495/**
1496 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1497 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1498 * @tfd_offset 0-12 - tx command byte count
1499 * 12-16 - station index
1500 */
1501struct iwm_agn_scd_bc_tbl {
1502 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1503} __packed;
1504
1505/*
1506 * END iwl-fh.h
1507 */
1508
1509/*
1510 * BEGIN mvm/fw-api.h
1511 */
1512
1513/* maximal number of Tx queues in any platform */
1514#define IWM_MVM_MAX_QUEUES 20
1515
1516/* Tx queue numbers */
1517enum {
1518 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1519 IWM_MVM_CMD_QUEUE = 9,
1520};
1521
1522#define IWM_MVM_CMD_FIFO 7
1523
1524#define IWM_MVM_STATION_COUNT 16
1525
1526/* commands */
1527enum {
1528 IWM_MVM_ALIVE = 0x1,
1529 IWM_REPLY_ERROR = 0x2,
1530
1531 IWM_INIT_COMPLETE_NOTIF = 0x4,
1532
1533 /* PHY context commands */
1534 IWM_PHY_CONTEXT_CMD = 0x8,
1535 IWM_DBG_CFG = 0x9,
1536
1537 /* station table */
1538 IWM_ADD_STA_KEY = 0x17,
1539 IWM_ADD_STA = 0x18,
1540 IWM_REMOVE_STA = 0x19,
1541
1542 /* TX */
1543 IWM_TX_CMD = 0x1c,
1544 IWM_TXPATH_FLUSH = 0x1e,
1545 IWM_MGMT_MCAST_KEY = 0x1f,
1546
1547 /* global key */
1548 IWM_WEP_KEY = 0x20,
1549
1550 /* MAC and Binding commands */
1551 IWM_MAC_CONTEXT_CMD = 0x28,
1552 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1553 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1554 IWM_BINDING_CONTEXT_CMD = 0x2b,
1555 IWM_TIME_QUOTA_CMD = 0x2c,
1556 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1557
1558 IWM_LQ_CMD = 0x4e,
1559
1560 /* Calibration */
1561 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1562 IWM_CALIBRATION_CFG_CMD = 0x65,
1563 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1564 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1565 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1566
1567 /* Scan offload */
1568 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1569 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1570 IWM_SCAN_OFFLOAD_COMPLETE = 0x6D,
1571 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
1572 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1573 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1574
1575 /* Phy */
1576 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1577 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1578 /* IWM_PHY_DB_CMD = 0x6c, */
1579
1580 /* Power - legacy power table command */
1581 IWM_POWER_TABLE_CMD = 0x77,
1582 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1583
1584 /* Thermal Throttling*/
1585 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1586
1587 /* Scanning */
1588 IWM_SCAN_REQUEST_CMD = 0x80,
1589 IWM_SCAN_ABORT_CMD = 0x81,
1590 IWM_SCAN_START_NOTIFICATION = 0x82,
1591 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1592 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84,
1593
1594 /* NVM */
1595 IWM_NVM_ACCESS_CMD = 0x88,
1596
1597 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1598
1599 IWM_BEACON_NOTIFICATION = 0x90,
1600 IWM_BEACON_TEMPLATE_CMD = 0x91,
1601 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1602 IWM_BT_CONFIG = 0x9b,
1603 IWM_STATISTICS_NOTIFICATION = 0x9d,
1604 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1605
1606 /* RF-KILL commands and notifications */
1607 IWM_CARD_STATE_CMD = 0xa0,
1608 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1609
1610 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1611
1612 /* Power - new power table command */
1613 IWM_MAC_PM_POWER_TABLE = 0xa9,
1614
1615 IWM_REPLY_RX_PHY_CMD = 0xc0,
1616 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1617 IWM_BA_NOTIF = 0xc5,
1618
1619 /* BT Coex */
1620 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1621 IWM_BT_COEX_PROT_ENV = 0xcd,
1622 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1623 IWM_BT_COEX_CI = 0x5d,
1624
1625 IWM_REPLY_SF_CFG_CMD = 0xd1,
1626 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1627
1628 IWM_REPLY_DEBUG_CMD = 0xf0,
1629 IWM_DEBUG_LOG_MSG = 0xf7,
1630
1631 IWM_MCAST_FILTER_CMD = 0xd0,
1632
1633 /* D3 commands/notifications */
1634 IWM_D3_CONFIG_CMD = 0xd3,
1635 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1636 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1637 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1638
1639 /* for WoWLAN in particular */
1640 IWM_WOWLAN_PATTERNS = 0xe0,
1641 IWM_WOWLAN_CONFIGURATION = 0xe1,
1642 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1643 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1644 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1645 IWM_WOWLAN_GET_STATUSES = 0xe5,
1646 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1647
1648 /* and for NetDetect */
1649 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1650 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1651 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1652 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1653 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1654
1655 IWM_REPLY_MAX = 0xff,
1656};
1657
1658/**
1659 * struct iwm_cmd_response - generic response struct for most commands
1660 * @status: status of the command asked, changes for each one
1661 */
1662struct iwm_cmd_response {
1663 uint32_t status;
1664};
1665
1666/*
1667 * struct iwm_tx_ant_cfg_cmd
1668 * @valid: valid antenna configuration
1669 */
1670struct iwm_tx_ant_cfg_cmd {
1671 uint32_t valid;
1672} __packed;
1673
1674/**
1675 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1676 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1677 * @flags: (reserved for future implementation)
1678 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1679 * @pwr_restriction: TX power restriction in dBms.
1680 */
1681struct iwm_reduce_tx_power_cmd {
1682 uint8_t flags;
1683 uint8_t mac_context_id;
1684 uint16_t pwr_restriction;
1685} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1686
1687/*
1688 * Calibration control struct.
1689 * Sent as part of the phy configuration command.
1690 * @flow_trigger: bitmap for which calibrations to perform according to
1691 * flow triggers.
1692 * @event_trigger: bitmap for which calibrations to perform according to
1693 * event triggers.
1694 */
1695struct iwm_calib_ctrl {
1696 uint32_t flow_trigger;
1697 uint32_t event_trigger;
1698} __packed;
1699
1700/* This enum defines the bitmap of various calibrations to enable in both
1701 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1702 */
1703enum iwm_calib_cfg {
1704 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1705 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1706 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1707 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1708 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1709 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1710 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1711 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1712 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1713 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1714 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1715 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1716 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1717 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1718 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1719 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1720 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1721 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1722 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1723};
1724
1725/*
1726 * Phy configuration command.
1727 */
1728struct iwm_phy_cfg_cmd {
1729 uint32_t phy_cfg;
1730 struct iwm_calib_ctrl calib_control;
1731} __packed;
1732
1733#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1734#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1735#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1736#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1737#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1738#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1739#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1740#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1741#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1742#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1743
1744
1745/* Target of the IWM_NVM_ACCESS_CMD */
1746enum {
1747 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1748 IWM_NVM_ACCESS_TARGET_OTP = 1,
1749 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1750};
1751
1752/* Section types for IWM_NVM_ACCESS_CMD */
1753enum {
1754 IWM_NVM_SECTION_TYPE_HW = 0,
1755 IWM_NVM_SECTION_TYPE_SW,
1756 IWM_NVM_SECTION_TYPE_PAPD,
1757 IWM_NVM_SECTION_TYPE_BT,
1758 IWM_NVM_SECTION_TYPE_CALIBRATION,
1759 IWM_NVM_SECTION_TYPE_PRODUCTION,
1760 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB,
1761 IWM_NVM_NUM_OF_SECTIONS,
1762};
1763
1764/**
1765 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1766 * @op_code: 0 - read, 1 - write
1767 * @target: IWM_NVM_ACCESS_TARGET_*
1768 * @type: IWM_NVM_SECTION_TYPE_*
1769 * @offset: offset in bytes into the section
1770 * @length: in bytes, to read/write
1771 * @data: if write operation, the data to write. On read its empty
1772 */
1773struct iwm_nvm_access_cmd {
1774 uint8_t op_code;
1775 uint8_t target;
1776 uint16_t type;
1777 uint16_t offset;
1778 uint16_t length;
1779 uint8_t data[];
1780} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
1781
1782/**
1783 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
1784 * @offset: offset in bytes into the section
1785 * @length: in bytes, either how much was written or read
1786 * @type: IWM_NVM_SECTION_TYPE_*
1787 * @status: 0 for success, fail otherwise
1788 * @data: if read operation, the data returned. Empty on write.
1789 */
1790struct iwm_nvm_access_resp {
1791 uint16_t offset;
1792 uint16_t length;
1793 uint16_t type;
1794 uint16_t status;
1795 uint8_t data[];
1796} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
1797
1798/* IWM_MVM_ALIVE 0x1 */
1799
1800/* alive response is_valid values */
1801#define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
1802#define IWM_ALIVE_RESP_RFKILL (1 << 1)
1803
1804/* alive response ver_type values */
1805enum {
1806 IWM_FW_TYPE_HW = 0,
1807 IWM_FW_TYPE_PROT = 1,
1808 IWM_FW_TYPE_AP = 2,
1809 IWM_FW_TYPE_WOWLAN = 3,
1810 IWM_FW_TYPE_TIMING = 4,
1811 IWM_FW_TYPE_WIPAN = 5
1812};
1813
1814/* alive response ver_subtype values */
1815enum {
1816 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
1817 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
1818 IWM_FW_SUBTYPE_REDUCED = 2,
1819 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
1820 IWM_FW_SUBTYPE_WOWLAN = 4,
1821 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
1822 IWM_FW_SUBTYPE_WIPAN = 6,
1823 IWM_FW_SUBTYPE_INITIALIZE = 9
1824};
1825
1826#define IWM_ALIVE_STATUS_ERR 0xDEAD
1827#define IWM_ALIVE_STATUS_OK 0xCAFE
1828
1829#define IWM_ALIVE_FLG_RFKILL (1 << 0)
1830
1831struct iwm_mvm_alive_resp {
1832 uint16_t status;
1833 uint16_t flags;
1834 uint8_t ucode_minor;
1835 uint8_t ucode_major;
1836 uint16_t id;
1837 uint8_t api_minor;
1838 uint8_t api_major;
1839 uint8_t ver_subtype;
1840 uint8_t ver_type;
1841 uint8_t mac;
1842 uint8_t opt;
1843 uint16_t reserved2;
1844 uint32_t timestamp;
1845 uint32_t error_event_table_ptr; /* SRAM address for error log */
1846 uint32_t log_event_table_ptr; /* SRAM address for event log */
1847 uint32_t cpu_register_ptr;
1848 uint32_t dbgm_config_ptr;
1849 uint32_t alive_counter_ptr;
1850 uint32_t scd_base_ptr; /* SRAM address for SCD */
1851} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
1852
1853/* Error response/notification */
1854enum {
1855 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
1856 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
1857 IWM_FW_ERR_SERVICE = 0x2,
1858 IWM_FW_ERR_ARC_MEMORY = 0x3,
1859 IWM_FW_ERR_ARC_CODE = 0x4,
1860 IWM_FW_ERR_WATCH_DOG = 0x5,
1861 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
1862 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
1863 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
1864 IWM_FW_ERR_UNEXPECTED = 0xFE,
1865 IWM_FW_ERR_FATAL = 0xFF
1866};
1867
1868/**
1869 * struct iwm_error_resp - FW error indication
1870 * ( IWM_REPLY_ERROR = 0x2 )
1871 * @error_type: one of IWM_FW_ERR_*
1872 * @cmd_id: the command ID for which the error occurred
1873 * @bad_cmd_seq_num: sequence number of the erroneous command
1874 * @error_service: which service created the error, applicable only if
1875 * error_type = 2, otherwise 0
1876 * @timestamp: TSF in usecs.
1877 */
1878struct iwm_error_resp {
1879 uint32_t error_type;
1880 uint8_t cmd_id;
1881 uint8_t reserved1;
1882 uint16_t bad_cmd_seq_num;
1883 uint32_t error_service;
1884 uint64_t timestamp;
1885} __packed;
1886
1887
1888/* Common PHY, MAC and Bindings definitions */
1889
1890#define IWM_MAX_MACS_IN_BINDING (3)
1891#define IWM_MAX_BINDINGS (4)
1892#define IWM_AUX_BINDING_INDEX (3)
1893#define IWM_MAX_PHYS (4)
1894
1895/* Used to extract ID and color from the context dword */
1896#define IWM_FW_CTXT_ID_POS (0)
1897#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
1898#define IWM_FW_CTXT_COLOR_POS (8)
1899#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
1900#define IWM_FW_CTXT_INVALID (0xffffffff)
1901
1902#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
1903 (_color << IWM_FW_CTXT_COLOR_POS))
1904
1905/* Possible actions on PHYs, MACs and Bindings */
1906enum {
1907 IWM_FW_CTXT_ACTION_STUB = 0,
1908 IWM_FW_CTXT_ACTION_ADD,
1909 IWM_FW_CTXT_ACTION_MODIFY,
1910 IWM_FW_CTXT_ACTION_REMOVE,
1911 IWM_FW_CTXT_ACTION_NUM
1912}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
1913
1914/* Time Events */
1915
1916/* Time Event types, according to MAC type */
1917enum iwm_time_event_type {
1918 /* BSS Station Events */
1919 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
1920 IWM_TE_BSS_STA_ASSOC,
1921 IWM_TE_BSS_EAP_DHCP_PROT,
1922 IWM_TE_BSS_QUIET_PERIOD,
1923
1924 /* P2P Device Events */
1925 IWM_TE_P2P_DEVICE_DISCOVERABLE,
1926 IWM_TE_P2P_DEVICE_LISTEN,
1927 IWM_TE_P2P_DEVICE_ACTION_SCAN,
1928 IWM_TE_P2P_DEVICE_FULL_SCAN,
1929
1930 /* P2P Client Events */
1931 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
1932 IWM_TE_P2P_CLIENT_ASSOC,
1933 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
1934
1935 /* P2P GO Events */
1936 IWM_TE_P2P_GO_ASSOC_PROT,
1937 IWM_TE_P2P_GO_REPETITIVE_NOA,
1938 IWM_TE_P2P_GO_CT_WINDOW,
1939
1940 /* WiDi Sync Events */
1941 IWM_TE_WIDI_TX_SYNC,
1942
1943 IWM_TE_MAX
1944}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
1945
1946
1947
1948/* Time event - defines for command API v1 */
1949
1950/*
1951 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
1952 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
1953 * the first fragment is scheduled.
1954 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
1955 * the first 2 fragments are scheduled.
1956 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
1957 * number of fragments are valid.
1958 *
1959 * Other than the constant defined above, specifying a fragmentation value 'x'
1960 * means that the event can be fragmented but only the first 'x' will be
1961 * scheduled.
1962 */
1963enum {
1964 IWM_TE_V1_FRAG_NONE = 0,
1965 IWM_TE_V1_FRAG_SINGLE = 1,
1966 IWM_TE_V1_FRAG_DUAL = 2,
1967 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
1968};
1969
1970/* If a Time Event can be fragmented, this is the max number of fragments */
1971#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
1972/* Repeat the time event endlessly (until removed) */
1973#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
1974/* If a Time Event has bounded repetitions, this is the maximal value */
1975#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
1976
1977/* Time Event dependencies: none, on another TE, or in a specific time */
1978enum {
1979 IWM_TE_V1_INDEPENDENT = 0,
1980 IWM_TE_V1_DEP_OTHER = (1 << 0),
1981 IWM_TE_V1_DEP_TSF = (1 << 1),
1982 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
1983}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
1984
1985/*
1986 * @IWM_TE_V1_NOTIF_NONE: no notifications
1987 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
1988 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
1989 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
1990 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
1991 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
1992 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
1993 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
1994 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
1995 *
1996 * Supported Time event notifications configuration.
1997 * A notification (both event and fragment) includes a status indicating weather
1998 * the FW was able to schedule the event or not. For fragment start/end
1999 * notification the status is always success. There is no start/end fragment
2000 * notification for monolithic events.
2001 */
2002enum {
2003 IWM_TE_V1_NOTIF_NONE = 0,
2004 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2005 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2006 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2007 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2008 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2009 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2010 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2011 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2012}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2013
2014
2015/**
2016 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2017 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2018 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2019 * ( IWM_TIME_EVENT_CMD = 0x29 )
2020 * @id_and_color: ID and color of the relevant MAC
2021 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2022 * @id: this field has two meanings, depending on the action:
2023 * If the action is ADD, then it means the type of event to add.
2024 * For all other actions it is the unique event ID assigned when the
2025 * event was added by the FW.
2026 * @apply_time: When to start the Time Event (in GP2)
2027 * @max_delay: maximum delay to event's start (apply time), in TU
2028 * @depends_on: the unique ID of the event we depend on (if any)
2029 * @interval: interval between repetitions, in TU
2030 * @interval_reciprocal: 2^32 / interval
2031 * @duration: duration of event in TU
2032 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2033 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2034 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2035 * @is_present: 0 or 1, are we present or absent during the Time Event
2036 * @max_frags: maximal number of fragments the Time Event can be divided to
2037 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2038 */
2039struct iwm_time_event_cmd_v1 {
2040 /* COMMON_INDEX_HDR_API_S_VER_1 */
2041 uint32_t id_and_color;
2042 uint32_t action;
2043 uint32_t id;
2044 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2045 uint32_t apply_time;
2046 uint32_t max_delay;
2047 uint32_t dep_policy;
2048 uint32_t depends_on;
2049 uint32_t is_present;
2050 uint32_t max_frags;
2051 uint32_t interval;
2052 uint32_t interval_reciprocal;
2053 uint32_t duration;
2054 uint32_t repeat;
2055 uint32_t notify;
2056} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2057
2058
2059/* Time event - defines for command API v2 */
2060
2061/*
2062 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2063 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2064 * the first fragment is scheduled.
2065 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2066 * the first 2 fragments are scheduled.
2067 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2068 * number of fragments are valid.
2069 *
2070 * Other than the constant defined above, specifying a fragmentation value 'x'
2071 * means that the event can be fragmented but only the first 'x' will be
2072 * scheduled.
2073 */
2074enum {
2075 IWM_TE_V2_FRAG_NONE = 0,
2076 IWM_TE_V2_FRAG_SINGLE = 1,
2077 IWM_TE_V2_FRAG_DUAL = 2,
2078 IWM_TE_V2_FRAG_MAX = 0xfe,
2079 IWM_TE_V2_FRAG_ENDLESS = 0xff
2080};
2081
2082/* Repeat the time event endlessly (until removed) */
2083#define IWM_TE_V2_REPEAT_ENDLESS 0xff
2084/* If a Time Event has bounded repetitions, this is the maximal value */
2085#define IWM_TE_V2_REPEAT_MAX 0xfe
2086
2087#define IWM_TE_V2_PLACEMENT_POS 12
2088#define IWM_TE_V2_ABSENCE_POS 15
2089
2090/* Time event policy values (for time event cmd api v2)
2091 * A notification (both event and fragment) includes a status indicating weather
2092 * the FW was able to schedule the event or not. For fragment start/end
2093 * notification the status is always success. There is no start/end fragment
2094 * notification for monolithic events.
2095 *
2096 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2097 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2098 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2099 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2100 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2101 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2102 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2103 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2104 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2105 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2106 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2107 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2108 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2109 */
2110enum {
2111 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2112
2113 /* notifications (event start/stop, fragment start/stop) */
2114 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2115 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2116 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2117 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2118
2119 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2120 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2121 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2122 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2123
2124 IWM_TE_V2_NOTIF_MSK = 0xff,
2125
2126 /* placement characteristics */
2127 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2128 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2129 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2130
2131 /* are we present or absent during the Time Event. */
2132 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2133};
2134
2135/**
2136 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2137 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2138 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2139 * ( IWM_TIME_EVENT_CMD = 0x29 )
2140 * @id_and_color: ID and color of the relevant MAC
2141 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2142 * @id: this field has two meanings, depending on the action:
2143 * If the action is ADD, then it means the type of event to add.
2144 * For all other actions it is the unique event ID assigned when the
2145 * event was added by the FW.
2146 * @apply_time: When to start the Time Event (in GP2)
2147 * @max_delay: maximum delay to event's start (apply time), in TU
2148 * @depends_on: the unique ID of the event we depend on (if any)
2149 * @interval: interval between repetitions, in TU
2150 * @duration: duration of event in TU
2151 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2152 * @max_frags: maximal number of fragments the Time Event can be divided to
2153 * @policy: defines whether uCode shall notify the host or other uCode modules
2154 * on event and/or fragment start and/or end
2155 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2156 * IWM_TE_EVENT_SOCIOPATHIC
2157 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2158 */
2159struct iwm_time_event_cmd_v2 {
2160 /* COMMON_INDEX_HDR_API_S_VER_1 */
2161 uint32_t id_and_color;
2162 uint32_t action;
2163 uint32_t id;
2164 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2165 uint32_t apply_time;
2166 uint32_t max_delay;
2167 uint32_t depends_on;
2168 uint32_t interval;
2169 uint32_t duration;
2170 uint8_t repeat;
2171 uint8_t max_frags;
2172 uint16_t policy;
2173} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2174
2175/**
2176 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2177 * @status: bit 0 indicates success, all others specify errors
2178 * @id: the Time Event type
2179 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2180 * @id_and_color: ID and color of the relevant MAC
2181 */
2182struct iwm_time_event_resp {
2183 uint32_t status;
2184 uint32_t id;
2185 uint32_t unique_id;
2186 uint32_t id_and_color;
2187} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2188
2189/**
2190 * struct iwm_time_event_notif - notifications of time event start/stop
2191 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2192 * @timestamp: action timestamp in GP2
2193 * @session_id: session's unique id
2194 * @unique_id: unique id of the Time Event itself
2195 * @id_and_color: ID and color of the relevant MAC
2196 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2197 * @status: true if scheduled, false otherwise (not executed)
2198 */
2199struct iwm_time_event_notif {
2200 uint32_t timestamp;
2201 uint32_t session_id;
2202 uint32_t unique_id;
2203 uint32_t id_and_color;
2204 uint32_t action;
2205 uint32_t status;
2206} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2207
2208
2209/* Bindings and Time Quota */
2210
2211/**
2212 * struct iwm_binding_cmd - configuring bindings
2213 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2214 * @id_and_color: ID and color of the relevant Binding
2215 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2216 * @macs: array of MAC id and colors which belong to the binding
2217 * @phy: PHY id and color which belongs to the binding
2218 */
2219struct iwm_binding_cmd {
2220 /* COMMON_INDEX_HDR_API_S_VER_1 */
2221 uint32_t id_and_color;
2222 uint32_t action;
2223 /* IWM_BINDING_DATA_API_S_VER_1 */
2224 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2225 uint32_t phy;
2226} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2227
2228/* The maximal number of fragments in the FW's schedule session */
2229#define IWM_MVM_MAX_QUOTA 128
2230
2231/**
2232 * struct iwm_time_quota_data - configuration of time quota per binding
2233 * @id_and_color: ID and color of the relevant Binding
2234 * @quota: absolute time quota in TU. The scheduler will try to divide the
2235 * remainig quota (after Time Events) according to this quota.
2236 * @max_duration: max uninterrupted context duration in TU
2237 */
2238struct iwm_time_quota_data {
2239 uint32_t id_and_color;
2240 uint32_t quota;
2241 uint32_t max_duration;
2242} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2243
2244/**
2245 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2246 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2247 * @quotas: allocations per binding
2248 */
2249struct iwm_time_quota_cmd {
2250 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2251} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2252
2253
2254/* PHY context */
2255
2256/* Supported bands */
2257#define IWM_PHY_BAND_5 (0)
2258#define IWM_PHY_BAND_24 (1)
2259
2260/* Supported channel width, vary if there is VHT support */
2261#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2262#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2263#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2264#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2265
2266/*
2267 * Control channel position:
2268 * For legacy set bit means upper channel, otherwise lower.
2269 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2270 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2271 * center_freq
2272 * |
2273 * 40Mhz |_______|_______|
2274 * 80Mhz |_______|_______|_______|_______|
2275 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2276 * code 011 010 001 000 | 100 101 110 111
2277 */
2278#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2279#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2280#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2281#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2282#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2283#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2284#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2285#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2286
2287/*
2288 * @band: IWM_PHY_BAND_*
2289 * @channel: channel number
2290 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2291 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2292 */
2293struct iwm_fw_channel_info {
2294 uint8_t band;
2295 uint8_t channel;
2296 uint8_t width;
2297 uint8_t ctrl_pos;
2298} __packed;
2299
2300#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2301#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2302 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2303#define IWM_PHY_RX_CHAIN_VALID_POS (1)
2304#define IWM_PHY_RX_CHAIN_VALID_MSK \
2305 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2306#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2307#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2308 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2309#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2310#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2311 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2312#define IWM_PHY_RX_CHAIN_CNT_POS (10)
2313#define IWM_PHY_RX_CHAIN_CNT_MSK \
2314 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2315#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2316#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2317 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2318#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2319#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2320 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2321
2322/* TODO: fix the value, make it depend on firmware at runtime? */
2323#define IWM_NUM_PHY_CTX 3
2324
2325/* TODO: complete missing documentation */
2326/**
2327 * struct iwm_phy_context_cmd - config of the PHY context
2328 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2329 * @id_and_color: ID and color of the relevant Binding
2330 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2331 * @apply_time: 0 means immediate apply and context switch.
2332 * other value means apply new params after X usecs
2333 * @tx_param_color: ???
2334 * @channel_info:
2335 * @txchain_info: ???
2336 * @rxchain_info: ???
2337 * @acquisition_data: ???
2338 * @dsp_cfg_flags: set to 0
2339 */
2340struct iwm_phy_context_cmd {
2341 /* COMMON_INDEX_HDR_API_S_VER_1 */
2342 uint32_t id_and_color;
2343 uint32_t action;
2344 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2345 uint32_t apply_time;
2346 uint32_t tx_param_color;
2347 struct iwm_fw_channel_info ci;
2348 uint32_t txchain_info;
2349 uint32_t rxchain_info;
2350 uint32_t acquisition_data;
2351 uint32_t dsp_cfg_flags;
2352} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2353
2354#define IWM_RX_INFO_PHY_CNT 8
2355#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2356#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2357#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2358#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2359#define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2360#define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2361#define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2362
2363#define IWM_RX_INFO_AGC_IDX 1
2364#define IWM_RX_INFO_RSSI_AB_IDX 2
2365#define IWM_OFDM_AGC_A_MSK 0x0000007f
2366#define IWM_OFDM_AGC_A_POS 0
2367#define IWM_OFDM_AGC_B_MSK 0x00003f80
2368#define IWM_OFDM_AGC_B_POS 7
2369#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2370#define IWM_OFDM_AGC_CODE_POS 20
2371#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2372#define IWM_OFDM_RSSI_A_POS 0
2373#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2374#define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2375#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2376#define IWM_OFDM_RSSI_B_POS 16
2377#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2378#define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2379
2380/**
2381 * struct iwm_rx_phy_info - phy info
2382 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2383 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2384 * @cfg_phy_cnt: configurable DSP phy data byte count
2385 * @stat_id: configurable DSP phy data set ID
2386 * @reserved1:
2387 * @system_timestamp: GP2 at on air rise
2388 * @timestamp: TSF at on air rise
2389 * @beacon_time_stamp: beacon at on-air rise
2390 * @phy_flags: general phy flags: band, modulation, ...
2391 * @channel: channel number
2392 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2393 * @rate_n_flags: IWM_RATE_MCS_*
2394 * @byte_count: frame's byte-count
2395 * @frame_time: frame's time on the air, based on byte count and frame rate
2396 * calculation
2397 * @mac_active_msk: what MACs were active when the frame was received
2398 *
2399 * Before each Rx, the device sends this data. It contains PHY information
2400 * about the reception of the packet.
2401 */
2402struct iwm_rx_phy_info {
2403 uint8_t non_cfg_phy_cnt;
2404 uint8_t cfg_phy_cnt;
2405 uint8_t stat_id;
2406 uint8_t reserved1;
2407 uint32_t system_timestamp;
2408 uint64_t timestamp;
2409 uint32_t beacon_time_stamp;
2410 uint16_t phy_flags;
2411#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2412 uint16_t channel;
2413 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2414 uint8_t rate;
2415 uint8_t rflags;
2416 uint16_t xrflags;
2417 uint32_t byte_count;
2418 uint16_t mac_active_msk;
2419 uint16_t frame_time;
2420} __packed;
2421
2422struct iwm_rx_mpdu_res_start {
2423 uint16_t byte_count;
2424 uint16_t reserved;
2425} __packed;
2426
2427/**
2428 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2429 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2430 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2431 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2432 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2433 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2434 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2435 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2436 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2437 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2438 */
2439enum iwm_rx_phy_flags {
2440 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2441 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2442 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2443 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2444 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2445 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2446 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2447 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2448 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2449 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2450};
2451
2452/**
2453 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2454 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2455 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2456 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2457 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2458 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2459 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2460 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2461 * in the driver.
2462 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2463 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2464 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2465 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2466 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2467 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2468 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2469 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2470 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2471 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2472 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2473 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2474 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2475 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2476 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2477 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2478 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2479 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2480 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2481 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2482 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2483 */
2484enum iwm_mvm_rx_status {
2485 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2486 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2487 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2488 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2489 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2490 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2491 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2492 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2493 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2494 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2495 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2496 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2497 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2498 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2499 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2500 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2501 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2502 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2503 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2504 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2505 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2506 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2507 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2508 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2509 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2510 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2511 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2512};
2513
2514/**
2515 * struct iwm_radio_version_notif - information on the radio version
2516 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2517 * @radio_flavor:
2518 * @radio_step:
2519 * @radio_dash:
2520 */
2521struct iwm_radio_version_notif {
2522 uint32_t radio_flavor;
2523 uint32_t radio_step;
2524 uint32_t radio_dash;
2525} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2526
2527enum iwm_card_state_flags {
2528 IWM_CARD_ENABLED = 0x00,
2529 IWM_HW_CARD_DISABLED = 0x01,
2530 IWM_SW_CARD_DISABLED = 0x02,
2531 IWM_CT_KILL_CARD_DISABLED = 0x04,
2532 IWM_HALT_CARD_DISABLED = 0x08,
2533 IWM_CARD_DISABLED_MSK = 0x0f,
2534 IWM_CARD_IS_RX_ON = 0x10,
2535};
2536
2537/**
2538 * struct iwm_radio_version_notif - information on the radio version
2539 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2540 * @flags: %iwm_card_state_flags
2541 */
2542struct iwm_card_state_notif {
2543 uint32_t flags;
2544} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2545
2546/**
2547 * struct iwm_missed_beacons_notif - information on missed beacons
2548 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2549 * @mac_id: interface ID
2550 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2551 * beacons since last RX.
2552 * @consec_missed_beacons: number of consecutive missed beacons
2553 * @num_expected_beacons:
2554 * @num_recvd_beacons:
2555 */
2556struct iwm_missed_beacons_notif {
2557 uint32_t mac_id;
2558 uint32_t consec_missed_beacons_since_last_rx;
2559 uint32_t consec_missed_beacons;
2560 uint32_t num_expected_beacons;
2561 uint32_t num_recvd_beacons;
2562} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2563
2564/**
2565 * struct iwm_set_calib_default_cmd - set default value for calibration.
2566 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2567 * @calib_index: the calibration to set value for
2568 * @length: of data
2569 * @data: the value to set for the calibration result
2570 */
2571struct iwm_set_calib_default_cmd {
2572 uint16_t calib_index;
2573 uint16_t length;
2574 uint8_t data[0];
2575} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2576
2577#define IWM_MAX_PORT_ID_NUM 2
2578#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2579
2580/**
2581 * struct iwm_mcast_filter_cmd - configure multicast filter.
2582 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2583 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2584 * to identify network interface adopted in host-device IF.
2585 * It is used by FW as index in array of addresses. This array has
2586 * IWM_MAX_PORT_ID_NUM members.
2587 * @count: Number of MAC addresses in the array
2588 * @pass_all: Set 1 to pass all multicast packets.
2589 * @bssid: current association BSSID.
2590 * @addr_list: Place holder for array of MAC addresses.
2591 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2592 */
2593struct iwm_mcast_filter_cmd {
2594 uint8_t filter_own;
2595 uint8_t port_id;
2596 uint8_t count;
2597 uint8_t pass_all;
2598 uint8_t bssid[6];
2599 uint8_t reserved[2];
2600 uint8_t addr_list[0];
2601} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2602
2603struct iwm_mvm_statistics_dbg {
2604 uint32_t burst_check;
2605 uint32_t burst_count;
2606 uint32_t wait_for_silence_timeout_cnt;
2607 uint32_t reserved[3];
2608} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2609
2610struct iwm_mvm_statistics_div {
2611 uint32_t tx_on_a;
2612 uint32_t tx_on_b;
2613 uint32_t exec_time;
2614 uint32_t probe_time;
2615 uint32_t rssi_ant;
2616 uint32_t reserved2;
2617} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2618
2619struct iwm_mvm_statistics_general_common {
2620 uint32_t temperature; /* radio temperature */
2621 uint32_t temperature_m; /* radio voltage */
2622 struct iwm_mvm_statistics_dbg dbg;
2623 uint32_t sleep_time;
2624 uint32_t slots_out;
2625 uint32_t slots_idle;
2626 uint32_t ttl_timestamp;
2627 struct iwm_mvm_statistics_div div;
2628 uint32_t rx_enable_counter;
2629 /*
2630 * num_of_sos_states:
2631 * count the number of times we have to re-tune
2632 * in order to get out of bad PHY status
2633 */
2634 uint32_t num_of_sos_states;
2635} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2636
2637struct iwm_mvm_statistics_rx_non_phy {
2638 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2639 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2640 uint32_t non_bssid_frames; /* number of frames with BSSID that
2641 * doesn't belong to the STA BSSID */
2642 uint32_t filtered_frames; /* count frames that were dumped in the
2643 * filtering process */
2644 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2645 * our serving channel */
2646 uint32_t channel_beacons; /* beacons with our bss id and in our
2647 * serving channel */
2648 uint32_t num_missed_bcon; /* number of missed beacons */
2649 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2650 * ADC was in saturation */
2651 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2652 * for INA */
2653 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2654 uint32_t interference_data_flag; /* flag for interference data
2655 * availability. 1 when data is
2656 * available. */
2657 uint32_t channel_load; /* counts RX Enable time in uSec */
2658 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2659 * and CCK) counter */
2660 uint32_t beacon_rssi_a;
2661 uint32_t beacon_rssi_b;
2662 uint32_t beacon_rssi_c;
2663 uint32_t beacon_energy_a;
2664 uint32_t beacon_energy_b;
2665 uint32_t beacon_energy_c;
2666 uint32_t num_bt_kills;
2667 uint32_t mac_id;
2668 uint32_t directed_data_mpdu;
2669} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2670
2671struct iwm_mvm_statistics_rx_phy {
2672 uint32_t ina_cnt;
2673 uint32_t fina_cnt;
2674 uint32_t plcp_err;
2675 uint32_t crc32_err;
2676 uint32_t overrun_err;
2677 uint32_t early_overrun_err;
2678 uint32_t crc32_good;
2679 uint32_t false_alarm_cnt;
2680 uint32_t fina_sync_err_cnt;
2681 uint32_t sfd_timeout;
2682 uint32_t fina_timeout;
2683 uint32_t unresponded_rts;
2684 uint32_t rxe_frame_limit_overrun;
2685 uint32_t sent_ack_cnt;
2686 uint32_t sent_cts_cnt;
2687 uint32_t sent_ba_rsp_cnt;
2688 uint32_t dsp_self_kill;
2689 uint32_t mh_format_err;
2690 uint32_t re_acq_main_rssi_sum;
2691 uint32_t reserved;
2692} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2693
2694struct iwm_mvm_statistics_rx_ht_phy {
2695 uint32_t plcp_err;
2696 uint32_t overrun_err;
2697 uint32_t early_overrun_err;
2698 uint32_t crc32_good;
2699 uint32_t crc32_err;
2700 uint32_t mh_format_err;
2701 uint32_t agg_crc32_good;
2702 uint32_t agg_mpdu_cnt;
2703 uint32_t agg_cnt;
2704 uint32_t unsupport_mcs;
2705} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
2706
2707#define IWM_MAX_CHAINS 3
2708
2709struct iwm_mvm_statistics_tx_non_phy_agg {
2710 uint32_t ba_timeout;
2711 uint32_t ba_reschedule_frames;
2712 uint32_t scd_query_agg_frame_cnt;
2713 uint32_t scd_query_no_agg;
2714 uint32_t scd_query_agg;
2715 uint32_t scd_query_mismatch;
2716 uint32_t frame_not_ready;
2717 uint32_t underrun;
2718 uint32_t bt_prio_kill;
2719 uint32_t rx_ba_rsp_cnt;
2720 int8_t txpower[IWM_MAX_CHAINS];
2721 int8_t reserved;
2722 uint32_t reserved2;
2723} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
2724
2725struct iwm_mvm_statistics_tx_channel_width {
2726 uint32_t ext_cca_narrow_ch20[1];
2727 uint32_t ext_cca_narrow_ch40[2];
2728 uint32_t ext_cca_narrow_ch80[3];
2729 uint32_t ext_cca_narrow_ch160[4];
2730 uint32_t last_tx_ch_width_indx;
2731 uint32_t rx_detected_per_ch_width[4];
2732 uint32_t success_per_ch_width[4];
2733 uint32_t fail_per_ch_width[4];
2734}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
2735
2736struct iwm_mvm_statistics_tx {
2737 uint32_t preamble_cnt;
2738 uint32_t rx_detected_cnt;
2739 uint32_t bt_prio_defer_cnt;
2740 uint32_t bt_prio_kill_cnt;
2741 uint32_t few_bytes_cnt;
2742 uint32_t cts_timeout;
2743 uint32_t ack_timeout;
2744 uint32_t expected_ack_cnt;
2745 uint32_t actual_ack_cnt;
2746 uint32_t dump_msdu_cnt;
2747 uint32_t burst_abort_next_frame_mismatch_cnt;
2748 uint32_t burst_abort_missing_next_frame_cnt;
2749 uint32_t cts_timeout_collision;
2750 uint32_t ack_or_ba_timeout_collision;
2751 struct iwm_mvm_statistics_tx_non_phy_agg agg;
2752 struct iwm_mvm_statistics_tx_channel_width channel_width;
2753} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
2754
2755
2756struct iwm_mvm_statistics_bt_activity {
2757 uint32_t hi_priority_tx_req_cnt;
2758 uint32_t hi_priority_tx_denied_cnt;
2759 uint32_t lo_priority_tx_req_cnt;
2760 uint32_t lo_priority_tx_denied_cnt;
2761 uint32_t hi_priority_rx_req_cnt;
2762 uint32_t hi_priority_rx_denied_cnt;
2763 uint32_t lo_priority_rx_req_cnt;
2764 uint32_t lo_priority_rx_denied_cnt;
2765} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
2766
2767struct iwm_mvm_statistics_general {
2768 struct iwm_mvm_statistics_general_common common;
2769 uint32_t beacon_filtered;
2770 uint32_t missed_beacons;
2771 int8_t beacon_filter_average_energy;
2772 int8_t beacon_filter_reason;
2773 int8_t beacon_filter_current_energy;
2774 int8_t beacon_filter_reserved;
2775 uint32_t beacon_filter_delta_time;
2776 struct iwm_mvm_statistics_bt_activity bt_activity;
2777} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2778
2779struct iwm_mvm_statistics_rx {
2780 struct iwm_mvm_statistics_rx_phy ofdm;
2781 struct iwm_mvm_statistics_rx_phy cck;
2782 struct iwm_mvm_statistics_rx_non_phy general;
2783 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
2784} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
2785
2786/*
2787 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
2788 *
2789 * By default, uCode issues this notification after receiving a beacon
2790 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
2791 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
2792 *
2793 * Statistics counters continue to increment beacon after beacon, but are
2794 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
2795 * 0x9c with CLEAR_STATS bit set (see above).
2796 *
2797 * uCode also issues this notification during scans. uCode clears statistics
2798 * appropriately so that each notification contains statistics for only the
2799 * one channel that has just been scanned.
2800 */
2801
2802struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
2803 uint32_t flag;
2804 struct iwm_mvm_statistics_rx rx;
2805 struct iwm_mvm_statistics_tx tx;
2806 struct iwm_mvm_statistics_general general;
2807} __packed;
2808
2809/***********************************
2810 * Smart Fifo API
2811 ***********************************/
2812/* Smart Fifo state */
2813enum iwm_sf_state {
2814 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
2815 IWM_SF_FULL_ON,
2816 IWM_SF_UNINIT,
2817 IWM_SF_INIT_OFF,
2818 IWM_SF_HW_NUM_STATES
2819};
2820
2821/* Smart Fifo possible scenario */
2822enum iwm_sf_scenario {
2823 IWM_SF_SCENARIO_SINGLE_UNICAST,
2824 IWM_SF_SCENARIO_AGG_UNICAST,
2825 IWM_SF_SCENARIO_MULTICAST,
2826 IWM_SF_SCENARIO_BA_RESP,
2827 IWM_SF_SCENARIO_TX_RESP,
2828 IWM_SF_NUM_SCENARIO
2829};
2830
2831#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
2832#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
2833
2834/* smart FIFO default values */
2835#define IWM_SF_W_MARK_SISO 4096
2836#define IWM_SF_W_MARK_MIMO2 8192
2837#define IWM_SF_W_MARK_MIMO3 6144
2838#define IWM_SF_W_MARK_LEGACY 4096
2839#define IWM_SF_W_MARK_SCAN 4096
2840
2841/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
2842#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2843#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2844#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2845#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2846#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
2847#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
2848#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
2849#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
2850#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
2851#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
2852
2853#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
2854
2855/**
2856 * Smart Fifo configuration command.
2857 * @state: smart fifo state, types listed in iwm_sf_sate.
2858 * @watermark: Minimum allowed available free space in RXF for transient state.
2859 * @long_delay_timeouts: aging and idle timer values for each scenario
2860 * in long delay state.
2861 * @full_on_timeouts: timer values for each scenario in full on state.
2862 */
2863struct iwm_sf_cfg_cmd {
2864 enum iwm_sf_state state;
2865 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
2866 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2867 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2868} __packed; /* IWM_SF_CFG_API_S_VER_2 */
2869
2870/*
2871 * END mvm/fw-api.h
2872 */
2873
2874/*
2875 * BEGIN mvm/fw-api-mac.h
2876 */
2877
2878/*
2879 * The first MAC indices (starting from 0)
2880 * are available to the driver, AUX follows
2881 */
2882#define IWM_MAC_INDEX_AUX 4
2883#define IWM_MAC_INDEX_MIN_DRIVER 0
2884#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
2885
2886enum iwm_ac {
2887 IWM_AC_BK,
2888 IWM_AC_BE,
2889 IWM_AC_VI,
2890 IWM_AC_VO,
2891 IWM_AC_NUM,
2892};
2893
2894/**
2895 * enum iwm_mac_protection_flags - MAC context flags
2896 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
2897 * this will require CCK RTS/CTS2self.
2898 * RTS/CTS will protect full burst time.
2899 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
2900 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
2901 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
2902 */
2903enum iwm_mac_protection_flags {
2904 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
2905 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
2906 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
2907 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
2908};
2909
2910#define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
2911#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
2912
2913/**
2914 * enum iwm_mac_types - Supported MAC types
2915 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
2916 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
2917 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
2918 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
2919 * @IWM_FW_MAC_TYPE_IBSS: IBSS
2920 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
2921 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
2922 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
2923 * @IWM_FW_MAC_TYPE_GO: P2P GO
2924 * @IWM_FW_MAC_TYPE_TEST: ?
2925 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
2926 */
2927enum iwm_mac_types {
2928 IWM_FW_MAC_TYPE_FIRST = 1,
2929 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
2930 IWM_FW_MAC_TYPE_LISTENER,
2931 IWM_FW_MAC_TYPE_PIBSS,
2932 IWM_FW_MAC_TYPE_IBSS,
2933 IWM_FW_MAC_TYPE_BSS_STA,
2934 IWM_FW_MAC_TYPE_P2P_DEVICE,
2935 IWM_FW_MAC_TYPE_P2P_STA,
2936 IWM_FW_MAC_TYPE_GO,
2937 IWM_FW_MAC_TYPE_TEST,
2938 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
2939}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
2940
2941/**
2942 * enum iwm_tsf_id - TSF hw timer ID
2943 * @IWM_TSF_ID_A: use TSF A
2944 * @IWM_TSF_ID_B: use TSF B
2945 * @IWM_TSF_ID_C: use TSF C
2946 * @IWM_TSF_ID_D: use TSF D
2947 * @IWM_NUM_TSF_IDS: number of TSF timers available
2948 */
2949enum iwm_tsf_id {
2950 IWM_TSF_ID_A = 0,
2951 IWM_TSF_ID_B = 1,
2952 IWM_TSF_ID_C = 2,
2953 IWM_TSF_ID_D = 3,
2954 IWM_NUM_TSF_IDS = 4,
2955}; /* IWM_TSF_ID_API_E_VER_1 */
2956
2957/**
2958 * struct iwm_mac_data_ap - configuration data for AP MAC context
2959 * @beacon_time: beacon transmit time in system time
2960 * @beacon_tsf: beacon transmit time in TSF
2961 * @bi: beacon interval in TU
2962 * @bi_reciprocal: 2^32 / bi
2963 * @dtim_interval: dtim transmit time in TU
2964 * @dtim_reciprocal: 2^32 / dtim_interval
2965 * @mcast_qid: queue ID for multicast traffic
2966 * @beacon_template: beacon template ID
2967 */
2968struct iwm_mac_data_ap {
2969 uint32_t beacon_time;
2970 uint64_t beacon_tsf;
2971 uint32_t bi;
2972 uint32_t bi_reciprocal;
2973 uint32_t dtim_interval;
2974 uint32_t dtim_reciprocal;
2975 uint32_t mcast_qid;
2976 uint32_t beacon_template;
2977} __packed; /* AP_MAC_DATA_API_S_VER_1 */
2978
2979/**
2980 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
2981 * @beacon_time: beacon transmit time in system time
2982 * @beacon_tsf: beacon transmit time in TSF
2983 * @bi: beacon interval in TU
2984 * @bi_reciprocal: 2^32 / bi
2985 * @beacon_template: beacon template ID
2986 */
2987struct iwm_mac_data_ibss {
2988 uint32_t beacon_time;
2989 uint64_t beacon_tsf;
2990 uint32_t bi;
2991 uint32_t bi_reciprocal;
2992 uint32_t beacon_template;
2993} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
2994
2995/**
2996 * struct iwm_mac_data_sta - configuration data for station MAC context
2997 * @is_assoc: 1 for associated state, 0 otherwise
2998 * @dtim_time: DTIM arrival time in system time
2999 * @dtim_tsf: DTIM arrival time in TSF
3000 * @bi: beacon interval in TU, applicable only when associated
3001 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3002 * @dtim_interval: DTIM interval in TU, applicable only when associated
3003 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3004 * @listen_interval: in beacon intervals, applicable only when associated
3005 * @assoc_id: unique ID assigned by the AP during association
3006 */
3007struct iwm_mac_data_sta {
3008 uint32_t is_assoc;
3009 uint32_t dtim_time;
3010 uint64_t dtim_tsf;
3011 uint32_t bi;
3012 uint32_t bi_reciprocal;
3013 uint32_t dtim_interval;
3014 uint32_t dtim_reciprocal;
3015 uint32_t listen_interval;
3016 uint32_t assoc_id;
3017 uint32_t assoc_beacon_arrive_time;
3018} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3019
3020/**
3021 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3022 * @ap: iwm_mac_data_ap struct with most config data
3023 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3024 * 0 indicates that there is no CT window.
3025 * @opp_ps_enabled: indicate that opportunistic PS allowed
3026 */
3027struct iwm_mac_data_go {
3028 struct iwm_mac_data_ap ap;
3029 uint32_t ctwin;
3030 uint32_t opp_ps_enabled;
3031} __packed; /* GO_MAC_DATA_API_S_VER_1 */
3032
3033/**
3034 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3035 * @sta: iwm_mac_data_sta struct with most config data
3036 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3037 * 0 indicates that there is no CT window.
3038 */
3039struct iwm_mac_data_p2p_sta {
3040 struct iwm_mac_data_sta sta;
3041 uint32_t ctwin;
3042} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3043
3044/**
3045 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3046 * @stats_interval: interval in TU between statistics notifications to host.
3047 */
3048struct iwm_mac_data_pibss {
3049 uint32_t stats_interval;
3050} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3051
3052/*
3053 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3054 * context.
3055 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3056 * other channels as well. This should be to true only in case that the
3057 * device is discoverable and there is an active GO. Note that setting this
3058 * field when not needed, will increase the number of interrupts and have
3059 * effect on the platform power, as this setting opens the Rx filters on
3060 * all macs.
3061 */
3062struct iwm_mac_data_p2p_dev {
3063 uint32_t is_disc_extended;
3064} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3065
3066/**
3067 * enum iwm_mac_filter_flags - MAC context filter flags
3068 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3069 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3070 * control frames to the host
3071 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3072 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3073 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3074 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3075 * (in station mode when associated)
3076 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3077 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3078 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3079 */
3080enum iwm_mac_filter_flags {
3081 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3082 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3083 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3084 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3085 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3086 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3087 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3088 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3089 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3090};
3091
3092/**
3093 * enum iwm_mac_qos_flags - QoS flags
3094 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3095 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3096 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3097 *
3098 */
3099enum iwm_mac_qos_flags {
3100 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3101 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3102 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3103};
3104
3105/**
3106 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3107 * @cw_min: Contention window, start value in numbers of slots.
3108 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3109 * @cw_max: Contention window, max value in numbers of slots.
3110 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3111 * @aifsn: Number of slots in Arbitration Interframe Space (before
3112 * performing random backoff timing prior to Tx). Device default 1.
3113 * @fifos_mask: FIFOs used by this MAC for this AC
3114 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3115 *
3116 * One instance of this config struct for each of 4 EDCA access categories
3117 * in struct iwm_qosparam_cmd.
3118 *
3119 * Device will automatically increase contention window by (2*CW) + 1 for each
3120 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3121 * value, to cap the CW value.
3122 */
3123struct iwm_ac_qos {
3124 uint16_t cw_min;
3125 uint16_t cw_max;
3126 uint8_t aifsn;
3127 uint8_t fifos_mask;
3128 uint16_t edca_txop;
3129} __packed; /* IWM_AC_QOS_API_S_VER_2 */
3130
3131/**
3132 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3133 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3134 * @id_and_color: ID and color of the MAC
3135 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3136 * @mac_type: one of IWM_FW_MAC_TYPE_*
3137 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3138 * @node_addr: MAC address
3139 * @bssid_addr: BSSID
3140 * @cck_rates: basic rates available for CCK
3141 * @ofdm_rates: basic rates available for OFDM
3142 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3143 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3144 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3145 * @filter_flags: combination of IWM_MAC_FILTER_*
3146 * @qos_flags: from IWM_MAC_QOS_FLG_*
3147 * @ac: one iwm_mac_qos configuration for each AC
3148 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3149 */
3150struct iwm_mac_ctx_cmd {
3151 /* COMMON_INDEX_HDR_API_S_VER_1 */
3152 uint32_t id_and_color;
3153 uint32_t action;
3154 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3155 uint32_t mac_type;
3156 uint32_t tsf_id;
3157 uint8_t node_addr[6];
3158 uint16_t reserved_for_node_addr;
3159 uint8_t bssid_addr[6];
3160 uint16_t reserved_for_bssid_addr;
3161 uint32_t cck_rates;
3162 uint32_t ofdm_rates;
3163 uint32_t protection_flags;
3164 uint32_t cck_short_preamble;
3165 uint32_t short_slot;
3166 uint32_t filter_flags;
3167 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3168 uint32_t qos_flags;
3169 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3170 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3171 union {
3172 struct iwm_mac_data_ap ap;
3173 struct iwm_mac_data_go go;
3174 struct iwm_mac_data_sta sta;
3175 struct iwm_mac_data_p2p_sta p2p_sta;
3176 struct iwm_mac_data_p2p_dev p2p_dev;
3177 struct iwm_mac_data_pibss pibss;
3178 struct iwm_mac_data_ibss ibss;
3179 };
3180} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3181
3182static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3183{
3184 if (!v)
3185 return 0;
3186 return 0xFFFFFFFF / v;
3187}
3188
3189#define IWM_NONQOS_SEQ_GET 0x1
3190#define IWM_NONQOS_SEQ_SET 0x2
3191struct iwm_nonqos_seq_query_cmd {
3192 uint32_t get_set_flag;
3193 uint32_t mac_id_n_color;
3194 uint16_t value;
3195 uint16_t reserved;
3196} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3197
3198/*
3199 * END mvm/fw-api-mac.h
3200 */
3201
3202/*
3203 * BEGIN mvm/fw-api-power.h
3204 */
3205
3206/* Power Management Commands, Responses, Notifications */
3207
3208/* Radio LP RX Energy Threshold measured in dBm */
3209#define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3210#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3211#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3212
3213/**
3214 * enum iwm_scan_flags - masks for power table command flags
3215 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3216 * receiver and transmitter. '0' - does not allow.
3217 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3218 * '1' Driver enables PM (use rest of parameters)
3219 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3220 * '1' PM could sleep over DTIM till listen Interval.
3221 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3222 * access categories are both delivery and trigger enabled.
3223 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3224 * PBW Snoozing enabled
3225 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3226 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3227 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3228 * detection enablement
3229*/
3230enum iwm_power_flags {
3231 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3232 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3233 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3234 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3235 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3236 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3237 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3238 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3239};
3240
3241#define IWM_POWER_VEC_SIZE 5
3242
3243/**
3244 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3245 * is used also with a new power API for device wide power settings.
3246 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3247 *
3248 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3249 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3250 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3251 * set regardless of power scheme or current power state.
3252 * FW use this value also when PM is disabled.
3253 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3254 * PSM transition - legacy PM
3255 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3256 * PSM transition - legacy PM
3257 * @sleep_interval: not in use
3258 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3259 * is set. For example, if it is required to skip over
3260 * one DTIM, this value need to be set to 2 (DTIM periods).
3261 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3262 * Default: 80dbm
3263 */
3264struct iwm_powertable_cmd {
3265 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3266 uint16_t flags;
3267 uint8_t keep_alive_seconds;
3268 uint8_t debug_flags;
3269 uint32_t rx_data_timeout;
3270 uint32_t tx_data_timeout;
3271 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3272 uint32_t skip_dtim_periods;
3273 uint32_t lprx_rssi_threshold;
3274} __packed;
3275
3276/**
3277 * enum iwm_device_power_flags - masks for device power command flags
3278 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3279 * receiver and transmitter. '0' - does not allow. This flag should be
3280 * always set to '1' unless one need to disable actual power down for debug
3281 * purposes.
3282 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3283 * that power management is disabled. '0' Power management is enabled, one
3284 * of power schemes is applied.
3285*/
3286enum iwm_device_power_flags {
3287 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3288 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3289};
3290
3291/**
3292 * struct iwm_device_power_cmd - device wide power command.
3293 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3294 *
3295 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3296 */
3297struct iwm_device_power_cmd {
3298 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3299 uint16_t flags;
3300 uint16_t reserved;
3301} __packed;
3302
3303/**
3304 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3305 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3306 * @id_and_color: MAC contex identifier
3307 * @flags: Power table command flags from POWER_FLAGS_*
3308 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3309 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3310 * set regardless of power scheme or current power state.
3311 * FW use this value also when PM is disabled.
3312 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3313 * PSM transition - legacy PM
3314 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3315 * PSM transition - legacy PM
3316 * @sleep_interval: not in use
3317 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3318 * is set. For example, if it is required to skip over
3319 * one DTIM, this value need to be set to 2 (DTIM periods).
3320 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3321 * PSM transition - uAPSD
3322 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3323 * PSM transition - uAPSD
3324 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3325 * Default: 80dbm
3326 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3327 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3328 * from the AP [msec]
3329 * @snooze_window: A window of time in which PBW snoozing insures that all
3330 * packets received. It is also the minimum time from last
3331 * received unicast RX packet, before client stops snoozing
3332 * for data. [msec]
3333 * @snooze_step: TBD
3334 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3335 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3336 * each corresponding AC.
3337 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3338 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3339 * values.
3340 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3341 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3342 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3343 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3344 * @limited_ps_threshold:
3345*/
3346struct iwm_mac_power_cmd {
3347 /* CONTEXT_DESC_API_T_VER_1 */
3348 uint32_t id_and_color;
3349
3350 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3351 uint16_t flags;
3352 uint16_t keep_alive_seconds;
3353 uint32_t rx_data_timeout;
3354 uint32_t tx_data_timeout;
3355 uint32_t rx_data_timeout_uapsd;
3356 uint32_t tx_data_timeout_uapsd;
3357 uint8_t lprx_rssi_threshold;
3358 uint8_t skip_dtim_periods;
3359 uint16_t snooze_interval;
3360 uint16_t snooze_window;
3361 uint8_t snooze_step;
3362 uint8_t qndp_tid;
3363 uint8_t uapsd_ac_flags;
3364 uint8_t uapsd_max_sp;
3365 uint8_t heavy_tx_thld_packets;
3366 uint8_t heavy_rx_thld_packets;
3367 uint8_t heavy_tx_thld_percentage;
3368 uint8_t heavy_rx_thld_percentage;
3369 uint8_t limited_ps_threshold;
3370 uint8_t reserved;
3371} __packed;
3372
3373/*
3374 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3375 * associated AP is identified as improperly implementing uAPSD protocol.
3376 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3377 * @sta_id: index of station in uCode's station table - associated AP ID in
3378 * this context.
3379 */
3380struct iwm_uapsd_misbehaving_ap_notif {
3381 uint32_t sta_id;
3382 uint8_t mac_id;
3383 uint8_t reserved[3];
3384} __packed;
3385
3386/**
3387 * struct iwm_beacon_filter_cmd
3388 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3389 * @id_and_color: MAC contex identifier
3390 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3391 * to driver if delta in Energy values calculated for this and last
3392 * passed beacon is greater than this threshold. Zero value means that
3393 * the Energy change is ignored for beacon filtering, and beacon will
3394 * not be forced to be sent to driver regardless of this delta. Typical
3395 * energy delta 5dB.
3396 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3397 * Send beacon to driver if delta in Energy values calculated for this
3398 * and last passed beacon is greater than this threshold. Zero value
3399 * means that the Energy change is ignored for beacon filtering while in
3400 * Roaming state, typical energy delta 1dB.
3401 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3402 * calculated for current beacon is less than the threshold, use
3403 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3404 * Threshold. Typical energy threshold is -72dBm.
3405 * @bf_temp_threshold: This threshold determines the type of temperature
3406 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3407 * If the current temperature is above this threshold - Fast filter
3408 * will be used, If the current temperature is below this threshold -
3409 * Slow filter will be used.
3410 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3411 * calculated for this and the last passed beacon is greater than this
3412 * threshold. Zero value means that the temperature change is ignored for
3413 * beacon filtering; beacons will not be forced to be sent to driver
3414 * regardless of whether its temperature has been changed.
3415 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3416 * calculated for this and the last passed beacon is greater than this
3417 * threshold. Zero value means that the temperature change is ignored for
3418 * beacon filtering; beacons will not be forced to be sent to driver
3419 * regardless of whether its temperature has been changed.
3420 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3421 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3422 * for a specific period of time. Units: Beacons.
3423 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3424 * for a longer period of time then this escape-timeout. Units: Beacons.
3425 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3426 */
3427struct iwm_beacon_filter_cmd {
3428 uint32_t bf_energy_delta;
3429 uint32_t bf_roaming_energy_delta;
3430 uint32_t bf_roaming_state;
3431 uint32_t bf_temp_threshold;
3432 uint32_t bf_temp_fast_filter;
3433 uint32_t bf_temp_slow_filter;
3434 uint32_t bf_enable_beacon_filter;
3435 uint32_t bf_debug_flag;
3436 uint32_t bf_escape_timer;
3437 uint32_t ba_escape_timer;
3438 uint32_t ba_enable_beacon_abort;
3439} __packed;
3440
3441/* Beacon filtering and beacon abort */
3442#define IWM_BF_ENERGY_DELTA_DEFAULT 5
3443#define IWM_BF_ENERGY_DELTA_MAX 255
3444#define IWM_BF_ENERGY_DELTA_MIN 0
3445
3446#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3447#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3448#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3449
3450#define IWM_BF_ROAMING_STATE_DEFAULT 72
3451#define IWM_BF_ROAMING_STATE_MAX 255
3452#define IWM_BF_ROAMING_STATE_MIN 0
3453
3454#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3455#define IWM_BF_TEMP_THRESHOLD_MAX 255
3456#define IWM_BF_TEMP_THRESHOLD_MIN 0
3457
3458#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3459#define IWM_BF_TEMP_FAST_FILTER_MAX 255
3460#define IWM_BF_TEMP_FAST_FILTER_MIN 0
3461
3462#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3463#define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3464#define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3465
3466#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3467
3468#define IWM_BF_DEBUG_FLAG_DEFAULT 0
3469
3470#define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3471#define IWM_BF_ESCAPE_TIMER_MAX 1024
3472#define IWM_BF_ESCAPE_TIMER_MIN 0
3473
3474#define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3475#define IWM_BA_ESCAPE_TIMER_D3 9
3476#define IWM_BA_ESCAPE_TIMER_MAX 1024
3477#define IWM_BA_ESCAPE_TIMER_MIN 0
3478
3479#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3480
3481#define IWM_BF_CMD_CONFIG_DEFAULTS \
3482 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3483 .bf_roaming_energy_delta = \
3484 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3485 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3486 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3487 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3488 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3489 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3490 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3491 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3492
3493/*
3494 * END mvm/fw-api-power.h
3495 */
3496
3497/*
3498 * BEGIN mvm/fw-api-rs.h
3499 */
3500
3501/*
3502 * These serve as indexes into
3503 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3504 * TODO: avoid overlap between legacy and HT rates
3505 */
3506enum {
3507 IWM_RATE_1M_INDEX = 0,
3508 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3509 IWM_RATE_2M_INDEX,
3510 IWM_RATE_5M_INDEX,
3511 IWM_RATE_11M_INDEX,
3512 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3513 IWM_RATE_6M_INDEX,
3514 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3515 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3516 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3517 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3518 IWM_RATE_9M_INDEX,
3519 IWM_RATE_12M_INDEX,
3520 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3521 IWM_RATE_18M_INDEX,
3522 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3523 IWM_RATE_24M_INDEX,
3524 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3525 IWM_RATE_36M_INDEX,
3526 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3527 IWM_RATE_48M_INDEX,
3528 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3529 IWM_RATE_54M_INDEX,
3530 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3531 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3532 IWM_RATE_60M_INDEX,
3533 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3534 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3535 IWM_RATE_MCS_8_INDEX,
3536 IWM_RATE_MCS_9_INDEX,
3537 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3538 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3539 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3540};
3541
3542#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3543
3544/* fw API values for legacy bit rates, both OFDM and CCK */
3545enum {
3546 IWM_RATE_6M_PLCP = 13,
3547 IWM_RATE_9M_PLCP = 15,
3548 IWM_RATE_12M_PLCP = 5,
3549 IWM_RATE_18M_PLCP = 7,
3550 IWM_RATE_24M_PLCP = 9,
3551 IWM_RATE_36M_PLCP = 11,
3552 IWM_RATE_48M_PLCP = 1,
3553 IWM_RATE_54M_PLCP = 3,
3554 IWM_RATE_1M_PLCP = 10,
3555 IWM_RATE_2M_PLCP = 20,
3556 IWM_RATE_5M_PLCP = 55,
3557 IWM_RATE_11M_PLCP = 110,
3558 IWM_RATE_INVM_PLCP = -1,
3559};
3560
3561/*
3562 * rate_n_flags bit fields
3563 *
3564 * The 32-bit value has different layouts in the low 8 bites depending on the
3565 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3566 * for CCK and OFDM).
3567 *
3568 * High-throughput (HT) rate format
3569 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3570 * Very High-throughput (VHT) rate format
3571 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3572 * Legacy OFDM rate format for bits 7:0
3573 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3574 * Legacy CCK rate format for bits 7:0:
3575 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3576 */
3577
3578/* Bit 8: (1) HT format, (0) legacy or VHT format */
3579#define IWM_RATE_MCS_HT_POS 8
3580#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3581
3582/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3583#define IWM_RATE_MCS_CCK_POS 9
3584#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3585
3586/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3587#define IWM_RATE_MCS_VHT_POS 26
3588#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3589
3590
3591/*
3592 * High-throughput (HT) rate format for bits 7:0
3593 *
3594 * 2-0: MCS rate base
3595 * 0) 6 Mbps
3596 * 1) 12 Mbps
3597 * 2) 18 Mbps
3598 * 3) 24 Mbps
3599 * 4) 36 Mbps
3600 * 5) 48 Mbps
3601 * 6) 54 Mbps
3602 * 7) 60 Mbps
3603 * 4-3: 0) Single stream (SISO)
3604 * 1) Dual stream (MIMO)
3605 * 2) Triple stream (MIMO)
3606 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3607 * (bits 7-6 are zero)
3608 *
3609 * Together the low 5 bits work out to the MCS index because we don't
3610 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3611 * streams and 16-23 have three streams. We could also support MCS 32
3612 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3613 */
3614#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3615#define IWM_RATE_HT_MCS_NSS_POS 3
3616#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3617
3618/* Bit 10: (1) Use Green Field preamble */
3619#define IWM_RATE_HT_MCS_GF_POS 10
3620#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3621
3622#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3623
3624/*
3625 * Very High-throughput (VHT) rate format for bits 7:0
3626 *
3627 * 3-0: VHT MCS (0-9)
3628 * 5-4: number of streams - 1:
3629 * 0) Single stream (SISO)
3630 * 1) Dual stream (MIMO)
3631 * 2) Triple stream (MIMO)
3632 */
3633
3634/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3635#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3636#define IWM_RATE_VHT_MCS_NSS_POS 4
3637#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3638
3639/*
3640 * Legacy OFDM rate format for bits 7:0
3641 *
3642 * 3-0: 0xD) 6 Mbps
3643 * 0xF) 9 Mbps
3644 * 0x5) 12 Mbps
3645 * 0x7) 18 Mbps
3646 * 0x9) 24 Mbps
3647 * 0xB) 36 Mbps
3648 * 0x1) 48 Mbps
3649 * 0x3) 54 Mbps
3650 * (bits 7-4 are 0)
3651 *
3652 * Legacy CCK rate format for bits 7:0:
3653 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3654 *
3655 * 6-0: 10) 1 Mbps
3656 * 20) 2 Mbps
3657 * 55) 5.5 Mbps
3658 * 110) 11 Mbps
3659 * (bit 7 is 0)
3660 */
3661#define IWM_RATE_LEGACY_RATE_MSK 0xff
3662
3663
3664/*
3665 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3666 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3667 */
3668#define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3669#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3670#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3671#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3672#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3673#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3674
3675/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3676#define IWM_RATE_MCS_SGI_POS 13
3677#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3678
3679/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3680#define IWM_RATE_MCS_ANT_POS 14
3681#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3682#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3683#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3684#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3685 IWM_RATE_MCS_ANT_B_MSK)
3686#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3687 IWM_RATE_MCS_ANT_C_MSK)
3688#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3689#define IWM_RATE_MCS_ANT_NUM 3
3690
3691/* Bit 17-18: (0) SS, (1) SS*2 */
3692#define IWM_RATE_MCS_STBC_POS 17
3693#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
3694
3695/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
3696#define IWM_RATE_MCS_BF_POS 19
3697#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
3698
3699/* Bit 20: (0) ZLF is off, (1) ZLF is on */
3700#define IWM_RATE_MCS_ZLF_POS 20
3701#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
3702
3703/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
3704#define IWM_RATE_MCS_DUP_POS 24
3705#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
3706
3707/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
3708#define IWM_RATE_MCS_LDPC_POS 27
3709#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
3710
3711
3712/* Link Quality definitions */
3713
3714/* # entries in rate scale table to support Tx retries */
3715#define IWM_LQ_MAX_RETRY_NUM 16
3716
3717/* Link quality command flags bit fields */
3718
3719/* Bit 0: (0) Don't use RTS (1) Use RTS */
3720#define IWM_LQ_FLAG_USE_RTS_POS 0
3721#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
3722
3723/* Bit 1-3: LQ command color. Used to match responses to LQ commands */
3724#define IWM_LQ_FLAG_COLOR_POS 1
3725#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
3726
3727/* Bit 4-5: Tx RTS BW Signalling
3728 * (0) No RTS BW signalling
3729 * (1) Static BW signalling
3730 * (2) Dynamic BW signalling
3731 */
3732#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
3733#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3734#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3735#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3736
3737/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
3738 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
3739 */
3740#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
3741#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
3742
3743/**
3744 * struct iwm_lq_cmd - link quality command
3745 * @sta_id: station to update
3746 * @control: not used
3747 * @flags: combination of IWM_LQ_FLAG_*
3748 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
3749 * and SISO rates
3750 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
3751 * Should be ANT_[ABC]
3752 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
3753 * @initial_rate_index: first index from rs_table per AC category
3754 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
3755 * value of 100 is one usec. Range is 100 to 8000
3756 * @agg_disable_start_th: try-count threshold for starting aggregation.
3757 * If a frame has higher try-count, it should not be selected for
3758 * starting an aggregation sequence.
3759 * @agg_frame_cnt_limit: max frame count in an aggregation.
3760 * 0: no limit
3761 * 1: no aggregation (one frame per aggregation)
3762 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
3763 * @rs_table: array of rates for each TX try, each is rate_n_flags,
3764 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
3765 * @bf_params: beam forming params, currently not used
3766 */
3767struct iwm_lq_cmd {
3768 uint8_t sta_id;
3769 uint8_t reserved1;
3770 uint16_t control;
3771 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
3772 uint8_t flags;
3773 uint8_t mimo_delim;
3774 uint8_t single_stream_ant_msk;
3775 uint8_t dual_stream_ant_msk;
3776 uint8_t initial_rate_index[IWM_AC_NUM];
3777 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
3778 uint16_t agg_time_limit;
3779 uint8_t agg_disable_start_th;
3780 uint8_t agg_frame_cnt_limit;
3781 uint32_t reserved2;
3782 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
3783 uint32_t bf_params;
3784}; /* LINK_QUALITY_CMD_API_S_VER_1 */
3785
3786/*
3787 * END mvm/fw-api-rs.h
3788 */
3789
3790/*
3791 * BEGIN mvm/fw-api-tx.h
3792 */
3793
3794/**
3795 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
3796 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
3797 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
3798 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
3799 * Otherwise, use rate_n_flags from the TX command
3800 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
3801 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
3802 * Must set IWM_TX_CMD_FLG_ACK with this flag.
3803 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
3804 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
3805 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
3806 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
3807 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
3808 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
3809 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
3810 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
3811 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
3812 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
3813 * Should be set for beacons and probe responses
3814 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
3815 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
3816 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
3817 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
3818 * Should be set for 26/30 length MAC headers
3819 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
3820 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
3821 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
3822 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
3823 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
3824 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
3825 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
3826 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
3827 */
3828enum iwm_tx_flags {
3829 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
3830 IWM_TX_CMD_FLG_ACK = (1 << 3),
3831 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
3832 IWM_TX_CMD_FLG_BA = (1 << 5),
3833 IWM_TX_CMD_FLG_BAR = (1 << 6),
3834 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
3835 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
3836 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
3837 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
3838 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
3839 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
3840 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
3841 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
3842 IWM_TX_CMD_FLG_TSF = (1 << 16),
3843 IWM_TX_CMD_FLG_CALIB = (1 << 17),
3844 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
3845 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
3846 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
3847 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
3848 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
3849 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
3850 IWM_TX_CMD_FLG_DUR = (1 << 25),
3851 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
3852 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
3853 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
3854 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
3855}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
3856
3857/*
3858 * TX command security control
3859 */
3860#define IWM_TX_CMD_SEC_WEP 0x01
3861#define IWM_TX_CMD_SEC_CCM 0x02
3862#define IWM_TX_CMD_SEC_TKIP 0x03
3863#define IWM_TX_CMD_SEC_EXT 0x04
3864#define IWM_TX_CMD_SEC_MSK 0x07
3865#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
3866#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
3867#define IWM_TX_CMD_SEC_KEY128 0x08
3868
3869/* TODO: how does these values are OK with only 16 bit variable??? */
3870/*
3871 * TX command next frame info
3872 *
3873 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
3874 * bit 3 - immediate ACK required
3875 * bit 4 - rate is taken from STA table
3876 * bit 5 - frame belongs to BA stream
3877 * bit 6 - immediate BA response expected
3878 * bit 7 - unused
3879 * bits 8:15 - Station ID
3880 * bits 16:31 - rate
3881 */
3882#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
3883#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
3884#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
3885#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
3886#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
3887#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
3888#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
3889#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
3890#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
3891
3892/*
3893 * TX command Frame life time in us - to be written in pm_frame_timeout
3894 */
3895#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
3896#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
3897#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
3898#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
3899
3900/*
3901 * TID for non QoS frames - to be written in tid_tspec
3902 */
3903#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
3904
3905/*
3906 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
3907 */
3908#define IWM_DEFAULT_TX_RETRY 15
3909#define IWM_MGMT_DFAULT_RETRY_LIMIT 3
3910#define IWM_RTS_DFAULT_RETRY_LIMIT 60
3911#define IWM_BAR_DFAULT_RETRY_LIMIT 60
3912#define IWM_LOW_RETRY_LIMIT 7
3913
3914/* TODO: complete documentation for try_cnt and btkill_cnt */
3915/**
3916 * struct iwm_tx_cmd - TX command struct to FW
3917 * ( IWM_TX_CMD = 0x1c )
3918 * @len: in bytes of the payload, see below for details
3919 * @next_frame_len: same as len, but for next frame (0 if not applicable)
3920 * Used for fragmentation and bursting, but not in 11n aggregation.
3921 * @tx_flags: combination of IWM_TX_CMD_FLG_*
3922 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
3923 * cleared. Combination of IWM_RATE_MCS_*
3924 * @sta_id: index of destination station in FW station table
3925 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
| 3
4/******************************************************************************
5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * USA
26 *
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
29 *
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *
34 * BSD LICENSE
35 *
36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
66#ifndef __IF_IWM_REG_H__
67#define __IF_IWM_REG_H__
68
69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
71
72/*
73 * BEGIN iwl-csr.h
74 */
75
76/*
77 * CSR (control and status registers)
78 *
79 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * whenever platform supplies power to device, even when device is in
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
83 *
84 * Use iwl_write32() and iwl_read32() family to access these registers;
85 * these provide simple PCI bus access, without waking up the MAC.
86 * Do not use iwl_write_direct32() family for these registers;
87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
89 * the CSR registers.
90 *
91 * NOTE: Device does need to be awake in order to read this memory
92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
93 */
94#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96#define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101#define IWM_CSR_GP_CNTRL (0x024)
102
103/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
104#define IWM_CSR_INT_PERIODIC_REG (0x005)
105
106/*
107 * Hardware revision info
108 * Bit fields:
109 * 31-16: Reserved
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
113 */
114#define IWM_CSR_HW_REV (0x028)
115
116/*
117 * EEPROM and OTP (one-time-programmable) memory reads
118 *
119 * NOTE: Device must be awake, initialized via apm_ops.init(),
120 * in order to read.
121 */
122#define IWM_CSR_EEPROM_REG (0x02c)
123#define IWM_CSR_EEPROM_GP (0x030)
124#define IWM_CSR_OTP_GP_REG (0x034)
125
126#define IWM_CSR_GIO_REG (0x03C)
127#define IWM_CSR_GP_UCODE_REG (0x048)
128#define IWM_CSR_GP_DRIVER_REG (0x050)
129
130/*
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
132 * SET/CLR registers set/clear bit(s) if "1" is written.
133 */
134#define IWM_CSR_UCODE_DRV_GP1 (0x054)
135#define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137#define IWM_CSR_UCODE_DRV_GP2 (0x060)
138
139#define IWM_CSR_LED_REG (0x094)
140#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
141#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
142
143
144/* GIO Chicken Bits (PCI Express bus link power management) */
145#define IWM_CSR_GIO_CHICKEN_BITS (0x100)
146
147/* Analog phase-lock-loop configuration */
148#define IWM_CSR_ANA_PLL_CFG (0x20c)
149
150/*
151 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
152 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
153 * See also IWM_CSR_HW_REV register.
154 * Bit fields:
155 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
156 * 1-0: "Dash" (-) value, as in C-1, etc.
157 */
158#define IWM_CSR_HW_REV_WA_REG (0x22C)
159
160#define IWM_CSR_DBG_HPET_MEM_REG (0x240)
161#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
162
163/* Bits for IWM_CSR_HW_IF_CONFIG_REG */
164#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
165#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
166#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
167#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
168#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
170#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
171#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
172
173#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
174#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
175#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
176#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
177#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
178#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
179
180#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
181#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
182#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
183#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
184#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
185
186#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
187#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
188
189/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
190 * acknowledged (reset) by host writing "1" to flagged bits. */
191#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
192#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
193#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
194#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
195#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
196#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
197#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
198#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
199#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
200#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
201#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
202
203#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
204 IWM_CSR_INT_BIT_HW_ERR | \
205 IWM_CSR_INT_BIT_FH_TX | \
206 IWM_CSR_INT_BIT_SW_ERR | \
207 IWM_CSR_INT_BIT_RF_KILL | \
208 IWM_CSR_INT_BIT_SW_RX | \
209 IWM_CSR_INT_BIT_WAKEUP | \
210 IWM_CSR_INT_BIT_ALIVE | \
211 IWM_CSR_INT_BIT_RX_PERIODIC)
212
213/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
214#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
215#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
216#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
217#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
218#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
219#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
220
221#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
222 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL0)
224
225#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
226 IWM_CSR_FH_INT_BIT_TX_CHNL0)
227
228/* GPIO */
229#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
230#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
231#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
232
233/* RESET */
234#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
235#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
236#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
237#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
238#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
239#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
240
241/*
242 * GP (general purpose) CONTROL REGISTER
243 * Bit fields:
244 * 27: HW_RF_KILL_SW
245 * Indicates state of (platform's) hardware RF-Kill switch
246 * 26-24: POWER_SAVE_TYPE
247 * Indicates current power-saving mode:
248 * 000 -- No power saving
249 * 001 -- MAC power-down
250 * 010 -- PHY (radio) power-down
251 * 011 -- Error
252 * 9-6: SYS_CONFIG
253 * Indicates current system configuration, reflecting pins on chip
254 * as forced high/low by device circuit board.
255 * 4: GOING_TO_SLEEP
256 * Indicates MAC is entering a power-saving sleep power-down.
257 * Not a good time to access device-internal resources.
258 * 3: MAC_ACCESS_REQ
259 * Host sets this to request and maintain MAC wakeup, to allow host
260 * access to device-internal resources. Host must wait for
261 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
262 * device registers.
263 * 2: INIT_DONE
264 * Host sets this to put device into fully operational D0 power mode.
265 * Host resets this after SW_RESET to put device into low power mode.
266 * 0: MAC_CLOCK_READY
267 * Indicates MAC (ucode processor, etc.) is powered up and can run.
268 * Internal resources are accessible.
269 * NOTE: This does not indicate that the processor is actually running.
270 * NOTE: This does not indicate that device has completed
271 * init or post-power-down restore of internal SRAM memory.
272 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
273 * SRAM is restored and uCode is in normal operation mode.
274 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
275 * do not need to save/restore it.
276 * NOTE: After device reset, this bit remains "0" until host sets
277 * INIT_DONE
278 */
279#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
280#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
281#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
282#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
283
284#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
285
286#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
287#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
288#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
289
290
291/* HW REV */
292#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
293#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
294
295#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
296#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
297#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
298#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
299#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
300#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
301#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
302#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
303#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
304#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
305#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
306#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
307#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
308#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
309#define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
310#define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
311#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
312
313/* EEPROM REG */
314#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
315#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
316#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
317#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
318
319/* EEPROM GP */
320#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
321#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
322#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
323#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
324#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
325#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
326
327/* One-time-programmable memory general purpose reg */
328#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
329#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
330#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
331#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
332
333/* GP REG */
334#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
335#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
336#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
337#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
338#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
339
340
341/* CSR GIO */
342#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
343
344/*
345 * UCODE-DRIVER GP (general purpose) mailbox register 1
346 * Host driver and uCode write and/or read this register to communicate with
347 * each other.
348 * Bit fields:
349 * 4: UCODE_DISABLE
350 * Host sets this to request permanent halt of uCode, same as
351 * sending CARD_STATE command with "halt" bit set.
352 * 3: CT_KILL_EXIT
353 * Host sets this to request exit from CT_KILL state, i.e. host thinks
354 * device temperature is low enough to continue normal operation.
355 * 2: CMD_BLOCKED
356 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
357 * to release uCode to clear all Tx and command queues, enter
358 * unassociated mode, and power down.
359 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
360 * 1: SW_BIT_RFKILL
361 * Host sets this when issuing CARD_STATE command to request
362 * device sleep.
363 * 0: MAC_SLEEP
364 * uCode sets this when preparing a power-saving power-down.
365 * uCode resets this when power-up is complete and SRAM is sane.
366 * NOTE: device saves internal SRAM data to host when powering down,
367 * and must restore this data after powering back up.
368 * MAC_SLEEP is the best indication that restore is complete.
369 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
370 * do not need to save/restore it.
371 */
372#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
373#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
374#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
375#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
376#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
377
378/* GP Driver */
379#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
380#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
381#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
382#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
383#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
384#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
385
386#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
387
388/* GIO Chicken Bits (PCI Express bus link power management) */
389#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
390#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
391
392/* LED */
393#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
394#define IWM_CSR_LED_REG_TURN_ON (0x60)
395#define IWM_CSR_LED_REG_TURN_OFF (0x20)
396
397/* ANA_PLL */
398#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
399
400/* HPET MEM debug */
401#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
402
403/* DRAM INT TABLE */
404#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
405#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
406
407/* SECURE boot registers */
408#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
409enum iwm_secure_boot_config_reg {
410 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
411 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
412};
413
414#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
415#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
416enum iwm_secure_boot_status_reg {
417 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
418 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
419 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
420 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
421 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
422};
423
424#define IWM_CSR_UCODE_LOAD_STATUS_ADDR (0x100)
425enum iwm_secure_load_status_reg {
426 IWM_CSR_CPU_STATUS_LOADING_STARTED = 0x00000001,
427 IWM_CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002,
428 IWM_CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
429 IWM_CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
430};
431
432#define IWM_CSR_SECURE_INSPECTOR_CODE_ADDR (0x100)
433#define IWM_CSR_SECURE_INSPECTOR_DATA_ADDR (0x100)
434
435#define IWM_CSR_SECURE_TIME_OUT (100)
436
437#define IWM_FH_TCSR_0_REG0 (0x1D00)
438
439/*
440 * HBUS (Host-side Bus)
441 *
442 * HBUS registers are mapped directly into PCI bus space, but are used
443 * to indirectly access device's internal memory or registers that
444 * may be powered-down.
445 *
446 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
447 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
448 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
449 * internal resources.
450 *
451 * Do not use iwl_write32()/iwl_read32() family to access these registers;
452 * these provide only simple PCI bus access, without waking up the MAC.
453 */
454#define IWM_HBUS_BASE (0x400)
455
456/*
457 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
458 * structures, error log, event log, verifying uCode load).
459 * First write to address register, then read from or write to data register
460 * to complete the job. Once the address register is set up, accesses to
461 * data registers auto-increment the address by one dword.
462 * Bit usage for address registers (read or write):
463 * 0-31: memory address within device
464 */
465#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
466#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
467#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
468#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
469
470/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
471#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
472#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
473
474/*
475 * Registers for accessing device's internal peripheral registers
476 * (e.g. SCD, BSM, etc.). First write to address register,
477 * then read from or write to data register to complete the job.
478 * Bit usage for address registers (read or write):
479 * 0-15: register address (offset) within device
480 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
481 */
482#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
483#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
484#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
485#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
486
487/* Used to enable DBGM */
488#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
489
490/*
491 * Per-Tx-queue write pointer (index, really!)
492 * Indicates index to next TFD that driver will fill (1 past latest filled).
493 * Bit usage:
494 * 0-7: queue write index
495 * 11-8: queue selector
496 */
497#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
498
499/**********************************************************
500 * CSR values
501 **********************************************************/
502 /*
503 * host interrupt timeout value
504 * used with setting interrupt coalescing timer
505 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
506 *
507 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
508 */
509#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
510#define IWM_HOST_INT_TIMEOUT_DEF (0x40)
511#define IWM_HOST_INT_TIMEOUT_MIN (0x0)
512#define IWM_HOST_INT_OPER_MODE (1 << 31)
513
514/*****************************************************************************
515 * 7000/3000 series SHR DTS addresses *
516 *****************************************************************************/
517
518/* Diode Results Register Structure: */
519enum iwm_dtd_diode_reg {
520 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
521 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
522 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
523 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
524 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
525 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
526/* Those are the masks INSIDE the flags bit-field: */
527 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
528 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
529 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
530 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
531};
532
533/*
534 * END iwl-csr.h
535 */
536
537/*
538 * BEGIN iwl-fw.h
539 */
540
541/**
542 * enum iwl_ucode_tlv_flag - ucode API flags
543 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
544 * was a separate TLV but moved here to save space.
545 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
546 * treats good CRC threshold as a boolean
547 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
548 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
549 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
550 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
551 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
552 * offload profile config command.
553 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
554 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
555 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
556 * (rather than two) IPv6 addresses
557 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
558 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
559 * from the probe request template.
560 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
561 * connection when going back to D0
562 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
563 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
564 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
565 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
566 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
567 * containing CAM (Continuous Active Mode) indication.
568 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
569 * single bound interface).
570 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
571 */
572enum iwm_ucode_tlv_flag {
573 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
574 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
575 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
576 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
577 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
578 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
579 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
580 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
581 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
582 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
583 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
584 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
585 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
586 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
587 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
588 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
589 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
590 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
591 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
592 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
593 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
594 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
595};
596
597/* The default calibrate table size if not specified by firmware file */
598#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
599#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
600#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
601
602/* The default max probe length if not specified by the firmware file */
603#define IWM_DEFAULT_MAX_PROBE_LENGTH 200
604
605/*
606 * enumeration of ucode section.
607 * This enumeration is used directly for older firmware (before 16.0).
608 * For new firmware, there can be up to 4 sections (see below) but the
609 * first one packaged into the firmware file is the DATA section and
610 * some debugging code accesses that.
611 */
612enum iwm_ucode_sec {
613 IWM_UCODE_SECTION_DATA,
614 IWM_UCODE_SECTION_INST,
615};
616/*
617 * For 16.0 uCode and above, there is no differentiation between sections,
618 * just an offset to the HW address.
619 */
620#define IWM_UCODE_SECTION_MAX 6
621#define IWM_UCODE_FIRST_SECTION_OF_SECOND_CPU (IWM_UCODE_SECTION_MAX/2)
622
623/* uCode version contains 4 values: Major/Minor/API/Serial */
624#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
625#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
626#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
627#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
628
629/*
630 * Calibration control struct.
631 * Sent as part of the phy configuration command.
632 * @flow_trigger: bitmap for which calibrations to perform according to
633 * flow triggers.
634 * @event_trigger: bitmap for which calibrations to perform according to
635 * event triggers.
636 */
637struct iwm_tlv_calib_ctrl {
638 uint32_t flow_trigger;
639 uint32_t event_trigger;
640} __packed;
641
642enum iwm_fw_phy_cfg {
643 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
644 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
645 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
646 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
647 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
648 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
649 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
650 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
651 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
652 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
653};
654
655#define IWM_UCODE_MAX_CS 1
656
657/**
658 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
659 * @cipher: a cipher suite selector
660 * @flags: cipher scheme flags (currently reserved for a future use)
661 * @hdr_len: a size of MPDU security header
662 * @pn_len: a size of PN
663 * @pn_off: an offset of pn from the beginning of the security header
664 * @key_idx_off: an offset of key index byte in the security header
665 * @key_idx_mask: a bit mask of key_idx bits
666 * @key_idx_shift: bit shift needed to get key_idx
667 * @mic_len: mic length in bytes
668 * @hw_cipher: a HW cipher index used in host commands
669 */
670struct iwm_fw_cipher_scheme {
671 uint32_t cipher;
672 uint8_t flags;
673 uint8_t hdr_len;
674 uint8_t pn_len;
675 uint8_t pn_off;
676 uint8_t key_idx_off;
677 uint8_t key_idx_mask;
678 uint8_t key_idx_shift;
679 uint8_t mic_len;
680 uint8_t hw_cipher;
681} __packed;
682
683/**
684 * struct iwm_fw_cscheme_list - a cipher scheme list
685 * @size: a number of entries
686 * @cs: cipher scheme entries
687 */
688struct iwm_fw_cscheme_list {
689 uint8_t size;
690 struct iwm_fw_cipher_scheme cs[];
691} __packed;
692
693/*
694 * END iwl-fw.h
695 */
696
697/*
698 * BEGIN iwl-fw-file.h
699 */
700
701/* v1/v2 uCode file layout */
702struct iwm_ucode_header {
703 uint32_t ver; /* major/minor/API/serial */
704 union {
705 struct {
706 uint32_t inst_size; /* bytes of runtime code */
707 uint32_t data_size; /* bytes of runtime data */
708 uint32_t init_size; /* bytes of init code */
709 uint32_t init_data_size; /* bytes of init data */
710 uint32_t boot_size; /* bytes of bootstrap code */
711 uint8_t data[0]; /* in same order as sizes */
712 } v1;
713 struct {
714 uint32_t build; /* build number */
715 uint32_t inst_size; /* bytes of runtime code */
716 uint32_t data_size; /* bytes of runtime data */
717 uint32_t init_size; /* bytes of init code */
718 uint32_t init_data_size; /* bytes of init data */
719 uint32_t boot_size; /* bytes of bootstrap code */
720 uint8_t data[0]; /* in same order as sizes */
721 } v2;
722 } u;
723};
724
725/*
726 * new TLV uCode file layout
727 *
728 * The new TLV file format contains TLVs, that each specify
729 * some piece of data.
730 */
731
732enum iwm_ucode_tlv_type {
733 IWM_UCODE_TLV_INVALID = 0, /* unused */
734 IWM_UCODE_TLV_INST = 1,
735 IWM_UCODE_TLV_DATA = 2,
736 IWM_UCODE_TLV_INIT = 3,
737 IWM_UCODE_TLV_INIT_DATA = 4,
738 IWM_UCODE_TLV_BOOT = 5,
739 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
740 IWM_UCODE_TLV_PAN = 7,
741 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
742 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
743 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
744 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
745 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
746 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
747 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
748 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
749 IWM_UCODE_TLV_WOWLAN_INST = 16,
750 IWM_UCODE_TLV_WOWLAN_DATA = 17,
751 IWM_UCODE_TLV_FLAGS = 18,
752 IWM_UCODE_TLV_SEC_RT = 19,
753 IWM_UCODE_TLV_SEC_INIT = 20,
754 IWM_UCODE_TLV_SEC_WOWLAN = 21,
755 IWM_UCODE_TLV_DEF_CALIB = 22,
756 IWM_UCODE_TLV_PHY_SKU = 23,
757 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
758 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
759 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
760 IWM_UCODE_TLV_NUM_OF_CPU = 27,
761 IWM_UCODE_TLV_CSCHEME = 28,
762
763 /*
764 * Following two are not in our base tag, but allow
765 * handling ucode version 9.
766 */
767 IWM_UCODE_TLV_API_CHANGES_SET = 29,
768 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30
769};
770
771struct iwm_ucode_tlv {
772 uint32_t type; /* see above */
773 uint32_t length; /* not including type/length fields */
774 uint8_t data[0];
775};
776
777#define IWM_TLV_UCODE_MAGIC 0x0a4c5749
778
779struct iwm_tlv_ucode_header {
780 /*
781 * The TLV style ucode header is distinguished from
782 * the v1/v2 style header by first four bytes being
783 * zero, as such is an invalid combination of
784 * major/minor/API/serial versions.
785 */
786 uint32_t zero;
787 uint32_t magic;
788 uint8_t human_readable[64];
789 uint32_t ver; /* major/minor/API/serial */
790 uint32_t build;
791 uint64_t ignore;
792 /*
793 * The data contained herein has a TLV layout,
794 * see above for the TLV header and types.
795 * Note that each TLV is padded to a length
796 * that is a multiple of 4 for alignment.
797 */
798 uint8_t data[0];
799};
800
801/*
802 * END iwl-fw-file.h
803 */
804
805/*
806 * BEGIN iwl-prph.h
807 */
808
809/*
810 * Registers in this file are internal, not PCI bus memory mapped.
811 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
812 */
813#define IWM_PRPH_BASE (0x00000)
814#define IWM_PRPH_END (0xFFFFF)
815
816/* APMG (power management) constants */
817#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
818#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
819#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
820#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
821#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
822#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
823#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
824#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
825#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
826#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
827#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
828
829#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
830#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
831#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
832
833#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
834#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
835#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
836#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
837#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
838#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
839#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
840
841#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
842
843#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
844
845/* Device system time */
846#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
847
848/* Device NMI register */
849#define IWM_DEVICE_SET_NMI_REG 0x00a01c30
850
851/*****************************************************************************
852 * 7000/3000 series SHR DTS addresses *
853 *****************************************************************************/
854
855#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
856#define IWM_DTSC_CFG_MODE (0x00a10604)
857#define IWM_DTSC_VREF_AVG (0x00a10648)
858#define IWM_DTSC_VREF5_AVG (0x00a1064c)
859#define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
860#define IWM_DTSC_PTAT_AVG (0x00a10650)
861
862
863/**
864 * Tx Scheduler
865 *
866 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
867 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
868 * host DRAM. It steers each frame's Tx command (which contains the frame
869 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
870 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
871 * but one DMA channel may take input from several queues.
872 *
873 * Tx DMA FIFOs have dedicated purposes.
874 *
875 * For 5000 series and up, they are used differently
876 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
877 *
878 * 0 -- EDCA BK (background) frames, lowest priority
879 * 1 -- EDCA BE (best effort) frames, normal priority
880 * 2 -- EDCA VI (video) frames, higher priority
881 * 3 -- EDCA VO (voice) and management frames, highest priority
882 * 4 -- unused
883 * 5 -- unused
884 * 6 -- unused
885 * 7 -- Commands
886 *
887 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
888 * In addition, driver can map the remaining queues to Tx DMA/FIFO
889 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
890 *
891 * The driver sets up each queue to work in one of two modes:
892 *
893 * 1) Scheduler-Ack, in which the scheduler automatically supports a
894 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
895 * contains TFDs for a unique combination of Recipient Address (RA)
896 * and Traffic Identifier (TID), that is, traffic of a given
897 * Quality-Of-Service (QOS) priority, destined for a single station.
898 *
899 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
900 * each frame within the BA window, including whether it's been transmitted,
901 * and whether it's been acknowledged by the receiving station. The device
902 * automatically processes block-acks received from the receiving STA,
903 * and reschedules un-acked frames to be retransmitted (successful
904 * Tx completion may end up being out-of-order).
905 *
906 * The driver must maintain the queue's Byte Count table in host DRAM
907 * for this mode.
908 * This mode does not support fragmentation.
909 *
910 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
911 * The device may automatically retry Tx, but will retry only one frame
912 * at a time, until receiving ACK from receiving station, or reaching
913 * retry limit and giving up.
914 *
915 * The command queue (#4/#9) must use this mode!
916 * This mode does not require use of the Byte Count table in host DRAM.
917 *
918 * Driver controls scheduler operation via 3 means:
919 * 1) Scheduler registers
920 * 2) Shared scheduler data base in internal SRAM
921 * 3) Shared data in host DRAM
922 *
923 * Initialization:
924 *
925 * When loading, driver should allocate memory for:
926 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
927 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
928 * (1024 bytes for each queue).
929 *
930 * After receiving "Alive" response from uCode, driver must initialize
931 * the scheduler (especially for queue #4/#9, the command queue, otherwise
932 * the driver can't issue commands!):
933 */
934#define IWM_SCD_MEM_LOWER_BOUND (0x0000)
935
936/**
937 * Max Tx window size is the max number of contiguous TFDs that the scheduler
938 * can keep track of at one time when creating block-ack chains of frames.
939 * Note that "64" matches the number of ack bits in a block-ack packet.
940 */
941#define IWM_SCD_WIN_SIZE 64
942#define IWM_SCD_FRAME_LIMIT 64
943
944#define IWM_SCD_TXFIFO_POS_TID (0)
945#define IWM_SCD_TXFIFO_POS_RA (4)
946#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
947
948/* agn SCD */
949#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
950#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
951#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
952#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
953#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
954
955#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
956#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
957#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
958#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
959#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
960#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
961#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
962#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
963
964/* Context Data */
965#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
966#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
967
968/* Tx status */
969#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
970#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
971
972/* Translation Data */
973#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
974#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
975
976#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
977 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
978
979#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
980 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
981
982#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
983 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
984
985#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
986
987#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
988#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
989#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
990#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
991#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
992#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
993#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
994#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
995#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
996
997static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
998{
999 if (chnl < 20)
1000 return IWM_SCD_BASE + 0x18 + chnl * 4;
1001 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1002}
1003
1004static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1005{
1006 if (chnl < 20)
1007 return IWM_SCD_BASE + 0x68 + chnl * 4;
1008 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1009}
1010
1011static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1012{
1013 if (chnl < 20)
1014 return IWM_SCD_BASE + 0x10c + chnl * 4;
1015 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1016}
1017
1018/*********************** END TX SCHEDULER *************************************/
1019
1020/* Oscillator clock */
1021#define IWM_OSC_CLK (0xa04068)
1022#define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1023
1024/*
1025 * END iwl-prph.h
1026 */
1027
1028/*
1029 * BEGIN iwl-fh.h
1030 */
1031
1032/****************************/
1033/* Flow Handler Definitions */
1034/****************************/
1035
1036/**
1037 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1038 * Addresses are offsets from device's PCI hardware base address.
1039 */
1040#define IWM_FH_MEM_LOWER_BOUND (0x1000)
1041#define IWM_FH_MEM_UPPER_BOUND (0x2000)
1042
1043/**
1044 * Keep-Warm (KW) buffer base address.
1045 *
1046 * Driver must allocate a 4KByte buffer that is for keeping the
1047 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1048 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1049 * from going into a power-savings mode that would cause higher DRAM latency,
1050 * and possible data over/under-runs, before all Tx/Rx is complete.
1051 *
1052 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1053 * of the buffer, which must be 4K aligned. Once this is set up, the device
1054 * automatically invokes keep-warm accesses when normal accesses might not
1055 * be sufficient to maintain fast DRAM response.
1056 *
1057 * Bit fields:
1058 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1059 */
1060#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1061
1062
1063/**
1064 * TFD Circular Buffers Base (CBBC) addresses
1065 *
1066 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1067 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1068 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1069 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1070 * aligned (address bits 0-7 must be 0).
1071 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1072 * for them are in different places.
1073 *
1074 * Bit fields in each pointer register:
1075 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1076 */
1077#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1078#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1079#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1080#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1081#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1082#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1083
1084/* Find TFD CB base pointer for given queue */
1085static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1086{
1087 if (chnl < 16)
1088 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1089 if (chnl < 20)
1090 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1091 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1092}
1093
1094
1095/**
1096 * Rx SRAM Control and Status Registers (RSCSR)
1097 *
1098 * These registers provide handshake between driver and device for the Rx queue
1099 * (this queue handles *all* command responses, notifications, Rx data, etc.
1100 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1101 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1102 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1103 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1104 * mapping between RBDs and RBs.
1105 *
1106 * Driver must allocate host DRAM memory for the following, and set the
1107 * physical address of each into device registers:
1108 *
1109 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1110 * entries (although any power of 2, up to 4096, is selectable by driver).
1111 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1112 * (typically 4K, although 8K or 16K are also selectable by driver).
1113 * Driver sets up RB size and number of RBDs in the CB via Rx config
1114 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1115 *
1116 * Bit fields within one RBD:
1117 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1118 *
1119 * Driver sets physical address [35:8] of base of RBD circular buffer
1120 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1121 *
1122 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1123 * (RBs) have been filled, via a "write pointer", actually the index of
1124 * the RB's corresponding RBD within the circular buffer. Driver sets
1125 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1126 *
1127 * Bit fields in lower dword of Rx status buffer (upper dword not used
1128 * by driver:
1129 * 31-12: Not used by driver
1130 * 11- 0: Index of last filled Rx buffer descriptor
1131 * (device writes, driver reads this value)
1132 *
1133 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1134 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1135 * and update the device's "write" index register,
1136 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1137 *
1138 * This "write" index corresponds to the *next* RBD that the driver will make
1139 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1140 * the circular buffer. This value should initially be 0 (before preparing any
1141 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1142 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1143 * "read" index has advanced past 1! See below).
1144 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1145 *
1146 * As the device fills RBs (referenced from contiguous RBDs within the circular
1147 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1148 * to tell the driver the index of the latest filled RBD. The driver must
1149 * read this "read" index from DRAM after receiving an Rx interrupt from device
1150 *
1151 * The driver must also internally keep track of a third index, which is the
1152 * next RBD to process. When receiving an Rx interrupt, driver should process
1153 * all filled but unprocessed RBs up to, but not including, the RB
1154 * corresponding to the "read" index. For example, if "read" index becomes "1",
1155 * driver may process the RB pointed to by RBD 0. Depending on volume of
1156 * traffic, there may be many RBs to process.
1157 *
1158 * If read index == write index, device thinks there is no room to put new data.
1159 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1160 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1161 * and "read" indexes; that is, make sure that there are no more than 254
1162 * buffers waiting to be filled.
1163 */
1164#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1165#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1166#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1167
1168/**
1169 * Physical base address of 8-byte Rx Status buffer.
1170 * Bit fields:
1171 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1172 */
1173#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1174
1175/**
1176 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1177 * Bit fields:
1178 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1179 */
1180#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1181
1182/**
1183 * Rx write pointer (index, really!).
1184 * Bit fields:
1185 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1186 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1187 */
1188#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1189#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1190
1191#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1192#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1193
1194/**
1195 * Rx Config/Status Registers (RCSR)
1196 * Rx Config Reg for channel 0 (only channel used)
1197 *
1198 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1199 * normal operation (see bit fields).
1200 *
1201 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1202 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1203 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1204 *
1205 * Bit fields:
1206 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1207 * '10' operate normally
1208 * 29-24: reserved
1209 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1210 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1211 * 19-18: reserved
1212 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1213 * '10' 12K, '11' 16K.
1214 * 15-14: reserved
1215 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1216 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1217 * typical value 0x10 (about 1/2 msec)
1218 * 3- 0: reserved
1219 */
1220#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1221#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1222#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1223
1224#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1225#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1226#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1227
1228#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1229#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1230#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1231#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1232#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1233#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1234
1235#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1236#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1237#define IWM_RX_RB_TIMEOUT (0x11)
1238
1239#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1240#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1241#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1242
1243#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1244#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1245#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1246#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1247
1248#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1249#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1250#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1251
1252/**
1253 * Rx Shared Status Registers (RSSR)
1254 *
1255 * After stopping Rx DMA channel (writing 0 to
1256 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1257 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1258 *
1259 * Bit fields:
1260 * 24: 1 = Channel 0 is idle
1261 *
1262 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1263 * contain default values that should not be altered by the driver.
1264 */
1265#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1266#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1267
1268#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1269#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1270#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1271 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1272
1273#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1274
1275#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1276
1277/* TFDB Area - TFDs buffer table */
1278#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1279#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1280#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1281#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1282#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1283
1284/**
1285 * Transmit DMA Channel Control/Status Registers (TCSR)
1286 *
1287 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1288 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1289 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1290 *
1291 * To use a Tx DMA channel, driver must initialize its
1292 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1293 *
1294 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1295 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1296 *
1297 * All other bits should be 0.
1298 *
1299 * Bit fields:
1300 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1301 * '10' operate normally
1302 * 29- 4: Reserved, set to "0"
1303 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1304 * 2- 0: Reserved, set to "0"
1305 */
1306#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1307#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1308
1309/* Find Control/Status reg for given Tx DMA/FIFO channel */
1310#define IWM_FH_TCSR_CHNL_NUM (8)
1311
1312/* TCSR: tx_config register values */
1313#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1314 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1315#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1316 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1317#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1318 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1319
1320#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1321#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1322
1323#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1324#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1325
1326#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1327#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1328#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1329
1330#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1331#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1332#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1333
1334#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1335#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1336#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1337
1338#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1339#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1340#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1341
1342#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1343#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1344
1345/**
1346 * Tx Shared Status Registers (TSSR)
1347 *
1348 * After stopping Tx DMA channel (writing 0 to
1349 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1350 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1351 * (channel's buffers empty | no pending requests).
1352 *
1353 * Bit fields:
1354 * 31-24: 1 = Channel buffers empty (channel 7:0)
1355 * 23-16: 1 = No pending requests (channel 7:0)
1356 */
1357#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1358#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1359
1360#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1361
1362/**
1363 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1364 * 31: Indicates an address error when accessed to internal memory
1365 * uCode/driver must write "1" in order to clear this flag
1366 * 30: Indicates that Host did not send the expected number of dwords to FH
1367 * uCode/driver must write "1" in order to clear this flag
1368 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1369 * command was received from the scheduler while the TRB was already full
1370 * with previous command
1371 * uCode/driver must write "1" in order to clear this flag
1372 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1373 * bit is set, it indicates that the FH has received a full indication
1374 * from the RTC TxFIFO and the current value of the TxCredit counter was
1375 * not equal to zero. This mean that the credit mechanism was not
1376 * synchronized to the TxFIFO status
1377 * uCode/driver must write "1" in order to clear this flag
1378 */
1379#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1380#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1381
1382#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1383
1384/* Tx service channels */
1385#define IWM_FH_SRVC_CHNL (9)
1386#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1387#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1388#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1389 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1390
1391#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1392#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1393 (_chan) * 4)
1394
1395/* Instruct FH to increment the retry count of a packet when
1396 * it is brought from the memory to TX-FIFO
1397 */
1398#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1399
1400#define IWM_RX_QUEUE_SIZE 256
1401#define IWM_RX_QUEUE_MASK 255
1402#define IWM_RX_QUEUE_SIZE_LOG 8
1403
1404/*
1405 * RX related structures and functions
1406 */
1407#define IWM_RX_FREE_BUFFERS 64
1408#define IWM_RX_LOW_WATERMARK 8
1409
1410/**
1411 * struct iwm_rb_status - reseve buffer status
1412 * host memory mapped FH registers
1413 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1414 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1415 * @finished_rb_num [0:11] - Indicates the index of the current RB
1416 * in which the last frame was written to
1417 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1418 * which was transferred
1419 */
1420struct iwm_rb_status {
1421 uint16_t closed_rb_num;
1422 uint16_t closed_fr_num;
1423 uint16_t finished_rb_num;
1424 uint16_t finished_fr_nam;
1425 uint32_t unused;
1426} __packed;
1427
1428
1429#define IWM_TFD_QUEUE_SIZE_MAX (256)
1430#define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1431#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1432 IWM_TFD_QUEUE_SIZE_BC_DUP)
1433#define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1434#define IWM_NUM_OF_TBS 20
1435
1436static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1437{
1438 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1439}
1440/**
1441 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1442 *
1443 * This structure contains dma address and length of transmission address
1444 *
1445 * @lo: low [31:0] portion of the dma address of TX buffer
1446 * every even is unaligned on 16 bit boundary
1447 * @hi_n_len 0-3 [35:32] portion of dma
1448 * 4-15 length of the tx buffer
1449 */
1450struct iwm_tfd_tb {
1451 uint32_t lo;
1452 uint16_t hi_n_len;
1453} __packed;
1454
1455/**
1456 * struct iwm_tfd
1457 *
1458 * Transmit Frame Descriptor (TFD)
1459 *
1460 * @ __reserved1[3] reserved
1461 * @ num_tbs 0-4 number of active tbs
1462 * 5 reserved
1463 * 6-7 padding (not used)
1464 * @ tbs[20] transmit frame buffer descriptors
1465 * @ __pad padding
1466 *
1467 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1468 * Both driver and device share these circular buffers, each of which must be
1469 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1470 *
1471 * Driver must indicate the physical address of the base of each
1472 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1473 *
1474 * Each TFD contains pointer/size information for up to 20 data buffers
1475 * in host DRAM. These buffers collectively contain the (one) frame described
1476 * by the TFD. Each buffer must be a single contiguous block of memory within
1477 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1478 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1479 * Tx frame, up to 8 KBytes in size.
1480 *
1481 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1482 */
1483struct iwm_tfd {
1484 uint8_t __reserved1[3];
1485 uint8_t num_tbs;
1486 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1487 uint32_t __pad;
1488} __packed;
1489
1490/* Keep Warm Size */
1491#define IWM_KW_SIZE 0x1000 /* 4k */
1492
1493/* Fixed (non-configurable) rx data from phy */
1494
1495/**
1496 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1497 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1498 * @tfd_offset 0-12 - tx command byte count
1499 * 12-16 - station index
1500 */
1501struct iwm_agn_scd_bc_tbl {
1502 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1503} __packed;
1504
1505/*
1506 * END iwl-fh.h
1507 */
1508
1509/*
1510 * BEGIN mvm/fw-api.h
1511 */
1512
1513/* maximal number of Tx queues in any platform */
1514#define IWM_MVM_MAX_QUEUES 20
1515
1516/* Tx queue numbers */
1517enum {
1518 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1519 IWM_MVM_CMD_QUEUE = 9,
1520};
1521
1522#define IWM_MVM_CMD_FIFO 7
1523
1524#define IWM_MVM_STATION_COUNT 16
1525
1526/* commands */
1527enum {
1528 IWM_MVM_ALIVE = 0x1,
1529 IWM_REPLY_ERROR = 0x2,
1530
1531 IWM_INIT_COMPLETE_NOTIF = 0x4,
1532
1533 /* PHY context commands */
1534 IWM_PHY_CONTEXT_CMD = 0x8,
1535 IWM_DBG_CFG = 0x9,
1536
1537 /* station table */
1538 IWM_ADD_STA_KEY = 0x17,
1539 IWM_ADD_STA = 0x18,
1540 IWM_REMOVE_STA = 0x19,
1541
1542 /* TX */
1543 IWM_TX_CMD = 0x1c,
1544 IWM_TXPATH_FLUSH = 0x1e,
1545 IWM_MGMT_MCAST_KEY = 0x1f,
1546
1547 /* global key */
1548 IWM_WEP_KEY = 0x20,
1549
1550 /* MAC and Binding commands */
1551 IWM_MAC_CONTEXT_CMD = 0x28,
1552 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1553 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1554 IWM_BINDING_CONTEXT_CMD = 0x2b,
1555 IWM_TIME_QUOTA_CMD = 0x2c,
1556 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1557
1558 IWM_LQ_CMD = 0x4e,
1559
1560 /* Calibration */
1561 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1562 IWM_CALIBRATION_CFG_CMD = 0x65,
1563 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1564 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1565 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1566
1567 /* Scan offload */
1568 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1569 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1570 IWM_SCAN_OFFLOAD_COMPLETE = 0x6D,
1571 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
1572 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1573 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1574
1575 /* Phy */
1576 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1577 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1578 /* IWM_PHY_DB_CMD = 0x6c, */
1579
1580 /* Power - legacy power table command */
1581 IWM_POWER_TABLE_CMD = 0x77,
1582 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1583
1584 /* Thermal Throttling*/
1585 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1586
1587 /* Scanning */
1588 IWM_SCAN_REQUEST_CMD = 0x80,
1589 IWM_SCAN_ABORT_CMD = 0x81,
1590 IWM_SCAN_START_NOTIFICATION = 0x82,
1591 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1592 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84,
1593
1594 /* NVM */
1595 IWM_NVM_ACCESS_CMD = 0x88,
1596
1597 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1598
1599 IWM_BEACON_NOTIFICATION = 0x90,
1600 IWM_BEACON_TEMPLATE_CMD = 0x91,
1601 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1602 IWM_BT_CONFIG = 0x9b,
1603 IWM_STATISTICS_NOTIFICATION = 0x9d,
1604 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1605
1606 /* RF-KILL commands and notifications */
1607 IWM_CARD_STATE_CMD = 0xa0,
1608 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1609
1610 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1611
1612 /* Power - new power table command */
1613 IWM_MAC_PM_POWER_TABLE = 0xa9,
1614
1615 IWM_REPLY_RX_PHY_CMD = 0xc0,
1616 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1617 IWM_BA_NOTIF = 0xc5,
1618
1619 /* BT Coex */
1620 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1621 IWM_BT_COEX_PROT_ENV = 0xcd,
1622 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1623 IWM_BT_COEX_CI = 0x5d,
1624
1625 IWM_REPLY_SF_CFG_CMD = 0xd1,
1626 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1627
1628 IWM_REPLY_DEBUG_CMD = 0xf0,
1629 IWM_DEBUG_LOG_MSG = 0xf7,
1630
1631 IWM_MCAST_FILTER_CMD = 0xd0,
1632
1633 /* D3 commands/notifications */
1634 IWM_D3_CONFIG_CMD = 0xd3,
1635 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1636 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1637 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1638
1639 /* for WoWLAN in particular */
1640 IWM_WOWLAN_PATTERNS = 0xe0,
1641 IWM_WOWLAN_CONFIGURATION = 0xe1,
1642 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1643 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1644 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1645 IWM_WOWLAN_GET_STATUSES = 0xe5,
1646 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1647
1648 /* and for NetDetect */
1649 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1650 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1651 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1652 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1653 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1654
1655 IWM_REPLY_MAX = 0xff,
1656};
1657
1658/**
1659 * struct iwm_cmd_response - generic response struct for most commands
1660 * @status: status of the command asked, changes for each one
1661 */
1662struct iwm_cmd_response {
1663 uint32_t status;
1664};
1665
1666/*
1667 * struct iwm_tx_ant_cfg_cmd
1668 * @valid: valid antenna configuration
1669 */
1670struct iwm_tx_ant_cfg_cmd {
1671 uint32_t valid;
1672} __packed;
1673
1674/**
1675 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1676 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1677 * @flags: (reserved for future implementation)
1678 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1679 * @pwr_restriction: TX power restriction in dBms.
1680 */
1681struct iwm_reduce_tx_power_cmd {
1682 uint8_t flags;
1683 uint8_t mac_context_id;
1684 uint16_t pwr_restriction;
1685} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1686
1687/*
1688 * Calibration control struct.
1689 * Sent as part of the phy configuration command.
1690 * @flow_trigger: bitmap for which calibrations to perform according to
1691 * flow triggers.
1692 * @event_trigger: bitmap for which calibrations to perform according to
1693 * event triggers.
1694 */
1695struct iwm_calib_ctrl {
1696 uint32_t flow_trigger;
1697 uint32_t event_trigger;
1698} __packed;
1699
1700/* This enum defines the bitmap of various calibrations to enable in both
1701 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1702 */
1703enum iwm_calib_cfg {
1704 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1705 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1706 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1707 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1708 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1709 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1710 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1711 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1712 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1713 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1714 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1715 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1716 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1717 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1718 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1719 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1720 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1721 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1722 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1723};
1724
1725/*
1726 * Phy configuration command.
1727 */
1728struct iwm_phy_cfg_cmd {
1729 uint32_t phy_cfg;
1730 struct iwm_calib_ctrl calib_control;
1731} __packed;
1732
1733#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1734#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1735#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1736#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1737#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1738#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1739#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1740#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1741#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1742#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1743
1744
1745/* Target of the IWM_NVM_ACCESS_CMD */
1746enum {
1747 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1748 IWM_NVM_ACCESS_TARGET_OTP = 1,
1749 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1750};
1751
1752/* Section types for IWM_NVM_ACCESS_CMD */
1753enum {
1754 IWM_NVM_SECTION_TYPE_HW = 0,
1755 IWM_NVM_SECTION_TYPE_SW,
1756 IWM_NVM_SECTION_TYPE_PAPD,
1757 IWM_NVM_SECTION_TYPE_BT,
1758 IWM_NVM_SECTION_TYPE_CALIBRATION,
1759 IWM_NVM_SECTION_TYPE_PRODUCTION,
1760 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB,
1761 IWM_NVM_NUM_OF_SECTIONS,
1762};
1763
1764/**
1765 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1766 * @op_code: 0 - read, 1 - write
1767 * @target: IWM_NVM_ACCESS_TARGET_*
1768 * @type: IWM_NVM_SECTION_TYPE_*
1769 * @offset: offset in bytes into the section
1770 * @length: in bytes, to read/write
1771 * @data: if write operation, the data to write. On read its empty
1772 */
1773struct iwm_nvm_access_cmd {
1774 uint8_t op_code;
1775 uint8_t target;
1776 uint16_t type;
1777 uint16_t offset;
1778 uint16_t length;
1779 uint8_t data[];
1780} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
1781
1782/**
1783 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
1784 * @offset: offset in bytes into the section
1785 * @length: in bytes, either how much was written or read
1786 * @type: IWM_NVM_SECTION_TYPE_*
1787 * @status: 0 for success, fail otherwise
1788 * @data: if read operation, the data returned. Empty on write.
1789 */
1790struct iwm_nvm_access_resp {
1791 uint16_t offset;
1792 uint16_t length;
1793 uint16_t type;
1794 uint16_t status;
1795 uint8_t data[];
1796} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
1797
1798/* IWM_MVM_ALIVE 0x1 */
1799
1800/* alive response is_valid values */
1801#define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
1802#define IWM_ALIVE_RESP_RFKILL (1 << 1)
1803
1804/* alive response ver_type values */
1805enum {
1806 IWM_FW_TYPE_HW = 0,
1807 IWM_FW_TYPE_PROT = 1,
1808 IWM_FW_TYPE_AP = 2,
1809 IWM_FW_TYPE_WOWLAN = 3,
1810 IWM_FW_TYPE_TIMING = 4,
1811 IWM_FW_TYPE_WIPAN = 5
1812};
1813
1814/* alive response ver_subtype values */
1815enum {
1816 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
1817 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
1818 IWM_FW_SUBTYPE_REDUCED = 2,
1819 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
1820 IWM_FW_SUBTYPE_WOWLAN = 4,
1821 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
1822 IWM_FW_SUBTYPE_WIPAN = 6,
1823 IWM_FW_SUBTYPE_INITIALIZE = 9
1824};
1825
1826#define IWM_ALIVE_STATUS_ERR 0xDEAD
1827#define IWM_ALIVE_STATUS_OK 0xCAFE
1828
1829#define IWM_ALIVE_FLG_RFKILL (1 << 0)
1830
1831struct iwm_mvm_alive_resp {
1832 uint16_t status;
1833 uint16_t flags;
1834 uint8_t ucode_minor;
1835 uint8_t ucode_major;
1836 uint16_t id;
1837 uint8_t api_minor;
1838 uint8_t api_major;
1839 uint8_t ver_subtype;
1840 uint8_t ver_type;
1841 uint8_t mac;
1842 uint8_t opt;
1843 uint16_t reserved2;
1844 uint32_t timestamp;
1845 uint32_t error_event_table_ptr; /* SRAM address for error log */
1846 uint32_t log_event_table_ptr; /* SRAM address for event log */
1847 uint32_t cpu_register_ptr;
1848 uint32_t dbgm_config_ptr;
1849 uint32_t alive_counter_ptr;
1850 uint32_t scd_base_ptr; /* SRAM address for SCD */
1851} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
1852
1853/* Error response/notification */
1854enum {
1855 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
1856 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
1857 IWM_FW_ERR_SERVICE = 0x2,
1858 IWM_FW_ERR_ARC_MEMORY = 0x3,
1859 IWM_FW_ERR_ARC_CODE = 0x4,
1860 IWM_FW_ERR_WATCH_DOG = 0x5,
1861 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
1862 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
1863 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
1864 IWM_FW_ERR_UNEXPECTED = 0xFE,
1865 IWM_FW_ERR_FATAL = 0xFF
1866};
1867
1868/**
1869 * struct iwm_error_resp - FW error indication
1870 * ( IWM_REPLY_ERROR = 0x2 )
1871 * @error_type: one of IWM_FW_ERR_*
1872 * @cmd_id: the command ID for which the error occurred
1873 * @bad_cmd_seq_num: sequence number of the erroneous command
1874 * @error_service: which service created the error, applicable only if
1875 * error_type = 2, otherwise 0
1876 * @timestamp: TSF in usecs.
1877 */
1878struct iwm_error_resp {
1879 uint32_t error_type;
1880 uint8_t cmd_id;
1881 uint8_t reserved1;
1882 uint16_t bad_cmd_seq_num;
1883 uint32_t error_service;
1884 uint64_t timestamp;
1885} __packed;
1886
1887
1888/* Common PHY, MAC and Bindings definitions */
1889
1890#define IWM_MAX_MACS_IN_BINDING (3)
1891#define IWM_MAX_BINDINGS (4)
1892#define IWM_AUX_BINDING_INDEX (3)
1893#define IWM_MAX_PHYS (4)
1894
1895/* Used to extract ID and color from the context dword */
1896#define IWM_FW_CTXT_ID_POS (0)
1897#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
1898#define IWM_FW_CTXT_COLOR_POS (8)
1899#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
1900#define IWM_FW_CTXT_INVALID (0xffffffff)
1901
1902#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
1903 (_color << IWM_FW_CTXT_COLOR_POS))
1904
1905/* Possible actions on PHYs, MACs and Bindings */
1906enum {
1907 IWM_FW_CTXT_ACTION_STUB = 0,
1908 IWM_FW_CTXT_ACTION_ADD,
1909 IWM_FW_CTXT_ACTION_MODIFY,
1910 IWM_FW_CTXT_ACTION_REMOVE,
1911 IWM_FW_CTXT_ACTION_NUM
1912}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
1913
1914/* Time Events */
1915
1916/* Time Event types, according to MAC type */
1917enum iwm_time_event_type {
1918 /* BSS Station Events */
1919 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
1920 IWM_TE_BSS_STA_ASSOC,
1921 IWM_TE_BSS_EAP_DHCP_PROT,
1922 IWM_TE_BSS_QUIET_PERIOD,
1923
1924 /* P2P Device Events */
1925 IWM_TE_P2P_DEVICE_DISCOVERABLE,
1926 IWM_TE_P2P_DEVICE_LISTEN,
1927 IWM_TE_P2P_DEVICE_ACTION_SCAN,
1928 IWM_TE_P2P_DEVICE_FULL_SCAN,
1929
1930 /* P2P Client Events */
1931 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
1932 IWM_TE_P2P_CLIENT_ASSOC,
1933 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
1934
1935 /* P2P GO Events */
1936 IWM_TE_P2P_GO_ASSOC_PROT,
1937 IWM_TE_P2P_GO_REPETITIVE_NOA,
1938 IWM_TE_P2P_GO_CT_WINDOW,
1939
1940 /* WiDi Sync Events */
1941 IWM_TE_WIDI_TX_SYNC,
1942
1943 IWM_TE_MAX
1944}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
1945
1946
1947
1948/* Time event - defines for command API v1 */
1949
1950/*
1951 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
1952 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
1953 * the first fragment is scheduled.
1954 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
1955 * the first 2 fragments are scheduled.
1956 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
1957 * number of fragments are valid.
1958 *
1959 * Other than the constant defined above, specifying a fragmentation value 'x'
1960 * means that the event can be fragmented but only the first 'x' will be
1961 * scheduled.
1962 */
1963enum {
1964 IWM_TE_V1_FRAG_NONE = 0,
1965 IWM_TE_V1_FRAG_SINGLE = 1,
1966 IWM_TE_V1_FRAG_DUAL = 2,
1967 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
1968};
1969
1970/* If a Time Event can be fragmented, this is the max number of fragments */
1971#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
1972/* Repeat the time event endlessly (until removed) */
1973#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
1974/* If a Time Event has bounded repetitions, this is the maximal value */
1975#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
1976
1977/* Time Event dependencies: none, on another TE, or in a specific time */
1978enum {
1979 IWM_TE_V1_INDEPENDENT = 0,
1980 IWM_TE_V1_DEP_OTHER = (1 << 0),
1981 IWM_TE_V1_DEP_TSF = (1 << 1),
1982 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
1983}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
1984
1985/*
1986 * @IWM_TE_V1_NOTIF_NONE: no notifications
1987 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
1988 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
1989 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
1990 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
1991 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
1992 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
1993 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
1994 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
1995 *
1996 * Supported Time event notifications configuration.
1997 * A notification (both event and fragment) includes a status indicating weather
1998 * the FW was able to schedule the event or not. For fragment start/end
1999 * notification the status is always success. There is no start/end fragment
2000 * notification for monolithic events.
2001 */
2002enum {
2003 IWM_TE_V1_NOTIF_NONE = 0,
2004 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2005 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2006 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2007 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2008 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2009 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2010 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2011 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2012}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2013
2014
2015/**
2016 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2017 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2018 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2019 * ( IWM_TIME_EVENT_CMD = 0x29 )
2020 * @id_and_color: ID and color of the relevant MAC
2021 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2022 * @id: this field has two meanings, depending on the action:
2023 * If the action is ADD, then it means the type of event to add.
2024 * For all other actions it is the unique event ID assigned when the
2025 * event was added by the FW.
2026 * @apply_time: When to start the Time Event (in GP2)
2027 * @max_delay: maximum delay to event's start (apply time), in TU
2028 * @depends_on: the unique ID of the event we depend on (if any)
2029 * @interval: interval between repetitions, in TU
2030 * @interval_reciprocal: 2^32 / interval
2031 * @duration: duration of event in TU
2032 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2033 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2034 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2035 * @is_present: 0 or 1, are we present or absent during the Time Event
2036 * @max_frags: maximal number of fragments the Time Event can be divided to
2037 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2038 */
2039struct iwm_time_event_cmd_v1 {
2040 /* COMMON_INDEX_HDR_API_S_VER_1 */
2041 uint32_t id_and_color;
2042 uint32_t action;
2043 uint32_t id;
2044 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2045 uint32_t apply_time;
2046 uint32_t max_delay;
2047 uint32_t dep_policy;
2048 uint32_t depends_on;
2049 uint32_t is_present;
2050 uint32_t max_frags;
2051 uint32_t interval;
2052 uint32_t interval_reciprocal;
2053 uint32_t duration;
2054 uint32_t repeat;
2055 uint32_t notify;
2056} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2057
2058
2059/* Time event - defines for command API v2 */
2060
2061/*
2062 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2063 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2064 * the first fragment is scheduled.
2065 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2066 * the first 2 fragments are scheduled.
2067 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2068 * number of fragments are valid.
2069 *
2070 * Other than the constant defined above, specifying a fragmentation value 'x'
2071 * means that the event can be fragmented but only the first 'x' will be
2072 * scheduled.
2073 */
2074enum {
2075 IWM_TE_V2_FRAG_NONE = 0,
2076 IWM_TE_V2_FRAG_SINGLE = 1,
2077 IWM_TE_V2_FRAG_DUAL = 2,
2078 IWM_TE_V2_FRAG_MAX = 0xfe,
2079 IWM_TE_V2_FRAG_ENDLESS = 0xff
2080};
2081
2082/* Repeat the time event endlessly (until removed) */
2083#define IWM_TE_V2_REPEAT_ENDLESS 0xff
2084/* If a Time Event has bounded repetitions, this is the maximal value */
2085#define IWM_TE_V2_REPEAT_MAX 0xfe
2086
2087#define IWM_TE_V2_PLACEMENT_POS 12
2088#define IWM_TE_V2_ABSENCE_POS 15
2089
2090/* Time event policy values (for time event cmd api v2)
2091 * A notification (both event and fragment) includes a status indicating weather
2092 * the FW was able to schedule the event or not. For fragment start/end
2093 * notification the status is always success. There is no start/end fragment
2094 * notification for monolithic events.
2095 *
2096 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2097 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2098 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2099 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2100 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2101 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2102 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2103 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2104 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2105 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2106 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2107 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2108 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2109 */
2110enum {
2111 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2112
2113 /* notifications (event start/stop, fragment start/stop) */
2114 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2115 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2116 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2117 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2118
2119 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2120 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2121 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2122 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2123
2124 IWM_TE_V2_NOTIF_MSK = 0xff,
2125
2126 /* placement characteristics */
2127 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2128 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2129 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2130
2131 /* are we present or absent during the Time Event. */
2132 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2133};
2134
2135/**
2136 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2137 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2138 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2139 * ( IWM_TIME_EVENT_CMD = 0x29 )
2140 * @id_and_color: ID and color of the relevant MAC
2141 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2142 * @id: this field has two meanings, depending on the action:
2143 * If the action is ADD, then it means the type of event to add.
2144 * For all other actions it is the unique event ID assigned when the
2145 * event was added by the FW.
2146 * @apply_time: When to start the Time Event (in GP2)
2147 * @max_delay: maximum delay to event's start (apply time), in TU
2148 * @depends_on: the unique ID of the event we depend on (if any)
2149 * @interval: interval between repetitions, in TU
2150 * @duration: duration of event in TU
2151 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2152 * @max_frags: maximal number of fragments the Time Event can be divided to
2153 * @policy: defines whether uCode shall notify the host or other uCode modules
2154 * on event and/or fragment start and/or end
2155 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2156 * IWM_TE_EVENT_SOCIOPATHIC
2157 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2158 */
2159struct iwm_time_event_cmd_v2 {
2160 /* COMMON_INDEX_HDR_API_S_VER_1 */
2161 uint32_t id_and_color;
2162 uint32_t action;
2163 uint32_t id;
2164 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2165 uint32_t apply_time;
2166 uint32_t max_delay;
2167 uint32_t depends_on;
2168 uint32_t interval;
2169 uint32_t duration;
2170 uint8_t repeat;
2171 uint8_t max_frags;
2172 uint16_t policy;
2173} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2174
2175/**
2176 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2177 * @status: bit 0 indicates success, all others specify errors
2178 * @id: the Time Event type
2179 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2180 * @id_and_color: ID and color of the relevant MAC
2181 */
2182struct iwm_time_event_resp {
2183 uint32_t status;
2184 uint32_t id;
2185 uint32_t unique_id;
2186 uint32_t id_and_color;
2187} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2188
2189/**
2190 * struct iwm_time_event_notif - notifications of time event start/stop
2191 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2192 * @timestamp: action timestamp in GP2
2193 * @session_id: session's unique id
2194 * @unique_id: unique id of the Time Event itself
2195 * @id_and_color: ID and color of the relevant MAC
2196 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2197 * @status: true if scheduled, false otherwise (not executed)
2198 */
2199struct iwm_time_event_notif {
2200 uint32_t timestamp;
2201 uint32_t session_id;
2202 uint32_t unique_id;
2203 uint32_t id_and_color;
2204 uint32_t action;
2205 uint32_t status;
2206} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2207
2208
2209/* Bindings and Time Quota */
2210
2211/**
2212 * struct iwm_binding_cmd - configuring bindings
2213 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2214 * @id_and_color: ID and color of the relevant Binding
2215 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2216 * @macs: array of MAC id and colors which belong to the binding
2217 * @phy: PHY id and color which belongs to the binding
2218 */
2219struct iwm_binding_cmd {
2220 /* COMMON_INDEX_HDR_API_S_VER_1 */
2221 uint32_t id_and_color;
2222 uint32_t action;
2223 /* IWM_BINDING_DATA_API_S_VER_1 */
2224 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2225 uint32_t phy;
2226} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2227
2228/* The maximal number of fragments in the FW's schedule session */
2229#define IWM_MVM_MAX_QUOTA 128
2230
2231/**
2232 * struct iwm_time_quota_data - configuration of time quota per binding
2233 * @id_and_color: ID and color of the relevant Binding
2234 * @quota: absolute time quota in TU. The scheduler will try to divide the
2235 * remainig quota (after Time Events) according to this quota.
2236 * @max_duration: max uninterrupted context duration in TU
2237 */
2238struct iwm_time_quota_data {
2239 uint32_t id_and_color;
2240 uint32_t quota;
2241 uint32_t max_duration;
2242} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2243
2244/**
2245 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2246 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2247 * @quotas: allocations per binding
2248 */
2249struct iwm_time_quota_cmd {
2250 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2251} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2252
2253
2254/* PHY context */
2255
2256/* Supported bands */
2257#define IWM_PHY_BAND_5 (0)
2258#define IWM_PHY_BAND_24 (1)
2259
2260/* Supported channel width, vary if there is VHT support */
2261#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2262#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2263#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2264#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2265
2266/*
2267 * Control channel position:
2268 * For legacy set bit means upper channel, otherwise lower.
2269 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2270 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2271 * center_freq
2272 * |
2273 * 40Mhz |_______|_______|
2274 * 80Mhz |_______|_______|_______|_______|
2275 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2276 * code 011 010 001 000 | 100 101 110 111
2277 */
2278#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2279#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2280#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2281#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2282#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2283#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2284#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2285#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2286
2287/*
2288 * @band: IWM_PHY_BAND_*
2289 * @channel: channel number
2290 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2291 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2292 */
2293struct iwm_fw_channel_info {
2294 uint8_t band;
2295 uint8_t channel;
2296 uint8_t width;
2297 uint8_t ctrl_pos;
2298} __packed;
2299
2300#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2301#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2302 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2303#define IWM_PHY_RX_CHAIN_VALID_POS (1)
2304#define IWM_PHY_RX_CHAIN_VALID_MSK \
2305 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2306#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2307#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2308 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2309#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2310#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2311 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2312#define IWM_PHY_RX_CHAIN_CNT_POS (10)
2313#define IWM_PHY_RX_CHAIN_CNT_MSK \
2314 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2315#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2316#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2317 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2318#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2319#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2320 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2321
2322/* TODO: fix the value, make it depend on firmware at runtime? */
2323#define IWM_NUM_PHY_CTX 3
2324
2325/* TODO: complete missing documentation */
2326/**
2327 * struct iwm_phy_context_cmd - config of the PHY context
2328 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2329 * @id_and_color: ID and color of the relevant Binding
2330 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2331 * @apply_time: 0 means immediate apply and context switch.
2332 * other value means apply new params after X usecs
2333 * @tx_param_color: ???
2334 * @channel_info:
2335 * @txchain_info: ???
2336 * @rxchain_info: ???
2337 * @acquisition_data: ???
2338 * @dsp_cfg_flags: set to 0
2339 */
2340struct iwm_phy_context_cmd {
2341 /* COMMON_INDEX_HDR_API_S_VER_1 */
2342 uint32_t id_and_color;
2343 uint32_t action;
2344 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2345 uint32_t apply_time;
2346 uint32_t tx_param_color;
2347 struct iwm_fw_channel_info ci;
2348 uint32_t txchain_info;
2349 uint32_t rxchain_info;
2350 uint32_t acquisition_data;
2351 uint32_t dsp_cfg_flags;
2352} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2353
2354#define IWM_RX_INFO_PHY_CNT 8
2355#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2356#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2357#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2358#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2359#define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2360#define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2361#define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2362
2363#define IWM_RX_INFO_AGC_IDX 1
2364#define IWM_RX_INFO_RSSI_AB_IDX 2
2365#define IWM_OFDM_AGC_A_MSK 0x0000007f
2366#define IWM_OFDM_AGC_A_POS 0
2367#define IWM_OFDM_AGC_B_MSK 0x00003f80
2368#define IWM_OFDM_AGC_B_POS 7
2369#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2370#define IWM_OFDM_AGC_CODE_POS 20
2371#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2372#define IWM_OFDM_RSSI_A_POS 0
2373#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2374#define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2375#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2376#define IWM_OFDM_RSSI_B_POS 16
2377#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2378#define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2379
2380/**
2381 * struct iwm_rx_phy_info - phy info
2382 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2383 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2384 * @cfg_phy_cnt: configurable DSP phy data byte count
2385 * @stat_id: configurable DSP phy data set ID
2386 * @reserved1:
2387 * @system_timestamp: GP2 at on air rise
2388 * @timestamp: TSF at on air rise
2389 * @beacon_time_stamp: beacon at on-air rise
2390 * @phy_flags: general phy flags: band, modulation, ...
2391 * @channel: channel number
2392 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2393 * @rate_n_flags: IWM_RATE_MCS_*
2394 * @byte_count: frame's byte-count
2395 * @frame_time: frame's time on the air, based on byte count and frame rate
2396 * calculation
2397 * @mac_active_msk: what MACs were active when the frame was received
2398 *
2399 * Before each Rx, the device sends this data. It contains PHY information
2400 * about the reception of the packet.
2401 */
2402struct iwm_rx_phy_info {
2403 uint8_t non_cfg_phy_cnt;
2404 uint8_t cfg_phy_cnt;
2405 uint8_t stat_id;
2406 uint8_t reserved1;
2407 uint32_t system_timestamp;
2408 uint64_t timestamp;
2409 uint32_t beacon_time_stamp;
2410 uint16_t phy_flags;
2411#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2412 uint16_t channel;
2413 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2414 uint8_t rate;
2415 uint8_t rflags;
2416 uint16_t xrflags;
2417 uint32_t byte_count;
2418 uint16_t mac_active_msk;
2419 uint16_t frame_time;
2420} __packed;
2421
2422struct iwm_rx_mpdu_res_start {
2423 uint16_t byte_count;
2424 uint16_t reserved;
2425} __packed;
2426
2427/**
2428 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2429 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2430 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2431 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2432 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2433 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2434 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2435 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2436 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2437 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2438 */
2439enum iwm_rx_phy_flags {
2440 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2441 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2442 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2443 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2444 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2445 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2446 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2447 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2448 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2449 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2450};
2451
2452/**
2453 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2454 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2455 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2456 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2457 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2458 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2459 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2460 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2461 * in the driver.
2462 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2463 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2464 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2465 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2466 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2467 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2468 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2469 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2470 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2471 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2472 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2473 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2474 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2475 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2476 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2477 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2478 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2479 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2480 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2481 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2482 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2483 */
2484enum iwm_mvm_rx_status {
2485 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2486 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2487 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2488 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2489 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2490 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2491 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2492 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2493 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2494 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2495 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2496 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2497 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2498 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2499 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2500 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2501 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2502 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2503 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2504 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2505 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2506 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2507 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2508 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2509 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2510 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2511 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2512};
2513
2514/**
2515 * struct iwm_radio_version_notif - information on the radio version
2516 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2517 * @radio_flavor:
2518 * @radio_step:
2519 * @radio_dash:
2520 */
2521struct iwm_radio_version_notif {
2522 uint32_t radio_flavor;
2523 uint32_t radio_step;
2524 uint32_t radio_dash;
2525} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2526
2527enum iwm_card_state_flags {
2528 IWM_CARD_ENABLED = 0x00,
2529 IWM_HW_CARD_DISABLED = 0x01,
2530 IWM_SW_CARD_DISABLED = 0x02,
2531 IWM_CT_KILL_CARD_DISABLED = 0x04,
2532 IWM_HALT_CARD_DISABLED = 0x08,
2533 IWM_CARD_DISABLED_MSK = 0x0f,
2534 IWM_CARD_IS_RX_ON = 0x10,
2535};
2536
2537/**
2538 * struct iwm_radio_version_notif - information on the radio version
2539 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2540 * @flags: %iwm_card_state_flags
2541 */
2542struct iwm_card_state_notif {
2543 uint32_t flags;
2544} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2545
2546/**
2547 * struct iwm_missed_beacons_notif - information on missed beacons
2548 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2549 * @mac_id: interface ID
2550 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2551 * beacons since last RX.
2552 * @consec_missed_beacons: number of consecutive missed beacons
2553 * @num_expected_beacons:
2554 * @num_recvd_beacons:
2555 */
2556struct iwm_missed_beacons_notif {
2557 uint32_t mac_id;
2558 uint32_t consec_missed_beacons_since_last_rx;
2559 uint32_t consec_missed_beacons;
2560 uint32_t num_expected_beacons;
2561 uint32_t num_recvd_beacons;
2562} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2563
2564/**
2565 * struct iwm_set_calib_default_cmd - set default value for calibration.
2566 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2567 * @calib_index: the calibration to set value for
2568 * @length: of data
2569 * @data: the value to set for the calibration result
2570 */
2571struct iwm_set_calib_default_cmd {
2572 uint16_t calib_index;
2573 uint16_t length;
2574 uint8_t data[0];
2575} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2576
2577#define IWM_MAX_PORT_ID_NUM 2
2578#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2579
2580/**
2581 * struct iwm_mcast_filter_cmd - configure multicast filter.
2582 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2583 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2584 * to identify network interface adopted in host-device IF.
2585 * It is used by FW as index in array of addresses. This array has
2586 * IWM_MAX_PORT_ID_NUM members.
2587 * @count: Number of MAC addresses in the array
2588 * @pass_all: Set 1 to pass all multicast packets.
2589 * @bssid: current association BSSID.
2590 * @addr_list: Place holder for array of MAC addresses.
2591 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2592 */
2593struct iwm_mcast_filter_cmd {
2594 uint8_t filter_own;
2595 uint8_t port_id;
2596 uint8_t count;
2597 uint8_t pass_all;
2598 uint8_t bssid[6];
2599 uint8_t reserved[2];
2600 uint8_t addr_list[0];
2601} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2602
2603struct iwm_mvm_statistics_dbg {
2604 uint32_t burst_check;
2605 uint32_t burst_count;
2606 uint32_t wait_for_silence_timeout_cnt;
2607 uint32_t reserved[3];
2608} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2609
2610struct iwm_mvm_statistics_div {
2611 uint32_t tx_on_a;
2612 uint32_t tx_on_b;
2613 uint32_t exec_time;
2614 uint32_t probe_time;
2615 uint32_t rssi_ant;
2616 uint32_t reserved2;
2617} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2618
2619struct iwm_mvm_statistics_general_common {
2620 uint32_t temperature; /* radio temperature */
2621 uint32_t temperature_m; /* radio voltage */
2622 struct iwm_mvm_statistics_dbg dbg;
2623 uint32_t sleep_time;
2624 uint32_t slots_out;
2625 uint32_t slots_idle;
2626 uint32_t ttl_timestamp;
2627 struct iwm_mvm_statistics_div div;
2628 uint32_t rx_enable_counter;
2629 /*
2630 * num_of_sos_states:
2631 * count the number of times we have to re-tune
2632 * in order to get out of bad PHY status
2633 */
2634 uint32_t num_of_sos_states;
2635} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2636
2637struct iwm_mvm_statistics_rx_non_phy {
2638 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2639 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2640 uint32_t non_bssid_frames; /* number of frames with BSSID that
2641 * doesn't belong to the STA BSSID */
2642 uint32_t filtered_frames; /* count frames that were dumped in the
2643 * filtering process */
2644 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2645 * our serving channel */
2646 uint32_t channel_beacons; /* beacons with our bss id and in our
2647 * serving channel */
2648 uint32_t num_missed_bcon; /* number of missed beacons */
2649 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2650 * ADC was in saturation */
2651 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2652 * for INA */
2653 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2654 uint32_t interference_data_flag; /* flag for interference data
2655 * availability. 1 when data is
2656 * available. */
2657 uint32_t channel_load; /* counts RX Enable time in uSec */
2658 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2659 * and CCK) counter */
2660 uint32_t beacon_rssi_a;
2661 uint32_t beacon_rssi_b;
2662 uint32_t beacon_rssi_c;
2663 uint32_t beacon_energy_a;
2664 uint32_t beacon_energy_b;
2665 uint32_t beacon_energy_c;
2666 uint32_t num_bt_kills;
2667 uint32_t mac_id;
2668 uint32_t directed_data_mpdu;
2669} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2670
2671struct iwm_mvm_statistics_rx_phy {
2672 uint32_t ina_cnt;
2673 uint32_t fina_cnt;
2674 uint32_t plcp_err;
2675 uint32_t crc32_err;
2676 uint32_t overrun_err;
2677 uint32_t early_overrun_err;
2678 uint32_t crc32_good;
2679 uint32_t false_alarm_cnt;
2680 uint32_t fina_sync_err_cnt;
2681 uint32_t sfd_timeout;
2682 uint32_t fina_timeout;
2683 uint32_t unresponded_rts;
2684 uint32_t rxe_frame_limit_overrun;
2685 uint32_t sent_ack_cnt;
2686 uint32_t sent_cts_cnt;
2687 uint32_t sent_ba_rsp_cnt;
2688 uint32_t dsp_self_kill;
2689 uint32_t mh_format_err;
2690 uint32_t re_acq_main_rssi_sum;
2691 uint32_t reserved;
2692} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2693
2694struct iwm_mvm_statistics_rx_ht_phy {
2695 uint32_t plcp_err;
2696 uint32_t overrun_err;
2697 uint32_t early_overrun_err;
2698 uint32_t crc32_good;
2699 uint32_t crc32_err;
2700 uint32_t mh_format_err;
2701 uint32_t agg_crc32_good;
2702 uint32_t agg_mpdu_cnt;
2703 uint32_t agg_cnt;
2704 uint32_t unsupport_mcs;
2705} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
2706
2707#define IWM_MAX_CHAINS 3
2708
2709struct iwm_mvm_statistics_tx_non_phy_agg {
2710 uint32_t ba_timeout;
2711 uint32_t ba_reschedule_frames;
2712 uint32_t scd_query_agg_frame_cnt;
2713 uint32_t scd_query_no_agg;
2714 uint32_t scd_query_agg;
2715 uint32_t scd_query_mismatch;
2716 uint32_t frame_not_ready;
2717 uint32_t underrun;
2718 uint32_t bt_prio_kill;
2719 uint32_t rx_ba_rsp_cnt;
2720 int8_t txpower[IWM_MAX_CHAINS];
2721 int8_t reserved;
2722 uint32_t reserved2;
2723} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
2724
2725struct iwm_mvm_statistics_tx_channel_width {
2726 uint32_t ext_cca_narrow_ch20[1];
2727 uint32_t ext_cca_narrow_ch40[2];
2728 uint32_t ext_cca_narrow_ch80[3];
2729 uint32_t ext_cca_narrow_ch160[4];
2730 uint32_t last_tx_ch_width_indx;
2731 uint32_t rx_detected_per_ch_width[4];
2732 uint32_t success_per_ch_width[4];
2733 uint32_t fail_per_ch_width[4];
2734}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
2735
2736struct iwm_mvm_statistics_tx {
2737 uint32_t preamble_cnt;
2738 uint32_t rx_detected_cnt;
2739 uint32_t bt_prio_defer_cnt;
2740 uint32_t bt_prio_kill_cnt;
2741 uint32_t few_bytes_cnt;
2742 uint32_t cts_timeout;
2743 uint32_t ack_timeout;
2744 uint32_t expected_ack_cnt;
2745 uint32_t actual_ack_cnt;
2746 uint32_t dump_msdu_cnt;
2747 uint32_t burst_abort_next_frame_mismatch_cnt;
2748 uint32_t burst_abort_missing_next_frame_cnt;
2749 uint32_t cts_timeout_collision;
2750 uint32_t ack_or_ba_timeout_collision;
2751 struct iwm_mvm_statistics_tx_non_phy_agg agg;
2752 struct iwm_mvm_statistics_tx_channel_width channel_width;
2753} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
2754
2755
2756struct iwm_mvm_statistics_bt_activity {
2757 uint32_t hi_priority_tx_req_cnt;
2758 uint32_t hi_priority_tx_denied_cnt;
2759 uint32_t lo_priority_tx_req_cnt;
2760 uint32_t lo_priority_tx_denied_cnt;
2761 uint32_t hi_priority_rx_req_cnt;
2762 uint32_t hi_priority_rx_denied_cnt;
2763 uint32_t lo_priority_rx_req_cnt;
2764 uint32_t lo_priority_rx_denied_cnt;
2765} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
2766
2767struct iwm_mvm_statistics_general {
2768 struct iwm_mvm_statistics_general_common common;
2769 uint32_t beacon_filtered;
2770 uint32_t missed_beacons;
2771 int8_t beacon_filter_average_energy;
2772 int8_t beacon_filter_reason;
2773 int8_t beacon_filter_current_energy;
2774 int8_t beacon_filter_reserved;
2775 uint32_t beacon_filter_delta_time;
2776 struct iwm_mvm_statistics_bt_activity bt_activity;
2777} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2778
2779struct iwm_mvm_statistics_rx {
2780 struct iwm_mvm_statistics_rx_phy ofdm;
2781 struct iwm_mvm_statistics_rx_phy cck;
2782 struct iwm_mvm_statistics_rx_non_phy general;
2783 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
2784} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
2785
2786/*
2787 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
2788 *
2789 * By default, uCode issues this notification after receiving a beacon
2790 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
2791 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
2792 *
2793 * Statistics counters continue to increment beacon after beacon, but are
2794 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
2795 * 0x9c with CLEAR_STATS bit set (see above).
2796 *
2797 * uCode also issues this notification during scans. uCode clears statistics
2798 * appropriately so that each notification contains statistics for only the
2799 * one channel that has just been scanned.
2800 */
2801
2802struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
2803 uint32_t flag;
2804 struct iwm_mvm_statistics_rx rx;
2805 struct iwm_mvm_statistics_tx tx;
2806 struct iwm_mvm_statistics_general general;
2807} __packed;
2808
2809/***********************************
2810 * Smart Fifo API
2811 ***********************************/
2812/* Smart Fifo state */
2813enum iwm_sf_state {
2814 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
2815 IWM_SF_FULL_ON,
2816 IWM_SF_UNINIT,
2817 IWM_SF_INIT_OFF,
2818 IWM_SF_HW_NUM_STATES
2819};
2820
2821/* Smart Fifo possible scenario */
2822enum iwm_sf_scenario {
2823 IWM_SF_SCENARIO_SINGLE_UNICAST,
2824 IWM_SF_SCENARIO_AGG_UNICAST,
2825 IWM_SF_SCENARIO_MULTICAST,
2826 IWM_SF_SCENARIO_BA_RESP,
2827 IWM_SF_SCENARIO_TX_RESP,
2828 IWM_SF_NUM_SCENARIO
2829};
2830
2831#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
2832#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
2833
2834/* smart FIFO default values */
2835#define IWM_SF_W_MARK_SISO 4096
2836#define IWM_SF_W_MARK_MIMO2 8192
2837#define IWM_SF_W_MARK_MIMO3 6144
2838#define IWM_SF_W_MARK_LEGACY 4096
2839#define IWM_SF_W_MARK_SCAN 4096
2840
2841/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
2842#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2843#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2844#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2845#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2846#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
2847#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
2848#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
2849#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
2850#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
2851#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
2852
2853#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
2854
2855/**
2856 * Smart Fifo configuration command.
2857 * @state: smart fifo state, types listed in iwm_sf_sate.
2858 * @watermark: Minimum allowed available free space in RXF for transient state.
2859 * @long_delay_timeouts: aging and idle timer values for each scenario
2860 * in long delay state.
2861 * @full_on_timeouts: timer values for each scenario in full on state.
2862 */
2863struct iwm_sf_cfg_cmd {
2864 enum iwm_sf_state state;
2865 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
2866 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2867 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2868} __packed; /* IWM_SF_CFG_API_S_VER_2 */
2869
2870/*
2871 * END mvm/fw-api.h
2872 */
2873
2874/*
2875 * BEGIN mvm/fw-api-mac.h
2876 */
2877
2878/*
2879 * The first MAC indices (starting from 0)
2880 * are available to the driver, AUX follows
2881 */
2882#define IWM_MAC_INDEX_AUX 4
2883#define IWM_MAC_INDEX_MIN_DRIVER 0
2884#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
2885
2886enum iwm_ac {
2887 IWM_AC_BK,
2888 IWM_AC_BE,
2889 IWM_AC_VI,
2890 IWM_AC_VO,
2891 IWM_AC_NUM,
2892};
2893
2894/**
2895 * enum iwm_mac_protection_flags - MAC context flags
2896 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
2897 * this will require CCK RTS/CTS2self.
2898 * RTS/CTS will protect full burst time.
2899 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
2900 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
2901 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
2902 */
2903enum iwm_mac_protection_flags {
2904 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
2905 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
2906 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
2907 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
2908};
2909
2910#define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
2911#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
2912
2913/**
2914 * enum iwm_mac_types - Supported MAC types
2915 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
2916 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
2917 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
2918 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
2919 * @IWM_FW_MAC_TYPE_IBSS: IBSS
2920 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
2921 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
2922 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
2923 * @IWM_FW_MAC_TYPE_GO: P2P GO
2924 * @IWM_FW_MAC_TYPE_TEST: ?
2925 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
2926 */
2927enum iwm_mac_types {
2928 IWM_FW_MAC_TYPE_FIRST = 1,
2929 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
2930 IWM_FW_MAC_TYPE_LISTENER,
2931 IWM_FW_MAC_TYPE_PIBSS,
2932 IWM_FW_MAC_TYPE_IBSS,
2933 IWM_FW_MAC_TYPE_BSS_STA,
2934 IWM_FW_MAC_TYPE_P2P_DEVICE,
2935 IWM_FW_MAC_TYPE_P2P_STA,
2936 IWM_FW_MAC_TYPE_GO,
2937 IWM_FW_MAC_TYPE_TEST,
2938 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
2939}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
2940
2941/**
2942 * enum iwm_tsf_id - TSF hw timer ID
2943 * @IWM_TSF_ID_A: use TSF A
2944 * @IWM_TSF_ID_B: use TSF B
2945 * @IWM_TSF_ID_C: use TSF C
2946 * @IWM_TSF_ID_D: use TSF D
2947 * @IWM_NUM_TSF_IDS: number of TSF timers available
2948 */
2949enum iwm_tsf_id {
2950 IWM_TSF_ID_A = 0,
2951 IWM_TSF_ID_B = 1,
2952 IWM_TSF_ID_C = 2,
2953 IWM_TSF_ID_D = 3,
2954 IWM_NUM_TSF_IDS = 4,
2955}; /* IWM_TSF_ID_API_E_VER_1 */
2956
2957/**
2958 * struct iwm_mac_data_ap - configuration data for AP MAC context
2959 * @beacon_time: beacon transmit time in system time
2960 * @beacon_tsf: beacon transmit time in TSF
2961 * @bi: beacon interval in TU
2962 * @bi_reciprocal: 2^32 / bi
2963 * @dtim_interval: dtim transmit time in TU
2964 * @dtim_reciprocal: 2^32 / dtim_interval
2965 * @mcast_qid: queue ID for multicast traffic
2966 * @beacon_template: beacon template ID
2967 */
2968struct iwm_mac_data_ap {
2969 uint32_t beacon_time;
2970 uint64_t beacon_tsf;
2971 uint32_t bi;
2972 uint32_t bi_reciprocal;
2973 uint32_t dtim_interval;
2974 uint32_t dtim_reciprocal;
2975 uint32_t mcast_qid;
2976 uint32_t beacon_template;
2977} __packed; /* AP_MAC_DATA_API_S_VER_1 */
2978
2979/**
2980 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
2981 * @beacon_time: beacon transmit time in system time
2982 * @beacon_tsf: beacon transmit time in TSF
2983 * @bi: beacon interval in TU
2984 * @bi_reciprocal: 2^32 / bi
2985 * @beacon_template: beacon template ID
2986 */
2987struct iwm_mac_data_ibss {
2988 uint32_t beacon_time;
2989 uint64_t beacon_tsf;
2990 uint32_t bi;
2991 uint32_t bi_reciprocal;
2992 uint32_t beacon_template;
2993} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
2994
2995/**
2996 * struct iwm_mac_data_sta - configuration data for station MAC context
2997 * @is_assoc: 1 for associated state, 0 otherwise
2998 * @dtim_time: DTIM arrival time in system time
2999 * @dtim_tsf: DTIM arrival time in TSF
3000 * @bi: beacon interval in TU, applicable only when associated
3001 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3002 * @dtim_interval: DTIM interval in TU, applicable only when associated
3003 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3004 * @listen_interval: in beacon intervals, applicable only when associated
3005 * @assoc_id: unique ID assigned by the AP during association
3006 */
3007struct iwm_mac_data_sta {
3008 uint32_t is_assoc;
3009 uint32_t dtim_time;
3010 uint64_t dtim_tsf;
3011 uint32_t bi;
3012 uint32_t bi_reciprocal;
3013 uint32_t dtim_interval;
3014 uint32_t dtim_reciprocal;
3015 uint32_t listen_interval;
3016 uint32_t assoc_id;
3017 uint32_t assoc_beacon_arrive_time;
3018} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3019
3020/**
3021 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3022 * @ap: iwm_mac_data_ap struct with most config data
3023 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3024 * 0 indicates that there is no CT window.
3025 * @opp_ps_enabled: indicate that opportunistic PS allowed
3026 */
3027struct iwm_mac_data_go {
3028 struct iwm_mac_data_ap ap;
3029 uint32_t ctwin;
3030 uint32_t opp_ps_enabled;
3031} __packed; /* GO_MAC_DATA_API_S_VER_1 */
3032
3033/**
3034 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3035 * @sta: iwm_mac_data_sta struct with most config data
3036 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3037 * 0 indicates that there is no CT window.
3038 */
3039struct iwm_mac_data_p2p_sta {
3040 struct iwm_mac_data_sta sta;
3041 uint32_t ctwin;
3042} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3043
3044/**
3045 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3046 * @stats_interval: interval in TU between statistics notifications to host.
3047 */
3048struct iwm_mac_data_pibss {
3049 uint32_t stats_interval;
3050} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3051
3052/*
3053 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3054 * context.
3055 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3056 * other channels as well. This should be to true only in case that the
3057 * device is discoverable and there is an active GO. Note that setting this
3058 * field when not needed, will increase the number of interrupts and have
3059 * effect on the platform power, as this setting opens the Rx filters on
3060 * all macs.
3061 */
3062struct iwm_mac_data_p2p_dev {
3063 uint32_t is_disc_extended;
3064} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3065
3066/**
3067 * enum iwm_mac_filter_flags - MAC context filter flags
3068 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3069 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3070 * control frames to the host
3071 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3072 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3073 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3074 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3075 * (in station mode when associated)
3076 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3077 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3078 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3079 */
3080enum iwm_mac_filter_flags {
3081 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3082 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3083 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3084 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3085 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3086 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3087 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3088 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3089 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3090};
3091
3092/**
3093 * enum iwm_mac_qos_flags - QoS flags
3094 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3095 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3096 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3097 *
3098 */
3099enum iwm_mac_qos_flags {
3100 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3101 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3102 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3103};
3104
3105/**
3106 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3107 * @cw_min: Contention window, start value in numbers of slots.
3108 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3109 * @cw_max: Contention window, max value in numbers of slots.
3110 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3111 * @aifsn: Number of slots in Arbitration Interframe Space (before
3112 * performing random backoff timing prior to Tx). Device default 1.
3113 * @fifos_mask: FIFOs used by this MAC for this AC
3114 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3115 *
3116 * One instance of this config struct for each of 4 EDCA access categories
3117 * in struct iwm_qosparam_cmd.
3118 *
3119 * Device will automatically increase contention window by (2*CW) + 1 for each
3120 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3121 * value, to cap the CW value.
3122 */
3123struct iwm_ac_qos {
3124 uint16_t cw_min;
3125 uint16_t cw_max;
3126 uint8_t aifsn;
3127 uint8_t fifos_mask;
3128 uint16_t edca_txop;
3129} __packed; /* IWM_AC_QOS_API_S_VER_2 */
3130
3131/**
3132 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3133 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3134 * @id_and_color: ID and color of the MAC
3135 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3136 * @mac_type: one of IWM_FW_MAC_TYPE_*
3137 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3138 * @node_addr: MAC address
3139 * @bssid_addr: BSSID
3140 * @cck_rates: basic rates available for CCK
3141 * @ofdm_rates: basic rates available for OFDM
3142 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3143 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3144 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3145 * @filter_flags: combination of IWM_MAC_FILTER_*
3146 * @qos_flags: from IWM_MAC_QOS_FLG_*
3147 * @ac: one iwm_mac_qos configuration for each AC
3148 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3149 */
3150struct iwm_mac_ctx_cmd {
3151 /* COMMON_INDEX_HDR_API_S_VER_1 */
3152 uint32_t id_and_color;
3153 uint32_t action;
3154 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3155 uint32_t mac_type;
3156 uint32_t tsf_id;
3157 uint8_t node_addr[6];
3158 uint16_t reserved_for_node_addr;
3159 uint8_t bssid_addr[6];
3160 uint16_t reserved_for_bssid_addr;
3161 uint32_t cck_rates;
3162 uint32_t ofdm_rates;
3163 uint32_t protection_flags;
3164 uint32_t cck_short_preamble;
3165 uint32_t short_slot;
3166 uint32_t filter_flags;
3167 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3168 uint32_t qos_flags;
3169 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3170 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3171 union {
3172 struct iwm_mac_data_ap ap;
3173 struct iwm_mac_data_go go;
3174 struct iwm_mac_data_sta sta;
3175 struct iwm_mac_data_p2p_sta p2p_sta;
3176 struct iwm_mac_data_p2p_dev p2p_dev;
3177 struct iwm_mac_data_pibss pibss;
3178 struct iwm_mac_data_ibss ibss;
3179 };
3180} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3181
3182static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3183{
3184 if (!v)
3185 return 0;
3186 return 0xFFFFFFFF / v;
3187}
3188
3189#define IWM_NONQOS_SEQ_GET 0x1
3190#define IWM_NONQOS_SEQ_SET 0x2
3191struct iwm_nonqos_seq_query_cmd {
3192 uint32_t get_set_flag;
3193 uint32_t mac_id_n_color;
3194 uint16_t value;
3195 uint16_t reserved;
3196} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3197
3198/*
3199 * END mvm/fw-api-mac.h
3200 */
3201
3202/*
3203 * BEGIN mvm/fw-api-power.h
3204 */
3205
3206/* Power Management Commands, Responses, Notifications */
3207
3208/* Radio LP RX Energy Threshold measured in dBm */
3209#define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3210#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3211#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3212
3213/**
3214 * enum iwm_scan_flags - masks for power table command flags
3215 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3216 * receiver and transmitter. '0' - does not allow.
3217 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3218 * '1' Driver enables PM (use rest of parameters)
3219 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3220 * '1' PM could sleep over DTIM till listen Interval.
3221 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3222 * access categories are both delivery and trigger enabled.
3223 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3224 * PBW Snoozing enabled
3225 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3226 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3227 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3228 * detection enablement
3229*/
3230enum iwm_power_flags {
3231 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3232 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3233 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3234 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3235 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3236 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3237 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3238 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3239};
3240
3241#define IWM_POWER_VEC_SIZE 5
3242
3243/**
3244 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3245 * is used also with a new power API for device wide power settings.
3246 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3247 *
3248 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3249 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3250 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3251 * set regardless of power scheme or current power state.
3252 * FW use this value also when PM is disabled.
3253 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3254 * PSM transition - legacy PM
3255 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3256 * PSM transition - legacy PM
3257 * @sleep_interval: not in use
3258 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3259 * is set. For example, if it is required to skip over
3260 * one DTIM, this value need to be set to 2 (DTIM periods).
3261 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3262 * Default: 80dbm
3263 */
3264struct iwm_powertable_cmd {
3265 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3266 uint16_t flags;
3267 uint8_t keep_alive_seconds;
3268 uint8_t debug_flags;
3269 uint32_t rx_data_timeout;
3270 uint32_t tx_data_timeout;
3271 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3272 uint32_t skip_dtim_periods;
3273 uint32_t lprx_rssi_threshold;
3274} __packed;
3275
3276/**
3277 * enum iwm_device_power_flags - masks for device power command flags
3278 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3279 * receiver and transmitter. '0' - does not allow. This flag should be
3280 * always set to '1' unless one need to disable actual power down for debug
3281 * purposes.
3282 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3283 * that power management is disabled. '0' Power management is enabled, one
3284 * of power schemes is applied.
3285*/
3286enum iwm_device_power_flags {
3287 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3288 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3289};
3290
3291/**
3292 * struct iwm_device_power_cmd - device wide power command.
3293 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3294 *
3295 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3296 */
3297struct iwm_device_power_cmd {
3298 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3299 uint16_t flags;
3300 uint16_t reserved;
3301} __packed;
3302
3303/**
3304 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3305 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3306 * @id_and_color: MAC contex identifier
3307 * @flags: Power table command flags from POWER_FLAGS_*
3308 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3309 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3310 * set regardless of power scheme or current power state.
3311 * FW use this value also when PM is disabled.
3312 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3313 * PSM transition - legacy PM
3314 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3315 * PSM transition - legacy PM
3316 * @sleep_interval: not in use
3317 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3318 * is set. For example, if it is required to skip over
3319 * one DTIM, this value need to be set to 2 (DTIM periods).
3320 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3321 * PSM transition - uAPSD
3322 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3323 * PSM transition - uAPSD
3324 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3325 * Default: 80dbm
3326 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3327 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3328 * from the AP [msec]
3329 * @snooze_window: A window of time in which PBW snoozing insures that all
3330 * packets received. It is also the minimum time from last
3331 * received unicast RX packet, before client stops snoozing
3332 * for data. [msec]
3333 * @snooze_step: TBD
3334 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3335 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3336 * each corresponding AC.
3337 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3338 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3339 * values.
3340 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3341 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3342 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3343 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3344 * @limited_ps_threshold:
3345*/
3346struct iwm_mac_power_cmd {
3347 /* CONTEXT_DESC_API_T_VER_1 */
3348 uint32_t id_and_color;
3349
3350 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3351 uint16_t flags;
3352 uint16_t keep_alive_seconds;
3353 uint32_t rx_data_timeout;
3354 uint32_t tx_data_timeout;
3355 uint32_t rx_data_timeout_uapsd;
3356 uint32_t tx_data_timeout_uapsd;
3357 uint8_t lprx_rssi_threshold;
3358 uint8_t skip_dtim_periods;
3359 uint16_t snooze_interval;
3360 uint16_t snooze_window;
3361 uint8_t snooze_step;
3362 uint8_t qndp_tid;
3363 uint8_t uapsd_ac_flags;
3364 uint8_t uapsd_max_sp;
3365 uint8_t heavy_tx_thld_packets;
3366 uint8_t heavy_rx_thld_packets;
3367 uint8_t heavy_tx_thld_percentage;
3368 uint8_t heavy_rx_thld_percentage;
3369 uint8_t limited_ps_threshold;
3370 uint8_t reserved;
3371} __packed;
3372
3373/*
3374 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3375 * associated AP is identified as improperly implementing uAPSD protocol.
3376 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3377 * @sta_id: index of station in uCode's station table - associated AP ID in
3378 * this context.
3379 */
3380struct iwm_uapsd_misbehaving_ap_notif {
3381 uint32_t sta_id;
3382 uint8_t mac_id;
3383 uint8_t reserved[3];
3384} __packed;
3385
3386/**
3387 * struct iwm_beacon_filter_cmd
3388 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3389 * @id_and_color: MAC contex identifier
3390 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3391 * to driver if delta in Energy values calculated for this and last
3392 * passed beacon is greater than this threshold. Zero value means that
3393 * the Energy change is ignored for beacon filtering, and beacon will
3394 * not be forced to be sent to driver regardless of this delta. Typical
3395 * energy delta 5dB.
3396 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3397 * Send beacon to driver if delta in Energy values calculated for this
3398 * and last passed beacon is greater than this threshold. Zero value
3399 * means that the Energy change is ignored for beacon filtering while in
3400 * Roaming state, typical energy delta 1dB.
3401 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3402 * calculated for current beacon is less than the threshold, use
3403 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3404 * Threshold. Typical energy threshold is -72dBm.
3405 * @bf_temp_threshold: This threshold determines the type of temperature
3406 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3407 * If the current temperature is above this threshold - Fast filter
3408 * will be used, If the current temperature is below this threshold -
3409 * Slow filter will be used.
3410 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3411 * calculated for this and the last passed beacon is greater than this
3412 * threshold. Zero value means that the temperature change is ignored for
3413 * beacon filtering; beacons will not be forced to be sent to driver
3414 * regardless of whether its temperature has been changed.
3415 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3416 * calculated for this and the last passed beacon is greater than this
3417 * threshold. Zero value means that the temperature change is ignored for
3418 * beacon filtering; beacons will not be forced to be sent to driver
3419 * regardless of whether its temperature has been changed.
3420 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3421 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3422 * for a specific period of time. Units: Beacons.
3423 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3424 * for a longer period of time then this escape-timeout. Units: Beacons.
3425 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3426 */
3427struct iwm_beacon_filter_cmd {
3428 uint32_t bf_energy_delta;
3429 uint32_t bf_roaming_energy_delta;
3430 uint32_t bf_roaming_state;
3431 uint32_t bf_temp_threshold;
3432 uint32_t bf_temp_fast_filter;
3433 uint32_t bf_temp_slow_filter;
3434 uint32_t bf_enable_beacon_filter;
3435 uint32_t bf_debug_flag;
3436 uint32_t bf_escape_timer;
3437 uint32_t ba_escape_timer;
3438 uint32_t ba_enable_beacon_abort;
3439} __packed;
3440
3441/* Beacon filtering and beacon abort */
3442#define IWM_BF_ENERGY_DELTA_DEFAULT 5
3443#define IWM_BF_ENERGY_DELTA_MAX 255
3444#define IWM_BF_ENERGY_DELTA_MIN 0
3445
3446#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3447#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3448#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3449
3450#define IWM_BF_ROAMING_STATE_DEFAULT 72
3451#define IWM_BF_ROAMING_STATE_MAX 255
3452#define IWM_BF_ROAMING_STATE_MIN 0
3453
3454#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3455#define IWM_BF_TEMP_THRESHOLD_MAX 255
3456#define IWM_BF_TEMP_THRESHOLD_MIN 0
3457
3458#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3459#define IWM_BF_TEMP_FAST_FILTER_MAX 255
3460#define IWM_BF_TEMP_FAST_FILTER_MIN 0
3461
3462#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3463#define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3464#define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3465
3466#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3467
3468#define IWM_BF_DEBUG_FLAG_DEFAULT 0
3469
3470#define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3471#define IWM_BF_ESCAPE_TIMER_MAX 1024
3472#define IWM_BF_ESCAPE_TIMER_MIN 0
3473
3474#define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3475#define IWM_BA_ESCAPE_TIMER_D3 9
3476#define IWM_BA_ESCAPE_TIMER_MAX 1024
3477#define IWM_BA_ESCAPE_TIMER_MIN 0
3478
3479#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3480
3481#define IWM_BF_CMD_CONFIG_DEFAULTS \
3482 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3483 .bf_roaming_energy_delta = \
3484 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3485 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3486 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3487 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3488 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3489 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3490 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3491 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3492
3493/*
3494 * END mvm/fw-api-power.h
3495 */
3496
3497/*
3498 * BEGIN mvm/fw-api-rs.h
3499 */
3500
3501/*
3502 * These serve as indexes into
3503 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3504 * TODO: avoid overlap between legacy and HT rates
3505 */
3506enum {
3507 IWM_RATE_1M_INDEX = 0,
3508 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3509 IWM_RATE_2M_INDEX,
3510 IWM_RATE_5M_INDEX,
3511 IWM_RATE_11M_INDEX,
3512 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3513 IWM_RATE_6M_INDEX,
3514 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3515 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3516 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3517 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3518 IWM_RATE_9M_INDEX,
3519 IWM_RATE_12M_INDEX,
3520 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3521 IWM_RATE_18M_INDEX,
3522 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3523 IWM_RATE_24M_INDEX,
3524 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3525 IWM_RATE_36M_INDEX,
3526 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3527 IWM_RATE_48M_INDEX,
3528 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3529 IWM_RATE_54M_INDEX,
3530 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3531 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3532 IWM_RATE_60M_INDEX,
3533 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3534 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3535 IWM_RATE_MCS_8_INDEX,
3536 IWM_RATE_MCS_9_INDEX,
3537 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3538 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3539 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3540};
3541
3542#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3543
3544/* fw API values for legacy bit rates, both OFDM and CCK */
3545enum {
3546 IWM_RATE_6M_PLCP = 13,
3547 IWM_RATE_9M_PLCP = 15,
3548 IWM_RATE_12M_PLCP = 5,
3549 IWM_RATE_18M_PLCP = 7,
3550 IWM_RATE_24M_PLCP = 9,
3551 IWM_RATE_36M_PLCP = 11,
3552 IWM_RATE_48M_PLCP = 1,
3553 IWM_RATE_54M_PLCP = 3,
3554 IWM_RATE_1M_PLCP = 10,
3555 IWM_RATE_2M_PLCP = 20,
3556 IWM_RATE_5M_PLCP = 55,
3557 IWM_RATE_11M_PLCP = 110,
3558 IWM_RATE_INVM_PLCP = -1,
3559};
3560
3561/*
3562 * rate_n_flags bit fields
3563 *
3564 * The 32-bit value has different layouts in the low 8 bites depending on the
3565 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3566 * for CCK and OFDM).
3567 *
3568 * High-throughput (HT) rate format
3569 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3570 * Very High-throughput (VHT) rate format
3571 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3572 * Legacy OFDM rate format for bits 7:0
3573 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3574 * Legacy CCK rate format for bits 7:0:
3575 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3576 */
3577
3578/* Bit 8: (1) HT format, (0) legacy or VHT format */
3579#define IWM_RATE_MCS_HT_POS 8
3580#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3581
3582/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3583#define IWM_RATE_MCS_CCK_POS 9
3584#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3585
3586/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3587#define IWM_RATE_MCS_VHT_POS 26
3588#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3589
3590
3591/*
3592 * High-throughput (HT) rate format for bits 7:0
3593 *
3594 * 2-0: MCS rate base
3595 * 0) 6 Mbps
3596 * 1) 12 Mbps
3597 * 2) 18 Mbps
3598 * 3) 24 Mbps
3599 * 4) 36 Mbps
3600 * 5) 48 Mbps
3601 * 6) 54 Mbps
3602 * 7) 60 Mbps
3603 * 4-3: 0) Single stream (SISO)
3604 * 1) Dual stream (MIMO)
3605 * 2) Triple stream (MIMO)
3606 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3607 * (bits 7-6 are zero)
3608 *
3609 * Together the low 5 bits work out to the MCS index because we don't
3610 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3611 * streams and 16-23 have three streams. We could also support MCS 32
3612 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3613 */
3614#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3615#define IWM_RATE_HT_MCS_NSS_POS 3
3616#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3617
3618/* Bit 10: (1) Use Green Field preamble */
3619#define IWM_RATE_HT_MCS_GF_POS 10
3620#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3621
3622#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3623
3624/*
3625 * Very High-throughput (VHT) rate format for bits 7:0
3626 *
3627 * 3-0: VHT MCS (0-9)
3628 * 5-4: number of streams - 1:
3629 * 0) Single stream (SISO)
3630 * 1) Dual stream (MIMO)
3631 * 2) Triple stream (MIMO)
3632 */
3633
3634/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3635#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3636#define IWM_RATE_VHT_MCS_NSS_POS 4
3637#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3638
3639/*
3640 * Legacy OFDM rate format for bits 7:0
3641 *
3642 * 3-0: 0xD) 6 Mbps
3643 * 0xF) 9 Mbps
3644 * 0x5) 12 Mbps
3645 * 0x7) 18 Mbps
3646 * 0x9) 24 Mbps
3647 * 0xB) 36 Mbps
3648 * 0x1) 48 Mbps
3649 * 0x3) 54 Mbps
3650 * (bits 7-4 are 0)
3651 *
3652 * Legacy CCK rate format for bits 7:0:
3653 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3654 *
3655 * 6-0: 10) 1 Mbps
3656 * 20) 2 Mbps
3657 * 55) 5.5 Mbps
3658 * 110) 11 Mbps
3659 * (bit 7 is 0)
3660 */
3661#define IWM_RATE_LEGACY_RATE_MSK 0xff
3662
3663
3664/*
3665 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3666 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3667 */
3668#define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3669#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3670#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3671#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3672#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3673#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3674
3675/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3676#define IWM_RATE_MCS_SGI_POS 13
3677#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3678
3679/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3680#define IWM_RATE_MCS_ANT_POS 14
3681#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3682#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3683#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3684#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3685 IWM_RATE_MCS_ANT_B_MSK)
3686#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3687 IWM_RATE_MCS_ANT_C_MSK)
3688#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3689#define IWM_RATE_MCS_ANT_NUM 3
3690
3691/* Bit 17-18: (0) SS, (1) SS*2 */
3692#define IWM_RATE_MCS_STBC_POS 17
3693#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
3694
3695/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
3696#define IWM_RATE_MCS_BF_POS 19
3697#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
3698
3699/* Bit 20: (0) ZLF is off, (1) ZLF is on */
3700#define IWM_RATE_MCS_ZLF_POS 20
3701#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
3702
3703/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
3704#define IWM_RATE_MCS_DUP_POS 24
3705#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
3706
3707/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
3708#define IWM_RATE_MCS_LDPC_POS 27
3709#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
3710
3711
3712/* Link Quality definitions */
3713
3714/* # entries in rate scale table to support Tx retries */
3715#define IWM_LQ_MAX_RETRY_NUM 16
3716
3717/* Link quality command flags bit fields */
3718
3719/* Bit 0: (0) Don't use RTS (1) Use RTS */
3720#define IWM_LQ_FLAG_USE_RTS_POS 0
3721#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
3722
3723/* Bit 1-3: LQ command color. Used to match responses to LQ commands */
3724#define IWM_LQ_FLAG_COLOR_POS 1
3725#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
3726
3727/* Bit 4-5: Tx RTS BW Signalling
3728 * (0) No RTS BW signalling
3729 * (1) Static BW signalling
3730 * (2) Dynamic BW signalling
3731 */
3732#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
3733#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3734#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3735#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3736
3737/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
3738 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
3739 */
3740#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
3741#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
3742
3743/**
3744 * struct iwm_lq_cmd - link quality command
3745 * @sta_id: station to update
3746 * @control: not used
3747 * @flags: combination of IWM_LQ_FLAG_*
3748 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
3749 * and SISO rates
3750 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
3751 * Should be ANT_[ABC]
3752 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
3753 * @initial_rate_index: first index from rs_table per AC category
3754 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
3755 * value of 100 is one usec. Range is 100 to 8000
3756 * @agg_disable_start_th: try-count threshold for starting aggregation.
3757 * If a frame has higher try-count, it should not be selected for
3758 * starting an aggregation sequence.
3759 * @agg_frame_cnt_limit: max frame count in an aggregation.
3760 * 0: no limit
3761 * 1: no aggregation (one frame per aggregation)
3762 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
3763 * @rs_table: array of rates for each TX try, each is rate_n_flags,
3764 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
3765 * @bf_params: beam forming params, currently not used
3766 */
3767struct iwm_lq_cmd {
3768 uint8_t sta_id;
3769 uint8_t reserved1;
3770 uint16_t control;
3771 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
3772 uint8_t flags;
3773 uint8_t mimo_delim;
3774 uint8_t single_stream_ant_msk;
3775 uint8_t dual_stream_ant_msk;
3776 uint8_t initial_rate_index[IWM_AC_NUM];
3777 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
3778 uint16_t agg_time_limit;
3779 uint8_t agg_disable_start_th;
3780 uint8_t agg_frame_cnt_limit;
3781 uint32_t reserved2;
3782 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
3783 uint32_t bf_params;
3784}; /* LINK_QUALITY_CMD_API_S_VER_1 */
3785
3786/*
3787 * END mvm/fw-api-rs.h
3788 */
3789
3790/*
3791 * BEGIN mvm/fw-api-tx.h
3792 */
3793
3794/**
3795 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
3796 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
3797 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
3798 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
3799 * Otherwise, use rate_n_flags from the TX command
3800 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
3801 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
3802 * Must set IWM_TX_CMD_FLG_ACK with this flag.
3803 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
3804 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
3805 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
3806 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
3807 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
3808 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
3809 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
3810 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
3811 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
3812 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
3813 * Should be set for beacons and probe responses
3814 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
3815 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
3816 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
3817 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
3818 * Should be set for 26/30 length MAC headers
3819 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
3820 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
3821 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
3822 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
3823 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
3824 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
3825 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
3826 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
3827 */
3828enum iwm_tx_flags {
3829 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
3830 IWM_TX_CMD_FLG_ACK = (1 << 3),
3831 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
3832 IWM_TX_CMD_FLG_BA = (1 << 5),
3833 IWM_TX_CMD_FLG_BAR = (1 << 6),
3834 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
3835 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
3836 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
3837 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
3838 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
3839 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
3840 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
3841 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
3842 IWM_TX_CMD_FLG_TSF = (1 << 16),
3843 IWM_TX_CMD_FLG_CALIB = (1 << 17),
3844 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
3845 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
3846 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
3847 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
3848 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
3849 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
3850 IWM_TX_CMD_FLG_DUR = (1 << 25),
3851 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
3852 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
3853 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
3854 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
3855}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
3856
3857/*
3858 * TX command security control
3859 */
3860#define IWM_TX_CMD_SEC_WEP 0x01
3861#define IWM_TX_CMD_SEC_CCM 0x02
3862#define IWM_TX_CMD_SEC_TKIP 0x03
3863#define IWM_TX_CMD_SEC_EXT 0x04
3864#define IWM_TX_CMD_SEC_MSK 0x07
3865#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
3866#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
3867#define IWM_TX_CMD_SEC_KEY128 0x08
3868
3869/* TODO: how does these values are OK with only 16 bit variable??? */
3870/*
3871 * TX command next frame info
3872 *
3873 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
3874 * bit 3 - immediate ACK required
3875 * bit 4 - rate is taken from STA table
3876 * bit 5 - frame belongs to BA stream
3877 * bit 6 - immediate BA response expected
3878 * bit 7 - unused
3879 * bits 8:15 - Station ID
3880 * bits 16:31 - rate
3881 */
3882#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
3883#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
3884#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
3885#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
3886#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
3887#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
3888#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
3889#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
3890#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
3891
3892/*
3893 * TX command Frame life time in us - to be written in pm_frame_timeout
3894 */
3895#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
3896#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
3897#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
3898#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
3899
3900/*
3901 * TID for non QoS frames - to be written in tid_tspec
3902 */
3903#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
3904
3905/*
3906 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
3907 */
3908#define IWM_DEFAULT_TX_RETRY 15
3909#define IWM_MGMT_DFAULT_RETRY_LIMIT 3
3910#define IWM_RTS_DFAULT_RETRY_LIMIT 60
3911#define IWM_BAR_DFAULT_RETRY_LIMIT 60
3912#define IWM_LOW_RETRY_LIMIT 7
3913
3914/* TODO: complete documentation for try_cnt and btkill_cnt */
3915/**
3916 * struct iwm_tx_cmd - TX command struct to FW
3917 * ( IWM_TX_CMD = 0x1c )
3918 * @len: in bytes of the payload, see below for details
3919 * @next_frame_len: same as len, but for next frame (0 if not applicable)
3920 * Used for fragmentation and bursting, but not in 11n aggregation.
3921 * @tx_flags: combination of IWM_TX_CMD_FLG_*
3922 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
3923 * cleared. Combination of IWM_RATE_MCS_*
3924 * @sta_id: index of destination station in FW station table
3925 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
|
4278 * and the TFD queues are empty.
4279 */
4280enum iwm_dump_control {
4281 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4282};
4283
4284/**
4285 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4286 * @queues_ctl: bitmap of queues to flush
4287 * @flush_ctl: control flags
4288 * @reserved: reserved
4289 */
4290struct iwm_tx_path_flush_cmd {
4291 uint32_t queues_ctl;
4292 uint16_t flush_ctl;
4293 uint16_t reserved;
4294} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4295
4296/**
4297 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4298 * @tx_resp: the Tx response from the fw (agg or non-agg)
4299 *
4300 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4301 * it can't know that everything will go well until the end of the AMPDU, it
4302 * can't know in advance the number of MPDUs that will be sent in the current
4303 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4304 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4305 * of the batch. This is why the SSN of the SCD is written at the end of the
4306 * whole struct at a variable offset. This function knows how to cope with the
4307 * variable offset and returns the SSN of the SCD.
4308 */
4309static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4310{
4311 return le32_to_cpup((uint32_t *)&tx_resp->status +
4312 tx_resp->frame_count) & 0xfff;
4313}
4314
4315/*
4316 * END mvm/fw-api-tx.h
4317 */
4318
4319/*
4320 * BEGIN mvm/fw-api-scan.h
4321 */
4322
4323/* Scan Commands, Responses, Notifications */
4324
4325/* Masks for iwm_scan_channel.type flags */
4326#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4327#define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22)
4328
4329/* Max number of IEs for direct SSID scans in a command */
4330#define IWM_PROBE_OPTION_MAX 20
4331
4332/**
4333 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table
4334 * @channel: band is selected by iwm_scan_cmd "flags" field
4335 * @tx_gain: gain for analog radio
4336 * @dsp_atten: gain for DSP
4337 * @active_dwell: dwell time for active scan in TU, typically 5-50
4338 * @passive_dwell: dwell time for passive scan in TU, typically 20-500
4339 * @type: type is broken down to these bits:
4340 * bit 0: 0 = passive, 1 = active
4341 * bits 1-20: SSID direct bit map. If any of these bits is set then
4342 * the corresponding SSID IE is transmitted in probe request
4343 * (bit i adds IE in position i to the probe request)
4344 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel
4345 *
4346 * @iteration_count:
4347 * @iteration_interval:
4348 * This struct is used once for each channel in the scan list.
4349 * Each channel can independently select:
4350 * 1) SSID for directed active scans
4351 * 2) Txpower setting (for rate specified within Tx command)
4352 * 3) How long to stay on-channel (behavior may be modified by quiet_time,
4353 * quiet_plcp_th, good_CRC_th)
4354 *
4355 * To avoid uCode errors, make sure the following are true (see comments
4356 * under struct iwm_scan_cmd about max_out_time and quiet_time):
4357 * 1) If using passive_dwell (i.e. passive_dwell != 0):
4358 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
4359 * 2) quiet_time <= active_dwell
4360 * 3) If restricting off-channel time (i.e. max_out_time !=0):
4361 * passive_dwell < max_out_time
4362 * active_dwell < max_out_time
4363 */
4364struct iwm_scan_channel {
4365 uint32_t type;
4366 uint16_t channel;
4367 uint16_t iteration_count;
4368 uint32_t iteration_interval;
4369 uint16_t active_dwell;
4370 uint16_t passive_dwell;
4371} __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */
4372
4373/**
4374 * struct iwm_ssid_ie - directed scan network information element
4375 *
4376 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4377 * selected by "type" bit field in struct iwm_scan_channel;
4378 * each channel may select different ssids from among the 20 entries.
4379 * SSID IEs get transmitted in reverse order of entry.
4380 */
4381struct iwm_ssid_ie {
4382 uint8_t id;
4383 uint8_t len;
4384 uint8_t ssid[IEEE80211_NWID_LEN];
4385} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4386
4387/**
4388 * iwm_scan_flags - masks for scan command flags
4389 *@IWM_SCAN_FLAGS_PERIODIC_SCAN:
4390 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX:
4391 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND:
4392 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND:
4393 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN:
4394 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active
4395 * in the past hour, even if they are marked as passive.
4396 */
4397enum iwm_scan_flags {
4398 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0),
4399 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1),
4400 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2),
4401 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3),
4402 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4),
4403 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5),
4404};
4405
4406/**
4407 * enum iwm_scan_type - Scan types for scan command
4408 * @IWM_SCAN_TYPE_FORCED:
4409 * @IWM_SCAN_TYPE_BACKGROUND:
4410 * @IWM_SCAN_TYPE_OS:
4411 * @IWM_SCAN_TYPE_ROAMING:
4412 * @IWM_SCAN_TYPE_ACTION:
4413 * @IWM_SCAN_TYPE_DISCOVERY:
4414 * @IWM_SCAN_TYPE_DISCOVERY_FORCED:
4415 */
4416enum iwm_scan_type {
4417 IWM_SCAN_TYPE_FORCED = 0,
4418 IWM_SCAN_TYPE_BACKGROUND = 1,
4419 IWM_SCAN_TYPE_OS = 2,
4420 IWM_SCAN_TYPE_ROAMING = 3,
4421 IWM_SCAN_TYPE_ACTION = 4,
4422 IWM_SCAN_TYPE_DISCOVERY = 5,
4423 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6,
4424}; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */
4425
4426/* Maximal number of channels to scan */
4427#define IWM_MAX_NUM_SCAN_CHANNELS 0x24
4428
4429/**
4430 * struct iwm_scan_cmd - scan request command
4431 * ( IWM_SCAN_REQUEST_CMD = 0x80 )
4432 * @len: command length in bytes
4433 * @scan_flags: scan flags from IWM_SCAN_FLAGS_*
4434 * @channel_count: num of channels in channel list (1 - IWM_MAX_NUM_SCAN_CHANNELS)
4435 * @quiet_time: in msecs, dwell this time for active scan on quiet channels
4436 * @quiet_plcp_th: quiet PLCP threshold (channel is quiet if less than
4437 * this number of packets were received (typically 1)
4438 * @passive2active: is auto switching from passive to active during scan allowed
4439 * @rxchain_sel_flags: RXON_RX_CHAIN_*
4440 * @max_out_time: in usecs, max out of serving channel time
4441 * @suspend_time: how long to pause scan when returning to service channel:
4442 * bits 0-19: beacon interval in usecs (suspend before executing)
4443 * bits 20-23: reserved
4444 * bits 24-31: number of beacons (suspend between channels)
4445 * @rxon_flags: RXON_FLG_*
4446 * @filter_flags: RXON_FILTER_*
4447 * @tx_cmd: for active scans (zero for passive), w/o payload,
4448 * no RS so specify TX rate
4449 * @direct_scan: direct scan SSIDs
4450 * @type: one of IWM_SCAN_TYPE_*
4451 * @repeats: how many time to repeat the scan
4452 */
4453struct iwm_scan_cmd {
4454 uint16_t len;
4455 uint8_t scan_flags;
4456 uint8_t channel_count;
4457 uint16_t quiet_time;
4458 uint16_t quiet_plcp_th;
4459 uint16_t passive2active;
4460 uint16_t rxchain_sel_flags;
4461 uint32_t max_out_time;
4462 uint32_t suspend_time;
4463 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4464 uint32_t rxon_flags;
4465 uint32_t filter_flags;
4466 struct iwm_tx_cmd tx_cmd;
4467 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4468 uint32_t type;
4469 uint32_t repeats;
4470
4471 /*
4472 * Probe request frame, followed by channel list.
4473 *
4474 * Size of probe request frame is specified by byte count in tx_cmd.
4475 * Channel list follows immediately after probe request frame.
4476 * Number of channels in list is specified by channel_count.
4477 * Each channel in list is of type:
4478 *
4479 * struct iwm_scan_channel channels[0];
4480 *
4481 * NOTE: Only one band of channels can be scanned per pass. You
4482 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
4483 * for one scan to complete (i.e. receive IWM_SCAN_COMPLETE_NOTIFICATION)
4484 * before requesting another scan.
4485 */
4486 uint8_t data[0];
4487} __packed; /* IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_5 */
4488
4489/* Response to scan request contains only status with one of these values */
4490#define IWM_SCAN_RESPONSE_OK 0x1
4491#define IWM_SCAN_RESPONSE_ERROR 0x2
4492
4493/*
4494 * IWM_SCAN_ABORT_CMD = 0x81
4495 * When scan abort is requested, the command has no fields except the common
4496 * header. The response contains only a status with one of these values.
4497 */
4498#define IWM_SCAN_ABORT_POSSIBLE 0x1
4499#define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */
4500
4501/* TODO: complete documentation */
4502#define IWM_SCAN_OWNER_STATUS 0x1
4503#define IWM_MEASURE_OWNER_STATUS 0x2
4504
4505/**
4506 * struct iwm_scan_start_notif - notifies start of scan in the device
4507 * ( IWM_SCAN_START_NOTIFICATION = 0x82 )
4508 * @tsf_low: TSF timer (lower half) in usecs
4509 * @tsf_high: TSF timer (higher half) in usecs
4510 * @beacon_timer: structured as follows:
4511 * bits 0:19 - beacon interval in usecs
4512 * bits 20:23 - reserved (0)
4513 * bits 24:31 - number of beacons
4514 * @channel: which channel is scanned
4515 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4516 * @status: one of *_OWNER_STATUS
4517 */
4518struct iwm_scan_start_notif {
4519 uint32_t tsf_low;
4520 uint32_t tsf_high;
4521 uint32_t beacon_timer;
4522 uint8_t channel;
4523 uint8_t band;
4524 uint8_t reserved[2];
4525 uint32_t status;
4526} __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */
4527
4528/* scan results probe_status first bit indicates success */
4529#define IWM_SCAN_PROBE_STATUS_OK 0
4530#define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0)
4531/* error statuses combined with TX_FAILED */
4532#define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1)
4533#define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2)
4534
4535/* How many statistics are gathered for each channel */
4536#define IWM_SCAN_RESULTS_STATISTICS 1
4537
4538/**
4539 * enum iwm_scan_complete_status - status codes for scan complete notifications
4540 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4541 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4542 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4543 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4544 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4545 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4546 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4547 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4548 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4549 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4550 * (not an error!)
4551 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4552 * asked for
4553 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4554*/
4555enum iwm_scan_complete_status {
4556 IWM_SCAN_COMP_STATUS_OK = 0x1,
4557 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4558 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4559 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4560 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4561 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4562 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4563 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4564 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4565 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4566 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4567 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4568};
4569
4570/**
4571 * struct iwm_scan_results_notif - scan results for one channel
4572 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4573 * @channel: which channel the results are from
4574 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4575 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4576 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4577 * @duration: duration spent in channel, in usecs
4578 * @statistics: statistics gathered for this channel
4579 */
4580struct iwm_scan_results_notif {
4581 uint8_t channel;
4582 uint8_t band;
4583 uint8_t probe_status;
4584 uint8_t num_probe_not_sent;
4585 uint32_t duration;
4586 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4587} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4588
4589/**
4590 * struct iwm_scan_complete_notif - notifies end of scanning (all channels)
4591 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 )
4592 * @scanned_channels: number of channels scanned (and number of valid results)
4593 * @status: one of IWM_SCAN_COMP_STATUS_*
4594 * @bt_status: BT on/off status
4595 * @last_channel: last channel that was scanned
4596 * @tsf_low: TSF timer (lower half) in usecs
4597 * @tsf_high: TSF timer (higher half) in usecs
4598 * @results: all scan results, only "scanned_channels" of them are valid
4599 */
4600struct iwm_scan_complete_notif {
4601 uint8_t scanned_channels;
4602 uint8_t status;
4603 uint8_t bt_status;
4604 uint8_t last_channel;
4605 uint32_t tsf_low;
4606 uint32_t tsf_high;
4607 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS];
4608} __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */
4609
4610/* scan offload */
4611#define IWM_MAX_SCAN_CHANNELS 40
4612#define IWM_SCAN_MAX_BLACKLIST_LEN 64
4613#define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4614#define IWM_SCAN_MAX_PROFILES 11
4615#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4616
4617/* Default watchdog (in MS) for scheduled scan iteration */
4618#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4619
4620#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4621#define IWM_CAN_ABORT_STATUS 1
4622
4623#define IWM_FULL_SCAN_MULTIPLIER 5
4624#define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4625
4626enum iwm_scan_framework_client {
4627 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4628 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4629 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4630};
4631
4632/**
4633 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6
4634 * @scan_flags: see enum iwm_scan_flags
4635 * @channel_count: channels in channel list
4636 * @quiet_time: dwell time, in milisiconds, on quiet channel
4637 * @quiet_plcp_th: quiet channel num of packets threshold
4638 * @good_CRC_th: passive to active promotion threshold
4639 * @rx_chain: RXON rx chain.
4640 * @max_out_time: max uSec to be out of assoceated channel
4641 * @suspend_time: pause scan this long when returning to service channel
4642 * @flags: RXON flags
4643 * @filter_flags: RXONfilter
4644 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz.
4645 * @direct_scan: list of SSIDs for directed active scan
4646 * @scan_type: see enum iwm_scan_type.
4647 * @rep_count: repetition count for each scheduled scan iteration.
4648 */
4649struct iwm_scan_offload_cmd {
4650 uint16_t len;
4651 uint8_t scan_flags;
4652 uint8_t channel_count;
4653 uint16_t quiet_time;
4654 uint16_t quiet_plcp_th;
4655 uint16_t good_CRC_th;
4656 uint16_t rx_chain;
4657 uint32_t max_out_time;
4658 uint32_t suspend_time;
4659 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4660 uint32_t flags;
4661 uint32_t filter_flags;
4662 struct iwm_tx_cmd tx_cmd[2];
4663 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4664 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4665 uint32_t scan_type;
4666 uint32_t rep_count;
4667} __packed;
4668
4669enum iwm_scan_offload_channel_flags {
4670 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0),
4671 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22),
4672 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24),
4673 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25),
4674};
4675
4676/**
4677 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S
4678 * @type: bitmap - see enum iwm_scan_offload_channel_flags.
4679 * 0: passive (0) or active (1) scan.
4680 * 1-20: directed scan to i'th ssid.
4681 * 22: channel width configuation - 1 for narrow.
4682 * 24: full scan.
4683 * 25: partial scan.
4684 * @channel_number: channel number 1-13 etc.
4685 * @iter_count: repetition count for the channel.
4686 * @iter_interval: interval between two innteration on one channel.
4687 * @dwell_time: entry 0 - active scan, entry 1 - passive scan.
4688 */
4689struct iwm_scan_channel_cfg {
4690 uint32_t type[IWM_MAX_SCAN_CHANNELS];
4691 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS];
4692 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS];
4693 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS];
4694 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2];
4695} __packed;
4696
4697/**
4698 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S
4699 * @scan_cmd: scan command fixed part
4700 * @channel_cfg: scan channel configuration
4701 * @data: probe request frames (one per band)
4702 */
4703struct iwm_scan_offload_cfg {
4704 struct iwm_scan_offload_cmd scan_cmd;
4705 struct iwm_scan_channel_cfg channel_cfg;
4706 uint8_t data[0];
4707} __packed;
4708
4709/**
4710 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4711 * @ssid: MAC address to filter out
4712 * @reported_rssi: AP rssi reported to the host
4713 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4714 */
4715struct iwm_scan_offload_blacklist {
4716 uint8_t ssid[IEEE80211_ADDR_LEN];
4717 uint8_t reported_rssi;
4718 uint8_t client_bitmap;
4719} __packed;
4720
4721enum iwm_scan_offload_network_type {
4722 IWM_NETWORK_TYPE_BSS = 1,
4723 IWM_NETWORK_TYPE_IBSS = 2,
4724 IWM_NETWORK_TYPE_ANY = 3,
4725};
4726
4727enum iwm_scan_offload_band_selection {
4728 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4729 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4730 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4731};
4732
4733/**
4734 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4735 * @ssid_index: index to ssid list in fixed part
4736 * @unicast_cipher: encryption olgorithm to match - bitmap
4737 * @aut_alg: authentication olgorithm to match - bitmap
4738 * @network_type: enum iwm_scan_offload_network_type
4739 * @band_selection: enum iwm_scan_offload_band_selection
4740 * @client_bitmap: clients waiting for match - enum scan_framework_client
4741 */
4742struct iwm_scan_offload_profile {
4743 uint8_t ssid_index;
4744 uint8_t unicast_cipher;
4745 uint8_t auth_alg;
4746 uint8_t network_type;
4747 uint8_t band_selection;
4748 uint8_t client_bitmap;
4749 uint8_t reserved[2];
4750} __packed;
4751
4752/**
4753 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4754 * @blaclist: AP list to filter off from scan results
4755 * @profiles: profiles to search for match
4756 * @blacklist_len: length of blacklist
4757 * @num_profiles: num of profiles in the list
4758 * @match_notify: clients waiting for match found notification
4759 * @pass_match: clients waiting for the results
4760 * @active_clients: active clients bitmap - enum scan_framework_client
4761 * @any_beacon_notify: clients waiting for match notification without match
4762 */
4763struct iwm_scan_offload_profile_cfg {
4764 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4765 uint8_t blacklist_len;
4766 uint8_t num_profiles;
4767 uint8_t match_notify;
4768 uint8_t pass_match;
4769 uint8_t active_clients;
4770 uint8_t any_beacon_notify;
4771 uint8_t reserved[2];
4772} __packed;
4773
4774/**
4775 * iwm_scan_offload_schedule - schedule of scan offload
4776 * @delay: delay between iterations, in seconds.
4777 * @iterations: num of scan iterations
4778 * @full_scan_mul: number of partial scans before each full scan
4779 */
4780struct iwm_scan_offload_schedule {
4781 uint16_t delay;
4782 uint8_t iterations;
4783 uint8_t full_scan_mul;
4784} __packed;
4785
4786/*
4787 * iwm_scan_offload_flags
4788 *
4789 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
4790 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
4791 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
4792 * on A band.
4793 */
4794enum iwm_scan_offload_flags {
4795 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0),
4796 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2),
4797 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3),
4798};
4799
4800/**
4801 * iwm_scan_offload_req - scan offload request command
4802 * @flags: bitmap - enum iwm_scan_offload_flags.
4803 * @watchdog: maximum scan duration in TU.
4804 * @delay: delay in seconds before first iteration.
4805 * @schedule_line: scan offload schedule, for fast and regular scan.
4806 */
4807struct iwm_scan_offload_req {
4808 uint16_t flags;
4809 uint16_t watchdog;
4810 uint16_t delay;
4811 uint16_t reserved;
4812 struct iwm_scan_offload_schedule schedule_line[2];
4813} __packed;
4814
4815enum iwm_scan_offload_compleate_status {
4816 IWM_SCAN_OFFLOAD_COMPLETED = 1,
4817 IWM_SCAN_OFFLOAD_ABORTED = 2,
4818};
4819
4820/**
4821 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1
4822 * @last_schedule_line: last schedule line executed (fast or regular)
4823 * @last_schedule_iteration: last scan iteration executed before scan abort
4824 * @status: enum iwm_scan_offload_compleate_status
4825 */
4826struct iwm_scan_offload_complete {
4827 uint8_t last_schedule_line;
4828 uint8_t last_schedule_iteration;
4829 uint8_t status;
4830 uint8_t reserved;
4831} __packed;
4832
4833/**
4834 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1
4835 * @ssid_bitmap: SSIDs indexes found in this iteration
4836 * @client_bitmap: clients that are active and wait for this notification
4837 */
4838struct iwm_sched_scan_results {
4839 uint16_t ssid_bitmap;
4840 uint8_t client_bitmap;
4841 uint8_t reserved;
4842};
4843
4844/*
4845 * END mvm/fw-api-scan.h
4846 */
4847
4848/*
4849 * BEGIN mvm/fw-api-sta.h
4850 */
4851
4852/**
4853 * enum iwm_sta_flags - flags for the ADD_STA host command
4854 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
4855 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
4856 * @IWM_STA_FLG_FLG_ANT_MSK: Antenna selection
4857 * @IWM_STA_FLG_PS: set if STA is in Power Save
4858 * @IWM_STA_FLG_INVALID: set if STA is invalid
4859 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
4860 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
4861 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
4862 * @IWM_STA_FLG_PAN: STA is for PAN interface
4863 * @IWM_STA_FLG_CLASS_AUTH:
4864 * @IWM_STA_FLG_CLASS_ASSOC:
4865 * @IWM_STA_FLG_CLASS_MIMO_PROT:
4866 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
4867 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
4868 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
4869 * initialised by driver and can be updated by fw upon reception of
4870 * action frames that can change the channel width. When cleared the fw
4871 * will send all the frames in 20MHz even when FAT channel is requested.
4872 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
4873 * driver and can be updated by fw upon reception of action frames.
4874 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
4875 */
4876enum iwm_sta_flags {
4877 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
4878 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
4879
4880 IWM_STA_FLG_FLG_ANT_A = (1 << 4),
4881 IWM_STA_FLG_FLG_ANT_B = (2 << 4),
4882 IWM_STA_FLG_FLG_ANT_MSK = (IWM_STA_FLG_FLG_ANT_A |
4883 IWM_STA_FLG_FLG_ANT_B),
4884
4885 IWM_STA_FLG_PS = (1 << 8),
4886 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
4887 IWM_STA_FLG_PAN = (1 << 13),
4888 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
4889 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
4890 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
4891
4892 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
4893 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4894 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4895 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4896 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4897 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4898 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4899 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4900 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4901 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4902
4903 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
4904 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4905 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4906 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4907 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4908 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4909
4910 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
4911 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
4912 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
4913 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
4914 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
4915
4916 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
4917 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
4918 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
4919 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
4920};
4921
4922/**
4923 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
4924 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
4925 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
4926 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
4927 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
4928 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
4929 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
4930 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
4931 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
4932 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
4933 * station info array (1 - n 1X mode)
4934 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
4935 * @IWM_STA_KEY_NOT_VALID: key is invalid
4936 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
4937 * @IWM_STA_KEY_MULTICAST: set for multical key
4938 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
4939 */
4940enum iwm_sta_key_flag {
4941 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
4942 IWM_STA_KEY_FLG_WEP = (1 << 0),
4943 IWM_STA_KEY_FLG_CCM = (2 << 0),
4944 IWM_STA_KEY_FLG_TKIP = (3 << 0),
4945 IWM_STA_KEY_FLG_EXT = (4 << 0),
4946 IWM_STA_KEY_FLG_CMAC = (6 << 0),
4947 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
4948 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
4949
4950 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
4951 IWM_STA_KEY_FLG_KEYID_POS = 8,
4952 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
4953 IWM_STA_KEY_NOT_VALID = (1 << 11),
4954 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
4955 IWM_STA_KEY_MULTICAST = (1 << 14),
4956 IWM_STA_KEY_MFP = (1 << 15),
4957};
4958
4959/**
4960 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
4961 * @IWM_STA_MODIFY_KEY: this command modifies %key
4962 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
4963 * @IWM_STA_MODIFY_TX_RATE: unused
4964 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
4965 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
4966 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
4967 * @IWM_STA_MODIFY_PROT_TH:
4968 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
4969 */
4970enum iwm_sta_modify_flag {
4971 IWM_STA_MODIFY_KEY = (1 << 0),
4972 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
4973 IWM_STA_MODIFY_TX_RATE = (1 << 2),
4974 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
4975 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
4976 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
4977 IWM_STA_MODIFY_PROT_TH = (1 << 6),
4978 IWM_STA_MODIFY_QUEUES = (1 << 7),
4979};
4980
4981#define IWM_STA_MODE_MODIFY 1
4982
4983/**
4984 * enum iwm_sta_sleep_flag - type of sleep of the station
4985 * @IWM_STA_SLEEP_STATE_AWAKE:
4986 * @IWM_STA_SLEEP_STATE_PS_POLL:
4987 * @IWM_STA_SLEEP_STATE_UAPSD:
4988 */
4989enum iwm_sta_sleep_flag {
4990 IWM_STA_SLEEP_STATE_AWAKE = 0,
4991 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
4992 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
4993};
4994
4995/* STA ID and color bits definitions */
4996#define IWM_STA_ID_SEED (0x0f)
4997#define IWM_STA_ID_POS (0)
4998#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
4999
5000#define IWM_STA_COLOR_SEED (0x7)
5001#define IWM_STA_COLOR_POS (4)
5002#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5003
5004#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5005 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5006#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5007 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5008
5009#define IWM_STA_KEY_MAX_NUM (16)
5010#define IWM_STA_KEY_IDX_INVALID (0xff)
5011#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5012#define IWM_MAX_GLOBAL_KEYS (4)
5013#define IWM_STA_KEY_LEN_WEP40 (5)
5014#define IWM_STA_KEY_LEN_WEP104 (13)
5015
5016/**
5017 * struct iwm_mvm_keyinfo - key information
5018 * @key_flags: type %iwm_sta_key_flag
5019 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5020 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5021 * @key_offset: key offset in the fw's key table
5022 * @key: 16-byte unicast decryption key
5023 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5024 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5025 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5026 */
5027struct iwm_mvm_keyinfo {
5028 uint16_t key_flags;
5029 uint8_t tkip_rx_tsc_byte2;
5030 uint8_t reserved1;
5031 uint16_t tkip_rx_ttak[5];
5032 uint8_t key_offset;
5033 uint8_t reserved2;
5034 uint8_t key[16];
5035 uint64_t tx_secur_seq_cnt;
5036 uint64_t hw_tkip_mic_rx_key;
5037 uint64_t hw_tkip_mic_tx_key;
5038} __packed;
5039
5040/**
5041 * struct iwm_mvm_add_sta_cmd_v5 - Add/modify a station in the fw's sta table.
5042 * ( IWM_REPLY_ADD_STA = 0x18 )
5043 * @add_modify: 1: modify existing, 0: add new station
5044 * @unicast_tx_key_id: unicast tx key id. Relevant only when unicast key sent
5045 * @multicast_tx_key_id: multicast tx key id. Relevant only when multicast key
5046 * sent
5047 * @mac_id_n_color: the Mac context this station belongs to
5048 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5049 * @sta_id: index of station in uCode's station table
5050 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5051 * alone. 1 - modify, 0 - don't change.
5052 * @key: look at %iwm_mvm_keyinfo
5053 * @station_flags: look at %iwm_sta_flags
5054 * @station_flags_msk: what of %station_flags have changed
5055 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5056 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5057 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5058 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5059 * add_immediate_ba_ssn.
5060 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5061 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5062 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5063 * add_immediate_ba_tid.
5064 * @sleep_tx_count: number of packets to transmit to station even though it is
5065 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5066 * keeps track of STA sleep state.
5067 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5068 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5069 * mac-addr.
5070 * @beamform_flags: beam forming controls
5071 * @tfd_queue_msk: tfd queues used by this station
5072 *
5073 * The device contains an internal table of per-station information, with info
5074 * on security keys, aggregation parameters, and Tx rates for initial Tx
5075 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5076 *
5077 * ADD_STA sets up the table entry for one station, either creating a new
5078 * entry, or modifying a pre-existing one.
5079 */
5080struct iwm_mvm_add_sta_cmd_v5 {
5081 uint8_t add_modify;
5082 uint8_t unicast_tx_key_id;
5083 uint8_t multicast_tx_key_id;
5084 uint8_t reserved1;
5085 uint32_t mac_id_n_color;
5086 uint8_t addr[IEEE80211_ADDR_LEN];
5087 uint16_t reserved2;
5088 uint8_t sta_id;
5089 uint8_t modify_mask;
5090 uint16_t reserved3;
5091 struct iwm_mvm_keyinfo key;
5092 uint32_t station_flags;
5093 uint32_t station_flags_msk;
5094 uint16_t tid_disable_tx;
5095 uint16_t reserved4;
5096 uint8_t add_immediate_ba_tid;
5097 uint8_t remove_immediate_ba_tid;
5098 uint16_t add_immediate_ba_ssn;
5099 uint16_t sleep_tx_count;
5100 uint16_t sleep_state_flags;
5101 uint16_t assoc_id;
5102 uint16_t beamform_flags;
5103 uint32_t tfd_queue_msk;
5104} __packed; /* IWM_ADD_STA_CMD_API_S_VER_5 */
5105
5106/**
5107 * struct iwm_mvm_add_sta_cmd_v6 - Add / modify a station
5108 * VER_6 of this command is quite similar to VER_5 except
5109 * exclusion of all fields related to the security key installation.
5110 */
5111struct iwm_mvm_add_sta_cmd_v6 {
5112 uint8_t add_modify;
5113 uint8_t reserved1;
5114 uint16_t tid_disable_tx;
5115 uint32_t mac_id_n_color;
5116 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5117 uint16_t reserved2;
5118 uint8_t sta_id;
5119 uint8_t modify_mask;
5120 uint16_t reserved3;
5121 uint32_t station_flags;
5122 uint32_t station_flags_msk;
5123 uint8_t add_immediate_ba_tid;
5124 uint8_t remove_immediate_ba_tid;
5125 uint16_t add_immediate_ba_ssn;
5126 uint16_t sleep_tx_count;
5127 uint16_t sleep_state_flags;
5128 uint16_t assoc_id;
5129 uint16_t beamform_flags;
5130 uint32_t tfd_queue_msk;
5131} __packed; /* IWM_ADD_STA_CMD_API_S_VER_6 */
5132
5133/**
5134 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5135 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5136 * @sta_id: index of station in uCode's station table
5137 * @key_offset: key offset in key storage
5138 * @key_flags: type %iwm_sta_key_flag
5139 * @key: key material data
5140 * @key2: key material data
5141 * @rx_secur_seq_cnt: RX security sequence counter for the key
5142 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5143 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5144 */
5145struct iwm_mvm_add_sta_key_cmd {
5146 uint8_t sta_id;
5147 uint8_t key_offset;
5148 uint16_t key_flags;
5149 uint8_t key[16];
5150 uint8_t key2[16];
5151 uint8_t rx_secur_seq_cnt[16];
5152 uint8_t tkip_rx_tsc_byte2;
5153 uint8_t reserved;
5154 uint16_t tkip_rx_ttak[5];
5155} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5156
5157/**
5158 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5159 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5160 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5161 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5162 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5163 * that doesn't exist.
5164 */
5165enum iwm_mvm_add_sta_rsp_status {
5166 IWM_ADD_STA_SUCCESS = 0x1,
5167 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5168 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5169 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5170};
5171
5172/**
5173 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5174 * ( IWM_REMOVE_STA = 0x19 )
5175 * @sta_id: the station id of the station to be removed
5176 */
5177struct iwm_mvm_rm_sta_cmd {
5178 uint8_t sta_id;
5179 uint8_t reserved[3];
5180} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5181
5182/**
5183 * struct iwm_mvm_mgmt_mcast_key_cmd
5184 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5185 * @ctrl_flags: %iwm_sta_key_flag
5186 * @IGTK:
5187 * @K1: IGTK master key
5188 * @K2: IGTK sub key
5189 * @sta_id: station ID that support IGTK
5190 * @key_id:
5191 * @receive_seq_cnt: initial RSC/PN needed for replay check
5192 */
5193struct iwm_mvm_mgmt_mcast_key_cmd {
5194 uint32_t ctrl_flags;
5195 uint8_t IGTK[16];
5196 uint8_t K1[16];
5197 uint8_t K2[16];
5198 uint32_t key_id;
5199 uint32_t sta_id;
5200 uint64_t receive_seq_cnt;
5201} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5202
5203struct iwm_mvm_wep_key {
5204 uint8_t key_index;
5205 uint8_t key_offset;
5206 uint16_t reserved1;
5207 uint8_t key_size;
5208 uint8_t reserved2[3];
5209 uint8_t key[16];
5210} __packed;
5211
5212struct iwm_mvm_wep_key_cmd {
5213 uint32_t mac_id_n_color;
5214 uint8_t num_keys;
5215 uint8_t decryption_type;
5216 uint8_t flags;
5217 uint8_t reserved;
5218 struct iwm_mvm_wep_key wep_key[0];
5219} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5220
5221
5222/*
5223 * END mvm/fw-api-sta.h
5224 */
5225
5226/*
5227 * Some cherry-picked definitions
5228 */
5229
5230#define IWM_FRAME_LIMIT 64
5231
5232struct iwm_cmd_header {
5233 uint8_t code;
5234 uint8_t flags;
5235 uint8_t idx;
5236 uint8_t qid;
5237} __packed;
5238
5239enum iwm_power_scheme {
5240 IWM_POWER_SCHEME_CAM = 1,
5241 IWM_POWER_SCHEME_BPS,
5242 IWM_POWER_SCHEME_LP
5243};
5244
5245#define IWM_DEF_CMD_PAYLOAD_SIZE 320
5246#define IWM_CMD_FAILED_MSK 0x40
5247
5248struct iwm_device_cmd {
5249 struct iwm_cmd_header hdr;
5250
5251 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5252} __packed;
5253
5254struct iwm_rx_packet {
5255 /*
5256 * The first 4 bytes of the RX frame header contain both the RX frame
5257 * size and some flags.
5258 * Bit fields:
5259 * 31: flag flush RB request
5260 * 30: flag ignore TC (terminal counter) request
5261 * 29: flag fast IRQ request
5262 * 28-14: Reserved
5263 * 13-00: RX frame size
5264 */
5265 uint32_t len_n_flags;
5266 struct iwm_cmd_header hdr;
5267 uint8_t data[];
5268} __packed;
5269
5270#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5271
5272static inline uint32_t
5273iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5274{
5275
5276 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
5277}
5278
5279static inline uint32_t
5280iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
5281{
5282
5283 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
5284}
5285
5286
5287#define IWM_MIN_DBM -100
5288#define IWM_MAX_DBM -33 /* realistic guess */
5289
5290#define IWM_READ(sc, reg) \
5291 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
5292
5293#define IWM_WRITE(sc, reg, val) \
5294 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5295
5296#define IWM_WRITE_1(sc, reg, val) \
5297 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5298
5299#define IWM_SETBITS(sc, reg, mask) \
5300 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
5301
5302#define IWM_CLRBITS(sc, reg, mask) \
5303 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
5304
5305#define IWM_BARRIER_WRITE(sc) \
5306 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5307 BUS_SPACE_BARRIER_WRITE)
5308
5309#define IWM_BARRIER_READ_WRITE(sc) \
5310 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5311 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
5312
5313#define IWM_FW_VALID_TX_ANT(sc) \
5314 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN) \
5315 >> IWM_FW_PHY_CFG_TX_CHAIN_POS)
5316#define IWM_FW_VALID_RX_ANT(sc) \
5317 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RX_CHAIN) \
5318 >> IWM_FW_PHY_CFG_RX_CHAIN_POS)
5319
5320#endif /* __IF_IWM_REG_H__ */
| 4278 * and the TFD queues are empty.
4279 */
4280enum iwm_dump_control {
4281 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4282};
4283
4284/**
4285 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4286 * @queues_ctl: bitmap of queues to flush
4287 * @flush_ctl: control flags
4288 * @reserved: reserved
4289 */
4290struct iwm_tx_path_flush_cmd {
4291 uint32_t queues_ctl;
4292 uint16_t flush_ctl;
4293 uint16_t reserved;
4294} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4295
4296/**
4297 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4298 * @tx_resp: the Tx response from the fw (agg or non-agg)
4299 *
4300 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4301 * it can't know that everything will go well until the end of the AMPDU, it
4302 * can't know in advance the number of MPDUs that will be sent in the current
4303 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4304 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4305 * of the batch. This is why the SSN of the SCD is written at the end of the
4306 * whole struct at a variable offset. This function knows how to cope with the
4307 * variable offset and returns the SSN of the SCD.
4308 */
4309static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4310{
4311 return le32_to_cpup((uint32_t *)&tx_resp->status +
4312 tx_resp->frame_count) & 0xfff;
4313}
4314
4315/*
4316 * END mvm/fw-api-tx.h
4317 */
4318
4319/*
4320 * BEGIN mvm/fw-api-scan.h
4321 */
4322
4323/* Scan Commands, Responses, Notifications */
4324
4325/* Masks for iwm_scan_channel.type flags */
4326#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4327#define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22)
4328
4329/* Max number of IEs for direct SSID scans in a command */
4330#define IWM_PROBE_OPTION_MAX 20
4331
4332/**
4333 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table
4334 * @channel: band is selected by iwm_scan_cmd "flags" field
4335 * @tx_gain: gain for analog radio
4336 * @dsp_atten: gain for DSP
4337 * @active_dwell: dwell time for active scan in TU, typically 5-50
4338 * @passive_dwell: dwell time for passive scan in TU, typically 20-500
4339 * @type: type is broken down to these bits:
4340 * bit 0: 0 = passive, 1 = active
4341 * bits 1-20: SSID direct bit map. If any of these bits is set then
4342 * the corresponding SSID IE is transmitted in probe request
4343 * (bit i adds IE in position i to the probe request)
4344 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel
4345 *
4346 * @iteration_count:
4347 * @iteration_interval:
4348 * This struct is used once for each channel in the scan list.
4349 * Each channel can independently select:
4350 * 1) SSID for directed active scans
4351 * 2) Txpower setting (for rate specified within Tx command)
4352 * 3) How long to stay on-channel (behavior may be modified by quiet_time,
4353 * quiet_plcp_th, good_CRC_th)
4354 *
4355 * To avoid uCode errors, make sure the following are true (see comments
4356 * under struct iwm_scan_cmd about max_out_time and quiet_time):
4357 * 1) If using passive_dwell (i.e. passive_dwell != 0):
4358 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
4359 * 2) quiet_time <= active_dwell
4360 * 3) If restricting off-channel time (i.e. max_out_time !=0):
4361 * passive_dwell < max_out_time
4362 * active_dwell < max_out_time
4363 */
4364struct iwm_scan_channel {
4365 uint32_t type;
4366 uint16_t channel;
4367 uint16_t iteration_count;
4368 uint32_t iteration_interval;
4369 uint16_t active_dwell;
4370 uint16_t passive_dwell;
4371} __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */
4372
4373/**
4374 * struct iwm_ssid_ie - directed scan network information element
4375 *
4376 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4377 * selected by "type" bit field in struct iwm_scan_channel;
4378 * each channel may select different ssids from among the 20 entries.
4379 * SSID IEs get transmitted in reverse order of entry.
4380 */
4381struct iwm_ssid_ie {
4382 uint8_t id;
4383 uint8_t len;
4384 uint8_t ssid[IEEE80211_NWID_LEN];
4385} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4386
4387/**
4388 * iwm_scan_flags - masks for scan command flags
4389 *@IWM_SCAN_FLAGS_PERIODIC_SCAN:
4390 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX:
4391 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND:
4392 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND:
4393 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN:
4394 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active
4395 * in the past hour, even if they are marked as passive.
4396 */
4397enum iwm_scan_flags {
4398 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0),
4399 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1),
4400 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2),
4401 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3),
4402 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4),
4403 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5),
4404};
4405
4406/**
4407 * enum iwm_scan_type - Scan types for scan command
4408 * @IWM_SCAN_TYPE_FORCED:
4409 * @IWM_SCAN_TYPE_BACKGROUND:
4410 * @IWM_SCAN_TYPE_OS:
4411 * @IWM_SCAN_TYPE_ROAMING:
4412 * @IWM_SCAN_TYPE_ACTION:
4413 * @IWM_SCAN_TYPE_DISCOVERY:
4414 * @IWM_SCAN_TYPE_DISCOVERY_FORCED:
4415 */
4416enum iwm_scan_type {
4417 IWM_SCAN_TYPE_FORCED = 0,
4418 IWM_SCAN_TYPE_BACKGROUND = 1,
4419 IWM_SCAN_TYPE_OS = 2,
4420 IWM_SCAN_TYPE_ROAMING = 3,
4421 IWM_SCAN_TYPE_ACTION = 4,
4422 IWM_SCAN_TYPE_DISCOVERY = 5,
4423 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6,
4424}; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */
4425
4426/* Maximal number of channels to scan */
4427#define IWM_MAX_NUM_SCAN_CHANNELS 0x24
4428
4429/**
4430 * struct iwm_scan_cmd - scan request command
4431 * ( IWM_SCAN_REQUEST_CMD = 0x80 )
4432 * @len: command length in bytes
4433 * @scan_flags: scan flags from IWM_SCAN_FLAGS_*
4434 * @channel_count: num of channels in channel list (1 - IWM_MAX_NUM_SCAN_CHANNELS)
4435 * @quiet_time: in msecs, dwell this time for active scan on quiet channels
4436 * @quiet_plcp_th: quiet PLCP threshold (channel is quiet if less than
4437 * this number of packets were received (typically 1)
4438 * @passive2active: is auto switching from passive to active during scan allowed
4439 * @rxchain_sel_flags: RXON_RX_CHAIN_*
4440 * @max_out_time: in usecs, max out of serving channel time
4441 * @suspend_time: how long to pause scan when returning to service channel:
4442 * bits 0-19: beacon interval in usecs (suspend before executing)
4443 * bits 20-23: reserved
4444 * bits 24-31: number of beacons (suspend between channels)
4445 * @rxon_flags: RXON_FLG_*
4446 * @filter_flags: RXON_FILTER_*
4447 * @tx_cmd: for active scans (zero for passive), w/o payload,
4448 * no RS so specify TX rate
4449 * @direct_scan: direct scan SSIDs
4450 * @type: one of IWM_SCAN_TYPE_*
4451 * @repeats: how many time to repeat the scan
4452 */
4453struct iwm_scan_cmd {
4454 uint16_t len;
4455 uint8_t scan_flags;
4456 uint8_t channel_count;
4457 uint16_t quiet_time;
4458 uint16_t quiet_plcp_th;
4459 uint16_t passive2active;
4460 uint16_t rxchain_sel_flags;
4461 uint32_t max_out_time;
4462 uint32_t suspend_time;
4463 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4464 uint32_t rxon_flags;
4465 uint32_t filter_flags;
4466 struct iwm_tx_cmd tx_cmd;
4467 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4468 uint32_t type;
4469 uint32_t repeats;
4470
4471 /*
4472 * Probe request frame, followed by channel list.
4473 *
4474 * Size of probe request frame is specified by byte count in tx_cmd.
4475 * Channel list follows immediately after probe request frame.
4476 * Number of channels in list is specified by channel_count.
4477 * Each channel in list is of type:
4478 *
4479 * struct iwm_scan_channel channels[0];
4480 *
4481 * NOTE: Only one band of channels can be scanned per pass. You
4482 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
4483 * for one scan to complete (i.e. receive IWM_SCAN_COMPLETE_NOTIFICATION)
4484 * before requesting another scan.
4485 */
4486 uint8_t data[0];
4487} __packed; /* IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_5 */
4488
4489/* Response to scan request contains only status with one of these values */
4490#define IWM_SCAN_RESPONSE_OK 0x1
4491#define IWM_SCAN_RESPONSE_ERROR 0x2
4492
4493/*
4494 * IWM_SCAN_ABORT_CMD = 0x81
4495 * When scan abort is requested, the command has no fields except the common
4496 * header. The response contains only a status with one of these values.
4497 */
4498#define IWM_SCAN_ABORT_POSSIBLE 0x1
4499#define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */
4500
4501/* TODO: complete documentation */
4502#define IWM_SCAN_OWNER_STATUS 0x1
4503#define IWM_MEASURE_OWNER_STATUS 0x2
4504
4505/**
4506 * struct iwm_scan_start_notif - notifies start of scan in the device
4507 * ( IWM_SCAN_START_NOTIFICATION = 0x82 )
4508 * @tsf_low: TSF timer (lower half) in usecs
4509 * @tsf_high: TSF timer (higher half) in usecs
4510 * @beacon_timer: structured as follows:
4511 * bits 0:19 - beacon interval in usecs
4512 * bits 20:23 - reserved (0)
4513 * bits 24:31 - number of beacons
4514 * @channel: which channel is scanned
4515 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4516 * @status: one of *_OWNER_STATUS
4517 */
4518struct iwm_scan_start_notif {
4519 uint32_t tsf_low;
4520 uint32_t tsf_high;
4521 uint32_t beacon_timer;
4522 uint8_t channel;
4523 uint8_t band;
4524 uint8_t reserved[2];
4525 uint32_t status;
4526} __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */
4527
4528/* scan results probe_status first bit indicates success */
4529#define IWM_SCAN_PROBE_STATUS_OK 0
4530#define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0)
4531/* error statuses combined with TX_FAILED */
4532#define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1)
4533#define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2)
4534
4535/* How many statistics are gathered for each channel */
4536#define IWM_SCAN_RESULTS_STATISTICS 1
4537
4538/**
4539 * enum iwm_scan_complete_status - status codes for scan complete notifications
4540 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4541 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4542 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4543 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4544 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4545 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4546 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4547 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4548 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4549 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4550 * (not an error!)
4551 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4552 * asked for
4553 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4554*/
4555enum iwm_scan_complete_status {
4556 IWM_SCAN_COMP_STATUS_OK = 0x1,
4557 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4558 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4559 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4560 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4561 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4562 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4563 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4564 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4565 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4566 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4567 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4568};
4569
4570/**
4571 * struct iwm_scan_results_notif - scan results for one channel
4572 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4573 * @channel: which channel the results are from
4574 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4575 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4576 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4577 * @duration: duration spent in channel, in usecs
4578 * @statistics: statistics gathered for this channel
4579 */
4580struct iwm_scan_results_notif {
4581 uint8_t channel;
4582 uint8_t band;
4583 uint8_t probe_status;
4584 uint8_t num_probe_not_sent;
4585 uint32_t duration;
4586 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4587} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4588
4589/**
4590 * struct iwm_scan_complete_notif - notifies end of scanning (all channels)
4591 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 )
4592 * @scanned_channels: number of channels scanned (and number of valid results)
4593 * @status: one of IWM_SCAN_COMP_STATUS_*
4594 * @bt_status: BT on/off status
4595 * @last_channel: last channel that was scanned
4596 * @tsf_low: TSF timer (lower half) in usecs
4597 * @tsf_high: TSF timer (higher half) in usecs
4598 * @results: all scan results, only "scanned_channels" of them are valid
4599 */
4600struct iwm_scan_complete_notif {
4601 uint8_t scanned_channels;
4602 uint8_t status;
4603 uint8_t bt_status;
4604 uint8_t last_channel;
4605 uint32_t tsf_low;
4606 uint32_t tsf_high;
4607 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS];
4608} __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */
4609
4610/* scan offload */
4611#define IWM_MAX_SCAN_CHANNELS 40
4612#define IWM_SCAN_MAX_BLACKLIST_LEN 64
4613#define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4614#define IWM_SCAN_MAX_PROFILES 11
4615#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4616
4617/* Default watchdog (in MS) for scheduled scan iteration */
4618#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4619
4620#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4621#define IWM_CAN_ABORT_STATUS 1
4622
4623#define IWM_FULL_SCAN_MULTIPLIER 5
4624#define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4625
4626enum iwm_scan_framework_client {
4627 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4628 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4629 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4630};
4631
4632/**
4633 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6
4634 * @scan_flags: see enum iwm_scan_flags
4635 * @channel_count: channels in channel list
4636 * @quiet_time: dwell time, in milisiconds, on quiet channel
4637 * @quiet_plcp_th: quiet channel num of packets threshold
4638 * @good_CRC_th: passive to active promotion threshold
4639 * @rx_chain: RXON rx chain.
4640 * @max_out_time: max uSec to be out of assoceated channel
4641 * @suspend_time: pause scan this long when returning to service channel
4642 * @flags: RXON flags
4643 * @filter_flags: RXONfilter
4644 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz.
4645 * @direct_scan: list of SSIDs for directed active scan
4646 * @scan_type: see enum iwm_scan_type.
4647 * @rep_count: repetition count for each scheduled scan iteration.
4648 */
4649struct iwm_scan_offload_cmd {
4650 uint16_t len;
4651 uint8_t scan_flags;
4652 uint8_t channel_count;
4653 uint16_t quiet_time;
4654 uint16_t quiet_plcp_th;
4655 uint16_t good_CRC_th;
4656 uint16_t rx_chain;
4657 uint32_t max_out_time;
4658 uint32_t suspend_time;
4659 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4660 uint32_t flags;
4661 uint32_t filter_flags;
4662 struct iwm_tx_cmd tx_cmd[2];
4663 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4664 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4665 uint32_t scan_type;
4666 uint32_t rep_count;
4667} __packed;
4668
4669enum iwm_scan_offload_channel_flags {
4670 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0),
4671 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22),
4672 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24),
4673 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25),
4674};
4675
4676/**
4677 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S
4678 * @type: bitmap - see enum iwm_scan_offload_channel_flags.
4679 * 0: passive (0) or active (1) scan.
4680 * 1-20: directed scan to i'th ssid.
4681 * 22: channel width configuation - 1 for narrow.
4682 * 24: full scan.
4683 * 25: partial scan.
4684 * @channel_number: channel number 1-13 etc.
4685 * @iter_count: repetition count for the channel.
4686 * @iter_interval: interval between two innteration on one channel.
4687 * @dwell_time: entry 0 - active scan, entry 1 - passive scan.
4688 */
4689struct iwm_scan_channel_cfg {
4690 uint32_t type[IWM_MAX_SCAN_CHANNELS];
4691 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS];
4692 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS];
4693 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS];
4694 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2];
4695} __packed;
4696
4697/**
4698 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S
4699 * @scan_cmd: scan command fixed part
4700 * @channel_cfg: scan channel configuration
4701 * @data: probe request frames (one per band)
4702 */
4703struct iwm_scan_offload_cfg {
4704 struct iwm_scan_offload_cmd scan_cmd;
4705 struct iwm_scan_channel_cfg channel_cfg;
4706 uint8_t data[0];
4707} __packed;
4708
4709/**
4710 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4711 * @ssid: MAC address to filter out
4712 * @reported_rssi: AP rssi reported to the host
4713 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4714 */
4715struct iwm_scan_offload_blacklist {
4716 uint8_t ssid[IEEE80211_ADDR_LEN];
4717 uint8_t reported_rssi;
4718 uint8_t client_bitmap;
4719} __packed;
4720
4721enum iwm_scan_offload_network_type {
4722 IWM_NETWORK_TYPE_BSS = 1,
4723 IWM_NETWORK_TYPE_IBSS = 2,
4724 IWM_NETWORK_TYPE_ANY = 3,
4725};
4726
4727enum iwm_scan_offload_band_selection {
4728 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4729 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4730 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4731};
4732
4733/**
4734 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4735 * @ssid_index: index to ssid list in fixed part
4736 * @unicast_cipher: encryption olgorithm to match - bitmap
4737 * @aut_alg: authentication olgorithm to match - bitmap
4738 * @network_type: enum iwm_scan_offload_network_type
4739 * @band_selection: enum iwm_scan_offload_band_selection
4740 * @client_bitmap: clients waiting for match - enum scan_framework_client
4741 */
4742struct iwm_scan_offload_profile {
4743 uint8_t ssid_index;
4744 uint8_t unicast_cipher;
4745 uint8_t auth_alg;
4746 uint8_t network_type;
4747 uint8_t band_selection;
4748 uint8_t client_bitmap;
4749 uint8_t reserved[2];
4750} __packed;
4751
4752/**
4753 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4754 * @blaclist: AP list to filter off from scan results
4755 * @profiles: profiles to search for match
4756 * @blacklist_len: length of blacklist
4757 * @num_profiles: num of profiles in the list
4758 * @match_notify: clients waiting for match found notification
4759 * @pass_match: clients waiting for the results
4760 * @active_clients: active clients bitmap - enum scan_framework_client
4761 * @any_beacon_notify: clients waiting for match notification without match
4762 */
4763struct iwm_scan_offload_profile_cfg {
4764 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4765 uint8_t blacklist_len;
4766 uint8_t num_profiles;
4767 uint8_t match_notify;
4768 uint8_t pass_match;
4769 uint8_t active_clients;
4770 uint8_t any_beacon_notify;
4771 uint8_t reserved[2];
4772} __packed;
4773
4774/**
4775 * iwm_scan_offload_schedule - schedule of scan offload
4776 * @delay: delay between iterations, in seconds.
4777 * @iterations: num of scan iterations
4778 * @full_scan_mul: number of partial scans before each full scan
4779 */
4780struct iwm_scan_offload_schedule {
4781 uint16_t delay;
4782 uint8_t iterations;
4783 uint8_t full_scan_mul;
4784} __packed;
4785
4786/*
4787 * iwm_scan_offload_flags
4788 *
4789 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
4790 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
4791 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
4792 * on A band.
4793 */
4794enum iwm_scan_offload_flags {
4795 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0),
4796 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2),
4797 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3),
4798};
4799
4800/**
4801 * iwm_scan_offload_req - scan offload request command
4802 * @flags: bitmap - enum iwm_scan_offload_flags.
4803 * @watchdog: maximum scan duration in TU.
4804 * @delay: delay in seconds before first iteration.
4805 * @schedule_line: scan offload schedule, for fast and regular scan.
4806 */
4807struct iwm_scan_offload_req {
4808 uint16_t flags;
4809 uint16_t watchdog;
4810 uint16_t delay;
4811 uint16_t reserved;
4812 struct iwm_scan_offload_schedule schedule_line[2];
4813} __packed;
4814
4815enum iwm_scan_offload_compleate_status {
4816 IWM_SCAN_OFFLOAD_COMPLETED = 1,
4817 IWM_SCAN_OFFLOAD_ABORTED = 2,
4818};
4819
4820/**
4821 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1
4822 * @last_schedule_line: last schedule line executed (fast or regular)
4823 * @last_schedule_iteration: last scan iteration executed before scan abort
4824 * @status: enum iwm_scan_offload_compleate_status
4825 */
4826struct iwm_scan_offload_complete {
4827 uint8_t last_schedule_line;
4828 uint8_t last_schedule_iteration;
4829 uint8_t status;
4830 uint8_t reserved;
4831} __packed;
4832
4833/**
4834 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1
4835 * @ssid_bitmap: SSIDs indexes found in this iteration
4836 * @client_bitmap: clients that are active and wait for this notification
4837 */
4838struct iwm_sched_scan_results {
4839 uint16_t ssid_bitmap;
4840 uint8_t client_bitmap;
4841 uint8_t reserved;
4842};
4843
4844/*
4845 * END mvm/fw-api-scan.h
4846 */
4847
4848/*
4849 * BEGIN mvm/fw-api-sta.h
4850 */
4851
4852/**
4853 * enum iwm_sta_flags - flags for the ADD_STA host command
4854 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
4855 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
4856 * @IWM_STA_FLG_FLG_ANT_MSK: Antenna selection
4857 * @IWM_STA_FLG_PS: set if STA is in Power Save
4858 * @IWM_STA_FLG_INVALID: set if STA is invalid
4859 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
4860 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
4861 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
4862 * @IWM_STA_FLG_PAN: STA is for PAN interface
4863 * @IWM_STA_FLG_CLASS_AUTH:
4864 * @IWM_STA_FLG_CLASS_ASSOC:
4865 * @IWM_STA_FLG_CLASS_MIMO_PROT:
4866 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
4867 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
4868 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
4869 * initialised by driver and can be updated by fw upon reception of
4870 * action frames that can change the channel width. When cleared the fw
4871 * will send all the frames in 20MHz even when FAT channel is requested.
4872 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
4873 * driver and can be updated by fw upon reception of action frames.
4874 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
4875 */
4876enum iwm_sta_flags {
4877 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
4878 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
4879
4880 IWM_STA_FLG_FLG_ANT_A = (1 << 4),
4881 IWM_STA_FLG_FLG_ANT_B = (2 << 4),
4882 IWM_STA_FLG_FLG_ANT_MSK = (IWM_STA_FLG_FLG_ANT_A |
4883 IWM_STA_FLG_FLG_ANT_B),
4884
4885 IWM_STA_FLG_PS = (1 << 8),
4886 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
4887 IWM_STA_FLG_PAN = (1 << 13),
4888 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
4889 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
4890 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
4891
4892 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
4893 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4894 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4895 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4896 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4897 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4898 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4899 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4900 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4901 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4902
4903 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
4904 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4905 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4906 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4907 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4908 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4909
4910 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
4911 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
4912 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
4913 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
4914 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
4915
4916 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
4917 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
4918 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
4919 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
4920};
4921
4922/**
4923 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
4924 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
4925 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
4926 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
4927 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
4928 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
4929 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
4930 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
4931 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
4932 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
4933 * station info array (1 - n 1X mode)
4934 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
4935 * @IWM_STA_KEY_NOT_VALID: key is invalid
4936 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
4937 * @IWM_STA_KEY_MULTICAST: set for multical key
4938 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
4939 */
4940enum iwm_sta_key_flag {
4941 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
4942 IWM_STA_KEY_FLG_WEP = (1 << 0),
4943 IWM_STA_KEY_FLG_CCM = (2 << 0),
4944 IWM_STA_KEY_FLG_TKIP = (3 << 0),
4945 IWM_STA_KEY_FLG_EXT = (4 << 0),
4946 IWM_STA_KEY_FLG_CMAC = (6 << 0),
4947 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
4948 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
4949
4950 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
4951 IWM_STA_KEY_FLG_KEYID_POS = 8,
4952 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
4953 IWM_STA_KEY_NOT_VALID = (1 << 11),
4954 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
4955 IWM_STA_KEY_MULTICAST = (1 << 14),
4956 IWM_STA_KEY_MFP = (1 << 15),
4957};
4958
4959/**
4960 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
4961 * @IWM_STA_MODIFY_KEY: this command modifies %key
4962 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
4963 * @IWM_STA_MODIFY_TX_RATE: unused
4964 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
4965 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
4966 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
4967 * @IWM_STA_MODIFY_PROT_TH:
4968 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
4969 */
4970enum iwm_sta_modify_flag {
4971 IWM_STA_MODIFY_KEY = (1 << 0),
4972 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
4973 IWM_STA_MODIFY_TX_RATE = (1 << 2),
4974 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
4975 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
4976 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
4977 IWM_STA_MODIFY_PROT_TH = (1 << 6),
4978 IWM_STA_MODIFY_QUEUES = (1 << 7),
4979};
4980
4981#define IWM_STA_MODE_MODIFY 1
4982
4983/**
4984 * enum iwm_sta_sleep_flag - type of sleep of the station
4985 * @IWM_STA_SLEEP_STATE_AWAKE:
4986 * @IWM_STA_SLEEP_STATE_PS_POLL:
4987 * @IWM_STA_SLEEP_STATE_UAPSD:
4988 */
4989enum iwm_sta_sleep_flag {
4990 IWM_STA_SLEEP_STATE_AWAKE = 0,
4991 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
4992 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
4993};
4994
4995/* STA ID and color bits definitions */
4996#define IWM_STA_ID_SEED (0x0f)
4997#define IWM_STA_ID_POS (0)
4998#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
4999
5000#define IWM_STA_COLOR_SEED (0x7)
5001#define IWM_STA_COLOR_POS (4)
5002#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5003
5004#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5005 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5006#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5007 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5008
5009#define IWM_STA_KEY_MAX_NUM (16)
5010#define IWM_STA_KEY_IDX_INVALID (0xff)
5011#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5012#define IWM_MAX_GLOBAL_KEYS (4)
5013#define IWM_STA_KEY_LEN_WEP40 (5)
5014#define IWM_STA_KEY_LEN_WEP104 (13)
5015
5016/**
5017 * struct iwm_mvm_keyinfo - key information
5018 * @key_flags: type %iwm_sta_key_flag
5019 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5020 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5021 * @key_offset: key offset in the fw's key table
5022 * @key: 16-byte unicast decryption key
5023 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5024 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5025 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5026 */
5027struct iwm_mvm_keyinfo {
5028 uint16_t key_flags;
5029 uint8_t tkip_rx_tsc_byte2;
5030 uint8_t reserved1;
5031 uint16_t tkip_rx_ttak[5];
5032 uint8_t key_offset;
5033 uint8_t reserved2;
5034 uint8_t key[16];
5035 uint64_t tx_secur_seq_cnt;
5036 uint64_t hw_tkip_mic_rx_key;
5037 uint64_t hw_tkip_mic_tx_key;
5038} __packed;
5039
5040/**
5041 * struct iwm_mvm_add_sta_cmd_v5 - Add/modify a station in the fw's sta table.
5042 * ( IWM_REPLY_ADD_STA = 0x18 )
5043 * @add_modify: 1: modify existing, 0: add new station
5044 * @unicast_tx_key_id: unicast tx key id. Relevant only when unicast key sent
5045 * @multicast_tx_key_id: multicast tx key id. Relevant only when multicast key
5046 * sent
5047 * @mac_id_n_color: the Mac context this station belongs to
5048 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5049 * @sta_id: index of station in uCode's station table
5050 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5051 * alone. 1 - modify, 0 - don't change.
5052 * @key: look at %iwm_mvm_keyinfo
5053 * @station_flags: look at %iwm_sta_flags
5054 * @station_flags_msk: what of %station_flags have changed
5055 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5056 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5057 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5058 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5059 * add_immediate_ba_ssn.
5060 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5061 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5062 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5063 * add_immediate_ba_tid.
5064 * @sleep_tx_count: number of packets to transmit to station even though it is
5065 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5066 * keeps track of STA sleep state.
5067 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5068 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5069 * mac-addr.
5070 * @beamform_flags: beam forming controls
5071 * @tfd_queue_msk: tfd queues used by this station
5072 *
5073 * The device contains an internal table of per-station information, with info
5074 * on security keys, aggregation parameters, and Tx rates for initial Tx
5075 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5076 *
5077 * ADD_STA sets up the table entry for one station, either creating a new
5078 * entry, or modifying a pre-existing one.
5079 */
5080struct iwm_mvm_add_sta_cmd_v5 {
5081 uint8_t add_modify;
5082 uint8_t unicast_tx_key_id;
5083 uint8_t multicast_tx_key_id;
5084 uint8_t reserved1;
5085 uint32_t mac_id_n_color;
5086 uint8_t addr[IEEE80211_ADDR_LEN];
5087 uint16_t reserved2;
5088 uint8_t sta_id;
5089 uint8_t modify_mask;
5090 uint16_t reserved3;
5091 struct iwm_mvm_keyinfo key;
5092 uint32_t station_flags;
5093 uint32_t station_flags_msk;
5094 uint16_t tid_disable_tx;
5095 uint16_t reserved4;
5096 uint8_t add_immediate_ba_tid;
5097 uint8_t remove_immediate_ba_tid;
5098 uint16_t add_immediate_ba_ssn;
5099 uint16_t sleep_tx_count;
5100 uint16_t sleep_state_flags;
5101 uint16_t assoc_id;
5102 uint16_t beamform_flags;
5103 uint32_t tfd_queue_msk;
5104} __packed; /* IWM_ADD_STA_CMD_API_S_VER_5 */
5105
5106/**
5107 * struct iwm_mvm_add_sta_cmd_v6 - Add / modify a station
5108 * VER_6 of this command is quite similar to VER_5 except
5109 * exclusion of all fields related to the security key installation.
5110 */
5111struct iwm_mvm_add_sta_cmd_v6 {
5112 uint8_t add_modify;
5113 uint8_t reserved1;
5114 uint16_t tid_disable_tx;
5115 uint32_t mac_id_n_color;
5116 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5117 uint16_t reserved2;
5118 uint8_t sta_id;
5119 uint8_t modify_mask;
5120 uint16_t reserved3;
5121 uint32_t station_flags;
5122 uint32_t station_flags_msk;
5123 uint8_t add_immediate_ba_tid;
5124 uint8_t remove_immediate_ba_tid;
5125 uint16_t add_immediate_ba_ssn;
5126 uint16_t sleep_tx_count;
5127 uint16_t sleep_state_flags;
5128 uint16_t assoc_id;
5129 uint16_t beamform_flags;
5130 uint32_t tfd_queue_msk;
5131} __packed; /* IWM_ADD_STA_CMD_API_S_VER_6 */
5132
5133/**
5134 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5135 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5136 * @sta_id: index of station in uCode's station table
5137 * @key_offset: key offset in key storage
5138 * @key_flags: type %iwm_sta_key_flag
5139 * @key: key material data
5140 * @key2: key material data
5141 * @rx_secur_seq_cnt: RX security sequence counter for the key
5142 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5143 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5144 */
5145struct iwm_mvm_add_sta_key_cmd {
5146 uint8_t sta_id;
5147 uint8_t key_offset;
5148 uint16_t key_flags;
5149 uint8_t key[16];
5150 uint8_t key2[16];
5151 uint8_t rx_secur_seq_cnt[16];
5152 uint8_t tkip_rx_tsc_byte2;
5153 uint8_t reserved;
5154 uint16_t tkip_rx_ttak[5];
5155} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5156
5157/**
5158 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5159 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5160 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5161 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5162 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5163 * that doesn't exist.
5164 */
5165enum iwm_mvm_add_sta_rsp_status {
5166 IWM_ADD_STA_SUCCESS = 0x1,
5167 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5168 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5169 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5170};
5171
5172/**
5173 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5174 * ( IWM_REMOVE_STA = 0x19 )
5175 * @sta_id: the station id of the station to be removed
5176 */
5177struct iwm_mvm_rm_sta_cmd {
5178 uint8_t sta_id;
5179 uint8_t reserved[3];
5180} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5181
5182/**
5183 * struct iwm_mvm_mgmt_mcast_key_cmd
5184 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5185 * @ctrl_flags: %iwm_sta_key_flag
5186 * @IGTK:
5187 * @K1: IGTK master key
5188 * @K2: IGTK sub key
5189 * @sta_id: station ID that support IGTK
5190 * @key_id:
5191 * @receive_seq_cnt: initial RSC/PN needed for replay check
5192 */
5193struct iwm_mvm_mgmt_mcast_key_cmd {
5194 uint32_t ctrl_flags;
5195 uint8_t IGTK[16];
5196 uint8_t K1[16];
5197 uint8_t K2[16];
5198 uint32_t key_id;
5199 uint32_t sta_id;
5200 uint64_t receive_seq_cnt;
5201} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5202
5203struct iwm_mvm_wep_key {
5204 uint8_t key_index;
5205 uint8_t key_offset;
5206 uint16_t reserved1;
5207 uint8_t key_size;
5208 uint8_t reserved2[3];
5209 uint8_t key[16];
5210} __packed;
5211
5212struct iwm_mvm_wep_key_cmd {
5213 uint32_t mac_id_n_color;
5214 uint8_t num_keys;
5215 uint8_t decryption_type;
5216 uint8_t flags;
5217 uint8_t reserved;
5218 struct iwm_mvm_wep_key wep_key[0];
5219} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5220
5221
5222/*
5223 * END mvm/fw-api-sta.h
5224 */
5225
5226/*
5227 * Some cherry-picked definitions
5228 */
5229
5230#define IWM_FRAME_LIMIT 64
5231
5232struct iwm_cmd_header {
5233 uint8_t code;
5234 uint8_t flags;
5235 uint8_t idx;
5236 uint8_t qid;
5237} __packed;
5238
5239enum iwm_power_scheme {
5240 IWM_POWER_SCHEME_CAM = 1,
5241 IWM_POWER_SCHEME_BPS,
5242 IWM_POWER_SCHEME_LP
5243};
5244
5245#define IWM_DEF_CMD_PAYLOAD_SIZE 320
5246#define IWM_CMD_FAILED_MSK 0x40
5247
5248struct iwm_device_cmd {
5249 struct iwm_cmd_header hdr;
5250
5251 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5252} __packed;
5253
5254struct iwm_rx_packet {
5255 /*
5256 * The first 4 bytes of the RX frame header contain both the RX frame
5257 * size and some flags.
5258 * Bit fields:
5259 * 31: flag flush RB request
5260 * 30: flag ignore TC (terminal counter) request
5261 * 29: flag fast IRQ request
5262 * 28-14: Reserved
5263 * 13-00: RX frame size
5264 */
5265 uint32_t len_n_flags;
5266 struct iwm_cmd_header hdr;
5267 uint8_t data[];
5268} __packed;
5269
5270#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5271
5272static inline uint32_t
5273iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5274{
5275
5276 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
5277}
5278
5279static inline uint32_t
5280iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
5281{
5282
5283 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
5284}
5285
5286
5287#define IWM_MIN_DBM -100
5288#define IWM_MAX_DBM -33 /* realistic guess */
5289
5290#define IWM_READ(sc, reg) \
5291 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
5292
5293#define IWM_WRITE(sc, reg, val) \
5294 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5295
5296#define IWM_WRITE_1(sc, reg, val) \
5297 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5298
5299#define IWM_SETBITS(sc, reg, mask) \
5300 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
5301
5302#define IWM_CLRBITS(sc, reg, mask) \
5303 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
5304
5305#define IWM_BARRIER_WRITE(sc) \
5306 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5307 BUS_SPACE_BARRIER_WRITE)
5308
5309#define IWM_BARRIER_READ_WRITE(sc) \
5310 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5311 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
5312
5313#define IWM_FW_VALID_TX_ANT(sc) \
5314 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN) \
5315 >> IWM_FW_PHY_CFG_TX_CHAIN_POS)
5316#define IWM_FW_VALID_RX_ANT(sc) \
5317 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RX_CHAIN) \
5318 >> IWM_FW_PHY_CFG_RX_CHAIN_POS)
5319
5320#endif /* __IF_IWM_REG_H__ */
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