1/* $FreeBSD: head/sys/dev/ipw/if_ipw.c 148887 2005-08-09 10:20:02Z rwatson $ */
2
3/*-
4 * Copyright (c) 2004, 2005
5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/ipw/if_ipw.c 148887 2005-08-09 10:20:02Z rwatson $");
32
33/*-
34 * Intel(R) PRO/Wireless 2100 MiniPCI driver
35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm
36 */
37
38#include <sys/param.h>
39#include <sys/sysctl.h>
40#include <sys/sockio.h>
41#include <sys/mbuf.h>
42#include <sys/kernel.h>
43#include <sys/socket.h>
44#include <sys/systm.h>
45#include <sys/malloc.h>
46#include <sys/module.h>
47#include <sys/bus.h>
48#include <sys/endian.h>
49
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <machine/clock.h>
53#include <sys/rman.h>
54
55#include <dev/pci/pcireg.h>
56#include <dev/pci/pcivar.h>
57
58#include <net/bpf.h>
59#include <net/if.h>
60#include <net/if_arp.h>
61#include <net/ethernet.h>
62#include <net/if_dl.h>
63#include <net/if_media.h>
64#include <net/if_types.h>
65
66#include <netinet/in.h>
67#include <netinet/in_systm.h>
68#include <netinet/in_var.h>
69#include <netinet/ip.h>
70#include <netinet/if_ether.h>
71
72#include <net80211/ieee80211_var.h>
73#include <net80211/ieee80211_radiotap.h>
74
75#include <dev/ipw/if_ipwreg.h>
76#include <dev/ipw/if_ipwvar.h>
77
78#ifdef IPW_DEBUG
79#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0)
80#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0)
81int ipw_debug = 0;
82SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level");
83#else
84#define DPRINTF(x)
85#define DPRINTFN(n, x)
86#endif
87
88MODULE_DEPEND(ipw, pci, 1, 1, 1);
89MODULE_DEPEND(ipw, wlan, 1, 1, 1);
90
91struct ipw_ident {
92 uint16_t vendor;
93 uint16_t device;
94 const char *name;
95};
96
97static const struct ipw_ident ipw_ident_table[] = {
98 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" },
99
100 { 0, 0, NULL }
101};
102
103static int ipw_dma_alloc(struct ipw_softc *);
104static void ipw_release(struct ipw_softc *);
105static int ipw_media_change(struct ifnet *);
106static void ipw_media_status(struct ifnet *, struct ifmediareq *);
107static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int);
108static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t);
109static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *);
110static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *);
111static void ipw_data_intr(struct ipw_softc *, struct ipw_status *,
112 struct ipw_soft_bd *, struct ipw_soft_buf *);
113static void ipw_rx_intr(struct ipw_softc *);
114static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *);
115static void ipw_tx_intr(struct ipw_softc *);
116static void ipw_intr(void *);
117static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int);
118static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t);
119static int ipw_tx_start(struct ifnet *, struct mbuf *,
120 struct ieee80211_node *);
121static void ipw_start(struct ifnet *);
122static void ipw_watchdog(struct ifnet *);
123static int ipw_ioctl(struct ifnet *, u_long, caddr_t);
124static void ipw_stop_master(struct ipw_softc *);
125static int ipw_reset(struct ipw_softc *);
126static int ipw_load_ucode(struct ipw_softc *, u_char *, int);
127static int ipw_load_firmware(struct ipw_softc *, u_char *, int);
128static int ipw_cache_firmware(struct ipw_softc *, void *);
129static void ipw_free_firmware(struct ipw_softc *);
130static int ipw_config(struct ipw_softc *);
131static void ipw_init(void *);
132static void ipw_stop(void *);
133#ifdef IPW_DEBUG
134static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS);
135#endif
136static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS);
137static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t);
138static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t);
139static int ipw_read_table2(struct ipw_softc *, uint32_t, void *,
140 uint32_t *);
141static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *,
142 bus_size_t);
143static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *,
144 bus_size_t);
145
146static int ipw_probe(device_t);
147static int ipw_attach(device_t);
148static int ipw_detach(device_t);
149static int ipw_shutdown(device_t);
150static int ipw_suspend(device_t);
151static int ipw_resume(device_t);
152
153static device_method_t ipw_methods[] = {
154 /* Device interface */
155 DEVMETHOD(device_probe, ipw_probe),
156 DEVMETHOD(device_attach, ipw_attach),
157 DEVMETHOD(device_detach, ipw_detach),
158 DEVMETHOD(device_shutdown, ipw_shutdown),
159 DEVMETHOD(device_suspend, ipw_suspend),
160 DEVMETHOD(device_resume, ipw_resume),
161
162 { 0, 0 }
163};
164
165static driver_t ipw_driver = {
166 "ipw",
167 ipw_methods,
168 sizeof (struct ipw_softc)
169};
170
171static devclass_t ipw_devclass;
172
173DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0);
174
175/*
176 * Supported rates for 802.11b mode (in 500Kbps unit).
177 */
178static const struct ieee80211_rateset ipw_rateset_11b =
179 { 4, { 2, 4, 11, 22 } };
180
181static __inline uint8_t
182MEM_READ_1(struct ipw_softc *sc, uint32_t addr)
183{
184 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
185 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA);
186}
187
188static __inline uint32_t
189MEM_READ_4(struct ipw_softc *sc, uint32_t addr)
190{
191 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
192 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA);
193}
194
195static int
196ipw_probe(device_t dev)
197{
198 const struct ipw_ident *ident;
199
200 for (ident = ipw_ident_table; ident->name != NULL; ident++) {
201 if (pci_get_vendor(dev) == ident->vendor &&
202 pci_get_device(dev) == ident->device) {
203 device_set_desc(dev, ident->name);
204 return 0;
205 }
206 }
207 return ENXIO;
208}
209
210/* Base Address Register */
211#define IPW_PCI_BAR0 0x10
212
213static int
214ipw_attach(device_t dev)
215{
216 struct ipw_softc *sc = device_get_softc(dev);
217 struct ifnet *ifp;
218 struct ieee80211com *ic = &sc->sc_ic;
219 uint16_t val;
220 int error, i;
221
222 sc->sc_dev = dev;
223
224 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
225 MTX_DEF | MTX_RECURSE);
226
227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
228 device_printf(dev, "chip is in D%d power mode "
229 "-- setting to D0\n", pci_get_powerstate(dev));
230 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
231 }
232
233 pci_write_config(dev, 0x41, 0, 1);
234
235 /* enable bus-mastering */
236 pci_enable_busmaster(dev);
237
238 sc->mem_rid = IPW_PCI_BAR0;
239 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
240 RF_ACTIVE);
241 if (sc->mem == NULL) {
242 device_printf(dev, "could not allocate memory resource\n");
243 goto fail;
244 }
245
246 sc->sc_st = rman_get_bustag(sc->mem);
247 sc->sc_sh = rman_get_bushandle(sc->mem);
248
249 sc->irq_rid = 0;
250 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
251 RF_ACTIVE | RF_SHAREABLE);
252 if (sc->irq == NULL) {
253 device_printf(dev, "could not allocate interrupt resource\n");
254 goto fail;
255 }
256
257 if (ipw_reset(sc) != 0) {
258 device_printf(dev, "could not reset adapter\n");
259 goto fail;
260 }
261
262 if (ipw_dma_alloc(sc) != 0) {
263 device_printf(dev, "could not allocate DMA resources\n");
264 goto fail;
265 }
266
267 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
268 if (ifp == NULL) {
269 device_printf(dev, "can not if_alloc()\n");
270 goto fail;
271 }
272
273 ifp->if_softc = sc;
274 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
275 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
276 ifp->if_init = ipw_init;
277 ifp->if_ioctl = ipw_ioctl;
278 ifp->if_start = ipw_start;
279 ifp->if_watchdog = ipw_watchdog;
280 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
281 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
282 IFQ_SET_READY(&ifp->if_snd);
283
284 ic->ic_ifp = ifp;
285 ic->ic_phytype = IEEE80211_T_DS;
286 ic->ic_opmode = IEEE80211_M_STA;
287 ic->ic_state = IEEE80211_S_INIT;
288
289 /* set device capabilities */
290 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT |
291 IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR |
292 IEEE80211_C_WPA;
293
294 /* read MAC address from EEPROM */
295 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0);
296 ic->ic_myaddr[0] = val >> 8;
297 ic->ic_myaddr[1] = val & 0xff;
298 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1);
299 ic->ic_myaddr[2] = val >> 8;
300 ic->ic_myaddr[3] = val & 0xff;
301 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2);
302 ic->ic_myaddr[4] = val >> 8;
303 ic->ic_myaddr[5] = val & 0xff;
304
305 /* set supported .11b rates */
306 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b;
307
308 /* set supported .11b channels (read from EEPROM) */
309 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0)
310 val = 0x7ff; /* default to channels 1-11 */
311 val <<= 1;
312 for (i = 1; i < 16; i++) {
313 if (val & (1 << i)) {
314 ic->ic_channels[i].ic_freq =
315 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B);
316 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B;
317 }
318 }
319
320 /* check support for radio transmitter switch in EEPROM */
321 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8))
322 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH;
323
324 ieee80211_ifattach(ic);
325 /* override state transition machine */
326 sc->sc_newstate = ic->ic_newstate;
327 ic->ic_newstate = ipw_newstate;
328 ieee80211_media_init(ic, ipw_media_change, ipw_media_status);
329
330 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
331 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf);
332
333 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
334 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
335 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT);
336
337 sc->sc_txtap_len = sizeof sc->sc_txtapu;
338 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
339 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT);
340
341 /*
342 * Add a few sysctl knobs.
343 */
344 sc->dwelltime = 100;
345
346 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
347 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio",
348 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I",
349 "radio transmitter switch state (0=off, 1=on)");
350
351#ifdef IPW_DEBUG
352 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
353 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats",
354 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S",
355 "statistics");
356#endif
357
358 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
359 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell",
360 CTLFLAG_RW, &sc->dwelltime, 0,
361 "channel dwell time (ms) for AP/station scanning");
362
363 /*
364 * Hook our interrupt after all initialization is complete.
365 */
366 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
367 ipw_intr, sc, &sc->sc_ih);
368 if (error != 0) {
369 device_printf(dev, "could not set up interrupt\n");
370 goto fail;
371 }
372
373 if (bootverbose)
374 ieee80211_announce(ic);
375
376 return 0;
377
378fail: ipw_detach(dev);
379 return ENXIO;
380}
381
382static int
383ipw_detach(device_t dev)
384{
385 struct ipw_softc *sc = device_get_softc(dev);
386 struct ieee80211com *ic = &sc->sc_ic;
387 struct ifnet *ifp = ic->ic_ifp;
388
389 IPW_LOCK(sc);
390
391 ipw_stop(sc);
392 ipw_free_firmware(sc);
393
394 IPW_UNLOCK(sc);
395
396 if (ifp != NULL) {
397 bpfdetach(ifp);
398 ieee80211_ifdetach(ic);
399 if_free(ifp);
400 }
401
402 ipw_release(sc);
403
404 if (sc->irq != NULL) {
405 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
406 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
407 }
408
409 if (sc->mem != NULL)
410 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
411
412 mtx_destroy(&sc->sc_mtx);
413
414 return 0;
415}
416
417static int
418ipw_dma_alloc(struct ipw_softc *sc)
419{
420 struct ipw_soft_bd *sbd;
421 struct ipw_soft_hdr *shdr;
422 struct ipw_soft_buf *sbuf;
423 bus_addr_t physaddr;
424 int error, i;
425
426 /*
427 * Allocate and map tx ring.
428 */
429 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
430 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL,
431 NULL, &sc->tbd_dmat);
432 if (error != 0) {
433 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n");
434 goto fail;
435 }
436
437 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list,
438 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map);
439 if (error != 0) {
440 device_printf(sc->sc_dev,
441 "could not allocate tx ring DMA memory\n");
442 goto fail;
443 }
444
445 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list,
446 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0);
447 if (error != 0) {
448 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n");
449 goto fail;
450 }
451
452 /*
453 * Allocate and map rx ring.
454 */
455 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
456 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL,
457 NULL, &sc->rbd_dmat);
458 if (error != 0) {
459 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n");
460 goto fail;
461 }
462
463 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list,
464 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map);
465 if (error != 0) {
466 device_printf(sc->sc_dev,
467 "could not allocate rx ring DMA memory\n");
468 goto fail;
469 }
470
471 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list,
472 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0);
473 if (error != 0) {
474 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n");
475 goto fail;
476 }
477
478 /*
479 * Allocate and map status ring.
480 */
481 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
482 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0,
483 NULL, NULL, &sc->status_dmat);
484 if (error != 0) {
485 device_printf(sc->sc_dev,
486 "could not create status ring DMA tag\n");
487 goto fail;
488 }
489
490 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list,
491 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map);
492 if (error != 0) {
493 device_printf(sc->sc_dev,
494 "could not allocate status ring DMA memory\n");
495 goto fail;
496 }
497
498 error = bus_dmamap_load(sc->status_dmat, sc->status_map,
499 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys,
500 0);
501 if (error != 0) {
502 device_printf(sc->sc_dev,
503 "could not map status ring DMA memory\n");
504 goto fail;
505 }
506
507 /*
508 * Allocate command DMA map.
509 */
510 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
511 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1,
512 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat);
513 if (error != 0) {
514 device_printf(sc->sc_dev, "could not create command DMA tag\n");
515 goto fail;
516 }
517
518 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map);
519 if (error != 0) {
520 device_printf(sc->sc_dev,
521 "could not create command DMA map\n");
522 goto fail;
523 }
524
525 /*
526 * Allocate headers DMA maps.
527 */
528 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
529 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1,
530 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat);
531 if (error != 0) {
532 device_printf(sc->sc_dev, "could not create header DMA tag\n");
533 goto fail;
534 }
535
536 SLIST_INIT(&sc->free_shdr);
537 for (i = 0; i < IPW_NDATA; i++) {
538 shdr = &sc->shdr_list[i];
539 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map);
540 if (error != 0) {
541 device_printf(sc->sc_dev,
542 "could not create header DMA map\n");
543 goto fail;
544 }
545 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next);
546 }
547
548 /*
549 * Allocate tx buffers DMA maps.
550 */
551 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
552 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0,
553 NULL, NULL, &sc->txbuf_dmat);
554 if (error != 0) {
555 device_printf(sc->sc_dev, "could not create tx DMA tag\n");
556 goto fail;
557 }
558
559 SLIST_INIT(&sc->free_sbuf);
560 for (i = 0; i < IPW_NDATA; i++) {
561 sbuf = &sc->tx_sbuf_list[i];
562 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map);
563 if (error != 0) {
564 device_printf(sc->sc_dev,
565 "could not create tx DMA map\n");
566 goto fail;
567 }
568 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next);
569 }
570
571 /*
572 * Initialize tx ring.
573 */
574 for (i = 0; i < IPW_NTBD; i++) {
575 sbd = &sc->stbd_list[i];
576 sbd->bd = &sc->tbd_list[i];
577 sbd->type = IPW_SBD_TYPE_NOASSOC;
578 }
579
580 /*
581 * Pre-allocate rx buffers and DMA maps.
582 */
583 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
584 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL,
585 NULL, &sc->rxbuf_dmat);
586 if (error != 0) {
587 device_printf(sc->sc_dev, "could not create rx DMA tag\n");
588 goto fail;
589 }
590
591 for (i = 0; i < IPW_NRBD; i++) {
592 sbd = &sc->srbd_list[i];
593 sbuf = &sc->rx_sbuf_list[i];
594 sbd->bd = &sc->rbd_list[i];
595
596 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
597 if (sbuf->m == NULL) {
598 device_printf(sc->sc_dev,
599 "could not allocate rx mbuf\n");
600 error = ENOMEM;
601 goto fail;
602 }
603
604 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map);
605 if (error != 0) {
606 device_printf(sc->sc_dev,
607 "could not create rx DMA map\n");
608 goto fail;
609 }
610
611 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map,
612 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr,
613 &physaddr, 0);
614 if (error != 0) {
615 device_printf(sc->sc_dev,
616 "could not map rx DMA memory\n");
617 goto fail;
618 }
619
620 sbd->type = IPW_SBD_TYPE_DATA;
621 sbd->priv = sbuf;
622 sbd->bd->physaddr = htole32(physaddr);
623 sbd->bd->len = htole32(MCLBYTES);
624 }
625
626 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE);
627
628 return 0;
629
630fail: ipw_release(sc);
631 return error;
632}
633
634static void
635ipw_release(struct ipw_softc *sc)
636{
637 struct ipw_soft_buf *sbuf;
638 int i;
639
640 if (sc->tbd_dmat != NULL) {
641 if (sc->stbd_list != NULL) {
642 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map);
643 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list,
644 sc->tbd_map);
645 }
646 bus_dma_tag_destroy(sc->tbd_dmat);
647 }
648
649 if (sc->rbd_dmat != NULL) {
650 if (sc->rbd_list != NULL) {
651 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map);
652 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list,
653 sc->rbd_map);
654 }
655 bus_dma_tag_destroy(sc->rbd_dmat);
656 }
657
658 if (sc->status_dmat != NULL) {
659 if (sc->status_list != NULL) {
660 bus_dmamap_unload(sc->status_dmat, sc->status_map);
661 bus_dmamem_free(sc->status_dmat, sc->status_list,
662 sc->status_map);
663 }
664 bus_dma_tag_destroy(sc->status_dmat);
665 }
666
667 for (i = 0; i < IPW_NTBD; i++)
668 ipw_release_sbd(sc, &sc->stbd_list[i]);
669
670 if (sc->cmd_dmat != NULL) {
671 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map);
672 bus_dma_tag_destroy(sc->cmd_dmat);
673 }
674
675 if (sc->hdr_dmat != NULL) {
676 for (i = 0; i < IPW_NDATA; i++)
677 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map);
678 bus_dma_tag_destroy(sc->hdr_dmat);
679 }
680
681 if (sc->txbuf_dmat != NULL) {
682 for (i = 0; i < IPW_NDATA; i++) {
683 bus_dmamap_destroy(sc->txbuf_dmat,
684 sc->tx_sbuf_list[i].map);
685 }
686 bus_dma_tag_destroy(sc->txbuf_dmat);
687 }
688
689 if (sc->rxbuf_dmat != NULL) {
690 for (i = 0; i < IPW_NRBD; i++) {
691 sbuf = &sc->rx_sbuf_list[i];
692 if (sbuf->m != NULL) {
693 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map,
694 BUS_DMASYNC_POSTREAD);
695 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map);
696 m_freem(sbuf->m);
697 }
698 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map);
699 }
700 bus_dma_tag_destroy(sc->rxbuf_dmat);
701 }
702}
703
704static int
705ipw_shutdown(device_t dev)
706{
707 struct ipw_softc *sc = device_get_softc(dev);
708
709 ipw_stop(sc);
710
711 return 0;
712}
713
714static int
715ipw_suspend(device_t dev)
716{
717 struct ipw_softc *sc = device_get_softc(dev);
718
719 ipw_stop(sc);
720
721 return 0;
722}
723
724static int
725ipw_resume(device_t dev)
726{
727 struct ipw_softc *sc = device_get_softc(dev);
728 struct ifnet *ifp = sc->sc_ic.ic_ifp;
729
730 IPW_LOCK(sc);
731
732 pci_write_config(dev, 0x41, 0, 1);
733
734 if (ifp->if_flags & IFF_UP) {
735 ifp->if_init(ifp->if_softc);
736 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
737 ifp->if_start(ifp);
738 }
739
740 IPW_UNLOCK(sc);
741
742 return 0;
743}
744
745static int
746ipw_media_change(struct ifnet *ifp)
747{
748 struct ipw_softc *sc = ifp->if_softc;
749 int error;
750
751 IPW_LOCK(sc);
752
753 error = ieee80211_media_change(ifp);
754 if (error != ENETRESET) {
755 IPW_UNLOCK(sc);
756 return error;
757 }
758
759 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
760 ipw_init(sc);
761
762 IPW_UNLOCK(sc);
763
764 return 0;
765}
766
767/*
768 * The firmware automaticly adapt the transmit speed. We report the current
769 * transmit speed here.
770 */
771static void
772ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
773{
774#define N(a) (sizeof (a) / sizeof (a[0]))
775 struct ipw_softc *sc = ifp->if_softc;
776 struct ieee80211com *ic = &sc->sc_ic;
777 static const struct {
778 uint32_t val;
779 int rate;
780 } rates[] = {
781 { IPW_RATE_DS1, 2 },
782 { IPW_RATE_DS2, 4 },
783 { IPW_RATE_DS5, 11 },
784 { IPW_RATE_DS11, 22 },
785 };
786 uint32_t val;
787 int rate, i;
788
789 imr->ifm_status = IFM_AVALID;
790 imr->ifm_active = IFM_IEEE80211;
791 if (ic->ic_state == IEEE80211_S_RUN)
792 imr->ifm_status |= IFM_ACTIVE;
793
794 /* read current transmission rate from adapter */
795 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf;
796
797 /* convert ipw rate to 802.11 rate */
798 for (i = 0; i < N(rates) && rates[i].val != val; i++);
799 rate = (i < N(rates)) ? rates[i].rate : 0;
800
801 imr->ifm_active |= IFM_IEEE80211_11B;
802 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B);
803 switch (ic->ic_opmode) {
804 case IEEE80211_M_STA:
805 break;
806
807 case IEEE80211_M_IBSS:
808 imr->ifm_active |= IFM_IEEE80211_IBSS;
809 break;
810
811 case IEEE80211_M_MONITOR:
812 imr->ifm_active |= IFM_IEEE80211_MONITOR;
813 break;
814
815 case IEEE80211_M_AHDEMO:
816 case IEEE80211_M_HOSTAP:
817 /* should not get there */
818 break;
819 }
820#undef N
821}
822
823static int
824ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
825{
826 struct ifnet *ifp = ic->ic_ifp;
827 struct ipw_softc *sc = ifp->if_softc;
828 struct ieee80211_node *ni;
829 uint8_t macaddr[IEEE80211_ADDR_LEN];
830 uint32_t len;
831
832 switch (nstate) {
833 case IEEE80211_S_RUN:
834 DELAY(200); /* firmware needs a short delay here */
835
836 len = IEEE80211_ADDR_LEN;
837 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len);
838
839 ni = ieee80211_find_node(&ic->ic_scan, macaddr);
840 if (ni == NULL)
841 break;
842
843 ieee80211_ref_node(ni);
844 ieee80211_sta_join(ic, ni);
845 ieee80211_node_authorize(ni);
846
847 if (ic->ic_opmode == IEEE80211_M_STA)
848 ieee80211_notify_node_join(ic, ni, 1);
849 break;
850
851 case IEEE80211_S_INIT:
852 case IEEE80211_S_SCAN:
853 case IEEE80211_S_AUTH:
854 case IEEE80211_S_ASSOC:
855 break;
856 }
857
858 ic->ic_state = nstate;
859 return 0;
860}
861
862/*
863 * Read 16 bits at address 'addr' from the serial EEPROM.
864 */
865static uint16_t
866ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr)
867{
868 uint32_t tmp;
869 uint16_t val;
870 int n;
871
872 /* clock C once before the first command */
873 IPW_EEPROM_CTL(sc, 0);
874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C);
876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
877
878 /* write start bit (1) */
879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D);
880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C);
881
882 /* write READ opcode (10) */
883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D);
884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C);
885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
886 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C);
887
888 /* write address A7-A0 */
889 for (n = 7; n >= 0; n--) {
890 IPW_EEPROM_CTL(sc, IPW_EEPROM_S |
891 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D));
892 IPW_EEPROM_CTL(sc, IPW_EEPROM_S |
893 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C);
894 }
895
896 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
897
898 /* read data Q15-Q0 */
899 val = 0;
900 for (n = 15; n >= 0; n--) {
901 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C);
902 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
903 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL);
904 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n;
905 }
906
907 IPW_EEPROM_CTL(sc, 0);
908
909 /* clear Chip Select and clock C */
910 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
911 IPW_EEPROM_CTL(sc, 0);
912 IPW_EEPROM_CTL(sc, IPW_EEPROM_C);
913
914 return le16toh(val);
915}
916
917static void
918ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf)
919{
920 struct ipw_cmd *cmd;
921
922 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD);
923
924 cmd = mtod(sbuf->m, struct ipw_cmd *);
925
926 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type),
927 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len),
928 le32toh(cmd->status)));
929
930 wakeup(sc);
931}
932
933static void
934ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf)
935{
936 struct ieee80211com *ic = &sc->sc_ic;
937 uint32_t state;
938
939 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD);
940
941 state = le32toh(*mtod(sbuf->m, uint32_t *));
942
943 DPRINTFN(2, ("entering state %u\n", state));
944
945 switch (state) {
946 case IPW_STATE_ASSOCIATED:
947 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
948 break;
949
950 case IPW_STATE_SCANNING:
951 /* don't leave run state on background scan */
952 if (ic->ic_state != IEEE80211_S_RUN)
953 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
954
955 ic->ic_flags |= IEEE80211_F_SCAN;
956 break;
957
958 case IPW_STATE_SCAN_COMPLETE:
959 ieee80211_notify_scan_done(ic);
960 ic->ic_flags &= ~IEEE80211_F_SCAN;
961 break;
962
963 case IPW_STATE_ASSOCIATION_LOST:
964 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
965 break;
966
967 case IPW_STATE_RADIO_DISABLED:
968 ic->ic_ifp->if_flags &= ~IFF_UP;
969 ipw_stop(sc);
970 break;
971 }
972}
973
974/*
975 * XXX: Hack to set the current channel to the value advertised in beacons or
976 * probe responses. Only used during AP detection.
977 */
978static void
979ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m)
980{
981 struct ieee80211_frame *wh;
982 uint8_t subtype;
983 uint8_t *frm, *efrm;
984
985 wh = mtod(m, struct ieee80211_frame *);
986
987 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT)
988 return;
989
990 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
991
992 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON &&
993 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP)
994 return;
995
996 frm = (uint8_t *)(wh + 1);
997 efrm = mtod(m, uint8_t *) + m->m_len;
998
999 frm += 12; /* skip tstamp, bintval and capinfo fields */
1000 while (frm < efrm) {
1001 if (*frm == IEEE80211_ELEMID_DSPARMS)
1002#if IEEE80211_CHAN_MAX < 255
1003 if (frm[2] <= IEEE80211_CHAN_MAX)
1004#endif
1005 ic->ic_bss->ni_chan = &ic->ic_channels[frm[2]];
1006
1007 frm += frm[1] + 2;
1008 }
1009}
1010
1011static void
1012ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status,
1013 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf)
1014{
1015 struct ieee80211com *ic = &sc->sc_ic;
1016 struct ifnet *ifp = ic->ic_ifp;
1017 struct mbuf *m;
1018 struct ieee80211_frame *wh;
1019 struct ieee80211_node *ni;
1020 bus_addr_t physaddr;
1021 int error;
1022
1023 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) ||
1024 le32toh(status->len) > MCLBYTES)
1025 return;
1026
1027 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD);
1028 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map);
1029
1030 /* finalize mbuf */
1031 m = sbuf->m;
1032 m->m_pkthdr.rcvif = ifp;
1033 m->m_pkthdr.len = m->m_len = le32toh(status->len);
1034
1035 if (sc->sc_drvbpf != NULL) {
1036 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap;
1037
1038 tap->wr_flags = 0;
1039 tap->wr_antsignal = status->rssi;
1040 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq);
1041 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags);
1042
1043 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
1044 }
1045
1046 if (ic->ic_state == IEEE80211_S_SCAN)
1047 ipw_fix_channel(ic, m);
1048
1049 wh = mtod(m, struct ieee80211_frame *);
1050 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
1051
1052 /* send the frame to the 802.11 layer */
1053 ieee80211_input(ic, m, ni, status->rssi, 0);
1054
1055 /* node is no longer needed */
1056 ieee80211_free_node(ni);
1057
1058 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1059 if (m == NULL) {
1060 device_printf(sc->sc_dev, "could not allocate rx mbuf\n");
1061 sbuf->m = NULL;
1062 return;
1063 }
1064
1065 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(m, void *),
1066 MCLBYTES, ipw_dma_map_addr, &physaddr, 0);
1067 if (error != 0) {
1068 device_printf(sc->sc_dev, "could not map rx DMA memory\n");
1069 m_freem(m);
1070 sbuf->m = NULL;
1071 return;
1072 }
1073
1074 sbuf->m = m;
1075 sbd->bd->physaddr = htole32(physaddr);
1076
1077 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len),
1078 status->rssi));
1079
1080 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE);
1081}
1082
1083static void
1084ipw_rx_intr(struct ipw_softc *sc)
1085{
1086 struct ipw_status *status;
1087 struct ipw_soft_bd *sbd;
1088 struct ipw_soft_buf *sbuf;
1089 uint32_t r, i;
1090
1091 if (!(sc->flags & IPW_FLAG_FW_INITED))
1092 return;
1093
1094 r = CSR_READ_4(sc, IPW_CSR_RX_READ);
1095
1096 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD);
1097
1098 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) {
1099 status = &sc->status_list[i];
1100 sbd = &sc->srbd_list[i];
1101 sbuf = sbd->priv;
1102
1103 switch (le16toh(status->code) & 0xf) {
1104 case IPW_STATUS_CODE_COMMAND:
1105 ipw_command_intr(sc, sbuf);
1106 break;
1107
1108 case IPW_STATUS_CODE_NEWSTATE:
1109 ipw_newstate_intr(sc, sbuf);
1110 break;
1111
1112 case IPW_STATUS_CODE_DATA_802_3:
1113 case IPW_STATUS_CODE_DATA_802_11:
1114 ipw_data_intr(sc, status, sbd, sbuf);
1115 break;
1116
1117 case IPW_STATUS_CODE_NOTIFICATION:
1118 DPRINTFN(2, ("received notification\n"));
1119 break;
1120
1121 default:
1122 device_printf(sc->sc_dev, "unknown status code %u\n",
1123 le16toh(status->code));
1124 }
1125
1126 /* firmware was killed, stop processing received frames */
1127 if (!(sc->flags & IPW_FLAG_FW_INITED))
1128 return;
1129
1130 sbd->bd->flags = 0;
1131 }
1132
1133 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE);
1134
1135 /* kick the firmware */
1136 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1;
1137 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
1138}
1139
1140static void
1141ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd)
1142{
1143 struct ipw_soft_hdr *shdr;
1144 struct ipw_soft_buf *sbuf;
1145
1146 switch (sbd->type) {
1147 case IPW_SBD_TYPE_COMMAND:
1148 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map,
1149 BUS_DMASYNC_POSTWRITE);
1150 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map);
1151 break;
1152
1153 case IPW_SBD_TYPE_HEADER:
1154 shdr = sbd->priv;
1155 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE);
1156 bus_dmamap_unload(sc->hdr_dmat, shdr->map);
1157 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next);
1158 break;
1159
1160 case IPW_SBD_TYPE_DATA:
1161 sbuf = sbd->priv;
1162 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map,
1163 BUS_DMASYNC_POSTWRITE);
1164 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map);
1165 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next);
1166
1167 m_freem(sbuf->m);
1168 ieee80211_free_node(sbuf->ni);
1169
1170 sc->sc_tx_timer = 0;
1171 break;
1172 }
1173
1174 sbd->type = IPW_SBD_TYPE_NOASSOC;
1175}
1176
1177static void
1178ipw_tx_intr(struct ipw_softc *sc)
1179{
1180 struct ifnet *ifp = sc->sc_ic.ic_ifp;
1181 struct ipw_soft_bd *sbd;
1182 uint32_t r, i;
1183
1184 if (!(sc->flags & IPW_FLAG_FW_INITED))
1185 return;
1186
1187 r = CSR_READ_4(sc, IPW_CSR_TX_READ);
1188
1189 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) {
1190 sbd = &sc->stbd_list[i];
1191
1192 if (sbd->type == IPW_SBD_TYPE_DATA)
1193 ifp->if_opackets++;
1194
1195 ipw_release_sbd(sc, sbd);
1196 sc->txfree++;
1197 }
1198
1199 /* remember what the firmware has processed */
1200 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1;
1201
1202 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1203 ipw_start(ifp);
1204}
1205
1206static void
1207ipw_intr(void *arg)
1208{
1209 struct ipw_softc *sc = arg;
1210 uint32_t r;
1211
1212 IPW_LOCK(sc);
1213
1214 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) {
1215 IPW_UNLOCK(sc);
1216 return;
1217 }
1218
1219 /* disable interrupts */
1220 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1221
1222 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) {
1223 device_printf(sc->sc_dev, "fatal error\n");
1224 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP;
1225 ipw_stop(sc);
1226 }
1227
1228 if (r & IPW_INTR_FW_INIT_DONE) {
1229 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)))
1230 wakeup(sc);
1231 }
1232
1233 if (r & IPW_INTR_RX_TRANSFER)
1234 ipw_rx_intr(sc);
1235
1236 if (r & IPW_INTR_TX_TRANSFER)
1237 ipw_tx_intr(sc);
1238
1239 /* acknowledge all interrupts */
1240 CSR_WRITE_4(sc, IPW_CSR_INTR, r);
1241
1242 /* re-enable interrupts */
1243 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1244
1245 IPW_UNLOCK(sc);
1246}
1247
1248static void
1249ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1250{
1251 if (error != 0)
1252 return;
1253
1254 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1255
1256 *(bus_addr_t *)arg = segs[0].ds_addr;
1257}
1258
1259/*
1260 * Send a command to the firmware and wait for the acknowledgement.
1261 */
1262static int
1263ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len)
1264{
1265 struct ipw_soft_bd *sbd;
1266 bus_addr_t physaddr;
1267 int error;
1268
1269 sbd = &sc->stbd_list[sc->txcur];
1270
1271 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd,
1272 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0);
1273 if (error != 0) {
1274 device_printf(sc->sc_dev, "could not map command DMA memory\n");
1275 return error;
1276 }
1277
1278 sc->cmd.type = htole32(type);
1279 sc->cmd.subtype = 0;
1280 sc->cmd.len = htole32(len);
1281 sc->cmd.seq = 0;
1282 bcopy(data, sc->cmd.data, len);
1283
1284 sbd->type = IPW_SBD_TYPE_COMMAND;
1285 sbd->bd->physaddr = htole32(physaddr);
1286 sbd->bd->len = htole32(sizeof (struct ipw_cmd));
1287 sbd->bd->nfrag = 1;
1288 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND |
1289 IPW_BD_FLAG_TX_LAST_FRAGMENT;
1290
1291 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE);
1292 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE);
1293
1294 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len));
1295
1296 /* kick firmware */
1297 sc->txfree--;
1298 sc->txcur = (sc->txcur + 1) % IPW_NTBD;
1299 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1300
1301 /* wait at most one second for command to complete */
1302 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz);
1303}
1304
1305static int
1306ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni)
1307{
1308 struct ipw_softc *sc = ifp->if_softc;
1309 struct ieee80211com *ic = &sc->sc_ic;
1310 struct ieee80211_frame *wh;
1311 struct ipw_soft_bd *sbd;
1312 struct ipw_soft_hdr *shdr;
1313 struct ipw_soft_buf *sbuf;
1314 struct ieee80211_key *k;
1315 struct mbuf *mnew;
1316 bus_dma_segment_t segs[IPW_MAX_NSEG];
1317 bus_addr_t physaddr;
1318 int nsegs, error, i;
1319
1320 wh = mtod(m0, struct ieee80211_frame *);
1321
1322 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1323 k = ieee80211_crypto_encap(ic, ni, m0);
1324 if (k == NULL) {
1325 m_freem(m0);
1326 return ENOBUFS;
1327 }
1328
1329 /* packet header may have moved, reset our local pointer */
1330 wh = mtod(m0, struct ieee80211_frame *);
1331 }
1332
1333 if (sc->sc_drvbpf != NULL) {
1334 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap;
1335
1336 tap->wt_flags = 0;
1337 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq);
1338 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags);
1339
1340 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0);
1341 }
1342
1343 shdr = SLIST_FIRST(&sc->free_shdr);
1344 sbuf = SLIST_FIRST(&sc->free_sbuf);
1345 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool"));
1346
1347 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND);
1348 shdr->hdr.subtype = 0;
1349 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0;
1350 shdr->hdr.encrypt = 0;
1351 shdr->hdr.keyidx = 0;
1352 shdr->hdr.keysz = 0;
1353 shdr->hdr.fragmentsz = 0;
1354 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2);
1355 if (ic->ic_opmode == IEEE80211_M_STA)
1356 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3);
1357 else
1358 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1);
1359
1360 /* trim IEEE802.11 header */
1361 m_adj(m0, sizeof (struct ieee80211_frame));
1362
1363 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs,
1364 &nsegs, 0);
1365 if (error != 0 && error != EFBIG) {
1366 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1367 error);
1368 m_freem(m0);
1369 return error;
1370 }
1371 if (error != 0) {
1372 mnew = m_defrag(m0, M_DONTWAIT);
1373 if (mnew == NULL) {
1374 device_printf(sc->sc_dev,
1375 "could not defragment mbuf\n");
1376 m_freem(m0);
1377 return ENOBUFS;
1378 }
1379 m0 = mnew;
1380
1381 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0,
1382 segs, &nsegs, 0);
1383 if (error != 0) {
1384 device_printf(sc->sc_dev,
1385 "could not map mbuf (error %d)\n", error);
1386 m_freem(m0);
1387 return error;
1388 }
1389 }
1390
1391 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr,
1392 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0);
1393 if (error != 0) {
1394 device_printf(sc->sc_dev, "could not map header DMA memory\n");
1395 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map);
1396 m_freem(m0);
1397 return error;
1398 }
1399
1400 SLIST_REMOVE_HEAD(&sc->free_sbuf, next);
1401 SLIST_REMOVE_HEAD(&sc->free_shdr, next);
1402
1403 sbd = &sc->stbd_list[sc->txcur];
1404 sbd->type = IPW_SBD_TYPE_HEADER;
1405 sbd->priv = shdr;
1406 sbd->bd->physaddr = htole32(physaddr);
1407 sbd->bd->len = htole32(sizeof (struct ipw_hdr));
1408 sbd->bd->nfrag = 1 + nsegs;
1409 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 |
1410 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT;
1411
1412 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n",
1413 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted,
1414 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr,
1415 ":"));
1416
1417 sc->txfree--;
1418 sc->txcur = (sc->txcur + 1) % IPW_NTBD;
1419
1420 sbuf->m = m0;
1421 sbuf->ni = ni;
1422
1423 for (i = 0; i < nsegs; i++) {
1424 sbd = &sc->stbd_list[sc->txcur];
1425
1426 sbd->bd->physaddr = htole32(segs[i].ds_addr);
1427 sbd->bd->len = htole32(segs[i].ds_len);
1428 sbd->bd->nfrag = 0;
1429 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3;
1430 if (i == nsegs - 1) {
1431 sbd->type = IPW_SBD_TYPE_DATA;
1432 sbd->priv = sbuf;
1433 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT;
1434 } else {
1435 sbd->type = IPW_SBD_TYPE_NOASSOC;
1436 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT;
1437 }
1438
1439 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len));
1440
1441 sc->txfree--;
1442 sc->txcur = (sc->txcur + 1) % IPW_NTBD;
1443 }
1444
1445 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE);
1446 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE);
1447 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE);
1448
1449 /* kick firmware */
1450 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1451
1452 return 0;
1453}
1454
1455static void
1456ipw_start(struct ifnet *ifp)
1457{
1458 struct ipw_softc *sc = ifp->if_softc;
1459 struct ieee80211com *ic = &sc->sc_ic;
1460 struct mbuf *m0;
1461 struct ether_header *eh;
1462 struct ieee80211_node *ni;
1463
1464 IPW_LOCK(sc);
1465
1466 if (ic->ic_state != IEEE80211_S_RUN) {
1467 IPW_UNLOCK(sc);
1468 return;
1469 }
1470
1471 for (;;) {
1472 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
1473 if (m0 == NULL)
1474 break;
1475
1476 if (sc->txfree < 1 + IPW_MAX_NSEG) {
1477 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
1478 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1479 break;
1480 }
1481
1482 if (m0->m_len < sizeof (struct ether_header) &&
1483 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL)
1484 continue;
1485
1486 eh = mtod(m0, struct ether_header *);
1487 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1488 if (ni == NULL) {
1489 m_freem(m0);
1490 continue;
1491 }
1492 BPF_MTAP(ifp, m0);
1493
1494 m0 = ieee80211_encap(ic, m0, ni);
1495 if (m0 == NULL) {
1496 ieee80211_free_node(ni);
1497 continue;
1498 }
1499
1500 if (ic->ic_rawbpf != NULL)
1501 bpf_mtap(ic->ic_rawbpf, m0);
1502
1503 if (ipw_tx_start(ifp, m0, ni) != 0) {
1504 ieee80211_free_node(ni);
1505 ifp->if_oerrors++;
1506 break;
1507 }
1508
1509 /* start watchdog timer */
1510 sc->sc_tx_timer = 5;
1511 ifp->if_timer = 1;
1512 }
1513
1514 IPW_UNLOCK(sc);
1515}
1516
1517static void
1518ipw_watchdog(struct ifnet *ifp)
1519{
1520 struct ipw_softc *sc = ifp->if_softc;
1521 struct ieee80211com *ic = &sc->sc_ic;
1522
1523 ifp->if_timer = 0;
1524
1525 if (sc->sc_tx_timer > 0) {
1526 if (--sc->sc_tx_timer == 0) {
1527 if_printf(ifp, "device timeout\n");
1528 ifp->if_oerrors++;
1529 ifp->if_flags &= ~IFF_UP;
1530 ipw_stop(sc);
1531 return;
1532 }
1533 ifp->if_timer = 1;
1534 }
1535
1536 ieee80211_watchdog(ic);
1537}
1538
1539static int
1540ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1541{
1542 struct ipw_softc *sc = ifp->if_softc;
1543 struct ieee80211com *ic = &sc->sc_ic;
1544 struct ifreq *ifr;
1545 int error = 0;
1546
1547 IPW_LOCK(sc);
1548
1549 switch (cmd) {
1550 case SIOCSIFFLAGS:
1551 if (ifp->if_flags & IFF_UP) {
1552 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1553 ipw_init(sc);
1554 } else {
1555 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1556 ipw_stop(sc);
1557 }
1558 break;
1559
1560 case SIOCSLOADFW:
1561 /* only super-user can do that! */
1562 if ((error = suser(curthread)) != 0)
1563 break;
1564
1565 ifr = (struct ifreq *)data;
1566 error = ipw_cache_firmware(sc, ifr->ifr_data);
1567 break;
1568
1569 case SIOCSKILLFW:
1570 /* only super-user can do that! */
1571 if ((error = suser(curthread)) != 0)
1572 break;
1573
1574 ifp->if_flags &= ~IFF_UP;
1575 ipw_stop(sc);
1576 ipw_free_firmware(sc);
1577 break;
1578
1579 default:
1580 error = ieee80211_ioctl(ic, cmd, data);
1581 }
1582
1583 if (error == ENETRESET) {
1584 if ((ifp->if_flags & IFF_UP) &&
1585 (ifp->if_drv_flags & IFF_DRV_RUNNING))
1586 ipw_init(sc);
1587 error = 0;
1588 }
1589
1590 IPW_UNLOCK(sc);
1591
1592 return error;
1593}
1594
1595static void
1596ipw_stop_master(struct ipw_softc *sc)
1597{
1598 int ntries;
1599
1600 /* disable interrupts */
1601 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1602
1603 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER);
1604 for (ntries = 0; ntries < 50; ntries++) {
1605 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)
1606 break;
1607 DELAY(10);
1608 }
1609 if (ntries == 50)
1610 device_printf(sc->sc_dev, "timeout waiting for master\n");
1611
1612 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1613 IPW_RST_PRINCETON_RESET);
1614
1615 sc->flags &= ~IPW_FLAG_FW_INITED;
1616}
1617
1618static int
1619ipw_reset(struct ipw_softc *sc)
1620{
1621 int ntries;
1622
1623 ipw_stop_master(sc);
1624
1625 /* move adapter to D0 state */
1626 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1627 IPW_CTL_INIT);
1628
1629 /* wait for clock stabilization */
1630 for (ntries = 0; ntries < 1000; ntries++) {
1631 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY)
1632 break;
1633 DELAY(200);
1634 }
1635 if (ntries == 1000)
1636 return EIO;
1637
1638 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1639 IPW_RST_SW_RESET);
1640
1641 DELAY(10);
1642
1643 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1644 IPW_CTL_INIT);
1645
1646 return 0;
1647}
1648
1649/*
1650 * Upload the microcode to the device.
1651 */
1652static int
1653ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size)
1654{
1655 int ntries;
1656
1657 MEM_WRITE_4(sc, 0x3000e0, 0x80000000);
1658 CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1659
1660 MEM_WRITE_2(sc, 0x220000, 0x0703);
1661 MEM_WRITE_2(sc, 0x220000, 0x0707);
1662
1663 MEM_WRITE_1(sc, 0x210014, 0x72);
1664 MEM_WRITE_1(sc, 0x210014, 0x72);
1665
1666 MEM_WRITE_1(sc, 0x210000, 0x40);
1667 MEM_WRITE_1(sc, 0x210000, 0x00);
1668 MEM_WRITE_1(sc, 0x210000, 0x40);
1669
1670 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size);
1671
1672 MEM_WRITE_1(sc, 0x210000, 0x00);
1673 MEM_WRITE_1(sc, 0x210000, 0x00);
1674 MEM_WRITE_1(sc, 0x210000, 0x80);
1675
1676 MEM_WRITE_2(sc, 0x220000, 0x0703);
1677 MEM_WRITE_2(sc, 0x220000, 0x0707);
1678
1679 MEM_WRITE_1(sc, 0x210014, 0x72);
1680 MEM_WRITE_1(sc, 0x210014, 0x72);
1681
1682 MEM_WRITE_1(sc, 0x210000, 0x00);
1683 MEM_WRITE_1(sc, 0x210000, 0x80);
1684
1685 for (ntries = 0; ntries < 10; ntries++) {
1686 if (MEM_READ_1(sc, 0x210000) & 1)
1687 break;
1688 DELAY(10);
1689 }
1690 if (ntries == 10) {
1691 device_printf(sc->sc_dev,
1692 "timeout waiting for ucode to initialize\n");
1693 return EIO;
1694 }
1695
1696 MEM_WRITE_4(sc, 0x3000e0, 0);
1697
1698 return 0;
1699}
1700
1701/* set of macros to handle unaligned little endian data in firmware image */
1702#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
1703#define GETLE16(p) ((p)[0] | (p)[1] << 8)
1704static int
1705ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size)
1706{
1707 u_char *p, *end;
1708 uint32_t dst;
1709 uint16_t len;
1710 int error;
1711
1712 p = fw;
1713 end = fw + size;
1714 while (p < end) {
1715 dst = GETLE32(p); p += 4;
1716 len = GETLE16(p); p += 2;
1717
1718 ipw_write_mem_1(sc, dst, p, len);
1719 p += len;
1720 }
1721
1722 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK |
1723 IPW_IO_LED_OFF);
1724
1725 /* enable interrupts */
1726 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1727
1728 /* kick the firmware */
1729 CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1730
1731 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1732 IPW_CTL_ALLOW_STANDBY);
1733
1734 /* wait at most one second for firmware initialization to complete */
1735 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) {
1736 device_printf(sc->sc_dev, "timeout waiting for firmware "
1737 "initialization to complete\n");
1738 return error;
1739 }
1740
1741 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) |
1742 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK);
1743
1744 return 0;
1745}
1746
1747/*
1748 * Store firmware into kernel memory so we can download it when we need to,
1749 * e.g when the adapter wakes up from suspend mode.
1750 */
1751static int
1752ipw_cache_firmware(struct ipw_softc *sc, void *data)
1753{
1754 struct ipw_firmware *fw = &sc->fw;
1755 struct ipw_firmware_hdr hdr;
1756 u_char *p = data;
1757 int error;
1758
1759 ipw_free_firmware(sc);
1760
1761 IPW_UNLOCK(sc);
1762
1763 if ((error = copyin(data, &hdr, sizeof hdr)) != 0)
1764 goto fail1;
1765
1766 fw->main_size = le32toh(hdr.main_size);
1767 fw->ucode_size = le32toh(hdr.ucode_size);
1768 p += sizeof hdr;
1769
1770 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT);
1771 if (fw->main == NULL) {
1772 error = ENOMEM;
1773 goto fail1;
1774 }
1775
1776 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT);
1777 if (fw->ucode == NULL) {
1778 error = ENOMEM;
1779 goto fail2;
1780 }
1781
1782 if ((error = copyin(p, fw->main, fw->main_size)) != 0)
1783 goto fail3;
1784
1785 p += fw->main_size;
1786 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0)
1787 goto fail3;
1788
1789 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size,
1790 fw->ucode_size));
1791
1792 IPW_LOCK(sc);
1793
1794 sc->flags |= IPW_FLAG_FW_CACHED;
1795
1796 return 0;
1797
1798fail3: free(fw->ucode, M_DEVBUF);
1799fail2: free(fw->main, M_DEVBUF);
1800fail1: IPW_LOCK(sc);
1801
1802 return error;
1803}
1804
1805static void
1806ipw_free_firmware(struct ipw_softc *sc)
1807{
1808 if (!(sc->flags & IPW_FLAG_FW_CACHED))
1809 return;
1810
1811 free(sc->fw.main, M_DEVBUF);
1812 free(sc->fw.ucode, M_DEVBUF);
1813
1814 sc->flags &= ~IPW_FLAG_FW_CACHED;
1815}
1816
1817static int
1818ipw_config(struct ipw_softc *sc)
1819{
1820 struct ieee80211com *ic = &sc->sc_ic;
1821 struct ifnet *ifp = ic->ic_ifp;
1822 struct ipw_security security;
1823 struct ieee80211_key *k;
1824 struct ipw_wep_key wepkey;
1825 struct ipw_scan_options options;
1826 struct ipw_configuration config;
1827 uint32_t data;
1828 int error, i;
1829
1830 switch (ic->ic_opmode) {
1831 case IEEE80211_M_STA:
1832 case IEEE80211_M_HOSTAP:
1833 data = htole32(IPW_MODE_BSS);
1834 break;
1835
1836 case IEEE80211_M_IBSS:
1837 case IEEE80211_M_AHDEMO:
1838 data = htole32(IPW_MODE_IBSS);
1839 break;
1840
1841 case IEEE80211_M_MONITOR:
1842 data = htole32(IPW_MODE_MONITOR);
1843 break;
1844 }
1845 DPRINTF(("Setting mode to %u\n", le32toh(data)));
1846 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data);
1847 if (error != 0)
1848 return error;
1849
1850 if (ic->ic_opmode == IEEE80211_M_IBSS ||
1851 ic->ic_opmode == IEEE80211_M_MONITOR) {
1852 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan));
1853 DPRINTF(("Setting channel to %u\n", le32toh(data)));
1854 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data);
1855 if (error != 0)
1856 return error;
1857 }
1858
1859 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1860 DPRINTF(("Enabling adapter\n"));
1861 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0);
1862 }
1863
1864 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1865 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":"));
1866 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr,
1867 IEEE80211_ADDR_LEN);
1868 if (error != 0)
1869 return error;
1870
1871 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK |
1872 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE);
1873 if (ic->ic_opmode == IEEE80211_M_IBSS)
1874 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START);
1875 if (ifp->if_flags & IFF_PROMISC)
1876 config.flags |= htole32(IPW_CFG_PROMISCUOUS);
1877 config.bss_chan = htole32(0x3fff); /* channels 1-14 */
1878 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */
1879 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags)));
1880 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config);
1881 if (error != 0)
1882 return error;
1883
1884 data = htole32(0x3); /* 1, 2 */
1885 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data)));
1886 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data);
1887 if (error != 0)
1888 return error;
1889
1890 data = htole32(0xf); /* 1, 2, 5.5, 11 */
1891 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data)));
1892 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data);
1893 if (error != 0)
1894 return error;
1895
1896 data = htole32(IPW_POWER_MODE_CAM);
1897 DPRINTF(("Setting power mode to %u\n", le32toh(data)));
1898 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data);
1899 if (error != 0)
1900 return error;
1901
1902 if (ic->ic_opmode == IEEE80211_M_IBSS) {
1903 data = htole32(32); /* default value */
1904 DPRINTF(("Setting tx power index to %u\n", le32toh(data)));
1905 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data,
1906 sizeof data);
1907 if (error != 0)
1908 return error;
1909 }
1910
1911 data = htole32(ic->ic_rtsthreshold);
1912 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data)));
1913 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data);
1914 if (error != 0)
1915 return error;
1916
1917 data = htole32(ic->ic_fragthreshold);
1918 DPRINTF(("Setting frag threshold to %u\n", le32toh(data)));
1919 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data);
1920 if (error != 0)
1921 return error;
1922
1923#ifdef IPW_DEBUG
1924 if (ipw_debug > 0) {
1925 printf("Setting ESSID to ");
1926 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen);
1927 printf("\n");
1928 }
1929#endif
1930 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid,
1931 ic->ic_des_esslen);
1932 if (error != 0)
1933 return error;
1934
1935 /* no mandatory BSSID */
1936 DPRINTF(("Setting mandatory BSSID to null\n"));
1937 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0);
1938 if (error != 0)
1939 return error;
1940
1941 if (ic->ic_flags & IEEE80211_F_DESBSSID) {
1942 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid,
1943 ":"));
1944 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID,
1945 ic->ic_des_bssid, IEEE80211_ADDR_LEN);
1946 if (error != 0)
1947 return error;
1948 }
1949
1950 bzero(&security, sizeof security);
1951 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ?
1952 IPW_AUTH_SHARED : IPW_AUTH_OPEN;
1953 security.ciphers = htole32(IPW_CIPHER_NONE);
1954 DPRINTF(("Setting authmode to %u\n", security.authmode));
1955 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security,
1956 sizeof security);
1957 if (error != 0)
1958 return error;
1959
1960 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
1961 k = ic->ic_crypto.cs_nw_keys;
1962 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) {
1963 if (k->wk_keylen == 0)
1964 continue;
1965
1966 wepkey.idx = i;
1967 wepkey.len = k->wk_keylen;
1968 bzero(wepkey.key, sizeof wepkey.key);
1969 bcopy(k->wk_key, wepkey.key, k->wk_keylen);
1970 DPRINTF(("Setting wep key index %u len %u\n",
1971 wepkey.idx, wepkey.len));
1972 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey,
1973 sizeof wepkey);
1974 if (error != 0)
1975 return error;
1976 }
1977
1978 data = htole32(ic->ic_crypto.cs_def_txkey);
1979 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data)));
1980 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data,
1981 sizeof data);
1982 if (error != 0)
1983 return error;
1984 }
1985
1986 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0);
1987 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data)));
1988 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data);
1989 if (error != 0)
1990 return error;
1991
1992#if 0
1993 struct ipw_wpa_ie ie;
1994
1995 bzero(&ie, sizeof ie);
1996 ie.len = htole32(sizeof (struct ieee80211_ie_wpa));
1997 DPRINTF(("Setting wpa ie\n"));
1998 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie);
1999 if (error != 0)
2000 return error;
2001#endif
2002
2003 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2004 data = htole32(ic->ic_bintval);
2005 DPRINTF(("Setting beacon interval to %u\n", le32toh(data)));
2006 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data,
2007 sizeof data);
2008 if (error != 0)
2009 return error;
2010 }
2011
2012 options.flags = 0;
2013 options.channels = htole32(0x3fff); /* scan channels 1-14 */
2014 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags)));
2015 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options);
2016 if (error != 0)
2017 return error;
2018
2019 /* finally, enable adapter (start scanning for an access point) */
2020 DPRINTF(("Enabling adapter\n"));
2021 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0);
2022}
2023
2024static void
2025ipw_init(void *priv)
2026{
2027 struct ipw_softc *sc = priv;
2028 struct ieee80211com *ic = &sc->sc_ic;
2029 struct ifnet *ifp = ic->ic_ifp;
2030 struct ipw_firmware *fw = &sc->fw;
2031
2032 /* exit immediately if firmware has not been ioctl'd */
2033 if (!(sc->flags & IPW_FLAG_FW_CACHED)) {
2034 if (!(sc->flags & IPW_FLAG_FW_WARNED))
2035 device_printf(sc->sc_dev, "Please load firmware\n");
2036 sc->flags |= IPW_FLAG_FW_WARNED;
2037 ifp->if_flags &= ~IFF_UP;
2038 return;
2039 }
2040
2041 ipw_stop(sc);
2042
2043 if (ipw_reset(sc) != 0) {
2044 device_printf(sc->sc_dev, "could not reset adapter\n");
2045 goto fail;
2046 }
2047
2048 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) {
2049 device_printf(sc->sc_dev, "could not load microcode\n");
2050 goto fail;
2051 }
2052
2053 ipw_stop_master(sc);
2054
2055 /*
2056 * Setup tx, rx and status rings.
2057 */
2058 sc->txold = IPW_NTBD - 1;
2059 sc->txcur = 0;
2060 sc->txfree = IPW_NTBD - 2;
2061 sc->rxcur = IPW_NRBD - 1;
2062
2063 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys);
2064 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD);
2065 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0);
2066 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
2067
2068 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys);
2069 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD);
2070 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0);
2071 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
2072
2073 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys);
2074
2075 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) {
2076 device_printf(sc->sc_dev, "could not load firmware\n");
2077 goto fail;
2078 }
2079
2080 sc->flags |= IPW_FLAG_FW_INITED;
2081
2082 /* retrieve information tables base addresses */
2083 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE);
2084 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE);
2085
2086 ipw_write_table1(sc, IPW_INFO_LOCK, 0);
2087
2088 if (ipw_config(sc) != 0) {
2089 device_printf(sc->sc_dev, "device configuration failed\n");
2090 goto fail;
2091 }
2092
2093 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2094 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2095
2096 return;
2097
2098fail: ifp->if_flags &= ~IFF_UP;
2099 ipw_stop(sc);
2100}
2101
2102static void
2103ipw_stop(void *priv)
2104{
2105 struct ipw_softc *sc = priv;
2106 struct ieee80211com *ic = &sc->sc_ic;
2107 struct ifnet *ifp = ic->ic_ifp;
2108 int i;
2109
2110 ipw_stop_master(sc);
2111
2112 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET);
2113
2114 /*
2115 * Release tx buffers.
2116 */
2117 for (i = 0; i < IPW_NTBD; i++)
2118 ipw_release_sbd(sc, &sc->stbd_list[i]);
2119
2120 sc->sc_tx_timer = 0;
2121 ifp->if_timer = 0;
2122 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2123
2124 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2125}
2126
2127#ifdef IPW_DEBUG
2128static int
2129ipw_sysctl_stats(SYSCTL_HANDLER_ARGS)
2130{
2131 struct ipw_softc *sc = arg1;
2132 uint32_t i, size, buf[256];
2133
2134 if (!(sc->flags & IPW_FLAG_FW_INITED)) {
2135 bzero(buf, sizeof buf);
2136 return SYSCTL_OUT(req, buf, sizeof buf);
2137 }
2138
2139 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base);
2140
2141 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256);
2142 for (i = 1; i < size; i++)
2143 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA));
2144
2145 return SYSCTL_OUT(req, buf, sizeof buf);
2146}
2147#endif
2148
2149static int
2150ipw_sysctl_radio(SYSCTL_HANDLER_ARGS)
2151{
2152 struct ipw_softc *sc = arg1;
2153 int val;
2154
2155 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) &&
2156 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED));
2157
2158 return SYSCTL_OUT(req, &val, sizeof val);
2159}
2160
2161static uint32_t
2162ipw_read_table1(struct ipw_softc *sc, uint32_t off)
2163{
2164 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off));
2165}
2166
2167static void
2168ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info)
2169{
2170 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info);
2171}
2172
2173static int
2174ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len)
2175{
2176 uint32_t addr, info;
2177 uint16_t count, size;
2178 uint32_t total;
2179
2180 /* addr[4] + count[2] + size[2] */
2181 addr = MEM_READ_4(sc, sc->table2_base + off);
2182 info = MEM_READ_4(sc, sc->table2_base + off + 4);
2183
2184 count = info >> 16;
2185 size = info & 0xffff;
2186 total = count * size;
2187
2188 if (total > *len) {
2189 *len = total;
2190 return EINVAL;
2191 }
2192
2193 *len = total;
2194 ipw_read_mem_1(sc, addr, buf, total);
2195
2196 return 0;
2197}
2198
2199static void
2200ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap,
2201 bus_size_t count)
2202{
2203 for (; count > 0; offset++, datap++, count--) {
2204 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2205 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));
2206 }
2207}
2208
2209static void
2210ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap,
2211 bus_size_t count)
2212{
2213 for (; count > 0; offset++, datap++, count--) {
2214 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2215 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap);
2216 }
2217}