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iir.h (92739) iir.h (114001)
1/* $FreeBSD: head/sys/dev/iir/iir.h 92739 2002-03-20 02:08:01Z alfred $ */
1/* $FreeBSD: head/sys/dev/iir/iir.h 114001 2003-04-25 05:37:04Z scottl $ */
2/*
2/*
3 * Copyright (c) 2000-01 Intel Corporation
3 * Copyright (c) 2000-03 Intel Corporation
4 * All Rights Reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.

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36 * Written by: Achim Leubner <achim.leubner@intel.com>
37 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
38 *
39 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
40 * FreeBSD.ORG; Great O/S to work on and for.
41 */
42
43
4 * All Rights Reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.

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36 * Written by: Achim Leubner <achim.leubner@intel.com>
37 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
38 *
39 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
40 * FreeBSD.ORG; Great O/S to work on and for.
41 */
42
43
44#ident "$Id: iir.h 1.3 2001/07/03 11:28:57 achim Exp $"
44#ident "$Id: iir.h 1.4 2003/03/21 16:28:57 achim Exp $"
45
46#ifndef _IIR_H
47#define _IIR_H
48
49#define IIR_DRIVER_VERSION 1
45
46#ifndef _IIR_H
47#define _IIR_H
48
49#define IIR_DRIVER_VERSION 1
50#define IIR_DRIVER_SUBVERSION 1
50#define IIR_DRIVER_SUBVERSION 3
51
52#define IIR_CDEV_MAJOR 164
53
54#define GDT_VENDOR_ID 0x1119
55#define GDT_DEVICE_ID_MIN 0x100
56#define GDT_DEVICE_ID_MAX 0x2ff
57#define GDT_DEVICE_ID_NEWRX 0x300
58

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137#define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
138#define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
139#define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
140#define GDT_CACHE_INFO 0x04 /* cache info */
141#define GDT_CACHE_CONFIG 0x05 /* cache configuration */
142#define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
143#define GDT_BOARD_FEATURES 0x15 /* controller features */
144#define GDT_BOARD_INFO 0x28 /* controller info */
51
52#define IIR_CDEV_MAJOR 164
53
54#define GDT_VENDOR_ID 0x1119
55#define GDT_DEVICE_ID_MIN 0x100
56#define GDT_DEVICE_ID_MAX 0x2ff
57#define GDT_DEVICE_ID_NEWRX 0x300
58

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137#define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
138#define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
139#define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
140#define GDT_CACHE_INFO 0x04 /* cache info */
141#define GDT_CACHE_CONFIG 0x05 /* cache configuration */
142#define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
143#define GDT_BOARD_FEATURES 0x15 /* controller features */
144#define GDT_BOARD_INFO 0x28 /* controller info */
145#define GDT_OEM_STR_RECORD 0x84 /* OEM info */
145#define GDT_HOST_GET 0x10001 /* get host drive list */
146#define GDT_IO_CHANNEL 0x20000 /* default IO channel */
147#define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
148
149/* IOCTLs */
150#define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
151#define GDT_IOCTL_DRVERS _IOWR('J', 1, int) /* get driver version */
152#define GDT_IOCTL_CTRTYPE _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */

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366
367/* Miscellaneous constants */
368#define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
369#define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
370#define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
371#define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
372#define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
373
146#define GDT_HOST_GET 0x10001 /* get host drive list */
147#define GDT_IO_CHANNEL 0x20000 /* default IO channel */
148#define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
149
150/* IOCTLs */
151#define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
152#define GDT_IOCTL_DRVERS _IOWR('J', 1, int) /* get driver version */
153#define GDT_IOCTL_CTRTYPE _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */

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367
368/* Miscellaneous constants */
369#define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
370#define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
371#define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
372#define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
373#define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
374
374/* macros */
375#define letoh32(v) le32toh(v)
376#define letoh16(v) le16toh(v)
377
378/* Map minor numbers to device identity */
379#define LUN_MASK 0x0007
380#define TARGET_MASK 0x03f8
381#define BUS_MASK 0x1c00
382#define HBA_MASK 0xe000
383
384#define minor2lun(minor) ( minor & LUN_MASK )
385#define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )

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453typedef struct gdt_osv {
454 u_int8_t oscode;
455 u_int8_t version;
456 u_int8_t subversion;
457 u_int16_t revision;
458 char name[64];
459} gdt_osv_t;
460
375/* Map minor numbers to device identity */
376#define LUN_MASK 0x0007
377#define TARGET_MASK 0x03f8
378#define BUS_MASK 0x1c00
379#define HBA_MASK 0xe000
380
381#define minor2lun(minor) ( minor & LUN_MASK )
382#define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )

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450typedef struct gdt_osv {
451 u_int8_t oscode;
452 u_int8_t version;
453 u_int8_t subversion;
454 u_int16_t revision;
455 char name[64];
456} gdt_osv_t;
457
458/* OEM */
459#define GDT_OEM_VERSION 0x00
460#define GDT_OEM_BUFSIZE 0x0c
461typedef struct {
462 u_int32_t ctl_version;
463 u_int32_t file_major_version;
464 u_int32_t file_minor_version;
465 u_int32_t buffer_size;
466 u_int32_t cpy_count;
467 u_int32_t ext_error;
468 u_int32_t oem_id;
469 u_int32_t board_id;
470} gdt_oem_param_t;
471
472typedef struct {
473 char product_0_1_name[16];
474 char product_4_5_name[16];
475 char product_cluster_name[16];
476 char product_reserved[16];
477 char scsi_cluster_target_vendor_id[16];
478 char cluster_raid_fw_name[16];
479 char oem_brand_name[16];
480 char oem_raid_type[16];
481 char bios_type[13];
482 char bios_title[50];
483 char oem_company_name[37];
484 u_int32_t pci_id_1;
485 u_int32_t pci_id_2;
486 char validation_status[80];
487 char reserved_1[4];
488 char scsi_host_drive_inquiry_vendor_id[16];
489 char library_file_template[32];
490 char tool_name_1[32];
491 char tool_name_2[32];
492 char tool_name_3[32];
493 char oem_contact_1[84];
494 char oem_contact_2[84];
495 char oem_contact_3[84];
496} gdt_oem_record_t;
497
498typedef struct {
499 gdt_oem_param_t parameters;
500 gdt_oem_record_t text;
501} gdt_oem_str_record_t;
502
503
461/* controller event structure */
462#define GDT_ES_ASYNC 1
463#define GDT_ES_DRIVER 2
464#define GDT_ES_TEST 3
465#define GDT_ES_SYNC 4
466typedef struct {
467 u_int16_t size; /* size of structure */
468 union {

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540struct gdt_softc {
541 int sc_hanum;
542 int sc_class; /* Controller class */
543#define GDT_MPR 0x05
544#define GDT_CLASS_MASK 0x07
545#define GDT_FC 0x10
546#define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
547 int sc_bus, sc_slot;
504/* controller event structure */
505#define GDT_ES_ASYNC 1
506#define GDT_ES_DRIVER 2
507#define GDT_ES_TEST 3
508#define GDT_ES_SYNC 4
509typedef struct {
510 u_int16_t size; /* size of structure */
511 union {

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583struct gdt_softc {
584 int sc_hanum;
585 int sc_class; /* Controller class */
586#define GDT_MPR 0x05
587#define GDT_CLASS_MASK 0x07
588#define GDT_FC 0x10
589#define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
590 int sc_bus, sc_slot;
591 u_int16_t sc_vendor;
548 u_int16_t sc_device, sc_subdevice;
549 u_int16_t sc_fw_vers;
550 int sc_init_level;
551 int sc_state;
552#define GDT_NORMAL 0x00
553#define GDT_POLLING 0x01
554#define GDT_SHUTDOWN 0x02
555#define GDT_POLL_WAIT 0x80

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601 u_int8_t hd_rw_attribs;
602 u_int32_t hd_start_sec;
603 } sc_hdr[GDT_MAX_HDRIVES];
604
605 u_int16_t sc_raw_feat;
606 u_int16_t sc_cache_feat;
607
608 gdt_evt_data sc_dvr;
592 u_int16_t sc_device, sc_subdevice;
593 u_int16_t sc_fw_vers;
594 int sc_init_level;
595 int sc_state;
596#define GDT_NORMAL 0x00
597#define GDT_POLLING 0x01
598#define GDT_SHUTDOWN 0x02
599#define GDT_POLL_WAIT 0x80

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645 u_int8_t hd_rw_attribs;
646 u_int32_t hd_start_sec;
647 } sc_hdr[GDT_MAX_HDRIVES];
648
649 u_int16_t sc_raw_feat;
650 u_int16_t sc_cache_feat;
651
652 gdt_evt_data sc_dvr;
653 char oem_name[8];
609
610 struct cam_sim *sims[GDT_MAXBUS];
611 struct cam_path *paths[GDT_MAXBUS];
612
613 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
614 u_int8_t (*sc_get_status)(struct gdt_softc *);
615 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
616 void (*sc_release_event)(struct gdt_softc *);

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671{
672 *(u_int32_t *)addr = htole32(value);
673}
674
675static __inline__ u_int16_t
676gdt_dec16(addr)
677 u_int8_t *addr;
678{
654
655 struct cam_sim *sims[GDT_MAXBUS];
656 struct cam_path *paths[GDT_MAXBUS];
657
658 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
659 u_int8_t (*sc_get_status)(struct gdt_softc *);
660 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
661 void (*sc_release_event)(struct gdt_softc *);

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716{
717 *(u_int32_t *)addr = htole32(value);
718}
719
720static __inline__ u_int16_t
721gdt_dec16(addr)
722 u_int8_t *addr;
723{
679 return letoh16(*(u_int16_t *)addr);
724 return le16toh(*(u_int16_t *)addr);
680}
681
682static __inline__ u_int32_t
683gdt_dec32(addr)
684 u_int8_t *addr;
685{
725}
726
727static __inline__ u_int32_t
728gdt_dec32(addr)
729 u_int8_t *addr;
730{
686 return letoh32(*(u_int32_t *)addr);
731 return le32toh(*(u_int32_t *)addr);
687}
688#endif
689
690#if defined(__alpha__)
691/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
692#undef vtophys
693#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
694#endif

--- 16 unchanged lines hidden --- 		732}
733#endif
734
735#if defined(__alpha__)
736/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
737#undef vtophys
738#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
739#endif

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