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iir.h (92739) iir.h (114001)
1/* $FreeBSD: head/sys/dev/iir/iir.h 92739 2002-03-20 02:08:01Z alfred $ */
1/* $FreeBSD: head/sys/dev/iir/iir.h 114001 2003-04-25 05:37:04Z scottl $ */
2/*
2/*
3 * Copyright (c) 2000-01 Intel Corporation
3 * Copyright (c) 2000-03 Intel Corporation
4 * All Rights Reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32/*
33 *
34 * iir.h: Definitions/Constants used by the Intel Integrated RAID driver
35 *
36 * Written by: Achim Leubner <achim.leubner@intel.com>
37 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
38 *
39 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
40 * FreeBSD.ORG; Great O/S to work on and for.
41 */
42
43
4 * All Rights Reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32/*
33 *
34 * iir.h: Definitions/Constants used by the Intel Integrated RAID driver
35 *
36 * Written by: Achim Leubner <achim.leubner@intel.com>
37 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
38 *
39 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
40 * FreeBSD.ORG; Great O/S to work on and for.
41 */
42
43
44#ident "$Id: iir.h 1.3 2001/07/03 11:28:57 achim Exp $"
44#ident "$Id: iir.h 1.4 2003/03/21 16:28:57 achim Exp $"
45
46#ifndef _IIR_H
47#define _IIR_H
48
49#define IIR_DRIVER_VERSION 1
45
46#ifndef _IIR_H
47#define _IIR_H
48
49#define IIR_DRIVER_VERSION 1
50#define IIR_DRIVER_SUBVERSION 1
50#define IIR_DRIVER_SUBVERSION 3
51
52#define IIR_CDEV_MAJOR 164
53
54#define GDT_VENDOR_ID 0x1119
55#define GDT_DEVICE_ID_MIN 0x100
56#define GDT_DEVICE_ID_MAX 0x2ff
57#define GDT_DEVICE_ID_NEWRX 0x300
58
59#define INTEL_VENDOR_ID 0x8086
60#define INTEL_DEVICE_ID_IIR 0x600
61
62#define GDT_MAXBUS 6 /* XXX Why not 5? */
63#define GDT_MAX_HDRIVES 100 /* max 100 host drives */
64#define GDT_MAXID_FC 127 /* Fibre-channel IDs */
65#define GDT_MAXID 16 /* SCSI IDs */
66#define GDT_MAXOFFSETS 128
67#define GDT_MAXSG 32 /* Max. s/g elements */
68#define GDT_PROTOCOL_VERSION 1
69#define GDT_LINUX_OS 8 /* Used for cache optimization */
70#define GDT_SCATTER_GATHER 1 /* s/g feature */
71#define GDT_SECS32 0x1f /* round capacity */
72#define GDT_LOCALBOARD 0 /* Board node always 0 */
73#define GDT_MAXCMDS 124
74#define GDT_SECTOR_SIZE 0x200 /* Always 512 bytes for cache devs */
75#define GDT_MAX_EVENTS 0x100 /* event buffer */
76
77/* DPMEM constants */
78#define GDT_MPR_MAGIC 0xc0ffee11
79#define GDT_IC_HEADER_BYTES 48
80#define GDT_IC_QUEUE_BYTES 4
81#define GDT_DPMEM_COMMAND_OFFSET \
82 (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
83
84/* geometry constants */
85#define GDT_MAXCYLS 1024
86#define GDT_HEADS 64
87#define GDT_SECS 32 /* mapping 64*32 */
88#define GDT_MEDHEADS 127
89#define GDT_MEDSECS 63 /* mapping 127*63 */
90#define GDT_BIGHEADS 255
91#define GDT_BIGSECS 63 /* mapping 255*63 */
92
93/* data direction raw service */
94#define GDT_DATA_IN 0x01000000L
95#define GDT_DATA_OUT 0x00000000L
96
97/* Cache/raw service commands */
98#define GDT_INIT 0 /* service initialization */
99#define GDT_READ 1 /* read command */
100#define GDT_WRITE 2 /* write command */
101#define GDT_INFO 3 /* information about devices */
102#define GDT_FLUSH 4 /* flush dirty cache buffers */
103#define GDT_IOCTL 5 /* ioctl command */
104#define GDT_DEVTYPE 9 /* additional information */
105#define GDT_MOUNT 10 /* mount cache device */
106#define GDT_UNMOUNT 11 /* unmount cache device */
107#define GDT_SET_FEAT 12 /* set features (scatter/gather) */
108#define GDT_GET_FEAT 13 /* get features */
109#define GDT_WRITE_THR 16 /* write through */
110#define GDT_READ_THR 17 /* read through */
111#define GDT_EXT_INFO 18 /* extended info */
112#define GDT_RESET 19 /* controller reset */
113#define GDT_FREEZE_IO 25 /* freeze all IOs */
114#define GDT_UNFREEZE_IO 26 /* unfreeze all IOs */
115
116/* Additional raw service commands */
117#define GDT_RESERVE 14 /* reserve device to raw service */
118#define GDT_RELEASE 15 /* release device */
119#define GDT_RESERVE_ALL 16 /* reserve all devices */
120#define GDT_RELEASE_ALL 17 /* release all devices */
121#define GDT_RESET_BUS 18 /* reset bus */
122#define GDT_SCAN_START 19 /* start device scan */
123#define GDT_SCAN_END 20 /* stop device scan */
124
125/* IOCTL command defines */
126#define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */
127#define GDT_SCSI_CHAN_CNT 0x05 /* SCSI channel count */
128#define GDT_SCSI_DR_LIST 0x06 /* SCSI drive list */
129#define GDT_SCSI_DEF_CNT 0x15 /* grown/primary defects */
130#define GDT_DSK_STATISTICS 0x4b /* SCSI disk statistics */
131#define GDT_IOCHAN_DESC 0x5d /* description of IO channel */
132#define GDT_IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
133
134#define GDT_L_CTRL_PATTERN 0x20000000 /* SCSI IOCTL mask */
135#define GDT_ARRAY_INFO 0x12 /* array drive info */
136#define GDT_ARRAY_DRV_LIST 0x0f /* array drive list */
137#define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
138#define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
139#define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
140#define GDT_CACHE_INFO 0x04 /* cache info */
141#define GDT_CACHE_CONFIG 0x05 /* cache configuration */
142#define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
143#define GDT_BOARD_FEATURES 0x15 /* controller features */
144#define GDT_BOARD_INFO 0x28 /* controller info */
51
52#define IIR_CDEV_MAJOR 164
53
54#define GDT_VENDOR_ID 0x1119
55#define GDT_DEVICE_ID_MIN 0x100
56#define GDT_DEVICE_ID_MAX 0x2ff
57#define GDT_DEVICE_ID_NEWRX 0x300
58
59#define INTEL_VENDOR_ID 0x8086
60#define INTEL_DEVICE_ID_IIR 0x600
61
62#define GDT_MAXBUS 6 /* XXX Why not 5? */
63#define GDT_MAX_HDRIVES 100 /* max 100 host drives */
64#define GDT_MAXID_FC 127 /* Fibre-channel IDs */
65#define GDT_MAXID 16 /* SCSI IDs */
66#define GDT_MAXOFFSETS 128
67#define GDT_MAXSG 32 /* Max. s/g elements */
68#define GDT_PROTOCOL_VERSION 1
69#define GDT_LINUX_OS 8 /* Used for cache optimization */
70#define GDT_SCATTER_GATHER 1 /* s/g feature */
71#define GDT_SECS32 0x1f /* round capacity */
72#define GDT_LOCALBOARD 0 /* Board node always 0 */
73#define GDT_MAXCMDS 124
74#define GDT_SECTOR_SIZE 0x200 /* Always 512 bytes for cache devs */
75#define GDT_MAX_EVENTS 0x100 /* event buffer */
76
77/* DPMEM constants */
78#define GDT_MPR_MAGIC 0xc0ffee11
79#define GDT_IC_HEADER_BYTES 48
80#define GDT_IC_QUEUE_BYTES 4
81#define GDT_DPMEM_COMMAND_OFFSET \
82 (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
83
84/* geometry constants */
85#define GDT_MAXCYLS 1024
86#define GDT_HEADS 64
87#define GDT_SECS 32 /* mapping 64*32 */
88#define GDT_MEDHEADS 127
89#define GDT_MEDSECS 63 /* mapping 127*63 */
90#define GDT_BIGHEADS 255
91#define GDT_BIGSECS 63 /* mapping 255*63 */
92
93/* data direction raw service */
94#define GDT_DATA_IN 0x01000000L
95#define GDT_DATA_OUT 0x00000000L
96
97/* Cache/raw service commands */
98#define GDT_INIT 0 /* service initialization */
99#define GDT_READ 1 /* read command */
100#define GDT_WRITE 2 /* write command */
101#define GDT_INFO 3 /* information about devices */
102#define GDT_FLUSH 4 /* flush dirty cache buffers */
103#define GDT_IOCTL 5 /* ioctl command */
104#define GDT_DEVTYPE 9 /* additional information */
105#define GDT_MOUNT 10 /* mount cache device */
106#define GDT_UNMOUNT 11 /* unmount cache device */
107#define GDT_SET_FEAT 12 /* set features (scatter/gather) */
108#define GDT_GET_FEAT 13 /* get features */
109#define GDT_WRITE_THR 16 /* write through */
110#define GDT_READ_THR 17 /* read through */
111#define GDT_EXT_INFO 18 /* extended info */
112#define GDT_RESET 19 /* controller reset */
113#define GDT_FREEZE_IO 25 /* freeze all IOs */
114#define GDT_UNFREEZE_IO 26 /* unfreeze all IOs */
115
116/* Additional raw service commands */
117#define GDT_RESERVE 14 /* reserve device to raw service */
118#define GDT_RELEASE 15 /* release device */
119#define GDT_RESERVE_ALL 16 /* reserve all devices */
120#define GDT_RELEASE_ALL 17 /* release all devices */
121#define GDT_RESET_BUS 18 /* reset bus */
122#define GDT_SCAN_START 19 /* start device scan */
123#define GDT_SCAN_END 20 /* stop device scan */
124
125/* IOCTL command defines */
126#define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */
127#define GDT_SCSI_CHAN_CNT 0x05 /* SCSI channel count */
128#define GDT_SCSI_DR_LIST 0x06 /* SCSI drive list */
129#define GDT_SCSI_DEF_CNT 0x15 /* grown/primary defects */
130#define GDT_DSK_STATISTICS 0x4b /* SCSI disk statistics */
131#define GDT_IOCHAN_DESC 0x5d /* description of IO channel */
132#define GDT_IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
133
134#define GDT_L_CTRL_PATTERN 0x20000000 /* SCSI IOCTL mask */
135#define GDT_ARRAY_INFO 0x12 /* array drive info */
136#define GDT_ARRAY_DRV_LIST 0x0f /* array drive list */
137#define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
138#define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
139#define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
140#define GDT_CACHE_INFO 0x04 /* cache info */
141#define GDT_CACHE_CONFIG 0x05 /* cache configuration */
142#define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
143#define GDT_BOARD_FEATURES 0x15 /* controller features */
144#define GDT_BOARD_INFO 0x28 /* controller info */
145#define GDT_OEM_STR_RECORD 0x84 /* OEM info */
145#define GDT_HOST_GET 0x10001 /* get host drive list */
146#define GDT_IO_CHANNEL 0x20000 /* default IO channel */
147#define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
148
149/* IOCTLs */
150#define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
151#define GDT_IOCTL_DRVERS _IOWR('J', 1, int) /* get driver version */
152#define GDT_IOCTL_CTRTYPE _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
153#define GDT_IOCTL_OSVERS _IOR('J', 3, gdt_osv_t) /* get OS version */
154#define GDT_IOCTL_CTRCNT _IOR('J', 5, int) /* get ctr. count */
155#define GDT_IOCTL_EVENT _IOWR('J', 8, gdt_event_t) /* get event */
156#define GDT_IOCTL_STATIST _IOR('J', 9, gdt_statist_t) /* get statistics */
157
158/* Service errors */
159#define GDT_S_OK 1 /* no error */
160#define GDT_S_BSY 7 /* controller busy */
161#define GDT_S_RAW_SCSI 12 /* raw service: target error */
162#define GDT_S_RAW_ILL 0xff /* raw service: illegal */
163#define GDT_S_NO_STATUS 0x1000 /* got no status (driver-generated) */
164
165/* Controller services */
166#define GDT_SCSIRAWSERVICE 3
167#define GDT_CACHESERVICE 9
168#define GDT_SCREENSERVICE 11
169
170/* Scatter/gather element */
171#define GDT_SG_PTR 0x00 /* u_int32_t, address */
172#define GDT_SG_LEN 0x04 /* u_int32_t, length */
173#define GDT_SG_SZ 0x08
174
175/* Cache service command */
176#define GDT_CACHE_DEVICENO 0x00 /* u_int16_t, number of cache drive */
177#define GDT_CACHE_BLOCKNO 0x02 /* u_int32_t, block number */
178#define GDT_CACHE_BLOCKCNT 0x06 /* u_int32_t, block count */
179#define GDT_CACHE_DESTADDR 0x0a /* u_int32_t, dest. addr. (-1: s/g) */
180#define GDT_CACHE_SG_CANZ 0x0e /* u_int32_t, s/g element count */
181#define GDT_CACHE_SG_LST 0x12 /* [GDT_MAXSG], s/g list */
182#define GDT_CACHE_SZ (0x12 + GDT_MAXSG * GDT_SG_SZ)
183
184/* Ioctl command */
185#define GDT_IOCTL_PARAM_SIZE 0x00 /* u_int16_t, size of buffer */
186#define GDT_IOCTL_SUBFUNC 0x02 /* u_int32_t, ioctl function */
187#define GDT_IOCTL_CHANNEL 0x06 /* u_int32_t, device */
188#define GDT_IOCTL_P_PARAM 0x0a /* u_int32_t, buffer */
189#define GDT_IOCTL_SZ 0x0e
190
191/* Screen service defines */
192#define GDT_MSG_INV_HANDLE -1 /* special message handle */
193#define GDT_MSGLEN 16 /* size of message text */
194#define GDT_MSG_SIZE 34 /* size of message structure */
195#define GDT_MSG_REQUEST 0 /* async. event. message */
196
197/* Screen service command */
198#define GDT_SCREEN_MSG_HANDLE 0x02 /* u_int32_t, message handle */
199#define GDT_SCREEN_MSG_ADDR 0x06 /* u_int32_t, message buffer address */
200#define GDT_SCREEN_SZ 0x0a
201
202/* Screen service message */
203#define GDT_SCR_MSG_HANDLE 0x00 /* u_int32_t, message handle */
204#define GDT_SCR_MSG_LEN 0x04 /* u_int32_t, size of message */
205#define GDT_SCR_MSG_ALEN 0x08 /* u_int32_t, answer length */
206#define GDT_SCR_MSG_ANSWER 0x0c /* u_int8_t, answer flag */
207#define GDT_SCR_MSG_EXT 0x0d /* u_int8_t, more messages? */
208#define GDT_SCR_MSG_RES 0x0e /* u_int16_t, reserved */
209#define GDT_SCR_MSG_TEXT 0x10 /* GDT_MSGLEN+2, message text */
210#define GDT_SCR_MSG_SZ (0x12 + GDT_MSGLEN)
211
212/* Raw service command */
213#define GDT_RAW_DIRECTION 0x02 /* u_int32_t, data direction */
214#define GDT_RAW_MDISC_TIME 0x06 /* u_int32_t, disc. time (0: none) */
215#define GDT_RAW_MCON_TIME 0x0a /* u_int32_t, conn. time (0: none) */
216#define GDT_RAW_SDATA 0x0e /* u_int32_t, dest. addr. (-1: s/g) */
217#define GDT_RAW_SDLEN 0x12 /* u_int32_t, data length */
218#define GDT_RAW_CLEN 0x16 /* u_int32_t, SCSI cmd len (6/10/12) */
219#define GDT_RAW_CMD 0x1a /* u_int8_t [12], SCSI command */
220#define GDT_RAW_TARGET 0x26 /* u_int8_t, target ID */
221#define GDT_RAW_LUN 0x27 /* u_int8_t, LUN */
222#define GDT_RAW_BUS 0x28 /* u_int8_t, SCSI bus number */
223#define GDT_RAW_PRIORITY 0x29 /* u_int8_t, only 0 used */
224#define GDT_RAW_SENSE_LEN 0x2a /* u_int32_t, sense data length */
225#define GDT_RAW_SENSE_DATA 0x2e /* u_int32_t, sense data address */
226#define GDT_RAW_SG_RANZ 0x36 /* u_int32_t, s/g element count */
227#define GDT_RAW_SG_LST 0x3a /* [GDT_MAXSG], s/g list */
228#define GDT_RAW_SZ (0x3a + GDT_MAXSG * GDT_SG_SZ)
229
230/* Command structure */
231#define GDT_CMD_BOARDNODE 0x00 /* u_int32_t, board node (always 0) */
232#define GDT_CMD_COMMANDINDEX 0x04 /* u_int32_t, command number */
233#define GDT_CMD_OPCODE 0x08 /* u_int16_t, opcode (READ, ...) */
234#define GDT_CMD_UNION 0x0a /* cache/screen/raw service command */
235#define GDT_CMD_UNION_SZ GDT_RAW_SZ
236#define GDT_CMD_SZ (0x0a + GDT_CMD_UNION_SZ)
237
238/* Command queue entries */
239#define GDT_OFFSET 0x00 /* u_int16_t, command offset in the DP RAM */
240#define GDT_SERV_ID 0x02 /* u_int16_t, service */
241#define GDT_COMM_Q_SZ 0x04
242
243/* Interface area */
244#define GDT_S_CMD_INDX 0x00 /* u_int8_t, special command */
245#define GDT_S_STATUS 0x01 /* volatile u_int8_t, status special command */
246#define GDT_S_INFO 0x04 /* u_int32_t [4], add. info special command */
247#define GDT_SEMA0 0x14 /* volatile u_int8_t, command semaphore */
248#define GDT_CMD_INDEX 0x18 /* u_int8_t, command number */
249#define GDT_STATUS 0x1c /* volatile u_int16_t, command status */
250#define GDT_SERVICE 0x1e /* u_int16_t, service (for asynch. events) */
251#define GDT_DPR_INFO 0x20 /* u_int32_t [2], additional info */
252#define GDT_COMM_QUEUE 0x28 /* command queue */
253#define GDT_DPR_CMD (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
254 /* u_int8_t [], commands */
255
256/* I/O channel header */
257#define GDT_IOC_VERSION 0x00 /* u_int32_t, version (~0: newest) */
258#define GDT_IOC_LIST_ENTRIES 0x04 /* u_int8_t, list entry count */
259#define GDT_IOC_FIRST_CHAN 0x05 /* u_int8_t, first channel number */
260#define GDT_IOC_LAST_CHAN 0x06 /* u_int8_t, last channel number */
261#define GDT_IOC_CHAN_COUNT 0x07 /* u_int8_t, (R) channel count */
262#define GDT_IOC_LIST_OFFSET 0x08 /* u_int32_t, offset of list[0] */
263#define GDT_IOC_HDR_SZ 0x0c
264
265#define GDT_IOC_NEWEST 0xffffffff /* goes into GDT_IOC_VERSION */
266
267/* Get I/O channel description */
268#define GDT_IOC_ADDRESS 0x00 /* u_int32_t, channel address */
269#define GDT_IOC_TYPE 0x04 /* u_int8_t, type (SCSI/FCSL) */
270#define GDT_IOC_LOCAL_NO 0x05 /* u_int8_t, local number */
271#define GDT_IOC_FEATURES 0x06 /* u_int16_t, channel features */
272#define GDT_IOC_SZ 0x08
273
274/* Get raw I/O channel description */
275#define GDT_RAWIOC_PROC_ID 0x00 /* u_int8_t, processor id */
276#define GDT_RAWIOC_PROC_DEFECT 0x01 /* u_int8_t, defect? */
277#define GDT_RAWIOC_SZ 0x04
278
279/* Get SCSI channel count */
280#define GDT_GETCH_CHANNEL_NO 0x00 /* u_int32_t, channel number */
281#define GDT_GETCH_DRIVE_CNT 0x04 /* u_int32_t, drive count */
282#define GDT_GETCH_SIOP_ID 0x08 /* u_int8_t, SCSI processor ID */
283#define GDT_GETCH_SIOP_STATE 0x09 /* u_int8_t, SCSI processor state */
284#define GDT_GETCH_SZ 0x0a
285
286/* Cache info/config IOCTL structures */
287#define GDT_CPAR_VERSION 0x00 /* u_int32_t, firmware version */
288#define GDT_CPAR_STATE 0x04 /* u_int16_t, cache state (on/off) */
289#define GDT_CPAR_STRATEGY 0x06 /* u_int16_t, cache strategy */
290#define GDT_CPAR_WRITE_BACK 0x08 /* u_int16_t, write back (on/off) */
291#define GDT_CPAR_BLOCK_SIZE 0x0a /* u_int16_t, cache block size */
292#define GDT_CPAR_SZ 0x0c
293
294#define GDT_CSTAT_CSIZE 0x00 /* u_int32_t, cache size */
295#define GDT_CSTAT_READ_CNT 0x04 /* u_int32_t, read counter */
296#define GDT_CSTAT_WRITE_CNT 0x08 /* u_int32_t, write counter */
297#define GDT_CSTAT_TR_HITS 0x0c /* u_int32_t, track hits */
298#define GDT_CSTAT_SEC_HITS 0x10 /* u_int32_t, sector hits */
299#define GDT_CSTAT_SEC_MISS 0x14 /* u_int32_t, sector misses */
300#define GDT_CSTAT_SZ 0x18
301
302/* Get cache info */
303#define GDT_CINFO_CPAR 0x00
304#define GDT_CINFO_CSTAT GDT_CPAR_SZ
305#define GDT_CINFO_SZ (GDT_CPAR_SZ + GDT_CSTAT_SZ)
306
307/* Get board info */
308#define GDT_BINFO_SER_NO 0x00 /* u_int32_t, serial number */
309#define GDT_BINFO_OEM_ID 0x04 /* u_int8_t [2], OEM ID */
310#define GDT_BINFO_EP_FLAGS 0x06 /* u_int16_t, eprom flags */
311#define GDT_BINFO_PROC_ID 0x08 /* u_int32_t, processor ID */
312#define GDT_BINFO_MEMSIZE 0x0c /* u_int32_t, memory size (bytes) */
313#define GDT_BINFO_MEM_BANKS 0x10 /* u_int8_t, memory banks */
314#define GDT_BINFO_CHAN_TYPE 0x11 /* u_int8_t, channel type */
315#define GDT_BINFO_CHAN_COUNT 0x12 /* u_int8_t, channel count */
316#define GDT_BINFO_RDONGLE_PRES 0x13 /* u_int8_t, dongle present */
317#define GDT_BINFO_EPR_FW_VER 0x14 /* u_int32_t, (eprom) firmware ver */
318#define GDT_BINFO_UPD_FW_VER 0x18 /* u_int32_t, (update) firmware ver */
319#define GDT_BINFO_UPD_REVISION 0x1c /* u_int32_t, update revision */
320#define GDT_BINFO_TYPE_STRING 0x20 /* char [16], controller name */
321#define GDT_BINFO_RAID_STRING 0x30 /* char [16], RAID firmware name */
322#define GDT_BINFO_UPDATE_PRES 0x40 /* u_int8_t, update present? */
323#define GDT_BINFO_XOR_PRES 0x41 /* u_int8_t, XOR engine present */
324#define GDT_BINFO_PROM_TYPE 0x42 /* u_int8_t, ROM type (eprom/flash) */
325#define GDT_BINFO_PROM_COUNT 0x43 /* u_int8_t, number of ROM devices */
326#define GDT_BINFO_DUP_PRES 0x44 /* u_int32_t, duplexing module pres? */
327#define GDT_BINFO_CHAN_PRES 0x48 /* u_int32_t, # of exp. channels */
328#define GDT_BINFO_MEM_PRES 0x4c /* u_int32_t, memory expansion inst? */
329#define GDT_BINFO_FT_BUS_SYSTEM 0x50 /* u_int8_t, fault bus supported? */
330#define GDT_BINFO_SUBTYPE_VALID 0x51 /* u_int8_t, board_subtype valid */
331#define GDT_BINFO_BOARD_SUBTYPE 0x52 /* u_int8_t, subtype/hardware level */
332#define GDT_BINFO_RAMPAR_PRES 0x53 /* u_int8_t, RAM parity check hw? */
333#define GDT_BINFO_SZ 0x54
334
335/* Get board features */
336#define GDT_BFEAT_CHAINING 0x00 /* u_int8_t, chaining supported */
337#define GDT_BFEAT_STRIPING 0x01 /* u_int8_t, striping (RAID-0) supp. */
338#define GDT_BFEAT_MIRRORING 0x02 /* u_int8_t, mirroring (RAID-1) supp */
339#define GDT_BFEAT_RAID 0x03 /* u_int8_t, RAID-4/5/10 supported */
340#define GDT_BFEAT_SZ 0x04
341
342/* Other defines */
343#define GDT_ASYNCINDEX 0 /* command index asynchronous event */
344#define GDT_SPEZINDEX 1 /* command index unknown service */
345
346/* Debugging */
347#ifdef GDT_DEBUG
348#define GDT_D_INTR 0x01
349#define GDT_D_MISC 0x02
350#define GDT_D_CMD 0x04
351#define GDT_D_QUEUE 0x08
352#define GDT_D_TIMEOUT 0x10
353#define GDT_D_INIT 0x20
354#define GDT_D_INVALID 0x40
355#define GDT_D_DEBUG 0x80
356extern int gdt_debug;
357#ifdef __SERIAL__
358extern int ser_printf(const char *fmt, ...);
359#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_printf args
360#else
361#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
362#endif
363#else
364#define GDT_DPRINTF(mask, args)
365#endif
366
367/* Miscellaneous constants */
368#define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
369#define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
370#define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
371#define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
372#define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
373
146#define GDT_HOST_GET 0x10001 /* get host drive list */
147#define GDT_IO_CHANNEL 0x20000 /* default IO channel */
148#define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
149
150/* IOCTLs */
151#define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
152#define GDT_IOCTL_DRVERS _IOWR('J', 1, int) /* get driver version */
153#define GDT_IOCTL_CTRTYPE _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
154#define GDT_IOCTL_OSVERS _IOR('J', 3, gdt_osv_t) /* get OS version */
155#define GDT_IOCTL_CTRCNT _IOR('J', 5, int) /* get ctr. count */
156#define GDT_IOCTL_EVENT _IOWR('J', 8, gdt_event_t) /* get event */
157#define GDT_IOCTL_STATIST _IOR('J', 9, gdt_statist_t) /* get statistics */
158
159/* Service errors */
160#define GDT_S_OK 1 /* no error */
161#define GDT_S_BSY 7 /* controller busy */
162#define GDT_S_RAW_SCSI 12 /* raw service: target error */
163#define GDT_S_RAW_ILL 0xff /* raw service: illegal */
164#define GDT_S_NO_STATUS 0x1000 /* got no status (driver-generated) */
165
166/* Controller services */
167#define GDT_SCSIRAWSERVICE 3
168#define GDT_CACHESERVICE 9
169#define GDT_SCREENSERVICE 11
170
171/* Scatter/gather element */
172#define GDT_SG_PTR 0x00 /* u_int32_t, address */
173#define GDT_SG_LEN 0x04 /* u_int32_t, length */
174#define GDT_SG_SZ 0x08
175
176/* Cache service command */
177#define GDT_CACHE_DEVICENO 0x00 /* u_int16_t, number of cache drive */
178#define GDT_CACHE_BLOCKNO 0x02 /* u_int32_t, block number */
179#define GDT_CACHE_BLOCKCNT 0x06 /* u_int32_t, block count */
180#define GDT_CACHE_DESTADDR 0x0a /* u_int32_t, dest. addr. (-1: s/g) */
181#define GDT_CACHE_SG_CANZ 0x0e /* u_int32_t, s/g element count */
182#define GDT_CACHE_SG_LST 0x12 /* [GDT_MAXSG], s/g list */
183#define GDT_CACHE_SZ (0x12 + GDT_MAXSG * GDT_SG_SZ)
184
185/* Ioctl command */
186#define GDT_IOCTL_PARAM_SIZE 0x00 /* u_int16_t, size of buffer */
187#define GDT_IOCTL_SUBFUNC 0x02 /* u_int32_t, ioctl function */
188#define GDT_IOCTL_CHANNEL 0x06 /* u_int32_t, device */
189#define GDT_IOCTL_P_PARAM 0x0a /* u_int32_t, buffer */
190#define GDT_IOCTL_SZ 0x0e
191
192/* Screen service defines */
193#define GDT_MSG_INV_HANDLE -1 /* special message handle */
194#define GDT_MSGLEN 16 /* size of message text */
195#define GDT_MSG_SIZE 34 /* size of message structure */
196#define GDT_MSG_REQUEST 0 /* async. event. message */
197
198/* Screen service command */
199#define GDT_SCREEN_MSG_HANDLE 0x02 /* u_int32_t, message handle */
200#define GDT_SCREEN_MSG_ADDR 0x06 /* u_int32_t, message buffer address */
201#define GDT_SCREEN_SZ 0x0a
202
203/* Screen service message */
204#define GDT_SCR_MSG_HANDLE 0x00 /* u_int32_t, message handle */
205#define GDT_SCR_MSG_LEN 0x04 /* u_int32_t, size of message */
206#define GDT_SCR_MSG_ALEN 0x08 /* u_int32_t, answer length */
207#define GDT_SCR_MSG_ANSWER 0x0c /* u_int8_t, answer flag */
208#define GDT_SCR_MSG_EXT 0x0d /* u_int8_t, more messages? */
209#define GDT_SCR_MSG_RES 0x0e /* u_int16_t, reserved */
210#define GDT_SCR_MSG_TEXT 0x10 /* GDT_MSGLEN+2, message text */
211#define GDT_SCR_MSG_SZ (0x12 + GDT_MSGLEN)
212
213/* Raw service command */
214#define GDT_RAW_DIRECTION 0x02 /* u_int32_t, data direction */
215#define GDT_RAW_MDISC_TIME 0x06 /* u_int32_t, disc. time (0: none) */
216#define GDT_RAW_MCON_TIME 0x0a /* u_int32_t, conn. time (0: none) */
217#define GDT_RAW_SDATA 0x0e /* u_int32_t, dest. addr. (-1: s/g) */
218#define GDT_RAW_SDLEN 0x12 /* u_int32_t, data length */
219#define GDT_RAW_CLEN 0x16 /* u_int32_t, SCSI cmd len (6/10/12) */
220#define GDT_RAW_CMD 0x1a /* u_int8_t [12], SCSI command */
221#define GDT_RAW_TARGET 0x26 /* u_int8_t, target ID */
222#define GDT_RAW_LUN 0x27 /* u_int8_t, LUN */
223#define GDT_RAW_BUS 0x28 /* u_int8_t, SCSI bus number */
224#define GDT_RAW_PRIORITY 0x29 /* u_int8_t, only 0 used */
225#define GDT_RAW_SENSE_LEN 0x2a /* u_int32_t, sense data length */
226#define GDT_RAW_SENSE_DATA 0x2e /* u_int32_t, sense data address */
227#define GDT_RAW_SG_RANZ 0x36 /* u_int32_t, s/g element count */
228#define GDT_RAW_SG_LST 0x3a /* [GDT_MAXSG], s/g list */
229#define GDT_RAW_SZ (0x3a + GDT_MAXSG * GDT_SG_SZ)
230
231/* Command structure */
232#define GDT_CMD_BOARDNODE 0x00 /* u_int32_t, board node (always 0) */
233#define GDT_CMD_COMMANDINDEX 0x04 /* u_int32_t, command number */
234#define GDT_CMD_OPCODE 0x08 /* u_int16_t, opcode (READ, ...) */
235#define GDT_CMD_UNION 0x0a /* cache/screen/raw service command */
236#define GDT_CMD_UNION_SZ GDT_RAW_SZ
237#define GDT_CMD_SZ (0x0a + GDT_CMD_UNION_SZ)
238
239/* Command queue entries */
240#define GDT_OFFSET 0x00 /* u_int16_t, command offset in the DP RAM */
241#define GDT_SERV_ID 0x02 /* u_int16_t, service */
242#define GDT_COMM_Q_SZ 0x04
243
244/* Interface area */
245#define GDT_S_CMD_INDX 0x00 /* u_int8_t, special command */
246#define GDT_S_STATUS 0x01 /* volatile u_int8_t, status special command */
247#define GDT_S_INFO 0x04 /* u_int32_t [4], add. info special command */
248#define GDT_SEMA0 0x14 /* volatile u_int8_t, command semaphore */
249#define GDT_CMD_INDEX 0x18 /* u_int8_t, command number */
250#define GDT_STATUS 0x1c /* volatile u_int16_t, command status */
251#define GDT_SERVICE 0x1e /* u_int16_t, service (for asynch. events) */
252#define GDT_DPR_INFO 0x20 /* u_int32_t [2], additional info */
253#define GDT_COMM_QUEUE 0x28 /* command queue */
254#define GDT_DPR_CMD (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
255 /* u_int8_t [], commands */
256
257/* I/O channel header */
258#define GDT_IOC_VERSION 0x00 /* u_int32_t, version (~0: newest) */
259#define GDT_IOC_LIST_ENTRIES 0x04 /* u_int8_t, list entry count */
260#define GDT_IOC_FIRST_CHAN 0x05 /* u_int8_t, first channel number */
261#define GDT_IOC_LAST_CHAN 0x06 /* u_int8_t, last channel number */
262#define GDT_IOC_CHAN_COUNT 0x07 /* u_int8_t, (R) channel count */
263#define GDT_IOC_LIST_OFFSET 0x08 /* u_int32_t, offset of list[0] */
264#define GDT_IOC_HDR_SZ 0x0c
265
266#define GDT_IOC_NEWEST 0xffffffff /* goes into GDT_IOC_VERSION */
267
268/* Get I/O channel description */
269#define GDT_IOC_ADDRESS 0x00 /* u_int32_t, channel address */
270#define GDT_IOC_TYPE 0x04 /* u_int8_t, type (SCSI/FCSL) */
271#define GDT_IOC_LOCAL_NO 0x05 /* u_int8_t, local number */
272#define GDT_IOC_FEATURES 0x06 /* u_int16_t, channel features */
273#define GDT_IOC_SZ 0x08
274
275/* Get raw I/O channel description */
276#define GDT_RAWIOC_PROC_ID 0x00 /* u_int8_t, processor id */
277#define GDT_RAWIOC_PROC_DEFECT 0x01 /* u_int8_t, defect? */
278#define GDT_RAWIOC_SZ 0x04
279
280/* Get SCSI channel count */
281#define GDT_GETCH_CHANNEL_NO 0x00 /* u_int32_t, channel number */
282#define GDT_GETCH_DRIVE_CNT 0x04 /* u_int32_t, drive count */
283#define GDT_GETCH_SIOP_ID 0x08 /* u_int8_t, SCSI processor ID */
284#define GDT_GETCH_SIOP_STATE 0x09 /* u_int8_t, SCSI processor state */
285#define GDT_GETCH_SZ 0x0a
286
287/* Cache info/config IOCTL structures */
288#define GDT_CPAR_VERSION 0x00 /* u_int32_t, firmware version */
289#define GDT_CPAR_STATE 0x04 /* u_int16_t, cache state (on/off) */
290#define GDT_CPAR_STRATEGY 0x06 /* u_int16_t, cache strategy */
291#define GDT_CPAR_WRITE_BACK 0x08 /* u_int16_t, write back (on/off) */
292#define GDT_CPAR_BLOCK_SIZE 0x0a /* u_int16_t, cache block size */
293#define GDT_CPAR_SZ 0x0c
294
295#define GDT_CSTAT_CSIZE 0x00 /* u_int32_t, cache size */
296#define GDT_CSTAT_READ_CNT 0x04 /* u_int32_t, read counter */
297#define GDT_CSTAT_WRITE_CNT 0x08 /* u_int32_t, write counter */
298#define GDT_CSTAT_TR_HITS 0x0c /* u_int32_t, track hits */
299#define GDT_CSTAT_SEC_HITS 0x10 /* u_int32_t, sector hits */
300#define GDT_CSTAT_SEC_MISS 0x14 /* u_int32_t, sector misses */
301#define GDT_CSTAT_SZ 0x18
302
303/* Get cache info */
304#define GDT_CINFO_CPAR 0x00
305#define GDT_CINFO_CSTAT GDT_CPAR_SZ
306#define GDT_CINFO_SZ (GDT_CPAR_SZ + GDT_CSTAT_SZ)
307
308/* Get board info */
309#define GDT_BINFO_SER_NO 0x00 /* u_int32_t, serial number */
310#define GDT_BINFO_OEM_ID 0x04 /* u_int8_t [2], OEM ID */
311#define GDT_BINFO_EP_FLAGS 0x06 /* u_int16_t, eprom flags */
312#define GDT_BINFO_PROC_ID 0x08 /* u_int32_t, processor ID */
313#define GDT_BINFO_MEMSIZE 0x0c /* u_int32_t, memory size (bytes) */
314#define GDT_BINFO_MEM_BANKS 0x10 /* u_int8_t, memory banks */
315#define GDT_BINFO_CHAN_TYPE 0x11 /* u_int8_t, channel type */
316#define GDT_BINFO_CHAN_COUNT 0x12 /* u_int8_t, channel count */
317#define GDT_BINFO_RDONGLE_PRES 0x13 /* u_int8_t, dongle present */
318#define GDT_BINFO_EPR_FW_VER 0x14 /* u_int32_t, (eprom) firmware ver */
319#define GDT_BINFO_UPD_FW_VER 0x18 /* u_int32_t, (update) firmware ver */
320#define GDT_BINFO_UPD_REVISION 0x1c /* u_int32_t, update revision */
321#define GDT_BINFO_TYPE_STRING 0x20 /* char [16], controller name */
322#define GDT_BINFO_RAID_STRING 0x30 /* char [16], RAID firmware name */
323#define GDT_BINFO_UPDATE_PRES 0x40 /* u_int8_t, update present? */
324#define GDT_BINFO_XOR_PRES 0x41 /* u_int8_t, XOR engine present */
325#define GDT_BINFO_PROM_TYPE 0x42 /* u_int8_t, ROM type (eprom/flash) */
326#define GDT_BINFO_PROM_COUNT 0x43 /* u_int8_t, number of ROM devices */
327#define GDT_BINFO_DUP_PRES 0x44 /* u_int32_t, duplexing module pres? */
328#define GDT_BINFO_CHAN_PRES 0x48 /* u_int32_t, # of exp. channels */
329#define GDT_BINFO_MEM_PRES 0x4c /* u_int32_t, memory expansion inst? */
330#define GDT_BINFO_FT_BUS_SYSTEM 0x50 /* u_int8_t, fault bus supported? */
331#define GDT_BINFO_SUBTYPE_VALID 0x51 /* u_int8_t, board_subtype valid */
332#define GDT_BINFO_BOARD_SUBTYPE 0x52 /* u_int8_t, subtype/hardware level */
333#define GDT_BINFO_RAMPAR_PRES 0x53 /* u_int8_t, RAM parity check hw? */
334#define GDT_BINFO_SZ 0x54
335
336/* Get board features */
337#define GDT_BFEAT_CHAINING 0x00 /* u_int8_t, chaining supported */
338#define GDT_BFEAT_STRIPING 0x01 /* u_int8_t, striping (RAID-0) supp. */
339#define GDT_BFEAT_MIRRORING 0x02 /* u_int8_t, mirroring (RAID-1) supp */
340#define GDT_BFEAT_RAID 0x03 /* u_int8_t, RAID-4/5/10 supported */
341#define GDT_BFEAT_SZ 0x04
342
343/* Other defines */
344#define GDT_ASYNCINDEX 0 /* command index asynchronous event */
345#define GDT_SPEZINDEX 1 /* command index unknown service */
346
347/* Debugging */
348#ifdef GDT_DEBUG
349#define GDT_D_INTR 0x01
350#define GDT_D_MISC 0x02
351#define GDT_D_CMD 0x04
352#define GDT_D_QUEUE 0x08
353#define GDT_D_TIMEOUT 0x10
354#define GDT_D_INIT 0x20
355#define GDT_D_INVALID 0x40
356#define GDT_D_DEBUG 0x80
357extern int gdt_debug;
358#ifdef __SERIAL__
359extern int ser_printf(const char *fmt, ...);
360#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_printf args
361#else
362#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
363#endif
364#else
365#define GDT_DPRINTF(mask, args)
366#endif
367
368/* Miscellaneous constants */
369#define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
370#define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
371#define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
372#define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
373#define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
374
374/* macros */
375#define letoh32(v) le32toh(v)
376#define letoh16(v) le16toh(v)
377
378/* Map minor numbers to device identity */
379#define LUN_MASK 0x0007
380#define TARGET_MASK 0x03f8
381#define BUS_MASK 0x1c00
382#define HBA_MASK 0xe000
383
384#define minor2lun(minor) ( minor & LUN_MASK )
385#define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )
386#define minor2bus(minor) ( (minor & BUS_MASK) >> 10 )
387#define minor2hba(minor) ( (minor & HBA_MASK) >> 13 )
388#define hba2minor(hba) ( (hba << 13) & HBA_MASK )
389
390
391/* struct for GDT_IOCTL_GENERAL */
392#pragma pack(1)
393typedef struct gdt_ucmd {
394 u_int16_t io_node;
395 u_int16_t service;
396 u_int32_t timeout;
397 u_int16_t status;
398 u_int32_t info;
399
400 u_int32_t BoardNode; /* board node (always 0) */
401 u_int32_t CommandIndex; /* command number */
402 u_int16_t OpCode; /* the command (READ,..) */
403 union {
404 struct {
405 u_int16_t DeviceNo; /* number of cache drive */
406 u_int32_t BlockNo; /* block number */
407 u_int32_t BlockCnt; /* block count */
408 void *DestAddr; /* data */
409 } cache; /* cache service cmd. str. */
410 struct {
411 u_int16_t param_size; /* size of p_param buffer */
412 u_int32_t subfunc; /* IOCTL function */
413 u_int32_t channel; /* device */
414 void *p_param; /* data */
415 } ioctl; /* IOCTL command structure */
416 struct {
417 u_int16_t reserved;
418 u_int32_t direction; /* data direction */
419 u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
420 u_int32_t mcon_time; /* connect time(0: no to.) */
421 void *sdata; /* dest. addr. (if s/g: -1) */
422 u_int32_t sdlen; /* data length (bytes) */
423 u_int32_t clen; /* SCSI cmd. length(6,10,12) */
424 u_int8_t cmd[12]; /* SCSI command */
425 u_int8_t target; /* target ID */
426 u_int8_t lun; /* LUN */
427 u_int8_t bus; /* SCSI bus number */
428 u_int8_t priority; /* only 0 used */
429 u_int32_t sense_len; /* sense data length */
430 void *sense_data; /* sense data addr. */
431 u_int32_t link_p; /* linked cmds (not supp.) */
432 } raw; /* raw service cmd. struct. */
433 } u;
434 u_int8_t data[GDT_SCRATCH_SZ];
435 int complete_flag;
436 TAILQ_ENTRY(gdt_ucmd) links;
437} gdt_ucmd_t;
438
439/* struct for GDT_IOCTL_CTRTYPE */
440typedef struct gdt_ctrt {
441 u_int16_t io_node;
442 u_int16_t oem_id;
443 u_int16_t type;
444 u_int32_t info;
445 u_int8_t access;
446 u_int8_t remote;
447 u_int16_t ext_type;
448 u_int16_t device_id;
449 u_int16_t sub_device_id;
450} gdt_ctrt_t;
451
452/* struct for GDT_IOCTL_OSVERS */
453typedef struct gdt_osv {
454 u_int8_t oscode;
455 u_int8_t version;
456 u_int8_t subversion;
457 u_int16_t revision;
458 char name[64];
459} gdt_osv_t;
460
375/* Map minor numbers to device identity */
376#define LUN_MASK 0x0007
377#define TARGET_MASK 0x03f8
378#define BUS_MASK 0x1c00
379#define HBA_MASK 0xe000
380
381#define minor2lun(minor) ( minor & LUN_MASK )
382#define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )
383#define minor2bus(minor) ( (minor & BUS_MASK) >> 10 )
384#define minor2hba(minor) ( (minor & HBA_MASK) >> 13 )
385#define hba2minor(hba) ( (hba << 13) & HBA_MASK )
386
387
388/* struct for GDT_IOCTL_GENERAL */
389#pragma pack(1)
390typedef struct gdt_ucmd {
391 u_int16_t io_node;
392 u_int16_t service;
393 u_int32_t timeout;
394 u_int16_t status;
395 u_int32_t info;
396
397 u_int32_t BoardNode; /* board node (always 0) */
398 u_int32_t CommandIndex; /* command number */
399 u_int16_t OpCode; /* the command (READ,..) */
400 union {
401 struct {
402 u_int16_t DeviceNo; /* number of cache drive */
403 u_int32_t BlockNo; /* block number */
404 u_int32_t BlockCnt; /* block count */
405 void *DestAddr; /* data */
406 } cache; /* cache service cmd. str. */
407 struct {
408 u_int16_t param_size; /* size of p_param buffer */
409 u_int32_t subfunc; /* IOCTL function */
410 u_int32_t channel; /* device */
411 void *p_param; /* data */
412 } ioctl; /* IOCTL command structure */
413 struct {
414 u_int16_t reserved;
415 u_int32_t direction; /* data direction */
416 u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
417 u_int32_t mcon_time; /* connect time(0: no to.) */
418 void *sdata; /* dest. addr. (if s/g: -1) */
419 u_int32_t sdlen; /* data length (bytes) */
420 u_int32_t clen; /* SCSI cmd. length(6,10,12) */
421 u_int8_t cmd[12]; /* SCSI command */
422 u_int8_t target; /* target ID */
423 u_int8_t lun; /* LUN */
424 u_int8_t bus; /* SCSI bus number */
425 u_int8_t priority; /* only 0 used */
426 u_int32_t sense_len; /* sense data length */
427 void *sense_data; /* sense data addr. */
428 u_int32_t link_p; /* linked cmds (not supp.) */
429 } raw; /* raw service cmd. struct. */
430 } u;
431 u_int8_t data[GDT_SCRATCH_SZ];
432 int complete_flag;
433 TAILQ_ENTRY(gdt_ucmd) links;
434} gdt_ucmd_t;
435
436/* struct for GDT_IOCTL_CTRTYPE */
437typedef struct gdt_ctrt {
438 u_int16_t io_node;
439 u_int16_t oem_id;
440 u_int16_t type;
441 u_int32_t info;
442 u_int8_t access;
443 u_int8_t remote;
444 u_int16_t ext_type;
445 u_int16_t device_id;
446 u_int16_t sub_device_id;
447} gdt_ctrt_t;
448
449/* struct for GDT_IOCTL_OSVERS */
450typedef struct gdt_osv {
451 u_int8_t oscode;
452 u_int8_t version;
453 u_int8_t subversion;
454 u_int16_t revision;
455 char name[64];
456} gdt_osv_t;
457
458/* OEM */
459#define GDT_OEM_VERSION 0x00
460#define GDT_OEM_BUFSIZE 0x0c
461typedef struct {
462 u_int32_t ctl_version;
463 u_int32_t file_major_version;
464 u_int32_t file_minor_version;
465 u_int32_t buffer_size;
466 u_int32_t cpy_count;
467 u_int32_t ext_error;
468 u_int32_t oem_id;
469 u_int32_t board_id;
470} gdt_oem_param_t;
471
472typedef struct {
473 char product_0_1_name[16];
474 char product_4_5_name[16];
475 char product_cluster_name[16];
476 char product_reserved[16];
477 char scsi_cluster_target_vendor_id[16];
478 char cluster_raid_fw_name[16];
479 char oem_brand_name[16];
480 char oem_raid_type[16];
481 char bios_type[13];
482 char bios_title[50];
483 char oem_company_name[37];
484 u_int32_t pci_id_1;
485 u_int32_t pci_id_2;
486 char validation_status[80];
487 char reserved_1[4];
488 char scsi_host_drive_inquiry_vendor_id[16];
489 char library_file_template[32];
490 char tool_name_1[32];
491 char tool_name_2[32];
492 char tool_name_3[32];
493 char oem_contact_1[84];
494 char oem_contact_2[84];
495 char oem_contact_3[84];
496} gdt_oem_record_t;
497
498typedef struct {
499 gdt_oem_param_t parameters;
500 gdt_oem_record_t text;
501} gdt_oem_str_record_t;
502
503
461/* controller event structure */
462#define GDT_ES_ASYNC 1
463#define GDT_ES_DRIVER 2
464#define GDT_ES_TEST 3
465#define GDT_ES_SYNC 4
466typedef struct {
467 u_int16_t size; /* size of structure */
468 union {
469 char stream[16];
470 struct {
471 u_int16_t ionode;
472 u_int16_t service;
473 u_int32_t index;
474 } driver;
475 struct {
476 u_int16_t ionode;
477 u_int16_t service;
478 u_int16_t status;
479 u_int32_t info;
480 u_int8_t scsi_coord[3];
481 } async;
482 struct {
483 u_int16_t ionode;
484 u_int16_t service;
485 u_int16_t status;
486 u_int32_t info;
487 u_int16_t hostdrive;
488 u_int8_t scsi_coord[3];
489 u_int8_t sense_key;
490 } sync;
491 struct {
492 u_int32_t l1, l2, l3, l4;
493 } test;
494 } eu;
495 u_int32_t severity;
496 u_int8_t event_string[256];
497} gdt_evt_data;
498
499/* dvrevt structure */
500typedef struct {
501 u_int32_t first_stamp;
502 u_int32_t last_stamp;
503 u_int16_t same_count;
504 u_int16_t event_source;
505 u_int16_t event_idx;
506 u_int8_t application;
507 u_int8_t reserved;
508 gdt_evt_data event_data;
509} gdt_evt_str;
510
511/* struct for GDT_IOCTL_EVENT */
512typedef struct gdt_event {
513 int erase;
514 int handle;
515 gdt_evt_str dvr;
516} gdt_event_t;
517
518/* struct for GDT_IOCTL_STATIST */
519typedef struct gdt_statist {
520 u_int16_t io_count_act;
521 u_int16_t io_count_max;
522 u_int16_t req_queue_act;
523 u_int16_t req_queue_max;
524 u_int16_t cmd_index_act;
525 u_int16_t cmd_index_max;
526 u_int16_t sg_count_act;
527 u_int16_t sg_count_max;
528} gdt_statist_t;
529
530#pragma pack()
531
532/* Context structure for interrupt services */
533struct gdt_intr_ctx {
534 u_int32_t info, info2;
535 u_int16_t cmd_status, service;
536 u_int8_t istatus;
537};
538
539/* softc structure */
540struct gdt_softc {
541 int sc_hanum;
542 int sc_class; /* Controller class */
543#define GDT_MPR 0x05
544#define GDT_CLASS_MASK 0x07
545#define GDT_FC 0x10
546#define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
547 int sc_bus, sc_slot;
504/* controller event structure */
505#define GDT_ES_ASYNC 1
506#define GDT_ES_DRIVER 2
507#define GDT_ES_TEST 3
508#define GDT_ES_SYNC 4
509typedef struct {
510 u_int16_t size; /* size of structure */
511 union {
512 char stream[16];
513 struct {
514 u_int16_t ionode;
515 u_int16_t service;
516 u_int32_t index;
517 } driver;
518 struct {
519 u_int16_t ionode;
520 u_int16_t service;
521 u_int16_t status;
522 u_int32_t info;
523 u_int8_t scsi_coord[3];
524 } async;
525 struct {
526 u_int16_t ionode;
527 u_int16_t service;
528 u_int16_t status;
529 u_int32_t info;
530 u_int16_t hostdrive;
531 u_int8_t scsi_coord[3];
532 u_int8_t sense_key;
533 } sync;
534 struct {
535 u_int32_t l1, l2, l3, l4;
536 } test;
537 } eu;
538 u_int32_t severity;
539 u_int8_t event_string[256];
540} gdt_evt_data;
541
542/* dvrevt structure */
543typedef struct {
544 u_int32_t first_stamp;
545 u_int32_t last_stamp;
546 u_int16_t same_count;
547 u_int16_t event_source;
548 u_int16_t event_idx;
549 u_int8_t application;
550 u_int8_t reserved;
551 gdt_evt_data event_data;
552} gdt_evt_str;
553
554/* struct for GDT_IOCTL_EVENT */
555typedef struct gdt_event {
556 int erase;
557 int handle;
558 gdt_evt_str dvr;
559} gdt_event_t;
560
561/* struct for GDT_IOCTL_STATIST */
562typedef struct gdt_statist {
563 u_int16_t io_count_act;
564 u_int16_t io_count_max;
565 u_int16_t req_queue_act;
566 u_int16_t req_queue_max;
567 u_int16_t cmd_index_act;
568 u_int16_t cmd_index_max;
569 u_int16_t sg_count_act;
570 u_int16_t sg_count_max;
571} gdt_statist_t;
572
573#pragma pack()
574
575/* Context structure for interrupt services */
576struct gdt_intr_ctx {
577 u_int32_t info, info2;
578 u_int16_t cmd_status, service;
579 u_int8_t istatus;
580};
581
582/* softc structure */
583struct gdt_softc {
584 int sc_hanum;
585 int sc_class; /* Controller class */
586#define GDT_MPR 0x05
587#define GDT_CLASS_MASK 0x07
588#define GDT_FC 0x10
589#define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
590 int sc_bus, sc_slot;
591 u_int16_t sc_vendor;
548 u_int16_t sc_device, sc_subdevice;
549 u_int16_t sc_fw_vers;
550 int sc_init_level;
551 int sc_state;
552#define GDT_NORMAL 0x00
553#define GDT_POLLING 0x01
554#define GDT_SHUTDOWN 0x02
555#define GDT_POLL_WAIT 0x80
556 dev_t sc_dev;
557 bus_space_tag_t sc_dpmemt;
558 bus_space_handle_t sc_dpmemh;
559 bus_addr_t sc_dpmembase;
560 bus_dma_tag_t sc_parent_dmat;
561 bus_dma_tag_t sc_buffer_dmat;
562 bus_dma_tag_t sc_gccb_dmat;
563 bus_dmamap_t sc_gccb_dmamap;
564 bus_addr_t sc_gccb_busbase;
565
566 struct gdt_ccb *sc_gccbs;
567 SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
568 TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
569 TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
570
571 u_int16_t sc_ic_all_size;
572 u_int16_t sc_cmd_len;
573 u_int16_t sc_cmd_off;
574 u_int16_t sc_cmd_cnt;
575 u_int8_t sc_cmd[GDT_CMD_SZ];
576
577 u_int32_t sc_info;
578 u_int32_t sc_info2;
579 u_int16_t sc_status;
580 u_int16_t sc_service;
581
582 u_int8_t sc_bus_cnt;
583 u_int8_t sc_virt_bus;
584 u_int8_t sc_bus_id[GDT_MAXBUS];
585 u_int8_t sc_more_proc;
586
587 struct {
588 u_int8_t hd_present;
589 u_int8_t hd_is_logdrv;
590 u_int8_t hd_is_arraydrv;
591 u_int8_t hd_is_master;
592 u_int8_t hd_is_parity;
593 u_int8_t hd_is_hotfix;
594 u_int8_t hd_master_no;
595 u_int8_t hd_lock;
596 u_int8_t hd_heads;
597 u_int8_t hd_secs;
598 u_int16_t hd_devtype;
599 u_int32_t hd_size;
600 u_int8_t hd_ldr_no;
601 u_int8_t hd_rw_attribs;
602 u_int32_t hd_start_sec;
603 } sc_hdr[GDT_MAX_HDRIVES];
604
605 u_int16_t sc_raw_feat;
606 u_int16_t sc_cache_feat;
607
608 gdt_evt_data sc_dvr;
592 u_int16_t sc_device, sc_subdevice;
593 u_int16_t sc_fw_vers;
594 int sc_init_level;
595 int sc_state;
596#define GDT_NORMAL 0x00
597#define GDT_POLLING 0x01
598#define GDT_SHUTDOWN 0x02
599#define GDT_POLL_WAIT 0x80
600 dev_t sc_dev;
601 bus_space_tag_t sc_dpmemt;
602 bus_space_handle_t sc_dpmemh;
603 bus_addr_t sc_dpmembase;
604 bus_dma_tag_t sc_parent_dmat;
605 bus_dma_tag_t sc_buffer_dmat;
606 bus_dma_tag_t sc_gccb_dmat;
607 bus_dmamap_t sc_gccb_dmamap;
608 bus_addr_t sc_gccb_busbase;
609
610 struct gdt_ccb *sc_gccbs;
611 SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
612 TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
613 TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
614
615 u_int16_t sc_ic_all_size;
616 u_int16_t sc_cmd_len;
617 u_int16_t sc_cmd_off;
618 u_int16_t sc_cmd_cnt;
619 u_int8_t sc_cmd[GDT_CMD_SZ];
620
621 u_int32_t sc_info;
622 u_int32_t sc_info2;
623 u_int16_t sc_status;
624 u_int16_t sc_service;
625
626 u_int8_t sc_bus_cnt;
627 u_int8_t sc_virt_bus;
628 u_int8_t sc_bus_id[GDT_MAXBUS];
629 u_int8_t sc_more_proc;
630
631 struct {
632 u_int8_t hd_present;
633 u_int8_t hd_is_logdrv;
634 u_int8_t hd_is_arraydrv;
635 u_int8_t hd_is_master;
636 u_int8_t hd_is_parity;
637 u_int8_t hd_is_hotfix;
638 u_int8_t hd_master_no;
639 u_int8_t hd_lock;
640 u_int8_t hd_heads;
641 u_int8_t hd_secs;
642 u_int16_t hd_devtype;
643 u_int32_t hd_size;
644 u_int8_t hd_ldr_no;
645 u_int8_t hd_rw_attribs;
646 u_int32_t hd_start_sec;
647 } sc_hdr[GDT_MAX_HDRIVES];
648
649 u_int16_t sc_raw_feat;
650 u_int16_t sc_cache_feat;
651
652 gdt_evt_data sc_dvr;
653 char oem_name[8];
609
610 struct cam_sim *sims[GDT_MAXBUS];
611 struct cam_path *paths[GDT_MAXBUS];
612
613 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
614 u_int8_t (*sc_get_status)(struct gdt_softc *);
615 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
616 void (*sc_release_event)(struct gdt_softc *);
617 void (*sc_set_sema0)(struct gdt_softc *);
618 int (*sc_test_busy)(struct gdt_softc *);
619
620 TAILQ_ENTRY(gdt_softc) links;
621};
622
623/*
624 * A command control block, one for each corresponding command index of the
625 * controller.
626 */
627struct gdt_ccb {
628 u_int8_t gc_scratch[GDT_SCRATCH_SZ];
629 union ccb *gc_ccb;
630 gdt_ucmd_t *gc_ucmd;
631 bus_dmamap_t gc_dmamap;
632 int gc_map_flag;
633 int gc_timeout;
634 int gc_state;
635 u_int8_t gc_service;
636 u_int8_t gc_cmd_index;
637 u_int8_t gc_flags;
638#define GDT_GCF_UNUSED 0
639#define GDT_GCF_INTERNAL 1
640#define GDT_GCF_SCREEN 2
641#define GDT_GCF_SCSI 3
642#define GDT_GCF_IOCTL 4
643 SLIST_ENTRY(gdt_ccb) sle;
644};
645
646
647int iir_init(struct gdt_softc *);
648void iir_free(struct gdt_softc *);
649void iir_attach(struct gdt_softc *);
650void iir_intr(void *arg);
651
652#ifdef __GNUC__
653/* These all require correctly aligned buffers */
654static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
655static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
656static __inline__ u_int16_t gdt_dec16(u_int8_t *);
657static __inline__ u_int32_t gdt_dec32(u_int8_t *);
658
659static __inline__ void
660gdt_enc16(addr, value)
661 u_int8_t *addr;
662 u_int16_t value;
663{
664 *(u_int16_t *)addr = htole16(value);
665}
666
667static __inline__ void
668gdt_enc32(addr, value)
669 u_int8_t *addr;
670 u_int32_t value;
671{
672 *(u_int32_t *)addr = htole32(value);
673}
674
675static __inline__ u_int16_t
676gdt_dec16(addr)
677 u_int8_t *addr;
678{
654
655 struct cam_sim *sims[GDT_MAXBUS];
656 struct cam_path *paths[GDT_MAXBUS];
657
658 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
659 u_int8_t (*sc_get_status)(struct gdt_softc *);
660 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
661 void (*sc_release_event)(struct gdt_softc *);
662 void (*sc_set_sema0)(struct gdt_softc *);
663 int (*sc_test_busy)(struct gdt_softc *);
664
665 TAILQ_ENTRY(gdt_softc) links;
666};
667
668/*
669 * A command control block, one for each corresponding command index of the
670 * controller.
671 */
672struct gdt_ccb {
673 u_int8_t gc_scratch[GDT_SCRATCH_SZ];
674 union ccb *gc_ccb;
675 gdt_ucmd_t *gc_ucmd;
676 bus_dmamap_t gc_dmamap;
677 int gc_map_flag;
678 int gc_timeout;
679 int gc_state;
680 u_int8_t gc_service;
681 u_int8_t gc_cmd_index;
682 u_int8_t gc_flags;
683#define GDT_GCF_UNUSED 0
684#define GDT_GCF_INTERNAL 1
685#define GDT_GCF_SCREEN 2
686#define GDT_GCF_SCSI 3
687#define GDT_GCF_IOCTL 4
688 SLIST_ENTRY(gdt_ccb) sle;
689};
690
691
692int iir_init(struct gdt_softc *);
693void iir_free(struct gdt_softc *);
694void iir_attach(struct gdt_softc *);
695void iir_intr(void *arg);
696
697#ifdef __GNUC__
698/* These all require correctly aligned buffers */
699static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
700static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
701static __inline__ u_int16_t gdt_dec16(u_int8_t *);
702static __inline__ u_int32_t gdt_dec32(u_int8_t *);
703
704static __inline__ void
705gdt_enc16(addr, value)
706 u_int8_t *addr;
707 u_int16_t value;
708{
709 *(u_int16_t *)addr = htole16(value);
710}
711
712static __inline__ void
713gdt_enc32(addr, value)
714 u_int8_t *addr;
715 u_int32_t value;
716{
717 *(u_int32_t *)addr = htole32(value);
718}
719
720static __inline__ u_int16_t
721gdt_dec16(addr)
722 u_int8_t *addr;
723{
679 return letoh16(*(u_int16_t *)addr);
724 return le16toh(*(u_int16_t *)addr);
680}
681
682static __inline__ u_int32_t
683gdt_dec32(addr)
684 u_int8_t *addr;
685{
725}
726
727static __inline__ u_int32_t
728gdt_dec32(addr)
729 u_int8_t *addr;
730{
686 return letoh32(*(u_int32_t *)addr);
731 return le32toh(*(u_int32_t *)addr);
687}
688#endif
689
690#if defined(__alpha__)
691/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
692#undef vtophys
693#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
694#endif
695
696extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
697extern u_int8_t gdt_polling;
698
699dev_t gdt_make_dev(int unit);
700void gdt_destroy_dev(dev_t dev);
701void gdt_next(struct gdt_softc *gdt);
702void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
703
704gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
705 gdt_evt_data *evt);
706int gdt_read_event(int handle, gdt_evt_str *estr);
707void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
708void gdt_clear_events(void);
709
710#endif
732}
733#endif
734
735#if defined(__alpha__)
736/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
737#undef vtophys
738#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
739#endif
740
741extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
742extern u_int8_t gdt_polling;
743
744dev_t gdt_make_dev(int unit);
745void gdt_destroy_dev(dev_t dev);
746void gdt_next(struct gdt_softc *gdt);
747void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
748
749gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
750 gdt_evt_data *evt);
751int gdt_read_event(int handle, gdt_evt_str *estr);
752void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
753void gdt_clear_events(void);
754
755#endif