1/*- 2 * Copyright (c) 1998 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 *
| 1/*- 2 * Copyright (c) 1998 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 *
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26 * $Id: iiconf.h,v 1.1.1.1 1998/09/03 20:51:50 nsouch Exp $
| 26 * $Id: iiconf.h,v 1.2 1998/10/31 11:31:07 nsouch Exp $
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27 */ 28#ifndef __IICONF_H 29#define __IICONF_H 30 31#include <sys/queue.h> 32 33#define IICPRI PZERO+8 /* XXX sleep/wakeup queue priority */ 34 35#define n(flags) (~(flags) & (flags)) 36 37#define LSB 0x1 38 39/* 40 * How tsleep() is called in iic_request_bus(). 41 */ 42#define IIC_DONTWAIT 0 43#define IIC_NOINTR 0 44#define IIC_WAIT 0x1 45#define IIC_INTR 0x2 46 47/* 48 * i2c modes 49 */ 50#define IIC_MASTER 0x1 51#define IIC_SLAVE 0x2 52#define IIC_POLLED 0x4 53 54/* 55 * i2c speed 56 */ 57#define IIC_UNKNOWN 0x0 58#define IIC_SLOW 0x1 59#define IIC_FAST 0x2 60#define IIC_FASTEST 0x3 61 62#define IIC_LAST_READ 0x1 63 64/* 65 * callback index 66 */ 67#define IIC_REQUEST_BUS 0x1 68#define IIC_RELEASE_BUS 0x2 69 70/* 71 * interrupt events 72 */ 73#define INTR_GENERAL 0x1 /* general call received */ 74#define INTR_START 0x2 /* the I2C interface is addressed */ 75#define INTR_STOP 0x3 /* stop condition received */ 76#define INTR_RECEIVE 0x4 /* character received */ 77#define INTR_TRANSMIT 0x5 /* character to transmit */ 78#define INTR_ERROR 0x6 /* error */ 79#define INTR_NOACK 0x7 /* no ack from master receiver */ 80 81/* 82 * adapter layer errors 83 */ 84#define IIC_NOERR 0x0 /* no error occured */ 85#define IIC_EBUSERR 0x1 /* bus error */ 86#define IIC_ENOACK 0x2 /* ack not received until timeout */ 87#define IIC_ETIMEOUT 0x3 /* timeout */ 88#define IIC_EBUSBSY 0x4 /* bus busy */ 89#define IIC_ESTATUS 0x5 /* status error */ 90#define IIC_EUNDERFLOW 0x6 /* slave ready for more data */ 91#define IIC_EOVERFLOW 0x7 /* too much data */ 92#define IIC_ENOTSUPP 0x8 /* request not supported */ 93#define IIC_ENOADDR 0x9 /* no address assigned to the interface */ 94 95/* 96 * ivars codes 97 */ 98#define IICBUS_IVAR_ADDR 0x1 /* I2C address of the device */ 99 100extern int iicbus_request_bus(device_t, device_t, int); 101extern int iicbus_release_bus(device_t, device_t); 102extern device_t iicbus_alloc_bus(device_t); 103 104extern void iicbus_intr(device_t, int, char *); 105 106extern int iicbus_null_repeated_start(device_t, u_char); 107extern int iicbus_null_callback(device_t, int, caddr_t); 108 109#define iicbus_repeated_start(bus,slave,timeout) \ 110 (IICBUS_REPEATED_START(device_get_parent(bus), slave, timeout))
| 27 */ 28#ifndef __IICONF_H 29#define __IICONF_H 30 31#include <sys/queue.h> 32 33#define IICPRI PZERO+8 /* XXX sleep/wakeup queue priority */ 34 35#define n(flags) (~(flags) & (flags)) 36 37#define LSB 0x1 38 39/* 40 * How tsleep() is called in iic_request_bus(). 41 */ 42#define IIC_DONTWAIT 0 43#define IIC_NOINTR 0 44#define IIC_WAIT 0x1 45#define IIC_INTR 0x2 46 47/* 48 * i2c modes 49 */ 50#define IIC_MASTER 0x1 51#define IIC_SLAVE 0x2 52#define IIC_POLLED 0x4 53 54/* 55 * i2c speed 56 */ 57#define IIC_UNKNOWN 0x0 58#define IIC_SLOW 0x1 59#define IIC_FAST 0x2 60#define IIC_FASTEST 0x3 61 62#define IIC_LAST_READ 0x1 63 64/* 65 * callback index 66 */ 67#define IIC_REQUEST_BUS 0x1 68#define IIC_RELEASE_BUS 0x2 69 70/* 71 * interrupt events 72 */ 73#define INTR_GENERAL 0x1 /* general call received */ 74#define INTR_START 0x2 /* the I2C interface is addressed */ 75#define INTR_STOP 0x3 /* stop condition received */ 76#define INTR_RECEIVE 0x4 /* character received */ 77#define INTR_TRANSMIT 0x5 /* character to transmit */ 78#define INTR_ERROR 0x6 /* error */ 79#define INTR_NOACK 0x7 /* no ack from master receiver */ 80 81/* 82 * adapter layer errors 83 */ 84#define IIC_NOERR 0x0 /* no error occured */ 85#define IIC_EBUSERR 0x1 /* bus error */ 86#define IIC_ENOACK 0x2 /* ack not received until timeout */ 87#define IIC_ETIMEOUT 0x3 /* timeout */ 88#define IIC_EBUSBSY 0x4 /* bus busy */ 89#define IIC_ESTATUS 0x5 /* status error */ 90#define IIC_EUNDERFLOW 0x6 /* slave ready for more data */ 91#define IIC_EOVERFLOW 0x7 /* too much data */ 92#define IIC_ENOTSUPP 0x8 /* request not supported */ 93#define IIC_ENOADDR 0x9 /* no address assigned to the interface */ 94 95/* 96 * ivars codes 97 */ 98#define IICBUS_IVAR_ADDR 0x1 /* I2C address of the device */ 99 100extern int iicbus_request_bus(device_t, device_t, int); 101extern int iicbus_release_bus(device_t, device_t); 102extern device_t iicbus_alloc_bus(device_t); 103 104extern void iicbus_intr(device_t, int, char *); 105 106extern int iicbus_null_repeated_start(device_t, u_char); 107extern int iicbus_null_callback(device_t, int, caddr_t); 108 109#define iicbus_repeated_start(bus,slave,timeout) \ 110 (IICBUS_REPEATED_START(device_get_parent(bus), slave, timeout))
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111#define iicbus_start(bus,slave,timeout) \ 112 (IICBUS_START(device_get_parent(bus), slave, timeout)) 113#define iicbus_stop(bus) \ 114 (IICBUS_STOP(device_get_parent(bus)))
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115#define iicbus_reset(bus,speed,addr,oldaddr) \ 116 (IICBUS_RESET(device_get_parent(bus), speed, addr, oldaddr))
| 111#define iicbus_reset(bus,speed,addr,oldaddr) \ 112 (IICBUS_RESET(device_get_parent(bus), speed, addr, oldaddr))
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117#define iicbus_write(bus,buf,len,sent,timeout) \ 118 (IICBUS_WRITE(device_get_parent(bus), buf, len, sent, timeout)) 119#define iicbus_read(bus,buf,len,sent,last,delay) \ 120 (IICBUS_READ(device_get_parent(bus), buf, len, sent, last, delay))
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121
| 113
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| 114/* basic I2C operations */ 115extern int iicbus_started(device_t); 116extern int iicbus_start(device_t, u_char, int); 117extern int iicbus_stop(device_t); 118extern int iicbus_write(device_t, char *, int, int *, int); 119extern int iicbus_read(device_t, char *, int, int *, int, int); 120 121/* Read/write operations with start/stop conditions managed */
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122extern int iicbus_block_write(device_t, u_char, char *, int, int *); 123extern int iicbus_block_read(device_t, u_char, char *, int, int *); 124 125extern u_char iicbus_get_addr(device_t); 126 127#endif
| 122extern int iicbus_block_write(device_t, u_char, char *, int, int *); 123extern int iicbus_block_read(device_t, u_char, char *, int, int *); 124 125extern u_char iicbus_get_addr(device_t); 126 127#endif
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