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hwpmc_piv.c (174395) hwpmc_piv.c (183266)
1/*-
2 * Copyright (c) 2003-2007 Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *

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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003-2007 Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *

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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_piv.c 174395 2007-12-07 08:20:17Z jkoshy $");
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_piv.c 183266 2008-09-22 10:37:02Z jkoshy $");
33
34#include <sys/param.h>
35#include <sys/lock.h>
36#include <sys/mutex.h>
37#include <sys/pmc.h>
38#include <sys/pmckern.h>
39#include <sys/smp.h>
40#include <sys/systm.h>

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527#define P4_ESCR_ROW_DISP_IS_THREAD(E) (p4_escrdisp[(E)] > 0)
528#define P4_ESCR_ROW_DISP_IS_STANDALONE(E) (p4_escrdisp[(E)] < 0)
529#define P4_ESCR_ROW_DISP_IS_FREE(E) (p4_escrdisp[(E)] == 0)
530
531#define P4_ESCR_MARK_ROW_STANDALONE(E) do { \
532 KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\
533 __LINE__)); \
534 atomic_add_int(&p4_escrdisp[(E)], -1); \
33
34#include <sys/param.h>
35#include <sys/lock.h>
36#include <sys/mutex.h>
37#include <sys/pmc.h>
38#include <sys/pmckern.h>
39#include <sys/smp.h>
40#include <sys/systm.h>

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527#define P4_ESCR_ROW_DISP_IS_THREAD(E) (p4_escrdisp[(E)] > 0)
528#define P4_ESCR_ROW_DISP_IS_STANDALONE(E) (p4_escrdisp[(E)] < 0)
529#define P4_ESCR_ROW_DISP_IS_FREE(E) (p4_escrdisp[(E)] == 0)
530
531#define P4_ESCR_MARK_ROW_STANDALONE(E) do { \
532 KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\
533 __LINE__)); \
534 atomic_add_int(&p4_escrdisp[(E)], -1); \
535 KASSERT(p4_escrdisp[(E)] >= (-mp_ncpus), ("[p4,%d] row " \
536 "disposition error", __LINE__)); \
535 KASSERT(p4_escrdisp[(E)] >= (-pmc_cpu_max_active()), \
536 ("[p4,%d] row disposition error", __LINE__)); \
537} while (0)
538
539#define P4_ESCR_UNMARK_ROW_STANDALONE(E) do { \
540 atomic_add_int(&p4_escrdisp[(E)], 1); \
541 KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\
542 __LINE__)); \
543} while (0)
544

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591p4_init(int cpu)
592{
593 int n, phycpu;
594 char *pescr;
595 struct p4_cpu *pcs;
596 struct p4_logicalcpu *plcs;
597 struct pmc_hw *phw;
598
537} while (0)
538
539#define P4_ESCR_UNMARK_ROW_STANDALONE(E) do { \
540 atomic_add_int(&p4_escrdisp[(E)], 1); \
541 KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\
542 __LINE__)); \
543} while (0)
544

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591p4_init(int cpu)
592{
593 int n, phycpu;
594 char *pescr;
595 struct p4_cpu *pcs;
596 struct p4_logicalcpu *plcs;
597 struct pmc_hw *phw;
598
599 KASSERT(cpu >= 0 && cpu < mp_ncpus,
599 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
600 ("[p4,%d] insane cpu number %d", __LINE__, cpu));
601
600 ("[p4,%d] insane cpu number %d", __LINE__, cpu));
601
602 PMCDBG(MDP,INI,0, "p4-init cpu=%d logical=%d", cpu,
603 pmc_cpu_is_logical(cpu) != 0);
602 PMCDBG(MDP,INI,0, "p4-init cpu=%d is-primary=%d", cpu,
603 pmc_cpu_is_primary(cpu) != 0);
604
605 /*
606 * The two CPUs in an HT pair share their per-cpu state.
607 *
608 * For HT capable CPUs, we assume that the two logical
609 * processors in the HT pair get two consecutive CPU ids
610 * starting with an even id #.
611 *
612 * The primary CPU (the even numbered CPU of the pair) would
613 * have been initialized prior to the initialization for the
614 * secondary.
615 */
616
604
605 /*
606 * The two CPUs in an HT pair share their per-cpu state.
607 *
608 * For HT capable CPUs, we assume that the two logical
609 * processors in the HT pair get two consecutive CPU ids
610 * starting with an even id #.
611 *
612 * The primary CPU (the even numbered CPU of the pair) would
613 * have been initialized prior to the initialization for the
614 * secondary.
615 */
616
617 if (pmc_cpu_is_logical(cpu) && (cpu & 1)) {
617 if (!pmc_cpu_is_primary(cpu) && (cpu & 1)) {
618
619 p4_system_has_htt = 1;
620
621 phycpu = P4_TO_HTT_PRIMARY(cpu);
622 pcs = (struct p4_cpu *) pmc_pcpu[phycpu];
623 PMCDBG(MDP,INI,1, "p4-init cpu=%d phycpu=%d pcs=%p",
624 cpu, phycpu, pcs);
625 KASSERT(pcs,

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756{
757 enum pmc_mode mode;
758 struct p4pmc_descr *pd;
759 struct pmc *pm;
760 struct p4_cpu *pc;
761 struct pmc_hw *phw;
762 pmc_value_t tmp;
763
618
619 p4_system_has_htt = 1;
620
621 phycpu = P4_TO_HTT_PRIMARY(cpu);
622 pcs = (struct p4_cpu *) pmc_pcpu[phycpu];
623 PMCDBG(MDP,INI,1, "p4-init cpu=%d phycpu=%d pcs=%p",
624 cpu, phycpu, pcs);
625 KASSERT(pcs,

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756{
757 enum pmc_mode mode;
758 struct p4pmc_descr *pd;
759 struct pmc *pm;
760 struct p4_cpu *pc;
761 struct pmc_hw *phw;
762 pmc_value_t tmp;
763
764 KASSERT(cpu >= 0 && cpu < mp_ncpus,
764 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
765 ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
766 KASSERT(ri >= 0 && ri < P4_NPMCS,
767 ("[p4,%d] illegal row-index %d", __LINE__, ri));
768
769
770 if (ri == 0) { /* TSC */
771#ifdef DEBUG
772 pc = (struct p4_cpu *) pmc_pcpu[cpu];

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834p4_write_pmc(int cpu, int ri, pmc_value_t v)
835{
836 enum pmc_mode mode;
837 struct pmc *pm;
838 struct p4_cpu *pc;
839 const struct pmc_hw *phw;
840 const struct p4pmc_descr *pd;
841
765 ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
766 KASSERT(ri >= 0 && ri < P4_NPMCS,
767 ("[p4,%d] illegal row-index %d", __LINE__, ri));
768
769
770 if (ri == 0) { /* TSC */
771#ifdef DEBUG
772 pc = (struct p4_cpu *) pmc_pcpu[cpu];

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834p4_write_pmc(int cpu, int ri, pmc_value_t v)
835{
836 enum pmc_mode mode;
837 struct pmc *pm;
838 struct p4_cpu *pc;
839 const struct pmc_hw *phw;
840 const struct p4pmc_descr *pd;
841
842 KASSERT(cpu >= 0 && cpu < mp_ncpus,
842 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
843 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
844 KASSERT(ri >= 0 && ri < P4_NPMCS,
845 ("[amd,%d] illegal row-index %d", __LINE__, ri));
846
847
848 /*
849 * The P4's TSC register is writeable, but we don't allow a
850 * write as changing the TSC's value could interfere with

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908
909static int
910p4_config_pmc(int cpu, int ri, struct pmc *pm)
911{
912 struct pmc_hw *phw;
913 struct p4_cpu *pc;
914 int cfgflags, cpuflag;
915
843 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
844 KASSERT(ri >= 0 && ri < P4_NPMCS,
845 ("[amd,%d] illegal row-index %d", __LINE__, ri));
846
847
848 /*
849 * The P4's TSC register is writeable, but we don't allow a
850 * write as changing the TSC's value could interfere with

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908
909static int
910p4_config_pmc(int cpu, int ri, struct pmc *pm)
911{
912 struct pmc_hw *phw;
913 struct p4_cpu *pc;
914 int cfgflags, cpuflag;
915
916 KASSERT(cpu >= 0 && cpu < mp_ncpus,
916 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
917 ("[p4,%d] illegal CPU %d", __LINE__, cpu));
918 KASSERT(ri >= 0 && ri < P4_NPMCS,
919 ("[p4,%d] illegal row-index %d", __LINE__, ri));
920
921 PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
922
923 if (ri == 0) { /* TSC */
924 pc = (struct p4_cpu *) pmc_pcpu[cpu];

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1045{
1046 int found, n, m;
1047 uint32_t caps, cccrvalue, escrvalue, tflags;
1048 enum pmc_p4escr escr;
1049 struct p4_cpu *pc;
1050 struct p4_event_descr *pevent;
1051 const struct p4pmc_descr *pd;
1052
917 ("[p4,%d] illegal CPU %d", __LINE__, cpu));
918 KASSERT(ri >= 0 && ri < P4_NPMCS,
919 ("[p4,%d] illegal row-index %d", __LINE__, ri));
920
921 PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
922
923 if (ri == 0) { /* TSC */
924 pc = (struct p4_cpu *) pmc_pcpu[cpu];

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1045{
1046 int found, n, m;
1047 uint32_t caps, cccrvalue, escrvalue, tflags;
1048 enum pmc_p4escr escr;
1049 struct p4_cpu *pc;
1050 struct p4_event_descr *pevent;
1051 const struct p4pmc_descr *pd;
1052
1053 KASSERT(cpu >= 0 && cpu < mp_ncpus,
1053 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1054 ("[p4,%d] illegal CPU %d", __LINE__, cpu));
1055 KASSERT(ri >= 0 && ri < P4_NPMCS,
1056 ("[p4,%d] illegal row-index value %d", __LINE__, ri));
1057
1058 pd = &p4_pmcdesc[ri];
1059
1060 PMCDBG(MDP,ALL,1, "p4-allocate ri=%d class=%d pmccaps=0x%x "
1061 "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps,

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1292{
1293 int rc;
1294 uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits;
1295 struct pmc *pm;
1296 struct p4_cpu *pc;
1297 struct pmc_hw *phw;
1298 struct p4pmc_descr *pd;
1299
1054 ("[p4,%d] illegal CPU %d", __LINE__, cpu));
1055 KASSERT(ri >= 0 && ri < P4_NPMCS,
1056 ("[p4,%d] illegal row-index value %d", __LINE__, ri));
1057
1058 pd = &p4_pmcdesc[ri];
1059
1060 PMCDBG(MDP,ALL,1, "p4-allocate ri=%d class=%d pmccaps=0x%x "
1061 "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps,

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1292{
1293 int rc;
1294 uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits;
1295 struct pmc *pm;
1296 struct p4_cpu *pc;
1297 struct pmc_hw *phw;
1298 struct p4pmc_descr *pd;
1299
1300 KASSERT(cpu >= 0 && cpu < mp_ncpus,
1300 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1301 ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
1302 KASSERT(ri >= 0 && ri < P4_NPMCS,
1303 ("[p4,%d] illegal row-index %d", __LINE__, ri));
1304
1305 pc = (struct p4_cpu *) pmc_pcpu[P4_TO_HTT_PRIMARY(cpu)];
1306 phw = pc->pc_hwpmcs[ri];
1307 pm = phw->phw_pmc;
1308 pd = &p4_pmcdesc[ri];

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1444 int rc;
1445 uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits;
1446 struct pmc *pm;
1447 struct p4_cpu *pc;
1448 struct pmc_hw *phw;
1449 struct p4pmc_descr *pd;
1450 pmc_value_t tmp;
1451
1301 ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
1302 KASSERT(ri >= 0 && ri < P4_NPMCS,
1303 ("[p4,%d] illegal row-index %d", __LINE__, ri));
1304
1305 pc = (struct p4_cpu *) pmc_pcpu[P4_TO_HTT_PRIMARY(cpu)];
1306 phw = pc->pc_hwpmcs[ri];
1307 pm = phw->phw_pmc;
1308 pd = &p4_pmcdesc[ri];

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1444 int rc;
1445 uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits;
1446 struct pmc *pm;
1447 struct p4_cpu *pc;
1448 struct pmc_hw *phw;
1449 struct p4pmc_descr *pd;
1450 pmc_value_t tmp;
1451
1452 KASSERT(cpu >= 0 && cpu < mp_ncpus,
1452 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1453 ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
1454 KASSERT(ri >= 0 && ri < P4_NPMCS,
1455 ("[p4,%d] illegal row index %d", __LINE__, ri));
1456
1457 pd = &p4_pmcdesc[ri];
1458
1459 if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
1460 return 0;

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1717p4_describe(int cpu, int ri, struct pmc_info *pi,
1718 struct pmc **ppmc)
1719{
1720 int error;
1721 size_t copied;
1722 struct pmc_hw *phw;
1723 const struct p4pmc_descr *pd;
1724
1453 ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
1454 KASSERT(ri >= 0 && ri < P4_NPMCS,
1455 ("[p4,%d] illegal row index %d", __LINE__, ri));
1456
1457 pd = &p4_pmcdesc[ri];
1458
1459 if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
1460 return 0;

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1717p4_describe(int cpu, int ri, struct pmc_info *pi,
1718 struct pmc **ppmc)
1719{
1720 int error;
1721 size_t copied;
1722 struct pmc_hw *phw;
1723 const struct p4pmc_descr *pd;
1724
1725 KASSERT(cpu >= 0 && cpu < mp_ncpus,
1725 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1726 ("[p4,%d] illegal CPU %d", __LINE__, cpu));
1727 KASSERT(ri >= 0 && ri < P4_NPMCS,
1728 ("[p4,%d] row-index %d out of range", __LINE__, ri));
1729
1730 PMCDBG(MDP,OPS,1,"p4-describe cpu=%d ri=%d", cpu, ri);
1731
1732 if (P4_CPU_IS_HTT_SECONDARY(cpu))
1733 return EINVAL;

--- 96 unchanged lines hidden --- 		1726 ("[p4,%d] illegal CPU %d", __LINE__, cpu));
1727 KASSERT(ri >= 0 && ri < P4_NPMCS,
1728 ("[p4,%d] row-index %d out of range", __LINE__, ri));
1729
1730 PMCDBG(MDP,OPS,1,"p4-describe cpu=%d ri=%d", cpu, ri);
1731
1732 if (P4_CPU_IS_HTT_SECONDARY(cpu))
1733 return EINVAL;

--- 96 unchanged lines hidden ---