29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/malloc.h>
35#include <sys/resource.h>
36#include <sys/time.h>
37#include <sys/callout.h>
38#include <sys/signalvar.h>
39#include <sys/eventhandler.h>
40#include <sys/proc.h>
41#include <sys/kthread.h>
42
43#include <sys/mutex.h>
44#include <sys/module.h>
45#include <sys/sx.h>
46
47#include <dev/pci/pcireg.h>
48#include <dev/pci/pcivar.h>
49
50#ifndef __KERNEL__
51#define __KERNEL__
52#endif
53
54#include <dev/hptmv/global.h>
55#include <dev/hptmv/hptintf.h>
56#include <dev/hptmv/osbsd.h>
57#include <dev/hptmv/access601.h>
58
59
60#ifdef DEBUG
61#ifdef DEBUG_LEVEL
62int hpt_dbg_level = DEBUG_LEVEL;
63#else
64int hpt_dbg_level = 0;
65#endif
66#endif
67
68#define MV_ERROR printf
69
70/*
71 * CAM SIM entry points
72 */
73static int hpt_probe (device_t dev);
74static void launch_worker_thread(void);
75static int hpt_attach(device_t dev);
76static int hpt_detach(device_t dev);
77static int hpt_shutdown(device_t dev);
78static void hpt_poll(struct cam_sim *sim);
79static void hpt_intr(void *arg);
80static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
81static void hpt_action(struct cam_sim *sim, union ccb *ccb);
82
83static device_method_t driver_methods[] = {
84 /* Device interface */
85 DEVMETHOD(device_probe, hpt_probe),
86 DEVMETHOD(device_attach, hpt_attach),
87 DEVMETHOD(device_detach, hpt_detach),
88
89 DEVMETHOD(device_shutdown, hpt_shutdown),
90 DEVMETHOD_END
91};
92
93static driver_t hpt_pci_driver = {
94 __str(PROC_DIR_NAME),
95 driver_methods,
96 sizeof(IAL_ADAPTER_T)
97};
98
99static devclass_t hpt_devclass;
100
101#define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6)
102__DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0);
103MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1);
104
105#define ccb_ccb_ptr spriv_ptr0
106#define ccb_adapter ccb_h.spriv_ptr1
107
108static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
109static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
110static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
111static void ccb_done(union ccb *ccb);
112static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
113static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
114static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter);
115static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
116static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
117static void handleEdmaError(_VBUS_ARG PCommand pCmd);
118static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
119static int fResetActiveCommands(PVBus _vbus_p);
120static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
121static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
122static void hptmv_handle_event_disconnect(void *data);
123static void hptmv_handle_event_connect(void *data);
124static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
125static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
126static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
127static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
128 int logical);
129static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
130 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
131 MV_U16 responseFlags, MV_U32 timeStamp,
132 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
133static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
134 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
135
136#define ccb_ccb_ptr spriv_ptr0
137#define ccb_adapter ccb_h.spriv_ptr1
138
139static struct sx hptmv_list_lock;
140SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list");
141IAL_ADAPTER_T *gIal_Adapter = 0;
142IAL_ADAPTER_T *pCurAdapter = 0;
143static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
144
145typedef struct st_HPT_DPC {
146 IAL_ADAPTER_T *pAdapter;
147 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
148 void *arg;
149 UCHAR flags;
150} ST_HPT_DPC;
151
152#define MAX_DPC 16
153UCHAR DPC_Request_Nums = 0;
154static ST_HPT_DPC DpcQueue[MAX_DPC];
155static int DpcQueue_First=0;
156static int DpcQueue_Last = 0;
157static struct mtx DpcQueue_Lock;
158MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF);
159
160char DRIVER_VERSION[] = "v1.16";
161
162/*******************************************************************************
163 * Name: hptmv_free_channel
164 *
165 * Description: free allocated queues for the given channel
166 *
167 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this
168 * channel connected to.
169 * channelNum - channel number.
170 *
171 ******************************************************************************/
172static void
173hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
174{
175 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
176 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
177}
178
179static void failDevice(PVDevice pVDev)
180{
181 PVBus _vbus_p = pVDev->pVBus;
182 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
183
184 pVDev->u.disk.df_on_line = 0;
185 pVDev->vf_online = 0;
186 if (pVDev->pfnDeviceFailed)
187 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
188
189 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
190
191#ifndef FOR_DEMO
192 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
193 pAdapter->beeping = 1;
194 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
195 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
196 }
197#endif
198}
199
200int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
201
202static void
203handleEdmaError(_VBUS_ARG PCommand pCmd)
204{
205 PDevice pDevice = &pCmd->pVDevice->u.disk;
206 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
207
208 if (!pDevice->df_on_line) {
209 KdPrint(("Device is offline"));
210 pCmd->Result = RETURN_BAD_DEVICE;
211 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
212 return;
213 }
214
215 if (pCmd->RetryCount++>5) {
216 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
217failed:
218 failDevice(pCmd->pVDevice);
219 pCmd->Result = RETURN_IDE_ERROR;
220 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
221 return;
222 }
223
224 /* reset the channel and retry the command */
225 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
226 goto failed;
227
228 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
229
230 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
231 fDeviceSendCommand(_VBUS_P pCmd);
232}
233
234/****************************************************************
235 * Name: hptmv_init_channel
236 *
237 * Description: allocate request and response queues for the EDMA of the
238 * given channel and sets other fields.
239 *
240 * Parameters:
241 * pAdapter - pointer to the emulated adapter data structure
242 * channelNum - channel number.
243 * Return: 0 on success, otherwise on failure
244 ****************************************************************/
245static int
246hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
247{
248 MV_SATA_CHANNEL *pMvSataChannel;
249 dma_addr_t req_dma_addr;
250 dma_addr_t rsp_dma_addr;
251
252 if (channelNum >= MV_SATA_CHANNELS_NUM)
253 {
254 MV_ERROR("RR18xx[%d]: Bad channelNum=%d",
255 pAdapter->mvSataAdapter.adapterId, channelNum);
256 return -1;
257 }
258
259 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
260 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
261 pMvSataChannel->channelNumber = channelNum;
262 pMvSataChannel->lba48Address = MV_FALSE;
263 pMvSataChannel->maxReadTransfer = MV_FALSE;
264
265 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
266 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
267 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
268
269
270 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
271
272 /* check the 1K alignment of the request queue*/
273 if (req_dma_addr & 0x3ff)
274 {
275 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned,"
276 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
277 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
278 return -1;
279 }
280 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
281 pMvSataChannel->requestQueuePciHiAddress = 0;
282 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p",
283 pAdapter->mvSataAdapter.adapterId, channelNum,
284 pMvSataChannel->requestQueue));
285 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
286 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
287 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
288
289 /* check the 256 alignment of the response queue*/
290 if (rsp_dma_addr & 0xff)
291 {
292 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte "
293 "aligned, dma_addr=%llx\n",
294 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
295 return -1;
296 }
297 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
298 pMvSataChannel->responseQueuePciHiAddress = 0;
299 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p",
300 pAdapter->mvSataAdapter.adapterId, channelNum,
301 pMvSataChannel->responseQueue));
302
303 pAdapter->mvChannel[channelNum].online = MV_TRUE;
304 return 0;
305}
306
307/******************************************************************************
308 * Name: hptmv_parse_identify_results
309 *
310 * Description: this functions parses the identify command results, checks
311 * that the connected deives can be accesed by RR18xx EDMA,
312 * and updates the channel stucture accordingly.
313 *
314 * Parameters: pMvSataChannel, pointer to the channel data structure.
315 *
316 * Returns: =0 ->success, < 0 ->failure.
317 *
318 ******************************************************************************/
319static int
320hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
321{
322 MV_U16 *iden = pMvSataChannel->identifyDevice;
323
324 /*LBA addressing*/
325 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
326 {
327 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
328 return -1;
329 }
330 else
331 {
332 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
333 }
334 /*DMA support*/
335 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
336 {
337 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
338 return -1;
339 }
340 else
341 {
342 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
343 }
344 /* PIO */
345 if ((iden[IDEN_VALID] & 2) == 0)
346 {
347 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
348 return -1;
349 }
350 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
351 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
352
353 /*UDMA*/
354 if ((iden[IDEN_VALID] & 4) == 0)
355 {
356 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
357 return -1;
358 }
359
360 /* 48 bit address */
361 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
362 {
363 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
364 pMvSataChannel->lba48Address = MV_TRUE;
365 }
366 else
367 {
368 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
369 pMvSataChannel->lba48Address = MV_FALSE;
370 }
371 return 0;
372}
373
374static void
375init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
376{
377 PVDevice pVDev = &pAdapter->VDevices[channel];
378 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
379 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
380
381 pMvSataChannel->outstandingCommands = 0;
382
383 pVDev->u.disk.mv = pMvSataChannel;
384 pVDev->u.disk.df_on_line = 1;
385 pVDev->u.disk.pVBus = &pAdapter->VBus;
386 pVDev->pVBus = &pAdapter->VBus;
387
388#ifdef SUPPORT_48BIT_LBA
389 if (pMvSataChannel->lba48Address == MV_TRUE)
390 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
391 else
392#endif
393 if(IdentifyData[53] & 1) {
394 pVDev->u.disk.dDeRealCapacity =
395 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
396 (IdentifyData[61]<<16 | IdentifyData[60]) :
397 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
398 } else
399 pVDev->u.disk.dDeRealCapacity =
400 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
401
402 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
403 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
404
405 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
406 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
407 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
408 }
409}
410
411static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
412{
413 PVDevice pVDev;
414 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
415 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
416
417 if (!pMvSataChannel) return;
418
419 if (plugged)
420 {
421 pVDev = &(pAdapter->VDevices[channelIndex]);
422 init_vdev_params(pAdapter, channelIndex);
423
424 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
425 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
426
427 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
428 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
429 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
430 pVDev->vf_online = 1;
431
432#ifdef SUPPORT_ARRAY
433 if(pVDev->pParent)
434 {
435 int iMember;
436 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
437 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
438 pVDev->pParent->u.array.pMember[iMember] = NULL;
439 pVDev->pParent = NULL;
440 }
441#endif
442 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
443 fCheckBootable(pVDev);
444 RegisterVDevice(pVDev);
445
446#ifndef FOR_DEMO
447 if (pAdapter->beeping) {
448 pAdapter->beeping = 0;
449 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
450 }
451#endif
452
453 }
454 else
455 {
456 pVDev = &(pAdapter->VDevices[channelIndex]);
457 failDevice(pVDev);
458 }
459}
460
461static int
462start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
463{
464 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
465 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
466 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
467 MV_U32 udmaMode,pioMode;
468
469 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId,
470 channelNum));
471
472
473 /* Software reset channel */
474 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
475 {
476 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
477 pMvSataAdapter->adapterId, channelNum);
478 return -1;
479 }
480
481 /* Hardware reset channel */
482 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
483 {
484 /* If failed, try again - this is when trying to hardreset a channel */
485 /* when drive is just spinning up */
486 StallExec(5000000); /* wait 5 sec before trying again */
487 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
488 {
489 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n",
490 pMvSataAdapter->adapterId, channelNum);
491 return -1;
492 }
493 }
494
495 /* identify device*/
496 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
497 {
498 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n"
499 , pMvSataAdapter->adapterId, channelNum);
500 return -1;
501 }
502 if (hptmv_parse_identify_results(pMvSataChannel))
503 {
504 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n"
505 , pMvSataAdapter->adapterId, channelNum);
506 return -1;
507 }
508
509 /* mvStorageDevATASetFeatures */
510 /* Disable 8 bit PIO in case CFA enabled */
511 if (pMvSataChannel->identifyDevice[86] & 4)
512 {
513 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n",
514 pMvSataAdapter->adapterId));
515 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
516 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
517 0, 0, 0) == MV_FALSE)
518 {
519 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures"
520 " failed\n", pMvSataAdapter->adapterId, channelNum);
521 return -1;
522 }
523 }
524 /* Write cache */
525#ifdef ENABLE_WRITE_CACHE
526 if (pMvSataChannel->identifyDevice[82] & 0x20)
527 {
528 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
529 {
530 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
531 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
532 0, 0, 0) == MV_FALSE)
533 {
534 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
535 pMvSataAdapter->adapterId, channelNum);
536 return -1;
537 }
538 }
539 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n",
540 pMvSataAdapter->adapterId, channelNum));
541 }
542 else
543 {
544 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n",
545 pMvSataAdapter->adapterId, channelNum));
546 }
547#else /* disable write cache */
548 {
549 if (pMvSataChannel->identifyDevice[85] & 0x20)
550 {
551 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n",
552 pMvSataAdapter->adapterId, channelNum));
553 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
554 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
555 0, 0, 0) == MV_FALSE)
556 {
557 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
558 pMvSataAdapter->adapterId, channelNum);
559 return -1;
560 }
561 }
562 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n",
563 pMvSataAdapter->adapterId, channelNum));
564 }
565#endif
566
567 /* Set transfer mode */
568 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n",
569 pMvSataAdapter->adapterId));
570 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
571 MV_ATA_SET_FEATURES_TRANSFER,
572 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
573 MV_FALSE)
574 {
575 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
576 pMvSataAdapter->adapterId, channelNum);
577 return -1;
578 }
579
580 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
581 {
582 pioMode = MV_ATA_TRANSFER_PIO_4;
583 }
584 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
585 {
586 pioMode = MV_ATA_TRANSFER_PIO_3;
587 }
588 else
589 {
590 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
591 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
592 }
593
594 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n",
595 pMvSataAdapter->adapterId));
596 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
597 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
598 MV_ATA_SET_FEATURES_TRANSFER,
599 pioMode, 0, 0, 0) == MV_FALSE)
600 {
601 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
602 pMvSataAdapter->adapterId, channelNum);
603 return -1;
604 }
605
606 udmaMode = MV_ATA_TRANSFER_UDMA_0;
607 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
608 {
609 udmaMode = MV_ATA_TRANSFER_UDMA_6;
610 }
611 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
612 {
613 udmaMode = MV_ATA_TRANSFER_UDMA_5;
614 }
615 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
616 {
617 udmaMode = MV_ATA_TRANSFER_UDMA_4;
618 }
619 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
620 {
621 udmaMode = MV_ATA_TRANSFER_UDMA_3;
622 }
623 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
624 {
625 udmaMode = MV_ATA_TRANSFER_UDMA_2;
626 }
627
628 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n",
629 pMvSataAdapter->adapterId, udmaMode & 0xf));
630 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
631
632 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
633 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
634 0, 0, 0) == MV_FALSE)
635 {
636 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
637 pMvSataAdapter->adapterId, channelNum);
638 return -1;
639 }*/
640 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
641 return TRUE;
642 else
643 do
644 {
645 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
646 MV_ATA_SET_FEATURES_TRANSFER,
647 pChannelInfo->maxUltraDmaModeSupported,
648 0, 0, 0) == MV_FALSE)
649 {
650 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
651 {
652 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
653 {
654 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
655 pMvSataChannel->eDmaRegsOffset +
656 0x11c, /* command reg */
657 MV_ATA_COMMAND_IDLE_IMMEDIATE);
658 mvMicroSecondsDelay(10000);
659 mvSataChannelHardReset(pMvSataAdapter, channelNum);
660 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
661 return FALSE;
662 }
663 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
664 return FALSE;
665 pChannelInfo->maxUltraDmaModeSupported--;
666 continue;
667 }
668 else return FALSE;
669 }
670 break;
671 }while (1);
672
673 /* Read look ahead */
674#ifdef ENABLE_READ_AHEAD
675 if (pMvSataChannel->identifyDevice[82] & 0x40)
676 {
677 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
678 {
679 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
680 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
681 0, 0) == MV_FALSE)
682 {
683 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
684 pMvSataAdapter->adapterId, channelNum);
685 return -1;
686 }
687 }
688 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n",
689 pMvSataAdapter->adapterId, channelNum));
690 }
691 else
692 {
693 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n",
694 pMvSataAdapter->adapterId, channelNum));
695 }
696#else
697 {
698 if (pMvSataChannel->identifyDevice[86] & 0x20)
699 {
700 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n",
701 pMvSataAdapter->adapterId, channelNum));
702 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
703 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
704 0, 0) == MV_FALSE)
705 {
706 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n",
707 pMvSataAdapter->adapterId, channelNum);
708 return -1;
709 }
710 }
711 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n",
712 pMvSataAdapter->adapterId, channelNum));
713 }
714#endif
715
716
717 {
718 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n",
719 pMvSataAdapter->adapterId,
720 channelNum));
721 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
722 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
723 {
724 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
725 pMvSataAdapter->adapterId, channelNum);
726 return -1;
727 }
728 }
729 /* Enable EDMA */
730 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
731 {
732 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n",
733 pMvSataAdapter->adapterId, channelNum);
734 return -1;
735 }
736 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n",
737 pMvSataAdapter->adapterId, channelNum);
738
739#ifndef FOR_DEMO
740 set_fail_led(pMvSataAdapter, channelNum, 0);
741#endif
742 return 0;
743}
744
745static void
746hptmv_handle_event(void * data, int flag)
747{
748 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
749 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
750 MV_U8 channelIndex;
751
752 mtx_assert(&pAdapter->lock, MA_OWNED);
753/* mvOsSemTake(&pMvSataAdapter->semaphore); */
754 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
755 {
756 switch(pAdapter->sataEvents[channelIndex])
757 {
758 case SATA_EVENT_CHANNEL_CONNECTED:
759 /* Handle only connects */
760 if (flag == 1)
761 break;
762 KdPrint(("RR18xx [%d,%d]: new device connected\n",
763 pMvSataAdapter->adapterId, channelIndex));
764 hptmv_init_channel(pAdapter, channelIndex);
765 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
766 {
767 MV_ERROR("RR18xx [%d,%d] Failed to configure\n",
768 pMvSataAdapter->adapterId, channelIndex);
769 hptmv_free_channel(pAdapter, channelIndex);
770 }
771 else
772 {
773 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
774 if (start_channel( pAdapter, channelIndex))
775 {
776 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n",
777 pMvSataAdapter->adapterId, channelIndex);
778 hptmv_free_channel(pAdapter, channelIndex);
779 }
780 else
781 {
782 device_change(pAdapter, channelIndex, TRUE);
783 }
784 }
785 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
786 break;
787
788 case SATA_EVENT_CHANNEL_DISCONNECTED:
789 /* Handle only disconnects */
790 if (flag == 0)
791 break;
792 KdPrint(("RR18xx [%d,%d]: device disconnected\n",
793 pMvSataAdapter->adapterId, channelIndex));
794 /* Flush pending commands */
795 if(pMvSataAdapter->sataChannel[channelIndex])
796 {
797 _VBUS_INST(&pAdapter->VBus)
798 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
799 MV_FLUSH_TYPE_CALLBACK);
800 CheckPendingCall(_VBUS_P0);
801 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
802 hptmv_free_channel(pAdapter, channelIndex);
803 pMvSataAdapter->sataChannel[channelIndex] = NULL;
804 KdPrint(("RR18xx [%d,%d]: channel removed\n",
805 pMvSataAdapter->adapterId, channelIndex));
806 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
807 Check_Idle_Call(pAdapter);
808 }
809 else
810 {
811 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n",
812 pMvSataAdapter->adapterId, channelIndex));
813 }
814 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
815 break;
816
817 case SATA_EVENT_NO_CHANGE:
818 break;
819
820 default:
821 break;
822 }
823 }
824/* mvOsSemRelease(&pMvSataAdapter->semaphore); */
825}
826
827#define EVENT_CONNECT 1
828#define EVENT_DISCONNECT 0
829
830static void
831hptmv_handle_event_connect(void *data)
832{
833 hptmv_handle_event (data, 0);
834}
835
836static void
837hptmv_handle_event_disconnect(void *data)
838{
839 hptmv_handle_event (data, 1);
840}
841
842static MV_BOOLEAN
843hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
844 MV_U32 param1, MV_U32 param2)
845{
846 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
847
848 switch (eventType)
849 {
850 case MV_EVENT_TYPE_SATA_CABLE:
851 {
852 MV_U8 channel = param2;
853
854 if (param1 == EVENT_CONNECT)
855 {
856 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
857 KdPrint(("RR18xx [%d,%d]: device connected event received\n",
858 pMvSataAdapter->adapterId, channel));
859 /* Delete previous timers (if multiple drives connected in the same time */
860 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter);
861 }
862 else if (param1 == EVENT_DISCONNECT)
863 {
864 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
865 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n",
866 pMvSataAdapter->adapterId, channel));
867 device_change(pAdapter, channel, FALSE);
868 /* Delete previous timers (if multiple drives disconnected in the same time */
869 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */
870 /*It is not necessary to wait, handle it directly*/
871 hptmv_handle_event_disconnect(pAdapter);
872 }
873 else
874 {
875
876 MV_ERROR("RR18xx: illegal value for param1(%d) at "
877 "connect/disconnect event, host=%d\n", param1,
878 pMvSataAdapter->adapterId );
879
880 }
881 }
882 break;
883 case MV_EVENT_TYPE_ADAPTER_ERROR:
884 KdPrint(("RR18xx: DEVICE error event received, pci cause "
885 "reg=%x, don't how to handle this\n", param1));
886 return MV_TRUE;
887 default:
888 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n",
889 pMvSataAdapter->adapterId, eventType);
890 return MV_FALSE;
891 }
892 return MV_TRUE;
893}
894
895static int
896hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
897{
898 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
899 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
900 if (pAdapter->requestsArrayBaseAddr == NULL)
901 {
902 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request"
903 " queues\n", pAdapter->mvSataAdapter.adapterId);
904 return -1;
905 }
906 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
907 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
908 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
909 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
910 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
911 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
912 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
913 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
914
915 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
916 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
917 {
918 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n",
919 pAdapter->mvSataAdapter.adapterId);
920 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
921 return -1;
922 }
923 /* response queues */
924 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
925 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
926 if (pAdapter->responsesArrayBaseAddr == NULL)
927 {
928 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response"
929 " queues\n", pAdapter->mvSataAdapter.adapterId);
930 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
931 return -1;
932 }
933 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
934 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
935 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
936 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
937 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
938 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
939 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
940 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
941
942 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
943 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
944 {
945 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n",
946 pAdapter->mvSataAdapter.adapterId);
947 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
948 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
949 return -1;
950 }
951 return 0;
952}
953
954static void
955hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
956{
957 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
958 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
959}
960
961static PVOID
962AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
963{
964 PVOID ret;
965 if (pAdapter->pFreePRDLink) {
966 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
967 ret = pAdapter->pFreePRDLink;
968 pAdapter->pFreePRDLink = *(void**)ret;
969 return ret;
970 }
971 return NULL;
972}
973
974static void
975FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable)
976{
977 *(void**)PRDTable = pAdapter->pFreePRDLink;
978 pAdapter->pFreePRDLink = PRDTable;
979}
980
981extern PVDevice fGetFirstChild(PVDevice pLogical);
982extern void fResetBootMark(PVDevice pLogical);
983static void
984fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
985{
986 PVDevice pPhysical, pLogical;
987 PVBus pVBus;
988 int i,j;
989
990 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) {
991 pPhysical = &(pAdapter->VDevices[i]);
992 pLogical = pPhysical;
993 while (pLogical->pParent) pLogical = pLogical->pParent;
994 if (pLogical->vf_online==0) {
995 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
996 continue;
997 }
998 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
999 continue;
1000
1001 pVBus = &pAdapter->VBus;
1002 if(pVBus)
1003 {
1004 j=0;
1005 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1006 if(j<MAX_VDEVICE_PER_VBUS){
1007 pVBus->pVDevice[j] = pLogical;
1008 pLogical->pVBus = pVBus;
1009
1010 if (j>0 && pLogical->vf_bootmark) {
1011 if (pVBus->pVDevice[0]->vf_bootmark) {
1012 fResetBootMark(pLogical);
1013 }
1014 else {
1015 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1016 pVBus->pVDevice[0] = pLogical;
1017 }
1018 }
1019 }
1020 }
1021 }
1022}
1023
1024PVDevice
1025GetSpareDisk(_VBUS_ARG PVDevice pArray)
1026{
1027 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1028 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1029 LBA_T thiscap, maxcap = MAX_LBA_T;
1030 PVDevice pVDevice, pFind = NULL;
1031 int i;
1032
1033 for(i=0;i<MV_SATA_CHANNELS_NUM;i++)
1034 {
1035 pVDevice = &pAdapter->VDevices[i];
1036 if(!pVDevice)
1037 continue;
1038 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1039 /* find the smallest usable spare disk */
1040 if (pVDevice->VDeviceType==VD_SPARE &&
1041 pVDevice->u.disk.df_on_line &&
1042 thiscap < maxcap &&
1043 thiscap >= capacity)
1044 {
1045 maxcap = pVDevice->VDeviceCapacity;
1046 pFind = pVDevice;
1047 }
1048 }
1049 return pFind;
1050}
1051
1052/******************************************************************
1053 * IO ATA Command
1054 *******************************************************************/
1055int HPTLIBAPI
1056fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1057{
1058 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1059}
1060
1061void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1062{
1063 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1064 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1065 MV_U8 channelIndex = pSataChannel->channelNumber;
1066 UCHAR mvMode;
1067 /* 508x don't use MW-DMA? */
1068 if (NewMode>4 && NewMode<8) NewMode = 4;
1069 pDev->bDeModeSetting = NewMode;
1070 if (NewMode<=4)
1071 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1072 else
1073 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1074
1075 /*To fix 88i8030 bug*/
1076 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1077 mvMode = MV_ATA_TRANSFER_UDMA_0;
1078
1079 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1080 /* Flush pending commands */
1081 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1082
1083 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1084 MV_ATA_SET_FEATURES_TRANSFER,
1085 mvMode, 0, 0, 0) == MV_FALSE)
1086 {
1087 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1088 }
1089 /* Enable EDMA */
1090 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1091 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1092}
1093
1094int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
1095{
1096 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1097 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1098 MV_U8 channelIndex = pSataChannel->channelNumber;
1099 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1100 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1101 int dmaActive = pSataChannel->queueCommandsEnabled;
1102 int ret = 0;
1103
1104 if (dmaActive) {
1105 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1106 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1107 }
1108
1109 if (enable) {
1110 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED &&
1111 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) {
1112 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1;
1113 channelInfo->queueDepth = (depth==32)? 31 : depth;
1114 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth);
1115 ret = 1;
1116 }
1117 }
1118 else
1119 {
1120 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) {
1121 channelInfo->queueDepth = 2;
1122 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0);
1123 ret = 1;
1124 }
1125 }
1126
1127 if (dmaActive)
1128 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1129 return ret;
1130}
1131
1132int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
1133{
1134 return 0;
1135}
1136
1137int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
1138{
1139 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1140 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1141 MV_U8 channelIndex = pSataChannel->channelNumber;
1142 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1143 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1144 int dmaActive = pSataChannel->queueCommandsEnabled;
1145 int ret = 0;
1146
1147 if (dmaActive) {
1148 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1149 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1150 }
1151
1152 if ((pSataChannel->identifyDevice[82] & (0x20))) {
1153 if (enable) {
1154 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1155 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0))
1156 {
1157 channelInfo->writeCacheEnabled = MV_TRUE;
1158 ret = 1;
1159 }
1160 }
1161 else {
1162 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1163 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0))
1164 {
1165 channelInfo->writeCacheEnabled = MV_FALSE;
1166 ret = 1;
1167 }
1168 }
1169 }
1170
1171 if (dmaActive)
1172 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1173 return ret;
1174}
1175
1176int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
1177{
1178 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1179 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1180 MV_U8 channelIndex = pSataChannel->channelNumber;
1181 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1182 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1183 int dmaActive = pSataChannel->queueCommandsEnabled;
1184 int ret = 0;
1185
1186 if (dmaActive) {
1187 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1188 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1189 }
1190
1191 if ((pSataChannel->identifyDevice[82] & (0x40))) {
1192 if (enable) {
1193 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1194 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0))
1195 {
1196 channelInfo->readAheadEnabled = MV_TRUE;
1197 ret = 1;
1198 }
1199 }
1200 else {
1201 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1202 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0))
1203 {
1204 channelInfo->readAheadEnabled = MV_FALSE;
1205 ret = 1;
1206 }
1207 }
1208 }
1209
1210 if (dmaActive)
1211 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1212 return ret;
1213}
1214
1215#ifdef SUPPORT_ARRAY
1216#define IdeRegisterVDevice fCheckArray
1217#else
1218void
1219IdeRegisterVDevice(PDevice pDev)
1220{
1221 PVDevice pVDev = Map2pVDevice(pDev);
1222
1223 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1224 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1225 pVDev->vf_online = 1;
1226 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1227 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1228 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1229}
1230#endif
1231
1232static __inline PBUS_DMAMAP
1233dmamap_get(struct IALAdapter * pAdapter)
1234{
1235 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1236 if (p)
1237 pAdapter->pbus_dmamap_list = p-> next;
1238 return p;
1239}
1240
1241static __inline void
1242dmamap_put(PBUS_DMAMAP p)
1243{
1244 p->next = p->pAdapter->pbus_dmamap_list;
1245 p->pAdapter->pbus_dmamap_list = p;
1246}
1247
1248static int num_adapters = 0;
1249static int
1250init_adapter(IAL_ADAPTER_T *pAdapter)
1251{
1252 PVBus _vbus_p = &pAdapter->VBus;
1253 MV_SATA_ADAPTER *pMvSataAdapter;
1254 int i, channel, rid;
1255
1256 PVDevice pVDev;
1257
1258 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF);
1259 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0);
1260 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0);
1261
1262 sx_xlock(&hptmv_list_lock);
1263 pAdapter->next = 0;
1264
1265 if(gIal_Adapter == 0){
1266 gIal_Adapter = pAdapter;
1267 pCurAdapter = gIal_Adapter;
1268 }
1269 else {
1270 pCurAdapter->next = pAdapter;
1271 pCurAdapter = pAdapter;
1272 }
1273 sx_xunlock(&hptmv_list_lock);
1274
1275 pAdapter->outstandingCommands = 0;
1276
1277 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1278 _vbus_p->OsExt = (void *)pAdapter;
1279 pMvSataAdapter->IALData = pAdapter;
1280
1281 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */
1282 4, /* alignment */
1283 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1284 BUS_SPACE_MAXADDR, /* lowaddr */
1285 BUS_SPACE_MAXADDR, /* highaddr */
1286 NULL, NULL, /* filter, filterarg */
1287 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1288 MAX_SG_DESCRIPTORS, /* nsegments */
1289 0x10000, /* maxsegsize */
1290 BUS_DMA_WAITOK, /* flags */
1291 busdma_lock_mutex, /* lockfunc */
1292 &pAdapter->lock, /* lockfuncarg */
1293 &pAdapter->io_dma_parent /* tag */))
1294 {
1295 return ENXIO;
1296 }
1297
1298
1299 if (hptmv_allocate_edma_queues(pAdapter))
1300 {
1301 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n");
1302 return ENOMEM;
1303 }
1304
1305 /* also map EPROM address */
1306 rid = 0x10;
| 29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/malloc.h>
35#include <sys/resource.h>
36#include <sys/time.h>
37#include <sys/callout.h>
38#include <sys/signalvar.h>
39#include <sys/eventhandler.h>
40#include <sys/proc.h>
41#include <sys/kthread.h>
42
43#include <sys/mutex.h>
44#include <sys/module.h>
45#include <sys/sx.h>
46
47#include <dev/pci/pcireg.h>
48#include <dev/pci/pcivar.h>
49
50#ifndef __KERNEL__
51#define __KERNEL__
52#endif
53
54#include <dev/hptmv/global.h>
55#include <dev/hptmv/hptintf.h>
56#include <dev/hptmv/osbsd.h>
57#include <dev/hptmv/access601.h>
58
59
60#ifdef DEBUG
61#ifdef DEBUG_LEVEL
62int hpt_dbg_level = DEBUG_LEVEL;
63#else
64int hpt_dbg_level = 0;
65#endif
66#endif
67
68#define MV_ERROR printf
69
70/*
71 * CAM SIM entry points
72 */
73static int hpt_probe (device_t dev);
74static void launch_worker_thread(void);
75static int hpt_attach(device_t dev);
76static int hpt_detach(device_t dev);
77static int hpt_shutdown(device_t dev);
78static void hpt_poll(struct cam_sim *sim);
79static void hpt_intr(void *arg);
80static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
81static void hpt_action(struct cam_sim *sim, union ccb *ccb);
82
83static device_method_t driver_methods[] = {
84 /* Device interface */
85 DEVMETHOD(device_probe, hpt_probe),
86 DEVMETHOD(device_attach, hpt_attach),
87 DEVMETHOD(device_detach, hpt_detach),
88
89 DEVMETHOD(device_shutdown, hpt_shutdown),
90 DEVMETHOD_END
91};
92
93static driver_t hpt_pci_driver = {
94 __str(PROC_DIR_NAME),
95 driver_methods,
96 sizeof(IAL_ADAPTER_T)
97};
98
99static devclass_t hpt_devclass;
100
101#define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6)
102__DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0);
103MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1);
104
105#define ccb_ccb_ptr spriv_ptr0
106#define ccb_adapter ccb_h.spriv_ptr1
107
108static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
109static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
110static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
111static void ccb_done(union ccb *ccb);
112static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
113static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
114static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter);
115static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
116static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
117static void handleEdmaError(_VBUS_ARG PCommand pCmd);
118static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
119static int fResetActiveCommands(PVBus _vbus_p);
120static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
121static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
122static void hptmv_handle_event_disconnect(void *data);
123static void hptmv_handle_event_connect(void *data);
124static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
125static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
126static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
127static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
128 int logical);
129static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
130 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
131 MV_U16 responseFlags, MV_U32 timeStamp,
132 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
133static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
134 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
135
136#define ccb_ccb_ptr spriv_ptr0
137#define ccb_adapter ccb_h.spriv_ptr1
138
139static struct sx hptmv_list_lock;
140SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list");
141IAL_ADAPTER_T *gIal_Adapter = 0;
142IAL_ADAPTER_T *pCurAdapter = 0;
143static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
144
145typedef struct st_HPT_DPC {
146 IAL_ADAPTER_T *pAdapter;
147 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
148 void *arg;
149 UCHAR flags;
150} ST_HPT_DPC;
151
152#define MAX_DPC 16
153UCHAR DPC_Request_Nums = 0;
154static ST_HPT_DPC DpcQueue[MAX_DPC];
155static int DpcQueue_First=0;
156static int DpcQueue_Last = 0;
157static struct mtx DpcQueue_Lock;
158MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF);
159
160char DRIVER_VERSION[] = "v1.16";
161
162/*******************************************************************************
163 * Name: hptmv_free_channel
164 *
165 * Description: free allocated queues for the given channel
166 *
167 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this
168 * channel connected to.
169 * channelNum - channel number.
170 *
171 ******************************************************************************/
172static void
173hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
174{
175 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
176 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
177}
178
179static void failDevice(PVDevice pVDev)
180{
181 PVBus _vbus_p = pVDev->pVBus;
182 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
183
184 pVDev->u.disk.df_on_line = 0;
185 pVDev->vf_online = 0;
186 if (pVDev->pfnDeviceFailed)
187 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
188
189 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
190
191#ifndef FOR_DEMO
192 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
193 pAdapter->beeping = 1;
194 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
195 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
196 }
197#endif
198}
199
200int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
201
202static void
203handleEdmaError(_VBUS_ARG PCommand pCmd)
204{
205 PDevice pDevice = &pCmd->pVDevice->u.disk;
206 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
207
208 if (!pDevice->df_on_line) {
209 KdPrint(("Device is offline"));
210 pCmd->Result = RETURN_BAD_DEVICE;
211 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
212 return;
213 }
214
215 if (pCmd->RetryCount++>5) {
216 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
217failed:
218 failDevice(pCmd->pVDevice);
219 pCmd->Result = RETURN_IDE_ERROR;
220 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
221 return;
222 }
223
224 /* reset the channel and retry the command */
225 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
226 goto failed;
227
228 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
229
230 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
231 fDeviceSendCommand(_VBUS_P pCmd);
232}
233
234/****************************************************************
235 * Name: hptmv_init_channel
236 *
237 * Description: allocate request and response queues for the EDMA of the
238 * given channel and sets other fields.
239 *
240 * Parameters:
241 * pAdapter - pointer to the emulated adapter data structure
242 * channelNum - channel number.
243 * Return: 0 on success, otherwise on failure
244 ****************************************************************/
245static int
246hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
247{
248 MV_SATA_CHANNEL *pMvSataChannel;
249 dma_addr_t req_dma_addr;
250 dma_addr_t rsp_dma_addr;
251
252 if (channelNum >= MV_SATA_CHANNELS_NUM)
253 {
254 MV_ERROR("RR18xx[%d]: Bad channelNum=%d",
255 pAdapter->mvSataAdapter.adapterId, channelNum);
256 return -1;
257 }
258
259 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
260 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
261 pMvSataChannel->channelNumber = channelNum;
262 pMvSataChannel->lba48Address = MV_FALSE;
263 pMvSataChannel->maxReadTransfer = MV_FALSE;
264
265 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
266 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
267 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
268
269
270 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
271
272 /* check the 1K alignment of the request queue*/
273 if (req_dma_addr & 0x3ff)
274 {
275 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned,"
276 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
277 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
278 return -1;
279 }
280 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
281 pMvSataChannel->requestQueuePciHiAddress = 0;
282 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p",
283 pAdapter->mvSataAdapter.adapterId, channelNum,
284 pMvSataChannel->requestQueue));
285 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
286 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
287 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
288
289 /* check the 256 alignment of the response queue*/
290 if (rsp_dma_addr & 0xff)
291 {
292 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte "
293 "aligned, dma_addr=%llx\n",
294 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
295 return -1;
296 }
297 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
298 pMvSataChannel->responseQueuePciHiAddress = 0;
299 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p",
300 pAdapter->mvSataAdapter.adapterId, channelNum,
301 pMvSataChannel->responseQueue));
302
303 pAdapter->mvChannel[channelNum].online = MV_TRUE;
304 return 0;
305}
306
307/******************************************************************************
308 * Name: hptmv_parse_identify_results
309 *
310 * Description: this functions parses the identify command results, checks
311 * that the connected deives can be accesed by RR18xx EDMA,
312 * and updates the channel stucture accordingly.
313 *
314 * Parameters: pMvSataChannel, pointer to the channel data structure.
315 *
316 * Returns: =0 ->success, < 0 ->failure.
317 *
318 ******************************************************************************/
319static int
320hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
321{
322 MV_U16 *iden = pMvSataChannel->identifyDevice;
323
324 /*LBA addressing*/
325 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
326 {
327 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
328 return -1;
329 }
330 else
331 {
332 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
333 }
334 /*DMA support*/
335 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
336 {
337 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
338 return -1;
339 }
340 else
341 {
342 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
343 }
344 /* PIO */
345 if ((iden[IDEN_VALID] & 2) == 0)
346 {
347 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
348 return -1;
349 }
350 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
351 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
352
353 /*UDMA*/
354 if ((iden[IDEN_VALID] & 4) == 0)
355 {
356 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
357 return -1;
358 }
359
360 /* 48 bit address */
361 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
362 {
363 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
364 pMvSataChannel->lba48Address = MV_TRUE;
365 }
366 else
367 {
368 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
369 pMvSataChannel->lba48Address = MV_FALSE;
370 }
371 return 0;
372}
373
374static void
375init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
376{
377 PVDevice pVDev = &pAdapter->VDevices[channel];
378 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
379 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
380
381 pMvSataChannel->outstandingCommands = 0;
382
383 pVDev->u.disk.mv = pMvSataChannel;
384 pVDev->u.disk.df_on_line = 1;
385 pVDev->u.disk.pVBus = &pAdapter->VBus;
386 pVDev->pVBus = &pAdapter->VBus;
387
388#ifdef SUPPORT_48BIT_LBA
389 if (pMvSataChannel->lba48Address == MV_TRUE)
390 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
391 else
392#endif
393 if(IdentifyData[53] & 1) {
394 pVDev->u.disk.dDeRealCapacity =
395 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
396 (IdentifyData[61]<<16 | IdentifyData[60]) :
397 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
398 } else
399 pVDev->u.disk.dDeRealCapacity =
400 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
401
402 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
403 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
404
405 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
406 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
407 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
408 }
409}
410
411static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
412{
413 PVDevice pVDev;
414 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
415 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
416
417 if (!pMvSataChannel) return;
418
419 if (plugged)
420 {
421 pVDev = &(pAdapter->VDevices[channelIndex]);
422 init_vdev_params(pAdapter, channelIndex);
423
424 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
425 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
426
427 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
428 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
429 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
430 pVDev->vf_online = 1;
431
432#ifdef SUPPORT_ARRAY
433 if(pVDev->pParent)
434 {
435 int iMember;
436 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
437 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
438 pVDev->pParent->u.array.pMember[iMember] = NULL;
439 pVDev->pParent = NULL;
440 }
441#endif
442 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
443 fCheckBootable(pVDev);
444 RegisterVDevice(pVDev);
445
446#ifndef FOR_DEMO
447 if (pAdapter->beeping) {
448 pAdapter->beeping = 0;
449 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
450 }
451#endif
452
453 }
454 else
455 {
456 pVDev = &(pAdapter->VDevices[channelIndex]);
457 failDevice(pVDev);
458 }
459}
460
461static int
462start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
463{
464 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
465 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
466 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
467 MV_U32 udmaMode,pioMode;
468
469 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId,
470 channelNum));
471
472
473 /* Software reset channel */
474 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
475 {
476 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
477 pMvSataAdapter->adapterId, channelNum);
478 return -1;
479 }
480
481 /* Hardware reset channel */
482 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
483 {
484 /* If failed, try again - this is when trying to hardreset a channel */
485 /* when drive is just spinning up */
486 StallExec(5000000); /* wait 5 sec before trying again */
487 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
488 {
489 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n",
490 pMvSataAdapter->adapterId, channelNum);
491 return -1;
492 }
493 }
494
495 /* identify device*/
496 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
497 {
498 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n"
499 , pMvSataAdapter->adapterId, channelNum);
500 return -1;
501 }
502 if (hptmv_parse_identify_results(pMvSataChannel))
503 {
504 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n"
505 , pMvSataAdapter->adapterId, channelNum);
506 return -1;
507 }
508
509 /* mvStorageDevATASetFeatures */
510 /* Disable 8 bit PIO in case CFA enabled */
511 if (pMvSataChannel->identifyDevice[86] & 4)
512 {
513 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n",
514 pMvSataAdapter->adapterId));
515 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
516 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
517 0, 0, 0) == MV_FALSE)
518 {
519 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures"
520 " failed\n", pMvSataAdapter->adapterId, channelNum);
521 return -1;
522 }
523 }
524 /* Write cache */
525#ifdef ENABLE_WRITE_CACHE
526 if (pMvSataChannel->identifyDevice[82] & 0x20)
527 {
528 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
529 {
530 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
531 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
532 0, 0, 0) == MV_FALSE)
533 {
534 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
535 pMvSataAdapter->adapterId, channelNum);
536 return -1;
537 }
538 }
539 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n",
540 pMvSataAdapter->adapterId, channelNum));
541 }
542 else
543 {
544 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n",
545 pMvSataAdapter->adapterId, channelNum));
546 }
547#else /* disable write cache */
548 {
549 if (pMvSataChannel->identifyDevice[85] & 0x20)
550 {
551 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n",
552 pMvSataAdapter->adapterId, channelNum));
553 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
554 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
555 0, 0, 0) == MV_FALSE)
556 {
557 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
558 pMvSataAdapter->adapterId, channelNum);
559 return -1;
560 }
561 }
562 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n",
563 pMvSataAdapter->adapterId, channelNum));
564 }
565#endif
566
567 /* Set transfer mode */
568 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n",
569 pMvSataAdapter->adapterId));
570 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
571 MV_ATA_SET_FEATURES_TRANSFER,
572 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
573 MV_FALSE)
574 {
575 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
576 pMvSataAdapter->adapterId, channelNum);
577 return -1;
578 }
579
580 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
581 {
582 pioMode = MV_ATA_TRANSFER_PIO_4;
583 }
584 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
585 {
586 pioMode = MV_ATA_TRANSFER_PIO_3;
587 }
588 else
589 {
590 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
591 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
592 }
593
594 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n",
595 pMvSataAdapter->adapterId));
596 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
597 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
598 MV_ATA_SET_FEATURES_TRANSFER,
599 pioMode, 0, 0, 0) == MV_FALSE)
600 {
601 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
602 pMvSataAdapter->adapterId, channelNum);
603 return -1;
604 }
605
606 udmaMode = MV_ATA_TRANSFER_UDMA_0;
607 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
608 {
609 udmaMode = MV_ATA_TRANSFER_UDMA_6;
610 }
611 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
612 {
613 udmaMode = MV_ATA_TRANSFER_UDMA_5;
614 }
615 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
616 {
617 udmaMode = MV_ATA_TRANSFER_UDMA_4;
618 }
619 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
620 {
621 udmaMode = MV_ATA_TRANSFER_UDMA_3;
622 }
623 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
624 {
625 udmaMode = MV_ATA_TRANSFER_UDMA_2;
626 }
627
628 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n",
629 pMvSataAdapter->adapterId, udmaMode & 0xf));
630 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
631
632 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
633 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
634 0, 0, 0) == MV_FALSE)
635 {
636 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
637 pMvSataAdapter->adapterId, channelNum);
638 return -1;
639 }*/
640 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
641 return TRUE;
642 else
643 do
644 {
645 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
646 MV_ATA_SET_FEATURES_TRANSFER,
647 pChannelInfo->maxUltraDmaModeSupported,
648 0, 0, 0) == MV_FALSE)
649 {
650 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
651 {
652 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
653 {
654 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
655 pMvSataChannel->eDmaRegsOffset +
656 0x11c, /* command reg */
657 MV_ATA_COMMAND_IDLE_IMMEDIATE);
658 mvMicroSecondsDelay(10000);
659 mvSataChannelHardReset(pMvSataAdapter, channelNum);
660 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
661 return FALSE;
662 }
663 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
664 return FALSE;
665 pChannelInfo->maxUltraDmaModeSupported--;
666 continue;
667 }
668 else return FALSE;
669 }
670 break;
671 }while (1);
672
673 /* Read look ahead */
674#ifdef ENABLE_READ_AHEAD
675 if (pMvSataChannel->identifyDevice[82] & 0x40)
676 {
677 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
678 {
679 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
680 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
681 0, 0) == MV_FALSE)
682 {
683 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
684 pMvSataAdapter->adapterId, channelNum);
685 return -1;
686 }
687 }
688 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n",
689 pMvSataAdapter->adapterId, channelNum));
690 }
691 else
692 {
693 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n",
694 pMvSataAdapter->adapterId, channelNum));
695 }
696#else
697 {
698 if (pMvSataChannel->identifyDevice[86] & 0x20)
699 {
700 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n",
701 pMvSataAdapter->adapterId, channelNum));
702 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
703 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
704 0, 0) == MV_FALSE)
705 {
706 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n",
707 pMvSataAdapter->adapterId, channelNum);
708 return -1;
709 }
710 }
711 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n",
712 pMvSataAdapter->adapterId, channelNum));
713 }
714#endif
715
716
717 {
718 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n",
719 pMvSataAdapter->adapterId,
720 channelNum));
721 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
722 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
723 {
724 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
725 pMvSataAdapter->adapterId, channelNum);
726 return -1;
727 }
728 }
729 /* Enable EDMA */
730 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
731 {
732 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n",
733 pMvSataAdapter->adapterId, channelNum);
734 return -1;
735 }
736 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n",
737 pMvSataAdapter->adapterId, channelNum);
738
739#ifndef FOR_DEMO
740 set_fail_led(pMvSataAdapter, channelNum, 0);
741#endif
742 return 0;
743}
744
745static void
746hptmv_handle_event(void * data, int flag)
747{
748 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
749 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
750 MV_U8 channelIndex;
751
752 mtx_assert(&pAdapter->lock, MA_OWNED);
753/* mvOsSemTake(&pMvSataAdapter->semaphore); */
754 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
755 {
756 switch(pAdapter->sataEvents[channelIndex])
757 {
758 case SATA_EVENT_CHANNEL_CONNECTED:
759 /* Handle only connects */
760 if (flag == 1)
761 break;
762 KdPrint(("RR18xx [%d,%d]: new device connected\n",
763 pMvSataAdapter->adapterId, channelIndex));
764 hptmv_init_channel(pAdapter, channelIndex);
765 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
766 {
767 MV_ERROR("RR18xx [%d,%d] Failed to configure\n",
768 pMvSataAdapter->adapterId, channelIndex);
769 hptmv_free_channel(pAdapter, channelIndex);
770 }
771 else
772 {
773 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
774 if (start_channel( pAdapter, channelIndex))
775 {
776 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n",
777 pMvSataAdapter->adapterId, channelIndex);
778 hptmv_free_channel(pAdapter, channelIndex);
779 }
780 else
781 {
782 device_change(pAdapter, channelIndex, TRUE);
783 }
784 }
785 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
786 break;
787
788 case SATA_EVENT_CHANNEL_DISCONNECTED:
789 /* Handle only disconnects */
790 if (flag == 0)
791 break;
792 KdPrint(("RR18xx [%d,%d]: device disconnected\n",
793 pMvSataAdapter->adapterId, channelIndex));
794 /* Flush pending commands */
795 if(pMvSataAdapter->sataChannel[channelIndex])
796 {
797 _VBUS_INST(&pAdapter->VBus)
798 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
799 MV_FLUSH_TYPE_CALLBACK);
800 CheckPendingCall(_VBUS_P0);
801 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
802 hptmv_free_channel(pAdapter, channelIndex);
803 pMvSataAdapter->sataChannel[channelIndex] = NULL;
804 KdPrint(("RR18xx [%d,%d]: channel removed\n",
805 pMvSataAdapter->adapterId, channelIndex));
806 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
807 Check_Idle_Call(pAdapter);
808 }
809 else
810 {
811 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n",
812 pMvSataAdapter->adapterId, channelIndex));
813 }
814 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
815 break;
816
817 case SATA_EVENT_NO_CHANGE:
818 break;
819
820 default:
821 break;
822 }
823 }
824/* mvOsSemRelease(&pMvSataAdapter->semaphore); */
825}
826
827#define EVENT_CONNECT 1
828#define EVENT_DISCONNECT 0
829
830static void
831hptmv_handle_event_connect(void *data)
832{
833 hptmv_handle_event (data, 0);
834}
835
836static void
837hptmv_handle_event_disconnect(void *data)
838{
839 hptmv_handle_event (data, 1);
840}
841
842static MV_BOOLEAN
843hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
844 MV_U32 param1, MV_U32 param2)
845{
846 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
847
848 switch (eventType)
849 {
850 case MV_EVENT_TYPE_SATA_CABLE:
851 {
852 MV_U8 channel = param2;
853
854 if (param1 == EVENT_CONNECT)
855 {
856 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
857 KdPrint(("RR18xx [%d,%d]: device connected event received\n",
858 pMvSataAdapter->adapterId, channel));
859 /* Delete previous timers (if multiple drives connected in the same time */
860 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter);
861 }
862 else if (param1 == EVENT_DISCONNECT)
863 {
864 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
865 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n",
866 pMvSataAdapter->adapterId, channel));
867 device_change(pAdapter, channel, FALSE);
868 /* Delete previous timers (if multiple drives disconnected in the same time */
869 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */
870 /*It is not necessary to wait, handle it directly*/
871 hptmv_handle_event_disconnect(pAdapter);
872 }
873 else
874 {
875
876 MV_ERROR("RR18xx: illegal value for param1(%d) at "
877 "connect/disconnect event, host=%d\n", param1,
878 pMvSataAdapter->adapterId );
879
880 }
881 }
882 break;
883 case MV_EVENT_TYPE_ADAPTER_ERROR:
884 KdPrint(("RR18xx: DEVICE error event received, pci cause "
885 "reg=%x, don't how to handle this\n", param1));
886 return MV_TRUE;
887 default:
888 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n",
889 pMvSataAdapter->adapterId, eventType);
890 return MV_FALSE;
891 }
892 return MV_TRUE;
893}
894
895static int
896hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
897{
898 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
899 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
900 if (pAdapter->requestsArrayBaseAddr == NULL)
901 {
902 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request"
903 " queues\n", pAdapter->mvSataAdapter.adapterId);
904 return -1;
905 }
906 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
907 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
908 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
909 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
910 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
911 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
912 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
913 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
914
915 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
916 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
917 {
918 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n",
919 pAdapter->mvSataAdapter.adapterId);
920 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
921 return -1;
922 }
923 /* response queues */
924 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
925 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
926 if (pAdapter->responsesArrayBaseAddr == NULL)
927 {
928 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response"
929 " queues\n", pAdapter->mvSataAdapter.adapterId);
930 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
931 return -1;
932 }
933 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
934 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
935 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
936 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
937 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
938 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
939 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
940 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
941
942 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
943 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
944 {
945 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n",
946 pAdapter->mvSataAdapter.adapterId);
947 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
948 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
949 return -1;
950 }
951 return 0;
952}
953
954static void
955hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
956{
957 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
958 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
959}
960
961static PVOID
962AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
963{
964 PVOID ret;
965 if (pAdapter->pFreePRDLink) {
966 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
967 ret = pAdapter->pFreePRDLink;
968 pAdapter->pFreePRDLink = *(void**)ret;
969 return ret;
970 }
971 return NULL;
972}
973
974static void
975FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable)
976{
977 *(void**)PRDTable = pAdapter->pFreePRDLink;
978 pAdapter->pFreePRDLink = PRDTable;
979}
980
981extern PVDevice fGetFirstChild(PVDevice pLogical);
982extern void fResetBootMark(PVDevice pLogical);
983static void
984fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
985{
986 PVDevice pPhysical, pLogical;
987 PVBus pVBus;
988 int i,j;
989
990 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) {
991 pPhysical = &(pAdapter->VDevices[i]);
992 pLogical = pPhysical;
993 while (pLogical->pParent) pLogical = pLogical->pParent;
994 if (pLogical->vf_online==0) {
995 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
996 continue;
997 }
998 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
999 continue;
1000
1001 pVBus = &pAdapter->VBus;
1002 if(pVBus)
1003 {
1004 j=0;
1005 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1006 if(j<MAX_VDEVICE_PER_VBUS){
1007 pVBus->pVDevice[j] = pLogical;
1008 pLogical->pVBus = pVBus;
1009
1010 if (j>0 && pLogical->vf_bootmark) {
1011 if (pVBus->pVDevice[0]->vf_bootmark) {
1012 fResetBootMark(pLogical);
1013 }
1014 else {
1015 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1016 pVBus->pVDevice[0] = pLogical;
1017 }
1018 }
1019 }
1020 }
1021 }
1022}
1023
1024PVDevice
1025GetSpareDisk(_VBUS_ARG PVDevice pArray)
1026{
1027 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1028 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1029 LBA_T thiscap, maxcap = MAX_LBA_T;
1030 PVDevice pVDevice, pFind = NULL;
1031 int i;
1032
1033 for(i=0;i<MV_SATA_CHANNELS_NUM;i++)
1034 {
1035 pVDevice = &pAdapter->VDevices[i];
1036 if(!pVDevice)
1037 continue;
1038 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1039 /* find the smallest usable spare disk */
1040 if (pVDevice->VDeviceType==VD_SPARE &&
1041 pVDevice->u.disk.df_on_line &&
1042 thiscap < maxcap &&
1043 thiscap >= capacity)
1044 {
1045 maxcap = pVDevice->VDeviceCapacity;
1046 pFind = pVDevice;
1047 }
1048 }
1049 return pFind;
1050}
1051
1052/******************************************************************
1053 * IO ATA Command
1054 *******************************************************************/
1055int HPTLIBAPI
1056fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1057{
1058 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1059}
1060
1061void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1062{
1063 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1064 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1065 MV_U8 channelIndex = pSataChannel->channelNumber;
1066 UCHAR mvMode;
1067 /* 508x don't use MW-DMA? */
1068 if (NewMode>4 && NewMode<8) NewMode = 4;
1069 pDev->bDeModeSetting = NewMode;
1070 if (NewMode<=4)
1071 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1072 else
1073 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1074
1075 /*To fix 88i8030 bug*/
1076 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1077 mvMode = MV_ATA_TRANSFER_UDMA_0;
1078
1079 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1080 /* Flush pending commands */
1081 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1082
1083 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1084 MV_ATA_SET_FEATURES_TRANSFER,
1085 mvMode, 0, 0, 0) == MV_FALSE)
1086 {
1087 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1088 }
1089 /* Enable EDMA */
1090 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1091 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1092}
1093
1094int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
1095{
1096 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1097 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1098 MV_U8 channelIndex = pSataChannel->channelNumber;
1099 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1100 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1101 int dmaActive = pSataChannel->queueCommandsEnabled;
1102 int ret = 0;
1103
1104 if (dmaActive) {
1105 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1106 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1107 }
1108
1109 if (enable) {
1110 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED &&
1111 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) {
1112 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1;
1113 channelInfo->queueDepth = (depth==32)? 31 : depth;
1114 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth);
1115 ret = 1;
1116 }
1117 }
1118 else
1119 {
1120 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) {
1121 channelInfo->queueDepth = 2;
1122 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0);
1123 ret = 1;
1124 }
1125 }
1126
1127 if (dmaActive)
1128 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1129 return ret;
1130}
1131
1132int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
1133{
1134 return 0;
1135}
1136
1137int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
1138{
1139 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1140 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1141 MV_U8 channelIndex = pSataChannel->channelNumber;
1142 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1143 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1144 int dmaActive = pSataChannel->queueCommandsEnabled;
1145 int ret = 0;
1146
1147 if (dmaActive) {
1148 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1149 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1150 }
1151
1152 if ((pSataChannel->identifyDevice[82] & (0x20))) {
1153 if (enable) {
1154 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1155 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0))
1156 {
1157 channelInfo->writeCacheEnabled = MV_TRUE;
1158 ret = 1;
1159 }
1160 }
1161 else {
1162 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1163 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0))
1164 {
1165 channelInfo->writeCacheEnabled = MV_FALSE;
1166 ret = 1;
1167 }
1168 }
1169 }
1170
1171 if (dmaActive)
1172 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1173 return ret;
1174}
1175
1176int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
1177{
1178 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1179 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1180 MV_U8 channelIndex = pSataChannel->channelNumber;
1181 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1182 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1183 int dmaActive = pSataChannel->queueCommandsEnabled;
1184 int ret = 0;
1185
1186 if (dmaActive) {
1187 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1188 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1189 }
1190
1191 if ((pSataChannel->identifyDevice[82] & (0x40))) {
1192 if (enable) {
1193 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1194 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0))
1195 {
1196 channelInfo->readAheadEnabled = MV_TRUE;
1197 ret = 1;
1198 }
1199 }
1200 else {
1201 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1202 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0))
1203 {
1204 channelInfo->readAheadEnabled = MV_FALSE;
1205 ret = 1;
1206 }
1207 }
1208 }
1209
1210 if (dmaActive)
1211 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1212 return ret;
1213}
1214
1215#ifdef SUPPORT_ARRAY
1216#define IdeRegisterVDevice fCheckArray
1217#else
1218void
1219IdeRegisterVDevice(PDevice pDev)
1220{
1221 PVDevice pVDev = Map2pVDevice(pDev);
1222
1223 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1224 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1225 pVDev->vf_online = 1;
1226 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1227 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1228 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1229}
1230#endif
1231
1232static __inline PBUS_DMAMAP
1233dmamap_get(struct IALAdapter * pAdapter)
1234{
1235 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1236 if (p)
1237 pAdapter->pbus_dmamap_list = p-> next;
1238 return p;
1239}
1240
1241static __inline void
1242dmamap_put(PBUS_DMAMAP p)
1243{
1244 p->next = p->pAdapter->pbus_dmamap_list;
1245 p->pAdapter->pbus_dmamap_list = p;
1246}
1247
1248static int num_adapters = 0;
1249static int
1250init_adapter(IAL_ADAPTER_T *pAdapter)
1251{
1252 PVBus _vbus_p = &pAdapter->VBus;
1253 MV_SATA_ADAPTER *pMvSataAdapter;
1254 int i, channel, rid;
1255
1256 PVDevice pVDev;
1257
1258 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF);
1259 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0);
1260 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0);
1261
1262 sx_xlock(&hptmv_list_lock);
1263 pAdapter->next = 0;
1264
1265 if(gIal_Adapter == 0){
1266 gIal_Adapter = pAdapter;
1267 pCurAdapter = gIal_Adapter;
1268 }
1269 else {
1270 pCurAdapter->next = pAdapter;
1271 pCurAdapter = pAdapter;
1272 }
1273 sx_xunlock(&hptmv_list_lock);
1274
1275 pAdapter->outstandingCommands = 0;
1276
1277 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1278 _vbus_p->OsExt = (void *)pAdapter;
1279 pMvSataAdapter->IALData = pAdapter;
1280
1281 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */
1282 4, /* alignment */
1283 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1284 BUS_SPACE_MAXADDR, /* lowaddr */
1285 BUS_SPACE_MAXADDR, /* highaddr */
1286 NULL, NULL, /* filter, filterarg */
1287 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1288 MAX_SG_DESCRIPTORS, /* nsegments */
1289 0x10000, /* maxsegsize */
1290 BUS_DMA_WAITOK, /* flags */
1291 busdma_lock_mutex, /* lockfunc */
1292 &pAdapter->lock, /* lockfuncarg */
1293 &pAdapter->io_dma_parent /* tag */))
1294 {
1295 return ENXIO;
1296 }
1297
1298
1299 if (hptmv_allocate_edma_queues(pAdapter))
1300 {
1301 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n");
1302 return ENOMEM;
1303 }
1304
1305 /* also map EPROM address */
1306 rid = 0x10;
|
1309 ||
1310 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1311 {
1312 MV_ERROR("RR18xx: Failed to remap memory space\n");
1313 hptmv_free_edma_queues(pAdapter);
1314 return ENXIO;
1315 }
1316 else
1317 {
1318 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1319 }
1320
1321 pMvSataAdapter->adapterId = num_adapters++;
1322 /* get the revision ID */
1323 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1324 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1325
1326 /* init RR18xx */
1327 pMvSataAdapter->intCoalThre[0]= 1;
1328 pMvSataAdapter->intCoalThre[1]= 1;
1329 pMvSataAdapter->intTimeThre[0] = 1;
1330 pMvSataAdapter->intTimeThre[1] = 1;
1331 pMvSataAdapter->pciCommand = 0x0107E371;
1332 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1333 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1334 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1335
1336 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1337 {
1338 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n",
1339 pMvSataAdapter->adapterId);
1340unregister:
1341 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1342 hptmv_free_edma_queues(pAdapter);
1343 return ENXIO;
1344 }
1345 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1346
1347#ifndef FOR_DEMO
1348 set_fail_leds(pMvSataAdapter, 0);
1349#endif
1350
1351 /* setup command blocks */
1352 KdPrint(("Allocate command blocks\n"));
1353 _vbus_(pFreeCommands) = 0;
1354 pAdapter->pCommandBlocks =
1355 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1356 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1357 if (!pAdapter->pCommandBlocks) {
1358 MV_ERROR("insufficient memory\n");
1359 goto unregister;
1360 }
1361
1362 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1363 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1364 }
1365
1366 /*Set up the bus_dmamap*/
1367 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1368 if(!pAdapter->pbus_dmamap) {
1369 MV_ERROR("insufficient memory\n");
1370 free(pAdapter->pCommandBlocks, M_DEVBUF);
1371 goto unregister;
1372 }
1373
1374 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1375 pAdapter->pbus_dmamap_list = 0;
1376 for (i=0; i < MAX_QUEUE_COMM; i++) {
1377 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1378 pmap->pAdapter = pAdapter;
1379 dmamap_put(pmap);
1380
1381 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1382 MV_ERROR("Can not allocate dma map\n");
1383 free(pAdapter->pCommandBlocks, M_DEVBUF);
1384 free(pAdapter->pbus_dmamap, M_DEVBUF);
1385 goto unregister;
1386 }
1387 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0);
1388 }
1389 /* setup PRD Tables */
1390 KdPrint(("Allocate PRD Tables\n"));
1391 pAdapter->pFreePRDLink = 0;
1392
1393 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1394 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1395
1396 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1397 if (!pAdapter->prdTableAddr) {
1398 MV_ERROR("insufficient PRD Tables\n");
1399 goto unregister;
1400 }
1401 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1402 {
1403 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1404 for (i=0; i<PRD_TABLES_FOR_VBUS; i++)
1405 {
1406/* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1407 FreePRDTable(pAdapter, PRDTable);
1408 PRDTable += PRD_ENTRIES_SIZE;
1409 }
1410 }
1411
1412 /* enable the adapter interrupts */
1413
1414 /* configure and start the connected channels*/
1415 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1416 {
1417 pAdapter->mvChannel[channel].online = MV_FALSE;
1418 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1419 == MV_TRUE)
1420 {
1421 KdPrint(("RR18xx[%d]: channel %d is connected\n",
1422 pMvSataAdapter->adapterId, channel));
1423
1424 if (hptmv_init_channel(pAdapter, channel) == 0)
1425 {
1426 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1427 {
1428 MV_ERROR("RR18xx[%d]: Failed to configure channel"
1429 " %d\n",pMvSataAdapter->adapterId, channel);
1430 hptmv_free_channel(pAdapter, channel);
1431 }
1432 else
1433 {
1434 if (start_channel(pAdapter, channel))
1435 {
1436 MV_ERROR("RR18xx[%d]: Failed to start channel,"
1437 " channel=%d\n",pMvSataAdapter->adapterId,
1438 channel);
1439 hptmv_free_channel(pAdapter, channel);
1440 }
1441 pAdapter->mvChannel[channel].online = MV_TRUE;
1442 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1443 channel,
1444 MV_TRUE);*/
1445 }
1446 }
1447 }
1448 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1449 pAdapter->mvChannel[channel].online, channel));
1450 }
1451
1452#ifdef SUPPORT_ARRAY
1453 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1454 pVDev = ArrayTables(i);
1455 mArFreeArrayTable(pVDev);
1456 }
1457#endif
1458
1459 KdPrint(("Initialize Devices\n"));
1460 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1461 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1462 if (pMvSataChannel) {
1463 init_vdev_params(pAdapter, channel);
1464 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1465 }
1466 }
1467#ifdef SUPPORT_ARRAY
1468 CheckArrayCritical(_VBUS_P0);
1469#endif
1470 _vbus_p->nInstances = 1;
1471 fRegisterVdevice(pAdapter);
1472
1473 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) {
1474 pVDev = _vbus_p->pVDevice[channel];
1475 if (pVDev && pVDev->vf_online)
1476 fCheckBootable(pVDev);
1477 }
1478
1479#if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1480 init_raid5_memory(_VBUS_P0);
1481 _vbus_(r5).enable_write_back = 1;
1482 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1483#endif
1484
1485 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1486 return 0;
1487}
1488
1489int
1490MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1491{
1492 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1493
1494 mvSataDisableChannelDma(pMvSataAdapter, channel);
1495 /* Flush pending commands */
1496 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1497
1498 /* Software reset channel */
1499 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1500 {
1501 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
1502 pMvSataAdapter->adapterId, channel);
1503 hptmv_free_channel(pAdapter, channel);
1504 return -1;
1505 }
1506
1507 /* Hardware reset channel */
1508 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1509 {
1510 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n",
1511 pMvSataAdapter->adapterId, channel);
1512 hptmv_free_channel(pAdapter, channel);
1513 return -1;
1514 }
1515
1516 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1517 {
1518 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n",
1519 pMvSataAdapter->adapterId, channel);
1520 hptmv_free_channel(pAdapter, channel);
1521 return -1;
1522 }else
1523 {
1524 MV_ERROR("channel %d: perform recalibrate command", channel);
1525 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1526 MV_NON_UDMA_PROTOCOL_NON_DATA,
1527 MV_FALSE,
1528 NULL, /* pBuffer*/
1529 0, /* count */
1530 0, /*features*/
1531 /* sectorCount */
1532 0,
1533 0, /* lbaLow */
1534 0, /* lbaMid */
1535 /* lbaHigh */
1536 0,
1537 0, /* device */
1538 /* command */
1539 0x10))
1540 MV_ERROR("channel %d: recalibrate failed", channel);
1541
1542 /* Set transfer mode */
1543 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1544 MV_ATA_SET_FEATURES_TRANSFER,
1545 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1546 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1547 MV_ATA_SET_FEATURES_TRANSFER,
1548 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1549 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1550 MV_ATA_SET_FEATURES_TRANSFER,
1551 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1552 {
1553 MV_ERROR("channel %d: Set Features failed", channel);
1554 hptmv_free_channel(pAdapter, channel);
1555 return -1;
1556 }
1557 /* Enable EDMA */
1558 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1559 {
1560 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1561 hptmv_free_channel(pAdapter, channel);
1562 return -1;
1563 }
1564 }
1565 return 0;
1566}
1567
1568static int
1569fResetActiveCommands(PVBus _vbus_p)
1570{
1571 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1572 MV_U8 channel;
1573 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1574 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1575 MvSataResetChannel(pMvSataAdapter,channel);
1576 }
1577 return 0;
1578}
1579
1580void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1581{
1582 UINT cont;
1583 ULONG ticks = 0;
1584 MV_U8 channel;
1585 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1586 MV_SATA_CHANNEL *pMvSataChannel;
1587
1588 do {
1589check_cmds:
1590 cont = 0;
1591 CheckPendingCall(_VBUS_P0);
1592#ifdef _RAID5N_
1593 dataxfer_poll();
1594 xor_poll();
1595#endif
1596 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1597 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1598 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1599 {
1600 while (pMvSataChannel->outstandingCommands) {
1601 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1602 StallExec(1000);
1603 if (ticks++ > 3000) {
1604 MvSataResetChannel(pMvSataAdapter,channel);
1605 goto check_cmds;
1606 }
1607 }
1608 else
1609 ticks = 0;
1610 }
1611 cont = 1;
1612 }
1613 }
1614 } while (cont);
1615}
1616
1617void
1618fResetVBus(_VBUS_ARG0)
1619{
1620 KdPrint(("fMvResetBus(%p)", _vbus_p));
1621
1622 /* some commands may already finished. */
1623 CheckPendingCall(_VBUS_P0);
1624
1625 fResetActiveCommands(_vbus_p);
1626 /*
1627 * the other pending commands may still be finished successfully.
1628 */
1629 fCompleteAllCommandsSynchronously(_vbus_p);
1630
1631 /* Now there should be no pending commands. No more action needed. */
1632 CheckIdleCall(_VBUS_P0);
1633
1634 KdPrint(("fMvResetBus() done"));
1635}
1636
1637/*No rescan function*/
1638void
1639fRescanAllDevice(_VBUS_ARG0)
1640{
1641}
1642
1643static MV_BOOLEAN
1644CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1645 MV_U8 channelNum,
1646 MV_COMPLETION_TYPE comp_type,
1647 MV_VOID_PTR commandId,
1648 MV_U16 responseFlags,
1649 MV_U32 timeStamp,
1650 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1651{
1652 PCommand pCmd = (PCommand) commandId;
1653 _VBUS_INST(pCmd->pVDevice->pVBus)
1654
1655 if (pCmd->uScratch.sata_param.prdAddr)
1656 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1657
1658 switch (comp_type)
1659 {
1660 case MV_COMPLETION_TYPE_NORMAL:
1661 pCmd->Result = RETURN_SUCCESS;
1662 break;
1663 case MV_COMPLETION_TYPE_ABORT:
1664 pCmd->Result = RETURN_BUS_RESET;
1665 break;
1666 case MV_COMPLETION_TYPE_ERROR:
1667 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1668 pMvSataAdapter->adapterId, channelNum, responseFlags);
1669
1670 if (responseFlags & 4) {
1671 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1672 " LBA high %x, device %x, status %x\n",
1673 registerStruct->errorRegister,
1674 registerStruct->sectorCountRegister,
1675 registerStruct->lbaLowRegister,
1676 registerStruct->lbaMidRegister,
1677 registerStruct->lbaHighRegister,
1678 registerStruct->deviceRegister,
1679 registerStruct->statusRegister);
1680 }
1681 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1682 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1683 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1684 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1685 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1686 pCmd->pVDevice->u.disk.QueueLength--;
1687 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1688 return TRUE;
1689
1690 default:
1691 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1692 return MV_FALSE;
1693 }
1694
1695 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1696 pCmd->uScratch.sata_param.cmd_priv --;
1697 return TRUE;
1698 }
1699 pCmd->pVDevice->u.disk.QueueLength--;
1700 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1701 return TRUE;
1702}
1703
1704void
1705fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1706{
1707 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1708 MV_SATA_ADAPTER *pMvSataAdapter;
1709 MV_SATA_CHANNEL *pMvSataChannel;
1710 PVDevice pVDevice = pCmd->pVDevice;
1711 PDevice pDevice = &pVDevice->u.disk;
1712 LBA_T Lba = pCmd->uCmd.Ide.Lba;
1713 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1714
1715 MV_QUEUE_COMMAND_RESULT result;
1716 MV_QUEUE_COMMAND_INFO commandInfo;
1717 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1718 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1719
1720 MV_BOOLEAN is48bit;
1721 MV_U8 channel;
1722 int i=0;
1723
1724 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1725
1726 if (!pDevice->df_on_line) {
1727 MV_ERROR("Device is offline");
1728 pCmd->Result = RETURN_BAD_DEVICE;
1729 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1730 return;
1731 }
1732
1733 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1734 pMvSataChannel = pDevice->mv;
1735 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1736 channel = pMvSataChannel->channelNumber;
1737
1738 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1739 Lba += pDevice->dDeHiddenLba;
1740 /* check LBA */
1741 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1742 pCmd->Result = RETURN_INVALID_REQUEST;
1743 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1744 return;
1745 }
1746
1747 /*
1748 * always use 48bit LBA if drive supports it.
1749 * Some Seagate drives report error if you use a 28-bit command
1750 * to access sector 0xfffffff.
1751 */
1752 is48bit = pMvSataChannel->lba48Address;
1753
1754 switch (pCmd->uCmd.Ide.Command)
1755 {
1756 case IDE_COMMAND_READ:
1757 case IDE_COMMAND_WRITE:
1758 if (pDevice->bDeModeSetting<8) goto pio;
1759
1760 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1761 pUdmaParams->isEXT = is48bit;
1762 pUdmaParams->numOfSectors = nSector;
1763 pUdmaParams->lowLBAAddress = Lba;
1764 pUdmaParams->highLBAAddress = 0;
1765 pUdmaParams->prdHighAddr = 0;
1766 pUdmaParams->callBack = CommandCompletionCB;
1767 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1768 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1769 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1770 else
1771 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1772
1773 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1774 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1775 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1776 }
1777 else {
1778 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1779pio:
1780 mvSataDisableChannelDma(pMvSataAdapter, channel);
1781 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1782
1783 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1784 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1785 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1786 }
1787 else {
1788 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1789 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1790 goto finish_cmd;
1791 }
1792 }
1793
1794 do {
1795 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1796 ULONG_PTR addr = tmpSg->dSgAddress;
1797 if (size & 0x1ff) {
1798 pCmd->Result = RETURN_INVALID_REQUEST;
1799 goto finish_cmd;
1800 }
1801 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1802 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1803 is48bit,
1804 (MV_U16_PTR)addr,
1805 size >> 1, /* count */
1806 0, /* features N/A */
1807 (MV_U16)(size>>9), /*sector count*/
1808 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1809 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1810 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1811 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1812 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1813 )==MV_FALSE)
1814 {
1815 pCmd->Result = RETURN_IDE_ERROR;
1816 goto finish_cmd;
1817 }
1818 Lba += size>>9;
1819 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1820 }
1821 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1822 pCmd->Result = RETURN_SUCCESS;
1823finish_cmd:
1824 mvSataEnableChannelDma(pMvSataAdapter,channel);
1825 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1826 return;
1827 }
1828 }
1829
1830 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1831 KdPrint(("pPRDTable:%p\n",pPRDTable));
1832 if (!pPRDTable) {
1833 pCmd->Result = RETURN_DEVICE_BUSY;
1834 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1835 HPT_ASSERT(0);
1836 return;
1837 }
1838
1839 do{
1840 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1841 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1842 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1843 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1844 pPRDTable[i].reserved = 0;
1845 i++;
1846 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1847
1848 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1849 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1850 pUdmaParams->numOfSectors = 0;
1851 }
1852
1853 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1854
1855 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1856
1857 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1858 {
1859queue_failed:
1860 switch (result)
1861 {
1862 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1863 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1864 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1865 pCmd->Result = RETURN_IDE_ERROR;
1866 break;
1867 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1868 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1869 " disabled adapter %d channel %d\n",
1870 pMvSataAdapter->adapterId, channel);
1871 mvSataEnableChannelDma(pMvSataAdapter,channel);
1872 pCmd->Result = RETURN_IDE_ERROR;
1873 break;
1874 case MV_QUEUE_COMMAND_RESULT_FULL:
1875 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1876 " Full adapter %d channel %d\n",
1877 pMvSataAdapter->adapterId, channel);
1878 pCmd->Result = RETURN_DEVICE_BUSY;
1879 break;
1880 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1881 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1882 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1883 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1884 pCmd->Result = RETURN_IDE_ERROR;
1885 break;
1886 default:
1887 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1888 " command\n", result);
1889 pCmd->Result = RETURN_IDE_ERROR;
1890 }
1891 if(pPRDTable)
1892 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1893 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1894 }
1895 pDevice->QueueLength++;
1896 return;
1897
1898 case IDE_COMMAND_VERIFY:
1899 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1900 pNoUdmaParams->bufPtr = NULL;
1901 pNoUdmaParams->callBack = CommandCompletionCB;
1902 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1903 pNoUdmaParams->count = 0;
1904 pNoUdmaParams->features = 0;
1905 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1906
1907 pCmd->uScratch.sata_param.cmd_priv = 1;
1908 if (pMvSataChannel->lba48Address == MV_TRUE){
1909 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1910 pNoUdmaParams->isEXT = MV_TRUE;
1911 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1912 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1913 pNoUdmaParams->lbaLow =
1914 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1915 pNoUdmaParams->sectorCount = nSector;
1916 pNoUdmaParams->device = 0x40;
1917 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1918 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1919 goto queue_failed;
1920 }
1921 return;
1922 }
1923 else{
1924 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1925 pNoUdmaParams->isEXT = MV_FALSE;
1926 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1927 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1928 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1929 pNoUdmaParams->sectorCount = 0xff & nSector;
1930 pNoUdmaParams->device = (MV_U8)(0x40 |
1931 ((Lba & 0xf000000) >> 24));
1932 pNoUdmaParams->callBack = CommandCompletionCB;
1933 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1934 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1935 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1936 goto queue_failed;
1937 }
1938 }
1939 break;
1940 default:
1941 pCmd->Result = RETURN_INVALID_REQUEST;
1942 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1943 break;
1944 }
1945}
1946
1947/**********************************************************
1948 *
1949 * Probe the hostadapter.
1950 *
1951 **********************************************************/
1952static int
1953hpt_probe(device_t dev)
1954{
1955 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1956 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1957#ifdef FOR_DEMO
1958 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1959#endif
1960 ))
1961 {
1962 KdPrintI((CONTROLLER_NAME " found\n"));
1963 device_set_desc(dev, CONTROLLER_NAME);
1964 return (BUS_PROBE_DEFAULT);
1965 }
1966 else
1967 return(ENXIO);
1968}
1969
1970/***********************************************************
1971 *
1972 * Auto configuration: attach and init a host adapter.
1973 *
1974 ***********************************************************/
1975static int
1976hpt_attach(device_t dev)
1977{
1978 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1979 int rid;
1980 union ccb *ccb;
1981 struct cam_devq *devq;
1982 struct cam_sim *hpt_vsim;
1983
1984 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1985
1986 pAdapter->hpt_dev = dev;
1987
1988 rid = init_adapter(pAdapter);
1989 if (rid)
1990 return rid;
1991
1992 rid = 0;
1993 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL)
1994 {
1995 hpt_printk(("can't allocate interrupt\n"));
1996 return(ENXIO);
1997 }
1998
1999 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq,
2000 INTR_TYPE_CAM | INTR_MPSAFE,
2001 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr))
2002 {
2003 hpt_printk(("can't set up interrupt\n"));
2004 free(pAdapter, M_DEVBUF);
2005 return(ENXIO);
2006 }
2007
2008
2009 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL)
2010 {
2011 bzero(ccb, sizeof(*ccb));
2012 ccb->ccb_h.pinfo.priority = 1;
2013 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2014 }
2015 else
2016 {
2017 return ENOMEM;
2018 }
2019 /*
2020 * Create the device queue for our SIM(s).
2021 */
2022 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
2023 {
2024 KdPrint(("ENXIO\n"));
2025 return ENOMEM;
2026 }
2027
2028 /*
2029 * Construct our SIM entry
2030 */
2031 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
2032 pAdapter, device_get_unit(pAdapter->hpt_dev),
2033 &pAdapter->lock, 1, 8, devq);
2034 if (hpt_vsim == NULL) {
2035 cam_simq_free(devq);
2036 return ENOMEM;
2037 }
2038
2039 mtx_lock(&pAdapter->lock);
2040 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS)
2041 {
2042 cam_sim_free(hpt_vsim, /*free devq*/ TRUE);
2043 mtx_unlock(&pAdapter->lock);
2044 hpt_vsim = NULL;
2045 return ENXIO;
2046 }
2047
2048 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2049 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
2050 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
2051 {
2052 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2053 cam_sim_free(hpt_vsim, /*free_devq*/TRUE);
2054 mtx_unlock(&pAdapter->lock);
2055 hpt_vsim = NULL;
2056 return ENXIO;
2057 }
2058 mtx_unlock(&pAdapter->lock);
2059
2060 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
2061 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2062 ccb->csa.event_enable = AC_LOST_DEVICE;
2063 ccb->csa.callback = hpt_async;
2064 ccb->csa.callback_arg = hpt_vsim;
2065 xpt_action((union ccb *)ccb);
2066 free(ccb, M_DEVBUF);
2067
2068 if (device_get_unit(dev) == 0) {
2069 /* Start the work thread. XXX */
2070 launch_worker_thread();
2071 }
2072
2073 return 0;
2074}
2075
2076static int
2077hpt_detach(device_t dev)
2078{
2079 return (EBUSY);
2080}
2081
2082
2083/***************************************************************
2084 * The poll function is used to simulate the interrupt when
2085 * the interrupt subsystem is not functioning.
2086 *
2087 ***************************************************************/
2088static void
2089hpt_poll(struct cam_sim *sim)
2090{
2091 IAL_ADAPTER_T *pAdapter;
2092
2093 pAdapter = cam_sim_softc(sim);
2094
2095 hpt_intr_locked((void *)cam_sim_softc(sim));
2096}
2097
2098/****************************************************************
2099 * Name: hpt_intr
2100 * Description: Interrupt handler.
2101 ****************************************************************/
2102static void
2103hpt_intr(void *arg)
2104{
2105 IAL_ADAPTER_T *pAdapter;
2106
2107 pAdapter = arg;
2108 mtx_lock(&pAdapter->lock);
2109 hpt_intr_locked(pAdapter);
2110 mtx_unlock(&pAdapter->lock);
2111}
2112
2113static void
2114hpt_intr_locked(IAL_ADAPTER_T *pAdapter)
2115{
2116
2117 mtx_assert(&pAdapter->lock, MA_OWNED);
2118 /* KdPrintI(("----- Entering Isr() -----\n")); */
2119 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2120 {
2121 _VBUS_INST(&pAdapter->VBus)
2122 CheckPendingCall(_VBUS_P0);
2123 }
2124
2125 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2126}
2127
2128/**********************************************************
2129 * Asynchronous Events
2130 *********************************************************/
2131#if (!defined(UNREFERENCED_PARAMETER))
2132#define UNREFERENCED_PARAMETER(x) (void)(x)
2133#endif
2134
2135static void
2136hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path,
2137 void * arg)
2138{
2139 /* debug XXXX */
2140 panic("Here");
2141 UNREFERENCED_PARAMETER(callback_arg);
2142 UNREFERENCED_PARAMETER(code);
2143 UNREFERENCED_PARAMETER(path);
2144 UNREFERENCED_PARAMETER(arg);
2145
2146}
2147
2148static void
2149FlushAdapter(IAL_ADAPTER_T *pAdapter)
2150{
2151 int i;
2152
2153 hpt_printk(("flush all devices\n"));
2154
2155 /* flush all devices */
2156 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) {
2157 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2158 if(pVDev) fFlushVDev(pVDev);
2159 }
2160}
2161
2162static int
2163hpt_shutdown(device_t dev)
2164{
2165 IAL_ADAPTER_T *pAdapter;
2166
2167 pAdapter = device_get_softc(dev);
2168
2169 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh);
2170 mtx_lock(&pAdapter->lock);
2171 FlushAdapter(pAdapter);
2172 mtx_unlock(&pAdapter->lock);
2173 /* give the flush some time to happen,
2174 *otherwise "shutdown -p now" will make file system corrupted */
2175 DELAY(1000 * 1000 * 5);
2176 return 0;
2177}
2178
2179void
2180Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2181{
2182 _VBUS_INST(&pAdapter->VBus)
2183
2184 if (mWaitingForIdle(_VBUS_P0)) {
2185 CheckIdleCall(_VBUS_P0);
2186#ifdef SUPPORT_ARRAY
2187 {
2188 int i;
2189 PVDevice pArray;
2190 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){
2191 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2192 continue;
2193 else if (pArray->u.array.rf_auto_rebuild) {
2194 KdPrint(("auto rebuild.\n"));
2195 pArray->u.array.rf_auto_rebuild = 0;
2196 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2197 }
2198 }
2199 }
2200#endif
2201 }
2202 /* launch the awaiting commands blocked by mWaitingForIdle */
2203 while(pAdapter->pending_Q!= NULL)
2204 {
2205 _VBUS_INST(&pAdapter->VBus)
2206 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2207 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2208 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2209 }
2210}
2211
2212static void
2213ccb_done(union ccb *ccb)
2214{
2215 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2216 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2217 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2218
2219 dmamap_put(pmap);
2220 xpt_done(ccb);
2221
2222 pAdapter->outstandingCommands--;
2223
2224 if (pAdapter->outstandingCommands == 0)
2225 {
2226 if(DPC_Request_Nums == 0)
2227 Check_Idle_Call(pAdapter);
2228 wakeup(pAdapter);
2229 }
2230}
2231
2232/****************************************************************
2233 * Name: hpt_action
2234 * Description: Process a queued command from the CAM layer.
2235 * Parameters: sim - Pointer to SIM object
2236 * ccb - Pointer to SCSI command structure.
2237 ****************************************************************/
2238
2239void
2240hpt_action(struct cam_sim *sim, union ccb *ccb)
2241{
2242 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2243 PBUS_DMAMAP pmap;
2244 _VBUS_INST(&pAdapter->VBus)
2245
2246 mtx_assert(&pAdapter->lock, MA_OWNED);
2247 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2248 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2249
2250 switch (ccb->ccb_h.func_code)
2251 {
2252 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2253 {
2254 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2255
2256 if (ccb->ccb_h.target_lun) {
2257 ccb->ccb_h.status = CAM_LUN_INVALID;
2258 xpt_done(ccb);
2259 return;
2260 }
2261 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2262 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2263 ccb->ccb_h.status = CAM_TID_INVALID;
2264 xpt_done(ccb);
2265 return;
2266 }
2267
2268 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2269 Check_Idle_Call(pAdapter);
2270
2271 pmap = dmamap_get(pAdapter);
2272 HPT_ASSERT(pmap);
2273 ccb->ccb_adapter = pmap;
2274 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2275
2276 if (mWaitingForIdle(_VBUS_P0))
2277 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2278 else
2279 OsSendCommand(_VBUS_P ccb);
2280
2281 /* KdPrint(("leave scsiio\n")); */
2282 break;
2283 }
2284
2285 case XPT_RESET_BUS:
2286 KdPrint(("reset bus\n"));
2287 fResetVBus(_VBUS_P0);
2288 xpt_done(ccb);
2289 break;
2290
2291 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2292 case XPT_EN_LUN: /* Enable LUN as a target */
2293 case XPT_TARGET_IO: /* Execute target I/O request */
2294 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2295 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2296 case XPT_ABORT: /* Abort the specified CCB */
2297 case XPT_TERM_IO: /* Terminate the I/O process */
2298 /* XXX Implement */
2299 ccb->ccb_h.status = CAM_REQ_INVALID;
2300 xpt_done(ccb);
2301 break;
2302
2303 case XPT_GET_TRAN_SETTINGS:
2304 case XPT_SET_TRAN_SETTINGS:
2305 /* XXX Implement */
2306 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2307 xpt_done(ccb);
2308 break;
2309
2310 case XPT_CALC_GEOMETRY:
2311 cam_calc_geometry(&ccb->ccg, 1);
2312 xpt_done(ccb);
2313 break;
2314
2315 case XPT_PATH_INQ: /* Path routing inquiry */
2316 {
2317 struct ccb_pathinq *cpi = &ccb->cpi;
2318
2319 cpi->version_num = 1; /* XXX??? */
2320 cpi->hba_inquiry = PI_SDTR_ABLE;
2321 cpi->target_sprt = 0;
2322 /* Not necessary to reset bus */
2323 cpi->hba_misc = PIM_NOBUSRESET;
2324 cpi->hba_eng_cnt = 0;
2325
2326 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2327 cpi->max_lun = 0;
2328 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2329
2330 cpi->bus_id = cam_sim_bus(sim);
2331 cpi->base_transfer_speed = 3300;
2332 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2333 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2334 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2335 cpi->unit_number = cam_sim_unit(sim);
2336 cpi->transport = XPORT_SPI;
2337 cpi->transport_version = 2;
2338 cpi->protocol = PROTO_SCSI;
2339 cpi->protocol_version = SCSI_REV_2;
2340 cpi->ccb_h.status = CAM_REQ_CMP;
2341 xpt_done(ccb);
2342 break;
2343 }
2344
2345 default:
2346 KdPrint(("invalid cmd\n"));
2347 ccb->ccb_h.status = CAM_REQ_INVALID;
2348 xpt_done(ccb);
2349 break;
2350 }
2351 /* KdPrint(("leave hpt_action..............\n")); */
2352}
2353
2354/* shall be called at lock_driver() */
2355static void
2356hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2357{
2358 if(*ccb_Q == NULL)
2359 ccb->ccb_h.ccb_ccb_ptr = ccb;
2360 else {
2361 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr;
2362 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb;
2363 }
2364
2365 *ccb_Q = ccb;
2366}
2367
2368/* shall be called at lock_driver() */
2369static void
2370hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2371{
2372 union ccb *TempCCB;
2373
2374 TempCCB = *ccb_Q;
2375
2376 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2377 *ccb_Q = NULL;
2378 else {
2379 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2380 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2381
2382 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2383
2384 if(*ccb_Q == ccb)
2385 *ccb_Q = TempCCB;
2386 }
2387}
2388
2389#ifdef SUPPORT_ARRAY
2390/***************************************************************************
2391 * Function: hpt_worker_thread
2392 * Description: Do background rebuilding. Execute in kernel thread context.
2393 * Returns: None
2394 ***************************************************************************/
2395static void hpt_worker_thread(void)
2396{
2397
2398 for(;;) {
2399 mtx_lock(&DpcQueue_Lock);
2400 while (DpcQueue_First!=DpcQueue_Last) {
2401 ST_HPT_DPC p;
2402 p = DpcQueue[DpcQueue_First];
2403 DpcQueue_First++;
2404 DpcQueue_First %= MAX_DPC;
2405 DPC_Request_Nums++;
2406 mtx_unlock(&DpcQueue_Lock);
2407 p.dpc(p.pAdapter, p.arg, p.flags);
2408
2409 mtx_lock(&p.pAdapter->lock);
2410 mtx_lock(&DpcQueue_Lock);
2411 DPC_Request_Nums--;
2412 /* since we may have prevented Check_Idle_Call, do it here */
2413 if (DPC_Request_Nums==0) {
2414 if (p.pAdapter->outstandingCommands == 0) {
2415 _VBUS_INST(&p.pAdapter->VBus);
2416 Check_Idle_Call(p.pAdapter);
2417 CheckPendingCall(_VBUS_P0);
2418 }
2419 }
2420 mtx_unlock(&p.pAdapter->lock);
2421 mtx_unlock(&DpcQueue_Lock);
2422
2423 /*Schedule out*/
2424 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2425 /* abort rebuilding process. */
2426 IAL_ADAPTER_T *pAdapter;
2427 PVDevice pArray;
2428 PVBus _vbus_p;
2429 int i;
2430
2431 sx_slock(&hptmv_list_lock);
2432 pAdapter = gIal_Adapter;
2433
2434 while(pAdapter != 0){
2435 mtx_lock(&pAdapter->lock);
2436 _vbus_p = &pAdapter->VBus;
2437
2438 for (i=0;i<MAX_ARRAY_PER_VBUS;i++)
2439 {
2440 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2441 continue;
2442 else if (pArray->u.array.rf_rebuilding ||
2443 pArray->u.array.rf_verifying ||
2444 pArray->u.array.rf_initializing)
2445 {
2446 pArray->u.array.rf_abort_rebuild = 1;
2447 }
2448 }
2449 mtx_unlock(&pAdapter->lock);
2450 pAdapter = pAdapter->next;
2451 }
2452 sx_sunlock(&hptmv_list_lock);
2453 }
2454 mtx_lock(&DpcQueue_Lock);
2455 }
2456 mtx_unlock(&DpcQueue_Lock);
2457
2458/*Remove this debug option*/
2459/*
2460#ifdef DEBUG
2461 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2462 pause("hptrdy", 2*hz);
2463#endif
2464*/
2465 kproc_suspend_check(curproc);
2466 pause("-", 2*hz); /* wait for something to do */
2467 }
2468}
2469
2470static struct proc *hptdaemonproc;
2471static struct kproc_desc hpt_kp = {
2472 "hpt_wt",
2473 hpt_worker_thread,
2474 &hptdaemonproc
2475};
2476
2477/*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2478static void
2479launch_worker_thread(void)
2480{
2481 IAL_ADAPTER_T *pAdapTemp;
2482
2483 kproc_start(&hpt_kp);
2484
2485 sx_slock(&hptmv_list_lock);
2486 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2487
2488 _VBUS_INST(&pAdapTemp->VBus)
2489 int i;
2490 PVDevice pVDev;
2491
2492 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2493 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2494 continue;
2495 else{
2496 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2497 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2498 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2499 }
2500 }
2501 sx_sunlock(&hptmv_list_lock);
2502
2503 /*
2504 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished.
2505 */
2506 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc,
2507 SHUTDOWN_PRI_LAST);
2508}
2509/*
2510 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2511*/
2512
2513#endif
2514
2515/********************************************************************************/
2516
2517int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2518{
2519 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2520
2521 if (logical) {
2522 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2523 pSg->wSgSize = ccb->csio.dxfer_len;
2524 pSg->wSgFlag = SG_FLAG_EOT;
2525 return TRUE;
2526 }
2527 /* since we have provided physical sg, nobody will ask us to build physical sg */
2528 HPT_ASSERT(0);
2529 return FALSE;
2530}
2531
2532/*******************************************************************************/
2533ULONG HPTLIBAPI
2534GetStamp(void)
2535{
2536 /*
2537 * the system variable, ticks, can't be used since it hasn't yet been active
2538 * when our driver starts (ticks==0, it's a invalid stamp value)
2539 */
2540 ULONG stamp;
2541 do { stamp = random(); } while (stamp==0);
2542 return stamp;
2543}
2544
2545
2546static void
2547SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2548{
2549 int i;
2550 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2551
2552 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2553 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2554#ifndef SERIAL_CMDS
2555 inquiryData->CommandQueue = 1;
2556#endif
2557
2558 switch(pVDev->VDeviceType) {
2559 case VD_SINGLE_DISK:
2560 case VD_ATAPI:
2561 case VD_REMOVABLE:
2562 /* Set the removable bit, if applicable. */
2563 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2564 inquiryData->RemovableMedia = 1;
2565
2566 /* Fill in vendor identification fields. */
2567 for (i = 0; i < 20; i += 2) {
2568 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2569 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2570
2571 }
2572
2573 /* Initialize unused portion of product id. */
2574 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2575
2576 /* firmware revision */
2577 for (i = 0; i < 4; i += 2)
2578 {
2579 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2580 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2581 }
2582 break;
2583 default:
2584 memcpy(&inquiryData->VendorId, "RR18xx ", 8);
2585#ifdef SUPPORT_ARRAY
2586 switch(pVDev->VDeviceType){
2587 case VD_RAID_0:
2588 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2589 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2590 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2591 else
2592 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2593 break;
2594 case VD_RAID_1:
2595 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2596 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2597 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2598 else
2599 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2600 break;
2601 case VD_RAID_5:
2602 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2603 break;
2604 case VD_JBOD:
2605 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2606 break;
2607 }
2608#endif
2609 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2610 break;
2611 }
2612}
2613
2614static void
2615hpt_timeout(void *arg)
2616{
2617 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter;
2618 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2619 _VBUS_INST(&pAdapter->VBus)
2620
2621 mtx_assert(&pAdapter->lock, MA_OWNED);
2622 fResetVBus(_VBUS_P0);
2623}
2624
2625static void
2626hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2627{
2628 PCommand pCmd = (PCommand)arg;
2629 union ccb *ccb = pCmd->pOrgCommand;
2630 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2631 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2632 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2633 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2634 FPSCAT_GATH psg = pCmd->pSgTable;
2635 int idx;
2636 _VBUS_INST(pVDev->pVBus)
2637
2638 HPT_ASSERT(pCmd->cf_physical_sg);
2639
2640 if (error)
2641 panic("busdma error");
2642
2643 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2644
2645 if (nsegs != 0) {
2646 for (idx = 0; idx < nsegs; idx++, psg++) {
2647 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2648 psg->wSgSize = segs[idx].ds_len;
2649 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2650 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2651 }
2652 /* psg[-1].wSgFlag = SG_FLAG_EOT; */
2653
2654 if (pCmd->cf_data_in) {
2655 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2656 BUS_DMASYNC_PREREAD);
2657 }
2658 else if (pCmd->cf_data_out) {
2659 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2660 BUS_DMASYNC_PREWRITE);
2661 }
2662 }
2663
2664 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb);
2665 pVDev->pfnSendCommand(_VBUS_P pCmd);
2666 CheckPendingCall(_VBUS_P0);
2667}
2668
2669
2670
2671static void HPTLIBAPI
2672OsSendCommand(_VBUS_ARG union ccb *ccb)
2673{
2674 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2675 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2676 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2677 struct ccb_scsiio *csio = &ccb->csio;
2678 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2679
2680 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2681 ccb,
2682 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2683 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2684 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2685 ));
2686
2687 pAdapter->outstandingCommands++;
2688
2689 if (pVDev == NULL || pVDev->vf_online == 0) {
2690 ccb->ccb_h.status = CAM_REQ_INVALID;
2691 ccb_done(ccb);
2692 goto Command_Complished;
2693 }
2694
2695 switch(ccb->csio.cdb_io.cdb_bytes[0])
2696 {
2697 case TEST_UNIT_READY:
2698 case START_STOP_UNIT:
2699 case SYNCHRONIZE_CACHE:
2700 /* FALLTHROUGH */
2701 ccb->ccb_h.status = CAM_REQ_CMP;
2702 break;
2703
2704 case INQUIRY:
2705 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2706 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2707 ccb_h->status = CAM_REQ_CMP;
2708 break;
2709
2710 case READ_CAPACITY:
2711 {
2712 UCHAR *rbuf=csio->data_ptr;
2713 unsigned int cap;
2714
2715 if (pVDev->VDeviceCapacity > 0xfffffffful) {
2716 cap = 0xfffffffful;
2717 } else {
2718 cap = pVDev->VDeviceCapacity - 1;
2719 }
2720
2721 rbuf[0] = (UCHAR)(cap>>24);
2722 rbuf[1] = (UCHAR)(cap>>16);
2723 rbuf[2] = (UCHAR)(cap>>8);
2724 rbuf[3] = (UCHAR)cap;
2725 /* Claim 512 byte blocks (big-endian). */
2726 rbuf[4] = 0;
2727 rbuf[5] = 0;
2728 rbuf[6] = 2;
2729 rbuf[7] = 0;
2730
2731 ccb_h->status = CAM_REQ_CMP;
2732 break;
2733 }
2734
2735 case 0x9e: /*SERVICE_ACTION_IN*/
2736 {
2737 UCHAR *rbuf = csio->data_ptr;
2738 LBA_T cap = pVDev->VDeviceCapacity - 1;
2739
2740 rbuf[0] = (UCHAR)(cap>>56);
2741 rbuf[1] = (UCHAR)(cap>>48);
2742 rbuf[2] = (UCHAR)(cap>>40);
2743 rbuf[3] = (UCHAR)(cap>>32);
2744 rbuf[4] = (UCHAR)(cap>>24);
2745 rbuf[5] = (UCHAR)(cap>>16);
2746 rbuf[6] = (UCHAR)(cap>>8);
2747 rbuf[7] = (UCHAR)cap;
2748 rbuf[8] = 0;
2749 rbuf[9] = 0;
2750 rbuf[10] = 2;
2751 rbuf[11] = 0;
2752
2753 ccb_h->status = CAM_REQ_CMP;
2754 break;
2755 }
2756
2757 case READ_6:
2758 case WRITE_6:
2759 case READ_10:
2760 case WRITE_10:
2761 case 0x88: /* READ_16 */
2762 case 0x8a: /* WRITE_16 */
2763 case 0x13:
2764 case 0x2f:
2765 {
2766 UCHAR Cdb[16];
2767 UCHAR CdbLength;
2768 _VBUS_INST(pVDev->pVBus)
2769 PCommand pCmd = AllocateCommand(_VBUS_P0);
2770 int error;
2771 HPT_ASSERT(pCmd);
2772
2773 CdbLength = csio->cdb_len;
2774 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2775 {
2776 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2777 {
2778 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2779 }
2780 else
2781 {
2782 KdPrintE(("ERROR!!!\n"));
2783 ccb->ccb_h.status = CAM_REQ_INVALID;
2784 break;
2785 }
2786 }
2787 else
2788 {
2789 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2790 }
2791
2792 pCmd->pOrgCommand = ccb;
2793 pCmd->pVDevice = pVDev;
2794 pCmd->pfnCompletion = fOsCommandDone;
2795 pCmd->pfnBuildSgl = fOsBuildSgl;
2796 pCmd->pSgTable = pmap->psg;
2797
2798 switch (Cdb[0])
2799 {
2800 case READ_6:
2801 case WRITE_6:
2802 case 0x13:
2803 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2804 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2805 break;
2806
2807 case 0x88: /* READ_16 */
2808 case 0x8a: /* WRITE_16 */
2809 pCmd->uCmd.Ide.Lba =
2810 (HPT_U64)Cdb[2] << 56 |
2811 (HPT_U64)Cdb[3] << 48 |
2812 (HPT_U64)Cdb[4] << 40 |
2813 (HPT_U64)Cdb[5] << 32 |
2814 (HPT_U64)Cdb[6] << 24 |
2815 (HPT_U64)Cdb[7] << 16 |
2816 (HPT_U64)Cdb[8] << 8 |
2817 (HPT_U64)Cdb[9];
2818 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13];
2819 break;
2820
2821 default:
2822 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2823 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2824 break;
2825 }
2826
2827 switch (Cdb[0])
2828 {
2829 case READ_6:
2830 case READ_10:
2831 case 0x88: /* READ_16 */
2832 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2833 pCmd->cf_data_in = 1;
2834 break;
2835
2836 case WRITE_6:
2837 case WRITE_10:
2838 case 0x8a: /* WRITE_16 */
2839 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2840 pCmd->cf_data_out = 1;
2841 break;
2842 case 0x13:
2843 case 0x2f:
2844 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2845 break;
2846 }
2847/*///////////////////////// */
2848 pCmd->cf_physical_sg = 1;
2849 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent,
2850 pmap->dma_map,
2851 ccb,
2852 hpt_io_dmamap_callback,
2853 pCmd, BUS_DMA_WAITOK
2854 );
2855 KdPrint(("bus_dmamap_load return %d\n", error));
2856 if (error && error!=EINPROGRESS) {
2857 hpt_printk(("bus_dmamap_load error %d\n", error));
2858 FreeCommand(_VBUS_P pCmd);
2859 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2860 dmamap_put(pmap);
2861 pAdapter->outstandingCommands--;
2862 if (pAdapter->outstandingCommands == 0)
2863 wakeup(pAdapter);
2864 xpt_done(ccb);
2865 }
2866 goto Command_Complished;
2867 }
2868
2869 default:
2870 ccb->ccb_h.status = CAM_REQ_INVALID;
2871 break;
2872 }
2873 ccb_done(ccb);
2874Command_Complished:
2875 CheckPendingCall(_VBUS_P0);
2876 return;
2877}
2878
2879static void HPTLIBAPI
2880fOsCommandDone(_VBUS_ARG PCommand pCmd)
2881{
2882 union ccb *ccb = pCmd->pOrgCommand;
2883 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2884 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2885
2886 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2887
2888 callout_stop(&pmap->timeout);
2889
2890 switch(pCmd->Result) {
2891 case RETURN_SUCCESS:
2892 ccb->ccb_h.status = CAM_REQ_CMP;
2893 break;
2894 case RETURN_BAD_DEVICE:
2895 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
2896 break;
2897 case RETURN_DEVICE_BUSY:
2898 ccb->ccb_h.status = CAM_BUSY;
2899 break;
2900 case RETURN_INVALID_REQUEST:
2901 ccb->ccb_h.status = CAM_REQ_INVALID;
2902 break;
2903 case RETURN_SELECTION_TIMEOUT:
2904 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2905 break;
2906 case RETURN_RETRY:
2907 ccb->ccb_h.status = CAM_BUSY;
2908 break;
2909 default:
2910 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2911 break;
2912 }
2913
2914 if (pCmd->cf_data_in) {
2915 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2916 }
2917 else if (pCmd->cf_data_out) {
2918 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2919 }
2920
2921 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2922
2923 FreeCommand(_VBUS_P pCmd);
2924 ccb_done(ccb);
2925}
2926
2927int
2928hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2929{
2930 int p;
2931
2932 mtx_lock(&DpcQueue_Lock);
2933 p = (DpcQueue_Last + 1) % MAX_DPC;
2934 if (p==DpcQueue_First) {
2935 KdPrint(("DPC Queue full!\n"));
2936 mtx_unlock(&DpcQueue_Lock);
2937 return -1;
2938 }
2939
2940 DpcQueue[DpcQueue_Last].dpc = dpc;
2941 DpcQueue[DpcQueue_Last].pAdapter = pAdapter;
2942 DpcQueue[DpcQueue_Last].arg = arg;
2943 DpcQueue[DpcQueue_Last].flags = flags;
2944 DpcQueue_Last = p;
2945 mtx_unlock(&DpcQueue_Lock);
2946
2947 return 0;
2948}
2949
2950#ifdef _RAID5N_
2951/*
2952 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2953 * How about the memory for 5081 request/response array and PRD table?
2954 */
2955void
2956*os_alloc_page(_VBUS_ARG0)
2957{
2958 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2959}
2960
2961void
2962*os_alloc_dma_page(_VBUS_ARG0)
2963{
2964 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2965}
2966
2967void
2968os_free_page(_VBUS_ARG void *p)
2969{
2970 contigfree(p, 0x1000, M_DEVBUF);
2971}
2972
2973void
2974os_free_dma_page(_VBUS_ARG void *p)
2975{
2976 contigfree(p, 0x1000, M_DEVBUF);
2977}
2978
2979void
2980DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
2981{
2982 UINT i;
2983 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
2984}
2985
2986void
2987DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
2988{
2989 UINT i;
2990 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
2991}
2992#endif
| 1309 ||
1310 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1311 {
1312 MV_ERROR("RR18xx: Failed to remap memory space\n");
1313 hptmv_free_edma_queues(pAdapter);
1314 return ENXIO;
1315 }
1316 else
1317 {
1318 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1319 }
1320
1321 pMvSataAdapter->adapterId = num_adapters++;
1322 /* get the revision ID */
1323 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1324 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1325
1326 /* init RR18xx */
1327 pMvSataAdapter->intCoalThre[0]= 1;
1328 pMvSataAdapter->intCoalThre[1]= 1;
1329 pMvSataAdapter->intTimeThre[0] = 1;
1330 pMvSataAdapter->intTimeThre[1] = 1;
1331 pMvSataAdapter->pciCommand = 0x0107E371;
1332 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1333 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1334 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1335
1336 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1337 {
1338 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n",
1339 pMvSataAdapter->adapterId);
1340unregister:
1341 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1342 hptmv_free_edma_queues(pAdapter);
1343 return ENXIO;
1344 }
1345 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1346
1347#ifndef FOR_DEMO
1348 set_fail_leds(pMvSataAdapter, 0);
1349#endif
1350
1351 /* setup command blocks */
1352 KdPrint(("Allocate command blocks\n"));
1353 _vbus_(pFreeCommands) = 0;
1354 pAdapter->pCommandBlocks =
1355 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1356 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1357 if (!pAdapter->pCommandBlocks) {
1358 MV_ERROR("insufficient memory\n");
1359 goto unregister;
1360 }
1361
1362 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1363 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1364 }
1365
1366 /*Set up the bus_dmamap*/
1367 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1368 if(!pAdapter->pbus_dmamap) {
1369 MV_ERROR("insufficient memory\n");
1370 free(pAdapter->pCommandBlocks, M_DEVBUF);
1371 goto unregister;
1372 }
1373
1374 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1375 pAdapter->pbus_dmamap_list = 0;
1376 for (i=0; i < MAX_QUEUE_COMM; i++) {
1377 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1378 pmap->pAdapter = pAdapter;
1379 dmamap_put(pmap);
1380
1381 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1382 MV_ERROR("Can not allocate dma map\n");
1383 free(pAdapter->pCommandBlocks, M_DEVBUF);
1384 free(pAdapter->pbus_dmamap, M_DEVBUF);
1385 goto unregister;
1386 }
1387 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0);
1388 }
1389 /* setup PRD Tables */
1390 KdPrint(("Allocate PRD Tables\n"));
1391 pAdapter->pFreePRDLink = 0;
1392
1393 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1394 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1395
1396 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1397 if (!pAdapter->prdTableAddr) {
1398 MV_ERROR("insufficient PRD Tables\n");
1399 goto unregister;
1400 }
1401 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1402 {
1403 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1404 for (i=0; i<PRD_TABLES_FOR_VBUS; i++)
1405 {
1406/* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1407 FreePRDTable(pAdapter, PRDTable);
1408 PRDTable += PRD_ENTRIES_SIZE;
1409 }
1410 }
1411
1412 /* enable the adapter interrupts */
1413
1414 /* configure and start the connected channels*/
1415 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1416 {
1417 pAdapter->mvChannel[channel].online = MV_FALSE;
1418 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1419 == MV_TRUE)
1420 {
1421 KdPrint(("RR18xx[%d]: channel %d is connected\n",
1422 pMvSataAdapter->adapterId, channel));
1423
1424 if (hptmv_init_channel(pAdapter, channel) == 0)
1425 {
1426 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1427 {
1428 MV_ERROR("RR18xx[%d]: Failed to configure channel"
1429 " %d\n",pMvSataAdapter->adapterId, channel);
1430 hptmv_free_channel(pAdapter, channel);
1431 }
1432 else
1433 {
1434 if (start_channel(pAdapter, channel))
1435 {
1436 MV_ERROR("RR18xx[%d]: Failed to start channel,"
1437 " channel=%d\n",pMvSataAdapter->adapterId,
1438 channel);
1439 hptmv_free_channel(pAdapter, channel);
1440 }
1441 pAdapter->mvChannel[channel].online = MV_TRUE;
1442 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1443 channel,
1444 MV_TRUE);*/
1445 }
1446 }
1447 }
1448 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1449 pAdapter->mvChannel[channel].online, channel));
1450 }
1451
1452#ifdef SUPPORT_ARRAY
1453 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1454 pVDev = ArrayTables(i);
1455 mArFreeArrayTable(pVDev);
1456 }
1457#endif
1458
1459 KdPrint(("Initialize Devices\n"));
1460 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1461 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1462 if (pMvSataChannel) {
1463 init_vdev_params(pAdapter, channel);
1464 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1465 }
1466 }
1467#ifdef SUPPORT_ARRAY
1468 CheckArrayCritical(_VBUS_P0);
1469#endif
1470 _vbus_p->nInstances = 1;
1471 fRegisterVdevice(pAdapter);
1472
1473 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) {
1474 pVDev = _vbus_p->pVDevice[channel];
1475 if (pVDev && pVDev->vf_online)
1476 fCheckBootable(pVDev);
1477 }
1478
1479#if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1480 init_raid5_memory(_VBUS_P0);
1481 _vbus_(r5).enable_write_back = 1;
1482 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1483#endif
1484
1485 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1486 return 0;
1487}
1488
1489int
1490MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1491{
1492 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1493
1494 mvSataDisableChannelDma(pMvSataAdapter, channel);
1495 /* Flush pending commands */
1496 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1497
1498 /* Software reset channel */
1499 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1500 {
1501 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
1502 pMvSataAdapter->adapterId, channel);
1503 hptmv_free_channel(pAdapter, channel);
1504 return -1;
1505 }
1506
1507 /* Hardware reset channel */
1508 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1509 {
1510 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n",
1511 pMvSataAdapter->adapterId, channel);
1512 hptmv_free_channel(pAdapter, channel);
1513 return -1;
1514 }
1515
1516 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1517 {
1518 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n",
1519 pMvSataAdapter->adapterId, channel);
1520 hptmv_free_channel(pAdapter, channel);
1521 return -1;
1522 }else
1523 {
1524 MV_ERROR("channel %d: perform recalibrate command", channel);
1525 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1526 MV_NON_UDMA_PROTOCOL_NON_DATA,
1527 MV_FALSE,
1528 NULL, /* pBuffer*/
1529 0, /* count */
1530 0, /*features*/
1531 /* sectorCount */
1532 0,
1533 0, /* lbaLow */
1534 0, /* lbaMid */
1535 /* lbaHigh */
1536 0,
1537 0, /* device */
1538 /* command */
1539 0x10))
1540 MV_ERROR("channel %d: recalibrate failed", channel);
1541
1542 /* Set transfer mode */
1543 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1544 MV_ATA_SET_FEATURES_TRANSFER,
1545 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1546 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1547 MV_ATA_SET_FEATURES_TRANSFER,
1548 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1549 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1550 MV_ATA_SET_FEATURES_TRANSFER,
1551 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1552 {
1553 MV_ERROR("channel %d: Set Features failed", channel);
1554 hptmv_free_channel(pAdapter, channel);
1555 return -1;
1556 }
1557 /* Enable EDMA */
1558 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1559 {
1560 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1561 hptmv_free_channel(pAdapter, channel);
1562 return -1;
1563 }
1564 }
1565 return 0;
1566}
1567
1568static int
1569fResetActiveCommands(PVBus _vbus_p)
1570{
1571 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1572 MV_U8 channel;
1573 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1574 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1575 MvSataResetChannel(pMvSataAdapter,channel);
1576 }
1577 return 0;
1578}
1579
1580void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1581{
1582 UINT cont;
1583 ULONG ticks = 0;
1584 MV_U8 channel;
1585 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1586 MV_SATA_CHANNEL *pMvSataChannel;
1587
1588 do {
1589check_cmds:
1590 cont = 0;
1591 CheckPendingCall(_VBUS_P0);
1592#ifdef _RAID5N_
1593 dataxfer_poll();
1594 xor_poll();
1595#endif
1596 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1597 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1598 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1599 {
1600 while (pMvSataChannel->outstandingCommands) {
1601 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1602 StallExec(1000);
1603 if (ticks++ > 3000) {
1604 MvSataResetChannel(pMvSataAdapter,channel);
1605 goto check_cmds;
1606 }
1607 }
1608 else
1609 ticks = 0;
1610 }
1611 cont = 1;
1612 }
1613 }
1614 } while (cont);
1615}
1616
1617void
1618fResetVBus(_VBUS_ARG0)
1619{
1620 KdPrint(("fMvResetBus(%p)", _vbus_p));
1621
1622 /* some commands may already finished. */
1623 CheckPendingCall(_VBUS_P0);
1624
1625 fResetActiveCommands(_vbus_p);
1626 /*
1627 * the other pending commands may still be finished successfully.
1628 */
1629 fCompleteAllCommandsSynchronously(_vbus_p);
1630
1631 /* Now there should be no pending commands. No more action needed. */
1632 CheckIdleCall(_VBUS_P0);
1633
1634 KdPrint(("fMvResetBus() done"));
1635}
1636
1637/*No rescan function*/
1638void
1639fRescanAllDevice(_VBUS_ARG0)
1640{
1641}
1642
1643static MV_BOOLEAN
1644CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1645 MV_U8 channelNum,
1646 MV_COMPLETION_TYPE comp_type,
1647 MV_VOID_PTR commandId,
1648 MV_U16 responseFlags,
1649 MV_U32 timeStamp,
1650 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1651{
1652 PCommand pCmd = (PCommand) commandId;
1653 _VBUS_INST(pCmd->pVDevice->pVBus)
1654
1655 if (pCmd->uScratch.sata_param.prdAddr)
1656 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1657
1658 switch (comp_type)
1659 {
1660 case MV_COMPLETION_TYPE_NORMAL:
1661 pCmd->Result = RETURN_SUCCESS;
1662 break;
1663 case MV_COMPLETION_TYPE_ABORT:
1664 pCmd->Result = RETURN_BUS_RESET;
1665 break;
1666 case MV_COMPLETION_TYPE_ERROR:
1667 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1668 pMvSataAdapter->adapterId, channelNum, responseFlags);
1669
1670 if (responseFlags & 4) {
1671 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1672 " LBA high %x, device %x, status %x\n",
1673 registerStruct->errorRegister,
1674 registerStruct->sectorCountRegister,
1675 registerStruct->lbaLowRegister,
1676 registerStruct->lbaMidRegister,
1677 registerStruct->lbaHighRegister,
1678 registerStruct->deviceRegister,
1679 registerStruct->statusRegister);
1680 }
1681 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1682 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1683 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1684 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1685 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1686 pCmd->pVDevice->u.disk.QueueLength--;
1687 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1688 return TRUE;
1689
1690 default:
1691 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1692 return MV_FALSE;
1693 }
1694
1695 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1696 pCmd->uScratch.sata_param.cmd_priv --;
1697 return TRUE;
1698 }
1699 pCmd->pVDevice->u.disk.QueueLength--;
1700 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1701 return TRUE;
1702}
1703
1704void
1705fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1706{
1707 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1708 MV_SATA_ADAPTER *pMvSataAdapter;
1709 MV_SATA_CHANNEL *pMvSataChannel;
1710 PVDevice pVDevice = pCmd->pVDevice;
1711 PDevice pDevice = &pVDevice->u.disk;
1712 LBA_T Lba = pCmd->uCmd.Ide.Lba;
1713 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1714
1715 MV_QUEUE_COMMAND_RESULT result;
1716 MV_QUEUE_COMMAND_INFO commandInfo;
1717 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1718 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1719
1720 MV_BOOLEAN is48bit;
1721 MV_U8 channel;
1722 int i=0;
1723
1724 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1725
1726 if (!pDevice->df_on_line) {
1727 MV_ERROR("Device is offline");
1728 pCmd->Result = RETURN_BAD_DEVICE;
1729 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1730 return;
1731 }
1732
1733 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1734 pMvSataChannel = pDevice->mv;
1735 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1736 channel = pMvSataChannel->channelNumber;
1737
1738 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1739 Lba += pDevice->dDeHiddenLba;
1740 /* check LBA */
1741 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1742 pCmd->Result = RETURN_INVALID_REQUEST;
1743 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1744 return;
1745 }
1746
1747 /*
1748 * always use 48bit LBA if drive supports it.
1749 * Some Seagate drives report error if you use a 28-bit command
1750 * to access sector 0xfffffff.
1751 */
1752 is48bit = pMvSataChannel->lba48Address;
1753
1754 switch (pCmd->uCmd.Ide.Command)
1755 {
1756 case IDE_COMMAND_READ:
1757 case IDE_COMMAND_WRITE:
1758 if (pDevice->bDeModeSetting<8) goto pio;
1759
1760 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1761 pUdmaParams->isEXT = is48bit;
1762 pUdmaParams->numOfSectors = nSector;
1763 pUdmaParams->lowLBAAddress = Lba;
1764 pUdmaParams->highLBAAddress = 0;
1765 pUdmaParams->prdHighAddr = 0;
1766 pUdmaParams->callBack = CommandCompletionCB;
1767 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1768 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1769 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1770 else
1771 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1772
1773 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1774 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1775 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1776 }
1777 else {
1778 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1779pio:
1780 mvSataDisableChannelDma(pMvSataAdapter, channel);
1781 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1782
1783 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1784 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1785 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1786 }
1787 else {
1788 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1789 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1790 goto finish_cmd;
1791 }
1792 }
1793
1794 do {
1795 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1796 ULONG_PTR addr = tmpSg->dSgAddress;
1797 if (size & 0x1ff) {
1798 pCmd->Result = RETURN_INVALID_REQUEST;
1799 goto finish_cmd;
1800 }
1801 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1802 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1803 is48bit,
1804 (MV_U16_PTR)addr,
1805 size >> 1, /* count */
1806 0, /* features N/A */
1807 (MV_U16)(size>>9), /*sector count*/
1808 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1809 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1810 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1811 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1812 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1813 )==MV_FALSE)
1814 {
1815 pCmd->Result = RETURN_IDE_ERROR;
1816 goto finish_cmd;
1817 }
1818 Lba += size>>9;
1819 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1820 }
1821 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1822 pCmd->Result = RETURN_SUCCESS;
1823finish_cmd:
1824 mvSataEnableChannelDma(pMvSataAdapter,channel);
1825 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1826 return;
1827 }
1828 }
1829
1830 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1831 KdPrint(("pPRDTable:%p\n",pPRDTable));
1832 if (!pPRDTable) {
1833 pCmd->Result = RETURN_DEVICE_BUSY;
1834 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1835 HPT_ASSERT(0);
1836 return;
1837 }
1838
1839 do{
1840 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1841 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1842 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1843 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1844 pPRDTable[i].reserved = 0;
1845 i++;
1846 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1847
1848 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1849 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1850 pUdmaParams->numOfSectors = 0;
1851 }
1852
1853 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1854
1855 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1856
1857 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1858 {
1859queue_failed:
1860 switch (result)
1861 {
1862 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1863 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1864 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1865 pCmd->Result = RETURN_IDE_ERROR;
1866 break;
1867 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1868 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1869 " disabled adapter %d channel %d\n",
1870 pMvSataAdapter->adapterId, channel);
1871 mvSataEnableChannelDma(pMvSataAdapter,channel);
1872 pCmd->Result = RETURN_IDE_ERROR;
1873 break;
1874 case MV_QUEUE_COMMAND_RESULT_FULL:
1875 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1876 " Full adapter %d channel %d\n",
1877 pMvSataAdapter->adapterId, channel);
1878 pCmd->Result = RETURN_DEVICE_BUSY;
1879 break;
1880 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1881 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1882 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1883 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1884 pCmd->Result = RETURN_IDE_ERROR;
1885 break;
1886 default:
1887 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1888 " command\n", result);
1889 pCmd->Result = RETURN_IDE_ERROR;
1890 }
1891 if(pPRDTable)
1892 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1893 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1894 }
1895 pDevice->QueueLength++;
1896 return;
1897
1898 case IDE_COMMAND_VERIFY:
1899 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1900 pNoUdmaParams->bufPtr = NULL;
1901 pNoUdmaParams->callBack = CommandCompletionCB;
1902 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1903 pNoUdmaParams->count = 0;
1904 pNoUdmaParams->features = 0;
1905 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1906
1907 pCmd->uScratch.sata_param.cmd_priv = 1;
1908 if (pMvSataChannel->lba48Address == MV_TRUE){
1909 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1910 pNoUdmaParams->isEXT = MV_TRUE;
1911 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1912 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1913 pNoUdmaParams->lbaLow =
1914 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1915 pNoUdmaParams->sectorCount = nSector;
1916 pNoUdmaParams->device = 0x40;
1917 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1918 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1919 goto queue_failed;
1920 }
1921 return;
1922 }
1923 else{
1924 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1925 pNoUdmaParams->isEXT = MV_FALSE;
1926 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1927 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1928 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1929 pNoUdmaParams->sectorCount = 0xff & nSector;
1930 pNoUdmaParams->device = (MV_U8)(0x40 |
1931 ((Lba & 0xf000000) >> 24));
1932 pNoUdmaParams->callBack = CommandCompletionCB;
1933 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1934 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1935 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1936 goto queue_failed;
1937 }
1938 }
1939 break;
1940 default:
1941 pCmd->Result = RETURN_INVALID_REQUEST;
1942 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1943 break;
1944 }
1945}
1946
1947/**********************************************************
1948 *
1949 * Probe the hostadapter.
1950 *
1951 **********************************************************/
1952static int
1953hpt_probe(device_t dev)
1954{
1955 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1956 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1957#ifdef FOR_DEMO
1958 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1959#endif
1960 ))
1961 {
1962 KdPrintI((CONTROLLER_NAME " found\n"));
1963 device_set_desc(dev, CONTROLLER_NAME);
1964 return (BUS_PROBE_DEFAULT);
1965 }
1966 else
1967 return(ENXIO);
1968}
1969
1970/***********************************************************
1971 *
1972 * Auto configuration: attach and init a host adapter.
1973 *
1974 ***********************************************************/
1975static int
1976hpt_attach(device_t dev)
1977{
1978 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1979 int rid;
1980 union ccb *ccb;
1981 struct cam_devq *devq;
1982 struct cam_sim *hpt_vsim;
1983
1984 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1985
1986 pAdapter->hpt_dev = dev;
1987
1988 rid = init_adapter(pAdapter);
1989 if (rid)
1990 return rid;
1991
1992 rid = 0;
1993 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL)
1994 {
1995 hpt_printk(("can't allocate interrupt\n"));
1996 return(ENXIO);
1997 }
1998
1999 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq,
2000 INTR_TYPE_CAM | INTR_MPSAFE,
2001 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr))
2002 {
2003 hpt_printk(("can't set up interrupt\n"));
2004 free(pAdapter, M_DEVBUF);
2005 return(ENXIO);
2006 }
2007
2008
2009 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL)
2010 {
2011 bzero(ccb, sizeof(*ccb));
2012 ccb->ccb_h.pinfo.priority = 1;
2013 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2014 }
2015 else
2016 {
2017 return ENOMEM;
2018 }
2019 /*
2020 * Create the device queue for our SIM(s).
2021 */
2022 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
2023 {
2024 KdPrint(("ENXIO\n"));
2025 return ENOMEM;
2026 }
2027
2028 /*
2029 * Construct our SIM entry
2030 */
2031 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
2032 pAdapter, device_get_unit(pAdapter->hpt_dev),
2033 &pAdapter->lock, 1, 8, devq);
2034 if (hpt_vsim == NULL) {
2035 cam_simq_free(devq);
2036 return ENOMEM;
2037 }
2038
2039 mtx_lock(&pAdapter->lock);
2040 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS)
2041 {
2042 cam_sim_free(hpt_vsim, /*free devq*/ TRUE);
2043 mtx_unlock(&pAdapter->lock);
2044 hpt_vsim = NULL;
2045 return ENXIO;
2046 }
2047
2048 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2049 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
2050 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
2051 {
2052 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2053 cam_sim_free(hpt_vsim, /*free_devq*/TRUE);
2054 mtx_unlock(&pAdapter->lock);
2055 hpt_vsim = NULL;
2056 return ENXIO;
2057 }
2058 mtx_unlock(&pAdapter->lock);
2059
2060 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
2061 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2062 ccb->csa.event_enable = AC_LOST_DEVICE;
2063 ccb->csa.callback = hpt_async;
2064 ccb->csa.callback_arg = hpt_vsim;
2065 xpt_action((union ccb *)ccb);
2066 free(ccb, M_DEVBUF);
2067
2068 if (device_get_unit(dev) == 0) {
2069 /* Start the work thread. XXX */
2070 launch_worker_thread();
2071 }
2072
2073 return 0;
2074}
2075
2076static int
2077hpt_detach(device_t dev)
2078{
2079 return (EBUSY);
2080}
2081
2082
2083/***************************************************************
2084 * The poll function is used to simulate the interrupt when
2085 * the interrupt subsystem is not functioning.
2086 *
2087 ***************************************************************/
2088static void
2089hpt_poll(struct cam_sim *sim)
2090{
2091 IAL_ADAPTER_T *pAdapter;
2092
2093 pAdapter = cam_sim_softc(sim);
2094
2095 hpt_intr_locked((void *)cam_sim_softc(sim));
2096}
2097
2098/****************************************************************
2099 * Name: hpt_intr
2100 * Description: Interrupt handler.
2101 ****************************************************************/
2102static void
2103hpt_intr(void *arg)
2104{
2105 IAL_ADAPTER_T *pAdapter;
2106
2107 pAdapter = arg;
2108 mtx_lock(&pAdapter->lock);
2109 hpt_intr_locked(pAdapter);
2110 mtx_unlock(&pAdapter->lock);
2111}
2112
2113static void
2114hpt_intr_locked(IAL_ADAPTER_T *pAdapter)
2115{
2116
2117 mtx_assert(&pAdapter->lock, MA_OWNED);
2118 /* KdPrintI(("----- Entering Isr() -----\n")); */
2119 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2120 {
2121 _VBUS_INST(&pAdapter->VBus)
2122 CheckPendingCall(_VBUS_P0);
2123 }
2124
2125 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2126}
2127
2128/**********************************************************
2129 * Asynchronous Events
2130 *********************************************************/
2131#if (!defined(UNREFERENCED_PARAMETER))
2132#define UNREFERENCED_PARAMETER(x) (void)(x)
2133#endif
2134
2135static void
2136hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path,
2137 void * arg)
2138{
2139 /* debug XXXX */
2140 panic("Here");
2141 UNREFERENCED_PARAMETER(callback_arg);
2142 UNREFERENCED_PARAMETER(code);
2143 UNREFERENCED_PARAMETER(path);
2144 UNREFERENCED_PARAMETER(arg);
2145
2146}
2147
2148static void
2149FlushAdapter(IAL_ADAPTER_T *pAdapter)
2150{
2151 int i;
2152
2153 hpt_printk(("flush all devices\n"));
2154
2155 /* flush all devices */
2156 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) {
2157 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2158 if(pVDev) fFlushVDev(pVDev);
2159 }
2160}
2161
2162static int
2163hpt_shutdown(device_t dev)
2164{
2165 IAL_ADAPTER_T *pAdapter;
2166
2167 pAdapter = device_get_softc(dev);
2168
2169 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh);
2170 mtx_lock(&pAdapter->lock);
2171 FlushAdapter(pAdapter);
2172 mtx_unlock(&pAdapter->lock);
2173 /* give the flush some time to happen,
2174 *otherwise "shutdown -p now" will make file system corrupted */
2175 DELAY(1000 * 1000 * 5);
2176 return 0;
2177}
2178
2179void
2180Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2181{
2182 _VBUS_INST(&pAdapter->VBus)
2183
2184 if (mWaitingForIdle(_VBUS_P0)) {
2185 CheckIdleCall(_VBUS_P0);
2186#ifdef SUPPORT_ARRAY
2187 {
2188 int i;
2189 PVDevice pArray;
2190 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){
2191 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2192 continue;
2193 else if (pArray->u.array.rf_auto_rebuild) {
2194 KdPrint(("auto rebuild.\n"));
2195 pArray->u.array.rf_auto_rebuild = 0;
2196 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2197 }
2198 }
2199 }
2200#endif
2201 }
2202 /* launch the awaiting commands blocked by mWaitingForIdle */
2203 while(pAdapter->pending_Q!= NULL)
2204 {
2205 _VBUS_INST(&pAdapter->VBus)
2206 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2207 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2208 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2209 }
2210}
2211
2212static void
2213ccb_done(union ccb *ccb)
2214{
2215 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2216 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2217 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2218
2219 dmamap_put(pmap);
2220 xpt_done(ccb);
2221
2222 pAdapter->outstandingCommands--;
2223
2224 if (pAdapter->outstandingCommands == 0)
2225 {
2226 if(DPC_Request_Nums == 0)
2227 Check_Idle_Call(pAdapter);
2228 wakeup(pAdapter);
2229 }
2230}
2231
2232/****************************************************************
2233 * Name: hpt_action
2234 * Description: Process a queued command from the CAM layer.
2235 * Parameters: sim - Pointer to SIM object
2236 * ccb - Pointer to SCSI command structure.
2237 ****************************************************************/
2238
2239void
2240hpt_action(struct cam_sim *sim, union ccb *ccb)
2241{
2242 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2243 PBUS_DMAMAP pmap;
2244 _VBUS_INST(&pAdapter->VBus)
2245
2246 mtx_assert(&pAdapter->lock, MA_OWNED);
2247 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2248 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2249
2250 switch (ccb->ccb_h.func_code)
2251 {
2252 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2253 {
2254 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2255
2256 if (ccb->ccb_h.target_lun) {
2257 ccb->ccb_h.status = CAM_LUN_INVALID;
2258 xpt_done(ccb);
2259 return;
2260 }
2261 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2262 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2263 ccb->ccb_h.status = CAM_TID_INVALID;
2264 xpt_done(ccb);
2265 return;
2266 }
2267
2268 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2269 Check_Idle_Call(pAdapter);
2270
2271 pmap = dmamap_get(pAdapter);
2272 HPT_ASSERT(pmap);
2273 ccb->ccb_adapter = pmap;
2274 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2275
2276 if (mWaitingForIdle(_VBUS_P0))
2277 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2278 else
2279 OsSendCommand(_VBUS_P ccb);
2280
2281 /* KdPrint(("leave scsiio\n")); */
2282 break;
2283 }
2284
2285 case XPT_RESET_BUS:
2286 KdPrint(("reset bus\n"));
2287 fResetVBus(_VBUS_P0);
2288 xpt_done(ccb);
2289 break;
2290
2291 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2292 case XPT_EN_LUN: /* Enable LUN as a target */
2293 case XPT_TARGET_IO: /* Execute target I/O request */
2294 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2295 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2296 case XPT_ABORT: /* Abort the specified CCB */
2297 case XPT_TERM_IO: /* Terminate the I/O process */
2298 /* XXX Implement */
2299 ccb->ccb_h.status = CAM_REQ_INVALID;
2300 xpt_done(ccb);
2301 break;
2302
2303 case XPT_GET_TRAN_SETTINGS:
2304 case XPT_SET_TRAN_SETTINGS:
2305 /* XXX Implement */
2306 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2307 xpt_done(ccb);
2308 break;
2309
2310 case XPT_CALC_GEOMETRY:
2311 cam_calc_geometry(&ccb->ccg, 1);
2312 xpt_done(ccb);
2313 break;
2314
2315 case XPT_PATH_INQ: /* Path routing inquiry */
2316 {
2317 struct ccb_pathinq *cpi = &ccb->cpi;
2318
2319 cpi->version_num = 1; /* XXX??? */
2320 cpi->hba_inquiry = PI_SDTR_ABLE;
2321 cpi->target_sprt = 0;
2322 /* Not necessary to reset bus */
2323 cpi->hba_misc = PIM_NOBUSRESET;
2324 cpi->hba_eng_cnt = 0;
2325
2326 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2327 cpi->max_lun = 0;
2328 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2329
2330 cpi->bus_id = cam_sim_bus(sim);
2331 cpi->base_transfer_speed = 3300;
2332 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2333 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2334 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2335 cpi->unit_number = cam_sim_unit(sim);
2336 cpi->transport = XPORT_SPI;
2337 cpi->transport_version = 2;
2338 cpi->protocol = PROTO_SCSI;
2339 cpi->protocol_version = SCSI_REV_2;
2340 cpi->ccb_h.status = CAM_REQ_CMP;
2341 xpt_done(ccb);
2342 break;
2343 }
2344
2345 default:
2346 KdPrint(("invalid cmd\n"));
2347 ccb->ccb_h.status = CAM_REQ_INVALID;
2348 xpt_done(ccb);
2349 break;
2350 }
2351 /* KdPrint(("leave hpt_action..............\n")); */
2352}
2353
2354/* shall be called at lock_driver() */
2355static void
2356hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2357{
2358 if(*ccb_Q == NULL)
2359 ccb->ccb_h.ccb_ccb_ptr = ccb;
2360 else {
2361 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr;
2362 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb;
2363 }
2364
2365 *ccb_Q = ccb;
2366}
2367
2368/* shall be called at lock_driver() */
2369static void
2370hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2371{
2372 union ccb *TempCCB;
2373
2374 TempCCB = *ccb_Q;
2375
2376 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2377 *ccb_Q = NULL;
2378 else {
2379 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2380 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2381
2382 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2383
2384 if(*ccb_Q == ccb)
2385 *ccb_Q = TempCCB;
2386 }
2387}
2388
2389#ifdef SUPPORT_ARRAY
2390/***************************************************************************
2391 * Function: hpt_worker_thread
2392 * Description: Do background rebuilding. Execute in kernel thread context.
2393 * Returns: None
2394 ***************************************************************************/
2395static void hpt_worker_thread(void)
2396{
2397
2398 for(;;) {
2399 mtx_lock(&DpcQueue_Lock);
2400 while (DpcQueue_First!=DpcQueue_Last) {
2401 ST_HPT_DPC p;
2402 p = DpcQueue[DpcQueue_First];
2403 DpcQueue_First++;
2404 DpcQueue_First %= MAX_DPC;
2405 DPC_Request_Nums++;
2406 mtx_unlock(&DpcQueue_Lock);
2407 p.dpc(p.pAdapter, p.arg, p.flags);
2408
2409 mtx_lock(&p.pAdapter->lock);
2410 mtx_lock(&DpcQueue_Lock);
2411 DPC_Request_Nums--;
2412 /* since we may have prevented Check_Idle_Call, do it here */
2413 if (DPC_Request_Nums==0) {
2414 if (p.pAdapter->outstandingCommands == 0) {
2415 _VBUS_INST(&p.pAdapter->VBus);
2416 Check_Idle_Call(p.pAdapter);
2417 CheckPendingCall(_VBUS_P0);
2418 }
2419 }
2420 mtx_unlock(&p.pAdapter->lock);
2421 mtx_unlock(&DpcQueue_Lock);
2422
2423 /*Schedule out*/
2424 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2425 /* abort rebuilding process. */
2426 IAL_ADAPTER_T *pAdapter;
2427 PVDevice pArray;
2428 PVBus _vbus_p;
2429 int i;
2430
2431 sx_slock(&hptmv_list_lock);
2432 pAdapter = gIal_Adapter;
2433
2434 while(pAdapter != 0){
2435 mtx_lock(&pAdapter->lock);
2436 _vbus_p = &pAdapter->VBus;
2437
2438 for (i=0;i<MAX_ARRAY_PER_VBUS;i++)
2439 {
2440 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2441 continue;
2442 else if (pArray->u.array.rf_rebuilding ||
2443 pArray->u.array.rf_verifying ||
2444 pArray->u.array.rf_initializing)
2445 {
2446 pArray->u.array.rf_abort_rebuild = 1;
2447 }
2448 }
2449 mtx_unlock(&pAdapter->lock);
2450 pAdapter = pAdapter->next;
2451 }
2452 sx_sunlock(&hptmv_list_lock);
2453 }
2454 mtx_lock(&DpcQueue_Lock);
2455 }
2456 mtx_unlock(&DpcQueue_Lock);
2457
2458/*Remove this debug option*/
2459/*
2460#ifdef DEBUG
2461 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2462 pause("hptrdy", 2*hz);
2463#endif
2464*/
2465 kproc_suspend_check(curproc);
2466 pause("-", 2*hz); /* wait for something to do */
2467 }
2468}
2469
2470static struct proc *hptdaemonproc;
2471static struct kproc_desc hpt_kp = {
2472 "hpt_wt",
2473 hpt_worker_thread,
2474 &hptdaemonproc
2475};
2476
2477/*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2478static void
2479launch_worker_thread(void)
2480{
2481 IAL_ADAPTER_T *pAdapTemp;
2482
2483 kproc_start(&hpt_kp);
2484
2485 sx_slock(&hptmv_list_lock);
2486 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2487
2488 _VBUS_INST(&pAdapTemp->VBus)
2489 int i;
2490 PVDevice pVDev;
2491
2492 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2493 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2494 continue;
2495 else{
2496 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2497 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2498 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2499 }
2500 }
2501 sx_sunlock(&hptmv_list_lock);
2502
2503 /*
2504 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished.
2505 */
2506 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc,
2507 SHUTDOWN_PRI_LAST);
2508}
2509/*
2510 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2511*/
2512
2513#endif
2514
2515/********************************************************************************/
2516
2517int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2518{
2519 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2520
2521 if (logical) {
2522 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2523 pSg->wSgSize = ccb->csio.dxfer_len;
2524 pSg->wSgFlag = SG_FLAG_EOT;
2525 return TRUE;
2526 }
2527 /* since we have provided physical sg, nobody will ask us to build physical sg */
2528 HPT_ASSERT(0);
2529 return FALSE;
2530}
2531
2532/*******************************************************************************/
2533ULONG HPTLIBAPI
2534GetStamp(void)
2535{
2536 /*
2537 * the system variable, ticks, can't be used since it hasn't yet been active
2538 * when our driver starts (ticks==0, it's a invalid stamp value)
2539 */
2540 ULONG stamp;
2541 do { stamp = random(); } while (stamp==0);
2542 return stamp;
2543}
2544
2545
2546static void
2547SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2548{
2549 int i;
2550 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2551
2552 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2553 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2554#ifndef SERIAL_CMDS
2555 inquiryData->CommandQueue = 1;
2556#endif
2557
2558 switch(pVDev->VDeviceType) {
2559 case VD_SINGLE_DISK:
2560 case VD_ATAPI:
2561 case VD_REMOVABLE:
2562 /* Set the removable bit, if applicable. */
2563 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2564 inquiryData->RemovableMedia = 1;
2565
2566 /* Fill in vendor identification fields. */
2567 for (i = 0; i < 20; i += 2) {
2568 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2569 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2570
2571 }
2572
2573 /* Initialize unused portion of product id. */
2574 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2575
2576 /* firmware revision */
2577 for (i = 0; i < 4; i += 2)
2578 {
2579 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2580 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2581 }
2582 break;
2583 default:
2584 memcpy(&inquiryData->VendorId, "RR18xx ", 8);
2585#ifdef SUPPORT_ARRAY
2586 switch(pVDev->VDeviceType){
2587 case VD_RAID_0:
2588 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2589 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2590 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2591 else
2592 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2593 break;
2594 case VD_RAID_1:
2595 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2596 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2597 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2598 else
2599 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2600 break;
2601 case VD_RAID_5:
2602 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2603 break;
2604 case VD_JBOD:
2605 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2606 break;
2607 }
2608#endif
2609 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2610 break;
2611 }
2612}
2613
2614static void
2615hpt_timeout(void *arg)
2616{
2617 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter;
2618 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2619 _VBUS_INST(&pAdapter->VBus)
2620
2621 mtx_assert(&pAdapter->lock, MA_OWNED);
2622 fResetVBus(_VBUS_P0);
2623}
2624
2625static void
2626hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2627{
2628 PCommand pCmd = (PCommand)arg;
2629 union ccb *ccb = pCmd->pOrgCommand;
2630 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2631 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2632 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2633 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2634 FPSCAT_GATH psg = pCmd->pSgTable;
2635 int idx;
2636 _VBUS_INST(pVDev->pVBus)
2637
2638 HPT_ASSERT(pCmd->cf_physical_sg);
2639
2640 if (error)
2641 panic("busdma error");
2642
2643 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2644
2645 if (nsegs != 0) {
2646 for (idx = 0; idx < nsegs; idx++, psg++) {
2647 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2648 psg->wSgSize = segs[idx].ds_len;
2649 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2650 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2651 }
2652 /* psg[-1].wSgFlag = SG_FLAG_EOT; */
2653
2654 if (pCmd->cf_data_in) {
2655 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2656 BUS_DMASYNC_PREREAD);
2657 }
2658 else if (pCmd->cf_data_out) {
2659 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2660 BUS_DMASYNC_PREWRITE);
2661 }
2662 }
2663
2664 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb);
2665 pVDev->pfnSendCommand(_VBUS_P pCmd);
2666 CheckPendingCall(_VBUS_P0);
2667}
2668
2669
2670
2671static void HPTLIBAPI
2672OsSendCommand(_VBUS_ARG union ccb *ccb)
2673{
2674 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2675 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2676 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2677 struct ccb_scsiio *csio = &ccb->csio;
2678 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2679
2680 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2681 ccb,
2682 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2683 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2684 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2685 ));
2686
2687 pAdapter->outstandingCommands++;
2688
2689 if (pVDev == NULL || pVDev->vf_online == 0) {
2690 ccb->ccb_h.status = CAM_REQ_INVALID;
2691 ccb_done(ccb);
2692 goto Command_Complished;
2693 }
2694
2695 switch(ccb->csio.cdb_io.cdb_bytes[0])
2696 {
2697 case TEST_UNIT_READY:
2698 case START_STOP_UNIT:
2699 case SYNCHRONIZE_CACHE:
2700 /* FALLTHROUGH */
2701 ccb->ccb_h.status = CAM_REQ_CMP;
2702 break;
2703
2704 case INQUIRY:
2705 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2706 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2707 ccb_h->status = CAM_REQ_CMP;
2708 break;
2709
2710 case READ_CAPACITY:
2711 {
2712 UCHAR *rbuf=csio->data_ptr;
2713 unsigned int cap;
2714
2715 if (pVDev->VDeviceCapacity > 0xfffffffful) {
2716 cap = 0xfffffffful;
2717 } else {
2718 cap = pVDev->VDeviceCapacity - 1;
2719 }
2720
2721 rbuf[0] = (UCHAR)(cap>>24);
2722 rbuf[1] = (UCHAR)(cap>>16);
2723 rbuf[2] = (UCHAR)(cap>>8);
2724 rbuf[3] = (UCHAR)cap;
2725 /* Claim 512 byte blocks (big-endian). */
2726 rbuf[4] = 0;
2727 rbuf[5] = 0;
2728 rbuf[6] = 2;
2729 rbuf[7] = 0;
2730
2731 ccb_h->status = CAM_REQ_CMP;
2732 break;
2733 }
2734
2735 case 0x9e: /*SERVICE_ACTION_IN*/
2736 {
2737 UCHAR *rbuf = csio->data_ptr;
2738 LBA_T cap = pVDev->VDeviceCapacity - 1;
2739
2740 rbuf[0] = (UCHAR)(cap>>56);
2741 rbuf[1] = (UCHAR)(cap>>48);
2742 rbuf[2] = (UCHAR)(cap>>40);
2743 rbuf[3] = (UCHAR)(cap>>32);
2744 rbuf[4] = (UCHAR)(cap>>24);
2745 rbuf[5] = (UCHAR)(cap>>16);
2746 rbuf[6] = (UCHAR)(cap>>8);
2747 rbuf[7] = (UCHAR)cap;
2748 rbuf[8] = 0;
2749 rbuf[9] = 0;
2750 rbuf[10] = 2;
2751 rbuf[11] = 0;
2752
2753 ccb_h->status = CAM_REQ_CMP;
2754 break;
2755 }
2756
2757 case READ_6:
2758 case WRITE_6:
2759 case READ_10:
2760 case WRITE_10:
2761 case 0x88: /* READ_16 */
2762 case 0x8a: /* WRITE_16 */
2763 case 0x13:
2764 case 0x2f:
2765 {
2766 UCHAR Cdb[16];
2767 UCHAR CdbLength;
2768 _VBUS_INST(pVDev->pVBus)
2769 PCommand pCmd = AllocateCommand(_VBUS_P0);
2770 int error;
2771 HPT_ASSERT(pCmd);
2772
2773 CdbLength = csio->cdb_len;
2774 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2775 {
2776 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2777 {
2778 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2779 }
2780 else
2781 {
2782 KdPrintE(("ERROR!!!\n"));
2783 ccb->ccb_h.status = CAM_REQ_INVALID;
2784 break;
2785 }
2786 }
2787 else
2788 {
2789 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2790 }
2791
2792 pCmd->pOrgCommand = ccb;
2793 pCmd->pVDevice = pVDev;
2794 pCmd->pfnCompletion = fOsCommandDone;
2795 pCmd->pfnBuildSgl = fOsBuildSgl;
2796 pCmd->pSgTable = pmap->psg;
2797
2798 switch (Cdb[0])
2799 {
2800 case READ_6:
2801 case WRITE_6:
2802 case 0x13:
2803 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2804 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2805 break;
2806
2807 case 0x88: /* READ_16 */
2808 case 0x8a: /* WRITE_16 */
2809 pCmd->uCmd.Ide.Lba =
2810 (HPT_U64)Cdb[2] << 56 |
2811 (HPT_U64)Cdb[3] << 48 |
2812 (HPT_U64)Cdb[4] << 40 |
2813 (HPT_U64)Cdb[5] << 32 |
2814 (HPT_U64)Cdb[6] << 24 |
2815 (HPT_U64)Cdb[7] << 16 |
2816 (HPT_U64)Cdb[8] << 8 |
2817 (HPT_U64)Cdb[9];
2818 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13];
2819 break;
2820
2821 default:
2822 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2823 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2824 break;
2825 }
2826
2827 switch (Cdb[0])
2828 {
2829 case READ_6:
2830 case READ_10:
2831 case 0x88: /* READ_16 */
2832 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2833 pCmd->cf_data_in = 1;
2834 break;
2835
2836 case WRITE_6:
2837 case WRITE_10:
2838 case 0x8a: /* WRITE_16 */
2839 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2840 pCmd->cf_data_out = 1;
2841 break;
2842 case 0x13:
2843 case 0x2f:
2844 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2845 break;
2846 }
2847/*///////////////////////// */
2848 pCmd->cf_physical_sg = 1;
2849 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent,
2850 pmap->dma_map,
2851 ccb,
2852 hpt_io_dmamap_callback,
2853 pCmd, BUS_DMA_WAITOK
2854 );
2855 KdPrint(("bus_dmamap_load return %d\n", error));
2856 if (error && error!=EINPROGRESS) {
2857 hpt_printk(("bus_dmamap_load error %d\n", error));
2858 FreeCommand(_VBUS_P pCmd);
2859 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2860 dmamap_put(pmap);
2861 pAdapter->outstandingCommands--;
2862 if (pAdapter->outstandingCommands == 0)
2863 wakeup(pAdapter);
2864 xpt_done(ccb);
2865 }
2866 goto Command_Complished;
2867 }
2868
2869 default:
2870 ccb->ccb_h.status = CAM_REQ_INVALID;
2871 break;
2872 }
2873 ccb_done(ccb);
2874Command_Complished:
2875 CheckPendingCall(_VBUS_P0);
2876 return;
2877}
2878
2879static void HPTLIBAPI
2880fOsCommandDone(_VBUS_ARG PCommand pCmd)
2881{
2882 union ccb *ccb = pCmd->pOrgCommand;
2883 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2884 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2885
2886 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2887
2888 callout_stop(&pmap->timeout);
2889
2890 switch(pCmd->Result) {
2891 case RETURN_SUCCESS:
2892 ccb->ccb_h.status = CAM_REQ_CMP;
2893 break;
2894 case RETURN_BAD_DEVICE:
2895 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
2896 break;
2897 case RETURN_DEVICE_BUSY:
2898 ccb->ccb_h.status = CAM_BUSY;
2899 break;
2900 case RETURN_INVALID_REQUEST:
2901 ccb->ccb_h.status = CAM_REQ_INVALID;
2902 break;
2903 case RETURN_SELECTION_TIMEOUT:
2904 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2905 break;
2906 case RETURN_RETRY:
2907 ccb->ccb_h.status = CAM_BUSY;
2908 break;
2909 default:
2910 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2911 break;
2912 }
2913
2914 if (pCmd->cf_data_in) {
2915 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2916 }
2917 else if (pCmd->cf_data_out) {
2918 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2919 }
2920
2921 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2922
2923 FreeCommand(_VBUS_P pCmd);
2924 ccb_done(ccb);
2925}
2926
2927int
2928hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2929{
2930 int p;
2931
2932 mtx_lock(&DpcQueue_Lock);
2933 p = (DpcQueue_Last + 1) % MAX_DPC;
2934 if (p==DpcQueue_First) {
2935 KdPrint(("DPC Queue full!\n"));
2936 mtx_unlock(&DpcQueue_Lock);
2937 return -1;
2938 }
2939
2940 DpcQueue[DpcQueue_Last].dpc = dpc;
2941 DpcQueue[DpcQueue_Last].pAdapter = pAdapter;
2942 DpcQueue[DpcQueue_Last].arg = arg;
2943 DpcQueue[DpcQueue_Last].flags = flags;
2944 DpcQueue_Last = p;
2945 mtx_unlock(&DpcQueue_Lock);
2946
2947 return 0;
2948}
2949
2950#ifdef _RAID5N_
2951/*
2952 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2953 * How about the memory for 5081 request/response array and PRD table?
2954 */
2955void
2956*os_alloc_page(_VBUS_ARG0)
2957{
2958 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2959}
2960
2961void
2962*os_alloc_dma_page(_VBUS_ARG0)
2963{
2964 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2965}
2966
2967void
2968os_free_page(_VBUS_ARG void *p)
2969{
2970 contigfree(p, 0x1000, M_DEVBUF);
2971}
2972
2973void
2974os_free_dma_page(_VBUS_ARG void *p)
2975{
2976 contigfree(p, 0x1000, M_DEVBUF);
2977}
2978
2979void
2980DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
2981{
2982 UINT i;
2983 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
2984}
2985
2986void
2987DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
2988{
2989 UINT i;
2990 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
2991}
2992#endif
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