1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 74178 2001-03-12 21:30:52Z jlemon $
| 27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 74259 2001-03-14 19:50:35Z jlemon $
|
28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
36 * Number of transmit control blocks. This determines the number
37 * of transmit buffers that can be chained in the CB list.
38 * This must be a power of two.
39 */
40#define FXP_NTXCB 128
41
42/*
43 * Number of completed TX commands at which point an interrupt
44 * will be generated to garbage collect the attached buffers.
45 * Must be at least one less than FXP_NTXCB, and should be
46 * enough less so that the transmitter doesn't becomes idle
47 * during the buffer rundown (which would reduce performance).
48 */
49#define FXP_CXINT_THRESH 120
50
51/*
52 * TxCB list index mask. This is used to do list wrap-around.
53 */
54#define FXP_TXCB_MASK (FXP_NTXCB - 1)
55
56/*
57 * Number of receive frame area buffers. These are large so chose
58 * wisely.
59 */
60#define FXP_NRFABUFS 64
61
62/*
63 * Maximum number of seconds that the receiver can be idle before we
64 * assume it's dead and attempt to reset it by reprogramming the
65 * multicast filter. This is part of a work-around for a bug in the
66 * NIC. See fxp_stats_update().
67 */
68#define FXP_MAX_RX_IDLE 15
69
70#if __FreeBSD_version < 500000
71#define FXP_LOCK(_sc)
72#define FXP_UNLOCK(_sc)
73#define mtx_init(a, b, c)
74#define mtx_destroy(a)
75struct mtx { int dummy; };
76#else
77#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
78#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
79#endif
80
81#ifdef __alpha__
82#undef vtophys
83#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
84#endif /* __alpha__ */
85
86/*
87 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
88 * for functional grouping.
89 */
90struct fxp_softc {
91 struct arpcom arpcom; /* per-interface network data */
92 struct resource *mem; /* resource descriptor for registers */
93 int rtp; /* register resource type */
94 int rgd; /* register descriptor in use */
95 struct resource *irq; /* resource descriptor for interrupt */
96 void *ih; /* interrupt handler cookie */
97 struct mtx sc_mtx;
98 bus_space_tag_t sc_st; /* bus space tag */
99 bus_space_handle_t sc_sh; /* bus space handle */
100 struct mbuf *rfa_headm; /* first mbuf in receive frame area */
101 struct mbuf *rfa_tailm; /* last mbuf in receive frame area */
102 struct fxp_cb_tx *cbl_first; /* first active TxCB in list */
103 int tx_queued; /* # of active TxCB's */
104 int need_mcsetup; /* multicast filter needs programming */
105 struct fxp_cb_tx *cbl_last; /* last active TxCB in list */
106 struct fxp_stats *fxp_stats; /* Pointer to interface stats */
107 int rx_idle_secs; /* # of seconds RX has been idle */
108 struct callout_handle stat_ch; /* Handle for canceling our stat timeout */
109 struct fxp_cb_tx *cbl_base; /* base of TxCB list */
110 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
111 struct ifmedia sc_media; /* media information */
112 device_t miibus;
113 device_t dev;
114 int eeprom_size; /* size of serial EEPROM */
115 int suspended; /* 0 = normal 1 = suspended (APM) */
| 28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
36 * Number of transmit control blocks. This determines the number
37 * of transmit buffers that can be chained in the CB list.
38 * This must be a power of two.
39 */
40#define FXP_NTXCB 128
41
42/*
43 * Number of completed TX commands at which point an interrupt
44 * will be generated to garbage collect the attached buffers.
45 * Must be at least one less than FXP_NTXCB, and should be
46 * enough less so that the transmitter doesn't becomes idle
47 * during the buffer rundown (which would reduce performance).
48 */
49#define FXP_CXINT_THRESH 120
50
51/*
52 * TxCB list index mask. This is used to do list wrap-around.
53 */
54#define FXP_TXCB_MASK (FXP_NTXCB - 1)
55
56/*
57 * Number of receive frame area buffers. These are large so chose
58 * wisely.
59 */
60#define FXP_NRFABUFS 64
61
62/*
63 * Maximum number of seconds that the receiver can be idle before we
64 * assume it's dead and attempt to reset it by reprogramming the
65 * multicast filter. This is part of a work-around for a bug in the
66 * NIC. See fxp_stats_update().
67 */
68#define FXP_MAX_RX_IDLE 15
69
70#if __FreeBSD_version < 500000
71#define FXP_LOCK(_sc)
72#define FXP_UNLOCK(_sc)
73#define mtx_init(a, b, c)
74#define mtx_destroy(a)
75struct mtx { int dummy; };
76#else
77#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
78#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
79#endif
80
81#ifdef __alpha__
82#undef vtophys
83#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
84#endif /* __alpha__ */
85
86/*
87 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
88 * for functional grouping.
89 */
90struct fxp_softc {
91 struct arpcom arpcom; /* per-interface network data */
92 struct resource *mem; /* resource descriptor for registers */
93 int rtp; /* register resource type */
94 int rgd; /* register descriptor in use */
95 struct resource *irq; /* resource descriptor for interrupt */
96 void *ih; /* interrupt handler cookie */
97 struct mtx sc_mtx;
98 bus_space_tag_t sc_st; /* bus space tag */
99 bus_space_handle_t sc_sh; /* bus space handle */
100 struct mbuf *rfa_headm; /* first mbuf in receive frame area */
101 struct mbuf *rfa_tailm; /* last mbuf in receive frame area */
102 struct fxp_cb_tx *cbl_first; /* first active TxCB in list */
103 int tx_queued; /* # of active TxCB's */
104 int need_mcsetup; /* multicast filter needs programming */
105 struct fxp_cb_tx *cbl_last; /* last active TxCB in list */
106 struct fxp_stats *fxp_stats; /* Pointer to interface stats */
107 int rx_idle_secs; /* # of seconds RX has been idle */
108 struct callout_handle stat_ch; /* Handle for canceling our stat timeout */
109 struct fxp_cb_tx *cbl_base; /* base of TxCB list */
110 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
111 struct ifmedia sc_media; /* media information */
112 device_t miibus;
113 device_t dev;
114 int eeprom_size; /* size of serial EEPROM */
115 int suspended; /* 0 = normal 1 = suspended (APM) */
|
| 116 int chip;
|
116 int flags;
117 u_int32_t saved_maps[5]; /* pci data */
118 u_int32_t saved_biosaddr;
119 u_int8_t saved_intline;
120 u_int8_t saved_cachelnsz;
121 u_int8_t saved_lattimer;
122};
123
| 117 int flags;
118 u_int32_t saved_maps[5]; /* pci data */
119 u_int32_t saved_biosaddr;
120 u_int8_t saved_intline;
121 u_int8_t saved_cachelnsz;
122 u_int8_t saved_lattimer;
123};
124
|
| 125#define FXP_CHIP_82557 1 /* 82557 chip type */
126
|
124#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */
125#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */
126#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */
127#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */
128#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */
129#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */
130#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
131
132/* Macros to ease CSR access. */
133#define CSR_READ_1(sc, reg) \
134 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
135#define CSR_READ_2(sc, reg) \
136 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
137#define CSR_READ_4(sc, reg) \
138 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
139#define CSR_WRITE_1(sc, reg, val) \
140 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
141#define CSR_WRITE_2(sc, reg, val) \
142 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
143#define CSR_WRITE_4(sc, reg, val) \
144 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
145
146#define sc_if arpcom.ac_if
147
148#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit
| 127#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */
128#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */
129#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */
130#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */
131#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */
132#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */
133#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
134
135/* Macros to ease CSR access. */
136#define CSR_READ_1(sc, reg) \
137 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
138#define CSR_READ_2(sc, reg) \
139 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
140#define CSR_READ_4(sc, reg) \
141 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
142#define CSR_WRITE_1(sc, reg, val) \
143 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
144#define CSR_WRITE_2(sc, reg, val) \
145 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
146#define CSR_WRITE_4(sc, reg, val) \
147 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
148
149#define sc_if arpcom.ac_if
150
151#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit
|