1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 185269 2008-11-25 00:48:05Z yongari $
| 27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 185285 2008-11-25 04:16:16Z yongari $
|
28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
36 * Number of transmit control blocks. This determines the number
37 * of transmit buffers that can be chained in the CB list.
38 * This must be a power of two.
39 */
40#define FXP_NTXCB 128
| 28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
36 * Number of transmit control blocks. This determines the number
37 * of transmit buffers that can be chained in the CB list.
38 * This must be a power of two.
39 */
40#define FXP_NTXCB 128
|
| 41#define FXP_NTXCB_HIWAT ((FXP_NTXCB * 7) / 10)
|
41
42/*
43 * Size of the TxCB list.
44 */
45#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx))
46
47/*
48 * Macro to obtain the DMA address of a virtual address in the
49 * TxCB list based on the base DMA address of the TxCB list.
50 */
51#define FXP_TXCB_DMA_ADDR(sc, addr) \
52 (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \
53 (uintptr_t)sc->fxp_desc.cbl_list)
54
55/*
56 * Number of completed TX commands at which point an interrupt
57 * will be generated to garbage collect the attached buffers.
58 * Must be at least one less than FXP_NTXCB, and should be
59 * enough less so that the transmitter doesn't becomes idle
60 * during the buffer rundown (which would reduce performance).
61 */
62#define FXP_CXINT_THRESH 120
63
64/*
65 * TxCB list index mask. This is used to do list wrap-around.
66 */
67#define FXP_TXCB_MASK (FXP_NTXCB - 1)
68
69/*
70 * Number of receive frame area buffers. These are large so chose
71 * wisely.
72 */
73#ifdef DEVICE_POLLING
74#define FXP_NRFABUFS 192
75#else
76#define FXP_NRFABUFS 64
77#endif
78
79/*
80 * Maximum number of seconds that the receiver can be idle before we
81 * assume it's dead and attempt to reset it by reprogramming the
82 * multicast filter. This is part of a work-around for a bug in the
83 * NIC. See fxp_stats_update().
84 */
85#define FXP_MAX_RX_IDLE 15
86
87/*
88 * Default maximum time, in microseconds, that an interrupt may be delayed
89 * in an attempt to coalesce interrupts. This is only effective if the Intel
90 * microcode is loaded, and may be changed via either loader tunables or
91 * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h.
92 */
93#define TUNABLE_INT_DELAY 1000
94
95/*
96 * Default number of packets that will be bundled, before an interrupt is
97 * generated. This is only effective if the Intel microcode is loaded, and
98 * may be changed via either loader tunables or sysctl. This may not be
99 * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD
100 * entry in rcvbundl.h.
101 */
102#define TUNABLE_BUNDLE_MAX 6
103
104#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
105#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
106#define FXP_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
107
108/*
109 * Structures to handle TX and RX descriptors.
110 */
111struct fxp_rx {
112 struct fxp_rx *rx_next;
113 struct mbuf *rx_mbuf;
114 bus_dmamap_t rx_map;
115 uint32_t rx_addr;
116};
117
118struct fxp_tx {
119 struct fxp_tx *tx_next;
120 struct fxp_cb_tx *tx_cb;
121 struct mbuf *tx_mbuf;
122 bus_dmamap_t tx_map;
123};
124
125struct fxp_desc_list {
126 struct fxp_rx rx_list[FXP_NRFABUFS];
127 struct fxp_tx tx_list[FXP_NTXCB];
128 struct fxp_tx mcs_tx;
129 struct fxp_rx *rx_head;
130 struct fxp_rx *rx_tail;
131 struct fxp_tx *tx_first;
132 struct fxp_tx *tx_last;
133 struct fxp_rfa *rfa_list;
134 struct fxp_cb_tx *cbl_list;
135 uint32_t cbl_addr;
136 bus_dma_tag_t rx_tag;
137};
138
139/*
140 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
141 * for functional grouping.
142 */
143struct fxp_softc {
144 struct ifnet *ifp; /* per-interface network data */
145 struct resource *fxp_res[2]; /* I/O and IRQ resources */
146 struct resource_spec *fxp_spec; /* the resource spec we used */
147 void *ih; /* interrupt handler cookie */
148 struct mtx sc_mtx;
149 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */
150 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */
151 bus_dmamap_t fxp_smap; /* bus DMA map for stats */
152 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */
153 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */
154 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */
155 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */
156 bus_dmamap_t spare_map; /* spare DMA map */
157 struct fxp_desc_list fxp_desc; /* descriptors management struct */
158 int maxtxseg; /* maximum # of TX segments */
159 int tx_queued; /* # of active TxCB's */
160 int need_mcsetup; /* multicast filter needs programming */
161 struct fxp_stats *fxp_stats; /* Pointer to interface stats */
162 uint32_t stats_addr; /* DMA address of the stats structure */
163 int rx_idle_secs; /* # of seconds RX has been idle */
164 struct callout stat_ch; /* stat callout */
165 int watchdog_timer; /* seconds until chip reset */
166 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
167 uint32_t mcs_addr; /* DMA address of the multicast cmd */
168 struct ifmedia sc_media; /* media information */
169 device_t miibus;
170 device_t dev;
171 int tunable_int_delay; /* interrupt delay value for ucode */
172 int tunable_bundle_max; /* max # frames per interrupt (ucode) */
173 int tunable_noflow; /* flow control disabled */
174 int rnr; /* RNR events */
175 int eeprom_size; /* size of serial EEPROM */
176 int suspended; /* 0 = normal 1 = suspended or dead */
177 int cu_resume_bug;
178 int revision;
179 int flags;
180 uint8_t rfa_size;
181 uint32_t tx_cmd;
182};
183
184#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */
185#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */
186#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */
187#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */
188#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */
189#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */
190#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
191#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */
192#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */
193#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */
194#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */
195#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */
196
197/* Macros to ease CSR access. */
198#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
199#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
200#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
201#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
202#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
203#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)
| 42
43/*
44 * Size of the TxCB list.
45 */
46#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx))
47
48/*
49 * Macro to obtain the DMA address of a virtual address in the
50 * TxCB list based on the base DMA address of the TxCB list.
51 */
52#define FXP_TXCB_DMA_ADDR(sc, addr) \
53 (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \
54 (uintptr_t)sc->fxp_desc.cbl_list)
55
56/*
57 * Number of completed TX commands at which point an interrupt
58 * will be generated to garbage collect the attached buffers.
59 * Must be at least one less than FXP_NTXCB, and should be
60 * enough less so that the transmitter doesn't becomes idle
61 * during the buffer rundown (which would reduce performance).
62 */
63#define FXP_CXINT_THRESH 120
64
65/*
66 * TxCB list index mask. This is used to do list wrap-around.
67 */
68#define FXP_TXCB_MASK (FXP_NTXCB - 1)
69
70/*
71 * Number of receive frame area buffers. These are large so chose
72 * wisely.
73 */
74#ifdef DEVICE_POLLING
75#define FXP_NRFABUFS 192
76#else
77#define FXP_NRFABUFS 64
78#endif
79
80/*
81 * Maximum number of seconds that the receiver can be idle before we
82 * assume it's dead and attempt to reset it by reprogramming the
83 * multicast filter. This is part of a work-around for a bug in the
84 * NIC. See fxp_stats_update().
85 */
86#define FXP_MAX_RX_IDLE 15
87
88/*
89 * Default maximum time, in microseconds, that an interrupt may be delayed
90 * in an attempt to coalesce interrupts. This is only effective if the Intel
91 * microcode is loaded, and may be changed via either loader tunables or
92 * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h.
93 */
94#define TUNABLE_INT_DELAY 1000
95
96/*
97 * Default number of packets that will be bundled, before an interrupt is
98 * generated. This is only effective if the Intel microcode is loaded, and
99 * may be changed via either loader tunables or sysctl. This may not be
100 * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD
101 * entry in rcvbundl.h.
102 */
103#define TUNABLE_BUNDLE_MAX 6
104
105#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
106#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
107#define FXP_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
108
109/*
110 * Structures to handle TX and RX descriptors.
111 */
112struct fxp_rx {
113 struct fxp_rx *rx_next;
114 struct mbuf *rx_mbuf;
115 bus_dmamap_t rx_map;
116 uint32_t rx_addr;
117};
118
119struct fxp_tx {
120 struct fxp_tx *tx_next;
121 struct fxp_cb_tx *tx_cb;
122 struct mbuf *tx_mbuf;
123 bus_dmamap_t tx_map;
124};
125
126struct fxp_desc_list {
127 struct fxp_rx rx_list[FXP_NRFABUFS];
128 struct fxp_tx tx_list[FXP_NTXCB];
129 struct fxp_tx mcs_tx;
130 struct fxp_rx *rx_head;
131 struct fxp_rx *rx_tail;
132 struct fxp_tx *tx_first;
133 struct fxp_tx *tx_last;
134 struct fxp_rfa *rfa_list;
135 struct fxp_cb_tx *cbl_list;
136 uint32_t cbl_addr;
137 bus_dma_tag_t rx_tag;
138};
139
140/*
141 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
142 * for functional grouping.
143 */
144struct fxp_softc {
145 struct ifnet *ifp; /* per-interface network data */
146 struct resource *fxp_res[2]; /* I/O and IRQ resources */
147 struct resource_spec *fxp_spec; /* the resource spec we used */
148 void *ih; /* interrupt handler cookie */
149 struct mtx sc_mtx;
150 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */
151 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */
152 bus_dmamap_t fxp_smap; /* bus DMA map for stats */
153 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */
154 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */
155 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */
156 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */
157 bus_dmamap_t spare_map; /* spare DMA map */
158 struct fxp_desc_list fxp_desc; /* descriptors management struct */
159 int maxtxseg; /* maximum # of TX segments */
160 int tx_queued; /* # of active TxCB's */
161 int need_mcsetup; /* multicast filter needs programming */
162 struct fxp_stats *fxp_stats; /* Pointer to interface stats */
163 uint32_t stats_addr; /* DMA address of the stats structure */
164 int rx_idle_secs; /* # of seconds RX has been idle */
165 struct callout stat_ch; /* stat callout */
166 int watchdog_timer; /* seconds until chip reset */
167 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
168 uint32_t mcs_addr; /* DMA address of the multicast cmd */
169 struct ifmedia sc_media; /* media information */
170 device_t miibus;
171 device_t dev;
172 int tunable_int_delay; /* interrupt delay value for ucode */
173 int tunable_bundle_max; /* max # frames per interrupt (ucode) */
174 int tunable_noflow; /* flow control disabled */
175 int rnr; /* RNR events */
176 int eeprom_size; /* size of serial EEPROM */
177 int suspended; /* 0 = normal 1 = suspended or dead */
178 int cu_resume_bug;
179 int revision;
180 int flags;
181 uint8_t rfa_size;
182 uint32_t tx_cmd;
183};
184
185#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */
186#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */
187#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */
188#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */
189#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */
190#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */
191#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
192#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */
193#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */
194#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */
195#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */
196#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */
197
198/* Macros to ease CSR access. */
199#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
200#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
201#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
202#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
203#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
204#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)
|