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if_fxpreg.h (85460) if_fxpreg.h (111578)
1/*
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
1/*
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 85460 2001-10-25 05:25:58Z jlemon $
28 * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 111578 2003-02-26 22:12:04Z wpaul $
29 */
30
31#define FXP_VENDORID_INTEL 0x8086
32
33#define FXP_PCI_MMBA 0x10
34#define FXP_PCI_IOBA 0x14
35
36/*

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149 tno_int_or_tco_en:1, /* 7,9 */
150 ci_int:1,
151 ext_txcb_dis:1, /* 8,9 */
152 ext_stats_dis:1, /* 8,9 */
153 keep_overrun_rx:1,
154 save_bf:1;
155 volatile u_int disc_short_rx:1,
156 underrun_retry:2,
29 */
30
31#define FXP_VENDORID_INTEL 0x8086
32
33#define FXP_PCI_MMBA 0x10
34#define FXP_PCI_IOBA 0x14
35
36/*

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149 tno_int_or_tco_en:1, /* 7,9 */
150 ci_int:1,
151 ext_txcb_dis:1, /* 8,9 */
152 ext_stats_dis:1, /* 8,9 */
153 keep_overrun_rx:1,
154 save_bf:1;
155 volatile u_int disc_short_rx:1,
156 underrun_retry:2,
157 :3,
157 :2,
158 ext_rfa:1, /* 550 */
158 two_frames:1, /* 8,9 */
159 dyn_tbd:1; /* 8,9 */
160 volatile u_int mediatype:1, /* 7 */
161 :6,
162 csma_dis:1; /* 8,9 */
163 volatile u_int tcp_udp_cksum:1, /* 9 */
164 :3,
165 vlan_tco:1, /* 8,9 */

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203 fdx_pin_en:1;
204 volatile u_int :5,
205 pri_fc_loc:1, /* 8,9 */
206 multi_ia:1,
207 :1;
208 volatile u_int :3,
209 mc_all:1,
210 :4;
159 two_frames:1, /* 8,9 */
160 dyn_tbd:1; /* 8,9 */
161 volatile u_int mediatype:1, /* 7 */
162 :6,
163 csma_dis:1; /* 8,9 */
164 volatile u_int tcp_udp_cksum:1, /* 9 */
165 :3,
166 vlan_tco:1, /* 8,9 */

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204 fdx_pin_en:1;
205 volatile u_int :5,
206 pri_fc_loc:1, /* 8,9 */
207 multi_ia:1,
208 :1;
209 volatile u_int :3,
210 mc_all:1,
211 :4;
212 volatile u_int8_t gamla_rx:1; /* 550 */
213 volatile u_int8_t pad[9]; /* 550 */
211};
212
213#define MAXMCADDR 80
214struct fxp_cb_mcs {
215 struct fxp_cb_tx *next;
216 struct mbuf *mb_head;
217 volatile u_int16_t cb_status;
218 volatile u_int16_t cb_command;

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238 */
239#define FXP_TXCB_FIXED 16 /* cb_status .. tbd_number */
240#define FXP_NTXSEG ((256 - (sizeof(void *) * 2) - FXP_TXCB_FIXED) / 8)
241
242struct fxp_tbd {
243 volatile u_int32_t tb_addr;
244 volatile u_int32_t tb_size;
245};
214};
215
216#define MAXMCADDR 80
217struct fxp_cb_mcs {
218 struct fxp_cb_tx *next;
219 struct mbuf *mb_head;
220 volatile u_int16_t cb_status;
221 volatile u_int16_t cb_command;

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241 */
242#define FXP_TXCB_FIXED 16 /* cb_status .. tbd_number */
243#define FXP_NTXSEG ((256 - (sizeof(void *) * 2) - FXP_TXCB_FIXED) / 8)
244
245struct fxp_tbd {
246 volatile u_int32_t tb_addr;
247 volatile u_int32_t tb_size;
248};
249
250struct fxp_ipcb {
251 /*
252 * The following fields are valid only when
253 * using the IPCB command block for TX checksum offload
254 * (and TCP large send, VLANs, and (I think) IPsec). To use
255 * them, you must enable extended TxCBs (available only
256 * on the 82559 and later) and use the IPCBXMIT command.
257 * Note that Intel defines the IPCB to be 32 bytes long,
258 * the last 8 bytes of which comprise the first entry
259 * in the TBD array (see note below). This means we only
260 * have to define 8 extra bytes here.
261 */
262 volatile u_int16_t ipcb_schedule_low;
263 volatile u_int8_t ipcb_ip_schedule;
264 volatile u_int8_t ipcb_ip_activation_high;
265 volatile u_int16_t ipcb_vlan_id;
266 volatile u_int8_t ipcb_ip_header_offset;
267 volatile u_int8_t ipcb_tcp_header_offset;
268};
269
246struct fxp_cb_tx {
247 struct fxp_cb_tx *next;
248 struct mbuf *mb_head;
249 volatile u_int16_t cb_status;
250 volatile u_int16_t cb_command;
251 volatile u_int32_t link_addr;
252 volatile u_int32_t tbd_array_addr;
253 volatile u_int16_t byte_count;
254 volatile u_int8_t tx_threshold;
255 volatile u_int8_t tbd_number;
270struct fxp_cb_tx {
271 struct fxp_cb_tx *next;
272 struct mbuf *mb_head;
273 volatile u_int16_t cb_status;
274 volatile u_int16_t cb_command;
275 volatile u_int32_t link_addr;
276 volatile u_int32_t tbd_array_addr;
277 volatile u_int16_t byte_count;
278 volatile u_int8_t tx_threshold;
279 volatile u_int8_t tbd_number;
280
256 /*
257 * The following structure isn't actually part of the TxCB,
258 * unless the extended TxCB feature is being used. In this
259 * case, the first two elements of the structure below are
260 * fetched along with the TxCB.
261 */
281 /*
282 * The following structure isn't actually part of the TxCB,
283 * unless the extended TxCB feature is being used. In this
284 * case, the first two elements of the structure below are
285 * fetched along with the TxCB.
286 */
262 volatile struct fxp_tbd tbd[FXP_NTXSEG];
287 union {
288 volatile struct fxp_ipcb;
289 volatile struct fxp_tbd tbd[FXP_NTXSEG];
290 } tx_cb_u;
263};
264
291};
292
293#define tbd tx_cb_u.tbd
294#define ipcb_schedule_low tx_cb_u.ipcb_schedule_low
295#define ipcb_ip_schedule tx_cb_u.ipcb_ip_schedule
296#define ipcb_ip_activation_high tx_cb_u.ipcb_ip_activation_high
297#define ipcb_vlan_id tx_cb_u.ipcb_vlan_id
298#define ipcb_ip_header_offset tx_cb_u.ipcb_ip_header_offset
299#define ipcb_tcp_header_offset tx_cb_u.ipcb_tcp_header_offset
300
265/*
301/*
302 * IPCB field definitions
303 */
304#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10
305#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20
306#define FXP_IPCB_TCP_PACKET 0x40
307#define FXP_IPCB_LARGESEND_ENABLE 0x80
308#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01
309#define FXP_IPCB_INSERTVLAN_ENABLE 0x02
310
311/*
266 * Control Block (CB) definitions
267 */
268
269/* status */
270#define FXP_CB_STATUS_OK 0x2000
271#define FXP_CB_STATUS_C 0x8000
272/* commands */
273#define FXP_CB_COMMAND_NOP 0x0
274#define FXP_CB_COMMAND_IAS 0x1
275#define FXP_CB_COMMAND_CONFIG 0x2
276#define FXP_CB_COMMAND_MCAS 0x3
277#define FXP_CB_COMMAND_XMIT 0x4
278#define FXP_CB_COMMAND_UCODE 0x5
279#define FXP_CB_COMMAND_DUMP 0x6
280#define FXP_CB_COMMAND_DIAG 0x7
312 * Control Block (CB) definitions
313 */
314
315/* status */
316#define FXP_CB_STATUS_OK 0x2000
317#define FXP_CB_STATUS_C 0x8000
318/* commands */
319#define FXP_CB_COMMAND_NOP 0x0
320#define FXP_CB_COMMAND_IAS 0x1
321#define FXP_CB_COMMAND_CONFIG 0x2
322#define FXP_CB_COMMAND_MCAS 0x3
323#define FXP_CB_COMMAND_XMIT 0x4
324#define FXP_CB_COMMAND_UCODE 0x5
325#define FXP_CB_COMMAND_DUMP 0x6
326#define FXP_CB_COMMAND_DIAG 0x7
327#define FXP_CB_COMMAND_LOADFILT 0x8
328#define FXP_CB_COMMAND_IPCBXMIT 0x9
329
281/* command flags */
282#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
283#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
284#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
285#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
286
287/*
288 * RFA definitions
289 */
290
291struct fxp_rfa {
292 volatile u_int16_t rfa_status;
293 volatile u_int16_t rfa_control;
294 volatile u_int8_t link_addr[4];
295 volatile u_int8_t rbd_addr[4];
296 volatile u_int16_t actual_size;
297 volatile u_int16_t size;
330/* command flags */
331#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
332#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
333#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
334#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
335
336/*
337 * RFA definitions
338 */
339
340struct fxp_rfa {
341 volatile u_int16_t rfa_status;
342 volatile u_int16_t rfa_control;
343 volatile u_int8_t link_addr[4];
344 volatile u_int8_t rbd_addr[4];
345 volatile u_int16_t actual_size;
346 volatile u_int16_t size;
347
348 /*
349 * The following fields are only available when using
350 * extended receive mode on an 82550/82551 chipset.
351 */
352 volatile u_int16_t rfax_vlan_id;
353 volatile u_int8_t rfax_rx_parser_sts;
354 volatile u_int8_t rfax_rsvd0;
355 volatile u_int16_t rfax_security_sts;
356 volatile u_int8_t rfax_csum_sts;
357 volatile u_int8_t rfax_zerocopy_sts;
358 volatile u_int8_t rfax_pad[8];
298};
359};
360#define FXP_RFAX_LEN 16
361
299#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
300#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
362#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
363#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
364#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */
365#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */
301#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
302#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
303#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
304#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
305#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
306#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
307#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
308#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
309#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
310#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
311#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
312#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
313#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
314
366#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
367#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
368#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
369#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
370#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
371#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
372#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
373#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
374#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
375#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
376#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
377#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
378#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
379
380/* Bits in the 'csum_sts' byte */
381#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10
382#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20
383#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01
384#define FXP_RFDX_CS_IP_CSUM_VALID 0x02
385
386/* Bits in the 'packet parser' byte */
387#define FXP_RFDX_P_PARSE_BIT 0x08
388#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03
389#define FXP_RFDX_P_TCP_PACKET 0x00
390#define FXP_RFDX_P_UDP_PACKET 0x01
391#define FXP_RFDX_P_IP_PACKET 0x03
392
315/*
316 * Statistics dump area definitions
317 */
318struct fxp_stats {
319 volatile u_int32_t tx_good;
320 volatile u_int32_t tx_maxcols;
321 volatile u_int32_t tx_latecols;
322 volatile u_int32_t tx_underruns;

--- 64 unchanged lines hidden --- 		393/*
394 * Statistics dump area definitions
395 */
396struct fxp_stats {
397 volatile u_int32_t tx_good;
398 volatile u_int32_t tx_maxcols;
399 volatile u_int32_t tx_latecols;
400 volatile u_int32_t tx_underruns;

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