4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 *
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29 */ 30 31#define FXP_VENDORID_INTEL 0x8086 32 33#define FXP_PCI_MMBA 0x10 34#define FXP_PCI_IOBA 0x14 35 36/* 37 * Control/status registers. 38 */ 39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44#define FXP_CSR_PORT 8 /* port (4 bytes) */ 45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48 49/* 50 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 51 * 52 * volatile u_int8_t :2, 53 * scb_rus:4, 54 * scb_cus:2; 55 */ 56 57#define FXP_PORT_SOFTWARE_RESET 0 58#define FXP_PORT_SELFTEST 1 59#define FXP_PORT_SELECTIVE_RESET 2 60#define FXP_PORT_DUMP 3 61 62#define FXP_SCB_RUS_IDLE 0 63#define FXP_SCB_RUS_SUSPENDED 1 64#define FXP_SCB_RUS_NORESOURCES 2 65#define FXP_SCB_RUS_READY 4 66#define FXP_SCB_RUS_SUSP_NORBDS 9 67#define FXP_SCB_RUS_NORES_NORBDS 10 68#define FXP_SCB_RUS_READY_NORBDS 12 69 70#define FXP_SCB_CUS_IDLE 0 71#define FXP_SCB_CUS_SUSPENDED 1 72#define FXP_SCB_CUS_ACTIVE 2 73 74#define FXP_SCB_STATACK_SWI 0x04 75#define FXP_SCB_STATACK_MDI 0x08 76#define FXP_SCB_STATACK_RNR 0x10 77#define FXP_SCB_STATACK_CNA 0x20 78#define FXP_SCB_STATACK_FR 0x40 79#define FXP_SCB_STATACK_CXTNO 0x80 80 81#define FXP_SCB_COMMAND_CU_NOP 0x00 82#define FXP_SCB_COMMAND_CU_START 0x10 83#define FXP_SCB_COMMAND_CU_RESUME 0x20 84#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 85#define FXP_SCB_COMMAND_CU_DUMP 0x50 86#define FXP_SCB_COMMAND_CU_BASE 0x60 87#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 88 89#define FXP_SCB_COMMAND_RU_NOP 0 90#define FXP_SCB_COMMAND_RU_START 1 91#define FXP_SCB_COMMAND_RU_RESUME 2 92#define FXP_SCB_COMMAND_RU_ABORT 4 93#define FXP_SCB_COMMAND_RU_LOADHDS 5 94#define FXP_SCB_COMMAND_RU_BASE 6 95#define FXP_SCB_COMMAND_RU_RBDRESUME 7 96 97/* 98 * Command block definitions 99 */ 100struct fxp_cb_nop { 101 void *fill[2]; 102 volatile u_int16_t cb_status; 103 volatile u_int16_t cb_command; 104 volatile u_int32_t link_addr; 105}; 106struct fxp_cb_ias { 107 void *fill[2]; 108 volatile u_int16_t cb_status; 109 volatile u_int16_t cb_command; 110 volatile u_int32_t link_addr; 111 volatile u_int8_t macaddr[6]; 112}; 113/* I hate bit-fields :-( */ 114struct fxp_cb_config { 115 void *fill[2]; 116 volatile u_int16_t cb_status; 117 volatile u_int16_t cb_command; 118 volatile u_int32_t link_addr; 119 volatile u_int byte_count:6, 120 :2; 121 volatile u_int rx_fifo_limit:4, 122 tx_fifo_limit:3, 123 :1; 124 volatile u_int8_t adaptive_ifs; 125 volatile u_int mwi_enable:1, /* 8,9 */ 126 type_enable:1, /* 8,9 */ 127 read_align_en:1, /* 8,9 */ 128 end_wr_on_cl:1, /* 8,9 */ 129 :4; 130 volatile u_int rx_dma_bytecount:7, 131 :1; 132 volatile u_int tx_dma_bytecount:7, 133 dma_mbce:1; 134 volatile u_int late_scb:1, /* 7 */ 135 direct_dma_dis:1, /* 8,9 */ 136 tno_int_or_tco_en:1, /* 7,9 */ 137 ci_int:1, 138 ext_txcb_dis:1, /* 8,9 */ 139 ext_stats_dis:1, /* 8,9 */ 140 keep_overrun_rx:1, 141 save_bf:1; 142 volatile u_int disc_short_rx:1, 143 underrun_retry:2, 144 :3, 145 two_frames:1, /* 8,9 */ 146 dyn_tbd:1; /* 8,9 */ 147 volatile u_int mediatype:1, /* 7 */ 148 :6, 149 csma_dis:1; /* 8,9 */ 150 volatile u_int tcp_udp_cksum:1, /* 9 */ 151 :3, 152 vlan_tco:1, /* 8,9 */ 153 link_wake_en:1, /* 8,9 */ 154 arp_wake_en:1, /* 8 */ 155 mc_wake_en:1; /* 8 */ 156 volatile u_int :3, 157 nsai:1, 158 preamble_length:2, 159 loopback:2; 160 volatile u_int linear_priority:3, /* 7 */ 161 :5; 162 volatile u_int linear_pri_mode:1, /* 7 */ 163 :3, 164 interfrm_spacing:4; 165 volatile u_int :8; 166 volatile u_int :8; 167 volatile u_int promiscuous:1, 168 bcast_disable:1, 169 wait_after_win:1, /* 8,9 */ 170 :1, 171 ignore_ul:1, /* 8,9 */ 172 crc16_en:1, /* 9 */ 173 :1, 174 crscdt:1; 175 volatile u_int fc_delay_lsb:8; /* 8,9 */ 176 volatile u_int fc_delay_msb:8; /* 8,9 */ 177 volatile u_int stripping:1, 178 padding:1, 179 rcv_crc_xfer:1, 180 long_rx_en:1, /* 8,9 */ 181 pri_fc_thresh:3, /* 8,9 */ 182 :1; 183 volatile u_int ia_wake_en:1, /* 8 */ 184 magic_pkt_dis:1, /* 8,9,!9ER */ 185 tx_fc_dis:1, /* 8,9 */ 186 rx_fc_restop:1, /* 8,9 */ 187 rx_fc_restart:1, /* 8,9 */ 188 fc_filter:1, /* 8,9 */ 189 force_fdx:1, 190 fdx_pin_en:1; 191 volatile u_int :5, 192 pri_fc_loc:1, /* 8,9 */ 193 multi_ia:1, 194 :1; 195 volatile u_int :3, 196 mc_all:1, 197 :4; 198}; 199 200#define MAXMCADDR 80 201struct fxp_cb_mcs { 202 struct fxp_cb_tx *next; 203 struct mbuf *mb_head; 204 volatile u_int16_t cb_status; 205 volatile u_int16_t cb_command; 206 volatile u_int32_t link_addr; 207 volatile u_int16_t mc_cnt; 208 volatile u_int8_t mc_addr[MAXMCADDR][6]; 209}; 210 211/* 212 * Number of DMA segments in a TxCB. Note that this is carefully 213 * chosen to make the total struct size an even power of two. It's 214 * critical that no TxCB be split across a page boundry since 215 * no attempt is made to allocate physically contiguous memory. 216 * 217 */ 218#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 219#define FXP_NTXSEG 28 220#else 221#define FXP_NTXSEG 29 222#endif 223 224struct fxp_tbd { 225 volatile u_int32_t tb_addr; 226 volatile u_int32_t tb_size; 227}; 228struct fxp_cb_tx { 229 struct fxp_cb_tx *next; 230 struct mbuf *mb_head; 231 volatile u_int16_t cb_status; 232 volatile u_int16_t cb_command; 233 volatile u_int32_t link_addr; 234 volatile u_int32_t tbd_array_addr; 235 volatile u_int16_t byte_count; 236 volatile u_int8_t tx_threshold; 237 volatile u_int8_t tbd_number; 238 /*
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