1/* 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 11 unchanged lines hidden (view full) --- 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * |
28 * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 113017 2003-04-03 14:08:35Z mux $ |
29 */ 30 31#define FXP_VENDORID_INTEL 0x8086 32 33#define FXP_PCI_MMBA 0x10 34#define FXP_PCI_IOBA 0x14 35 36/* --- 69 unchanged lines hidden (view full) --- 106#define FXP_SCB_COMMAND_RU_LOADHDS 5 107#define FXP_SCB_COMMAND_RU_BASE 6 108#define FXP_SCB_COMMAND_RU_RBDRESUME 7 109 110/* 111 * Command block definitions 112 */ 113struct fxp_cb_nop { |
114 u_int16_t cb_status; 115 u_int16_t cb_command; 116 u_int32_t link_addr; |
117}; 118struct fxp_cb_ias { |
119 u_int16_t cb_status; 120 u_int16_t cb_command; 121 u_int32_t link_addr; 122 u_int8_t macaddr[6]; |
123}; 124/* I hate bit-fields :-( */ 125struct fxp_cb_config { |
126 u_int16_t cb_status; 127 u_int16_t cb_command; 128 u_int32_t link_addr; 129 u_int byte_count:6, 130 :2; 131 u_int rx_fifo_limit:4, 132 tx_fifo_limit:3, 133 :1; 134 u_int8_t adaptive_ifs; 135 u_int mwi_enable:1, /* 8,9 */ 136 type_enable:1, /* 8,9 */ 137 read_align_en:1, /* 8,9 */ 138 end_wr_on_cl:1, /* 8,9 */ 139 :4; 140 u_int rx_dma_bytecount:7, 141 :1; 142 u_int tx_dma_bytecount:7, 143 dma_mbce:1; 144 u_int late_scb:1, /* 7 */ 145 direct_dma_dis:1, /* 8,9 */ 146 tno_int_or_tco_en:1, /* 7,9 */ 147 ci_int:1, 148 ext_txcb_dis:1, /* 8,9 */ 149 ext_stats_dis:1, /* 8,9 */ 150 keep_overrun_rx:1, 151 save_bf:1; 152 u_int disc_short_rx:1, 153 underrun_retry:2, 154 :2, 155 ext_rfa:1, /* 550 */ 156 two_frames:1, /* 8,9 */ 157 dyn_tbd:1; /* 8,9 */ 158 u_int mediatype:1, /* 7 */ 159 :6, 160 csma_dis:1; /* 8,9 */ 161 u_int tcp_udp_cksum:1, /* 9 */ 162 :3, 163 vlan_tco:1, /* 8,9 */ 164 link_wake_en:1, /* 8,9 */ 165 arp_wake_en:1, /* 8 */ 166 mc_wake_en:1; /* 8 */ 167 u_int :3, 168 nsai:1, 169 preamble_length:2, 170 loopback:2; 171 u_int linear_priority:3, /* 7 */ 172 :5; 173 u_int linear_pri_mode:1, /* 7 */ 174 :3, 175 interfrm_spacing:4; 176 u_int :8; 177 u_int :8; 178 u_int promiscuous:1, 179 bcast_disable:1, 180 wait_after_win:1, /* 8,9 */ 181 :1, 182 ignore_ul:1, /* 8,9 */ 183 crc16_en:1, /* 9 */ 184 :1, 185 crscdt:1; 186 u_int fc_delay_lsb:8; /* 8,9 */ 187 u_int fc_delay_msb:8; /* 8,9 */ 188 u_int stripping:1, 189 padding:1, 190 rcv_crc_xfer:1, 191 long_rx_en:1, /* 8,9 */ 192 pri_fc_thresh:3, /* 8,9 */ 193 :1; 194 u_int ia_wake_en:1, /* 8 */ 195 magic_pkt_dis:1, /* 8,9,!9ER */ 196 tx_fc_dis:1, /* 8,9 */ 197 rx_fc_restop:1, /* 8,9 */ 198 rx_fc_restart:1, /* 8,9 */ 199 fc_filter:1, /* 8,9 */ 200 force_fdx:1, 201 fdx_pin_en:1; 202 u_int :5, 203 pri_fc_loc:1, /* 8,9 */ 204 multi_ia:1, 205 :1; 206 u_int :3, 207 mc_all:1, 208 :4; 209 u_int8_t gamla_rx:1; /* 550 */ 210 u_int8_t pad[9]; /* 550 */ |
211}; 212 213#define MAXMCADDR 80 214struct fxp_cb_mcs { |
215 u_int16_t cb_status; 216 u_int16_t cb_command; 217 u_int32_t link_addr; 218 u_int16_t mc_cnt; 219 u_int8_t mc_addr[MAXMCADDR][6]; |
220}; 221 222#define MAXUCODESIZE 192 223struct fxp_cb_ucode { 224 u_int16_t cb_status; 225 u_int16_t cb_command; 226 u_int32_t link_addr; 227 u_int32_t ucode[MAXUCODESIZE]; 228}; 229 230/* 231 * Number of DMA segments in a TxCB. 232 */ 233#define FXP_NTXSEG 32 234 235struct fxp_tbd { |
236 u_int32_t tb_addr; 237 u_int32_t tb_size; |
238}; 239 240struct fxp_ipcb { 241 /* 242 * The following fields are valid only when 243 * using the IPCB command block for TX checksum offload 244 * (and TCP large send, VLANs, and (I think) IPsec). To use 245 * them, you must enable extended TxCBs (available only 246 * on the 82559 and later) and use the IPCBXMIT command. 247 * Note that Intel defines the IPCB to be 32 bytes long, 248 * the last 8 bytes of which comprise the first entry 249 * in the TBD array (see note below). This means we only 250 * have to define 8 extra bytes here. 251 */ |
252 u_int16_t ipcb_schedule_low; 253 u_int8_t ipcb_ip_schedule; 254 u_int8_t ipcb_ip_activation_high; 255 u_int16_t ipcb_vlan_id; 256 u_int8_t ipcb_ip_header_offset; 257 u_int8_t ipcb_tcp_header_offset; |
258}; 259 260struct fxp_cb_tx { |
261 u_int16_t cb_status; 262 u_int16_t cb_command; 263 u_int32_t link_addr; 264 u_int32_t tbd_array_addr; 265 u_int16_t byte_count; 266 u_int8_t tx_threshold; 267 u_int8_t tbd_number; |
268 269 /* 270 * The following structure isn't actually part of the TxCB, 271 * unless the extended TxCB feature is being used. In this 272 * case, the first two elements of the structure below are 273 * fetched along with the TxCB. 274 */ 275 union { |
276 struct fxp_ipcb; 277 struct fxp_tbd tbd[FXP_NTXSEG]; |
278 } tx_cb_u; 279}; 280 281#define tbd tx_cb_u.tbd 282#define ipcb_schedule_low tx_cb_u.ipcb_schedule_low 283#define ipcb_ip_schedule tx_cb_u.ipcb_ip_schedule 284#define ipcb_ip_activation_high tx_cb_u.ipcb_ip_activation_high 285#define ipcb_vlan_id tx_cb_u.ipcb_vlan_id --- 35 unchanged lines hidden (view full) --- 321#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 322#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 323 324/* 325 * RFA definitions 326 */ 327 328struct fxp_rfa { |
329 u_int16_t rfa_status; 330 u_int16_t rfa_control; 331 u_int32_t link_addr; 332 u_int32_t rbd_addr; 333 u_int16_t actual_size; 334 u_int16_t size; |
335 336 /* 337 * The following fields are only available when using 338 * extended receive mode on an 82550/82551 chipset. 339 */ |
340 u_int16_t rfax_vlan_id; 341 u_int8_t rfax_rx_parser_sts; 342 u_int8_t rfax_rsvd0; 343 u_int16_t rfax_security_sts; 344 u_int8_t rfax_csum_sts; 345 u_int8_t rfax_zerocopy_sts; 346 u_int8_t rfax_pad[8]; |
347}; 348#define FXP_RFAX_LEN 16 349 350#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 351#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 352#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 353#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 354#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ --- 22 unchanged lines hidden (view full) --- 377#define FXP_RFDX_P_TCP_PACKET 0x00 378#define FXP_RFDX_P_UDP_PACKET 0x01 379#define FXP_RFDX_P_IP_PACKET 0x03 380 381/* 382 * Statistics dump area definitions 383 */ 384struct fxp_stats { |
385 u_int32_t tx_good; 386 u_int32_t tx_maxcols; 387 u_int32_t tx_latecols; 388 u_int32_t tx_underruns; 389 u_int32_t tx_lostcrs; 390 u_int32_t tx_deffered; 391 u_int32_t tx_single_collisions; 392 u_int32_t tx_multiple_collisions; 393 u_int32_t tx_total_collisions; 394 u_int32_t rx_good; 395 u_int32_t rx_crc_errors; 396 u_int32_t rx_alignment_errors; 397 u_int32_t rx_rnr_errors; 398 u_int32_t rx_overrun_errors; 399 u_int32_t rx_cdt_errors; 400 u_int32_t rx_shortframes; 401 u_int32_t completion_status; |
402}; 403#define FXP_STATS_DUMP_COMPLETE 0xa005 404#define FXP_STATS_DR_COMPLETE 0xa007 405 406/* 407 * Serial EEPROM control register bits 408 */ 409#define FXP_EEPROM_EESK 0x01 /* shift clock */ --- 43 unchanged lines hidden --- |