1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
27 * $Id: if_fxpreg.h,v 1.11 1997/09/29 11:27:42 davidg Exp $
| 27 * $Id: if_fxpreg.h,v 1.12 1998/03/03 14:19:09 dg Exp $
|
28 */
29
30#define FXP_VENDORID_INTEL 0x8086
31#define FXP_DEVICEID_i82557 0x1229
32
33#define FXP_PCI_MMBA 0x10
34#define FXP_PCI_IOBA 0x14
35
36/*
37 * Control/status registers.
38 */
39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
44#define FXP_CSR_PORT 8 /* port (4 bytes) */
45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
48
49/*
50 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
51 *
52 * volatile u_int8_t :2,
53 * scb_rus:4,
54 * scb_cus:2;
55 */
56
57#define FXP_PORT_SOFTWARE_RESET 0
58#define FXP_PORT_SELFTEST 1
59#define FXP_PORT_SELECTIVE_RESET 2
60#define FXP_PORT_DUMP 3
61
62#define FXP_SCB_RUS_IDLE 0
63#define FXP_SCB_RUS_SUSPENDED 1
64#define FXP_SCB_RUS_NORESOURCES 2
65#define FXP_SCB_RUS_READY 4
66#define FXP_SCB_RUS_SUSP_NORBDS 9
67#define FXP_SCB_RUS_NORES_NORBDS 10
68#define FXP_SCB_RUS_READY_NORBDS 12
69
70#define FXP_SCB_CUS_IDLE 0
71#define FXP_SCB_CUS_SUSPENDED 1
72#define FXP_SCB_CUS_ACTIVE 2
73
74#define FXP_SCB_STATACK_SWI 0x04
75#define FXP_SCB_STATACK_MDI 0x08
76#define FXP_SCB_STATACK_RNR 0x10
77#define FXP_SCB_STATACK_CNA 0x20
78#define FXP_SCB_STATACK_FR 0x40
79#define FXP_SCB_STATACK_CXTNO 0x80
80
81#define FXP_SCB_COMMAND_CU_NOP 0x00
82#define FXP_SCB_COMMAND_CU_START 0x10
83#define FXP_SCB_COMMAND_CU_RESUME 0x20
84#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
85#define FXP_SCB_COMMAND_CU_DUMP 0x50
86#define FXP_SCB_COMMAND_CU_BASE 0x60
87#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
88
89#define FXP_SCB_COMMAND_RU_NOP 0
90#define FXP_SCB_COMMAND_RU_START 1
91#define FXP_SCB_COMMAND_RU_RESUME 2
92#define FXP_SCB_COMMAND_RU_ABORT 4
93#define FXP_SCB_COMMAND_RU_LOADHDS 5
94#define FXP_SCB_COMMAND_RU_BASE 6
95#define FXP_SCB_COMMAND_RU_RBDRESUME 7
96
97/*
98 * Command block definitions
99 */
100struct fxp_cb_nop {
101 void *fill[2];
102 volatile u_int16_t cb_status;
103 volatile u_int16_t cb_command;
104 volatile u_int32_t link_addr;
105};
106struct fxp_cb_ias {
107 void *fill[2];
108 volatile u_int16_t cb_status;
109 volatile u_int16_t cb_command;
110 volatile u_int32_t link_addr;
111 volatile u_int8_t macaddr[6];
112};
113/* I hate bit-fields :-( */
114struct fxp_cb_config {
115 void *fill[2];
116 volatile u_int16_t cb_status;
117 volatile u_int16_t cb_command;
118 volatile u_int32_t link_addr;
| 28 */
29
30#define FXP_VENDORID_INTEL 0x8086
31#define FXP_DEVICEID_i82557 0x1229
32
33#define FXP_PCI_MMBA 0x10
34#define FXP_PCI_IOBA 0x14
35
36/*
37 * Control/status registers.
38 */
39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
44#define FXP_CSR_PORT 8 /* port (4 bytes) */
45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
48
49/*
50 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
51 *
52 * volatile u_int8_t :2,
53 * scb_rus:4,
54 * scb_cus:2;
55 */
56
57#define FXP_PORT_SOFTWARE_RESET 0
58#define FXP_PORT_SELFTEST 1
59#define FXP_PORT_SELECTIVE_RESET 2
60#define FXP_PORT_DUMP 3
61
62#define FXP_SCB_RUS_IDLE 0
63#define FXP_SCB_RUS_SUSPENDED 1
64#define FXP_SCB_RUS_NORESOURCES 2
65#define FXP_SCB_RUS_READY 4
66#define FXP_SCB_RUS_SUSP_NORBDS 9
67#define FXP_SCB_RUS_NORES_NORBDS 10
68#define FXP_SCB_RUS_READY_NORBDS 12
69
70#define FXP_SCB_CUS_IDLE 0
71#define FXP_SCB_CUS_SUSPENDED 1
72#define FXP_SCB_CUS_ACTIVE 2
73
74#define FXP_SCB_STATACK_SWI 0x04
75#define FXP_SCB_STATACK_MDI 0x08
76#define FXP_SCB_STATACK_RNR 0x10
77#define FXP_SCB_STATACK_CNA 0x20
78#define FXP_SCB_STATACK_FR 0x40
79#define FXP_SCB_STATACK_CXTNO 0x80
80
81#define FXP_SCB_COMMAND_CU_NOP 0x00
82#define FXP_SCB_COMMAND_CU_START 0x10
83#define FXP_SCB_COMMAND_CU_RESUME 0x20
84#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
85#define FXP_SCB_COMMAND_CU_DUMP 0x50
86#define FXP_SCB_COMMAND_CU_BASE 0x60
87#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
88
89#define FXP_SCB_COMMAND_RU_NOP 0
90#define FXP_SCB_COMMAND_RU_START 1
91#define FXP_SCB_COMMAND_RU_RESUME 2
92#define FXP_SCB_COMMAND_RU_ABORT 4
93#define FXP_SCB_COMMAND_RU_LOADHDS 5
94#define FXP_SCB_COMMAND_RU_BASE 6
95#define FXP_SCB_COMMAND_RU_RBDRESUME 7
96
97/*
98 * Command block definitions
99 */
100struct fxp_cb_nop {
101 void *fill[2];
102 volatile u_int16_t cb_status;
103 volatile u_int16_t cb_command;
104 volatile u_int32_t link_addr;
105};
106struct fxp_cb_ias {
107 void *fill[2];
108 volatile u_int16_t cb_status;
109 volatile u_int16_t cb_command;
110 volatile u_int32_t link_addr;
111 volatile u_int8_t macaddr[6];
112};
113/* I hate bit-fields :-( */
114struct fxp_cb_config {
115 void *fill[2];
116 volatile u_int16_t cb_status;
117 volatile u_int16_t cb_command;
118 volatile u_int32_t link_addr;
|
119 volatile u_int8_t byte_count:6,
| 119 volatile u_int byte_count:6,
|
120 :2;
| 120 :2;
|
121 volatile u_int8_t rx_fifo_limit:4,
| 121 volatile u_int rx_fifo_limit:4,
|
122 tx_fifo_limit:3,
123 :1;
124 volatile u_int8_t adaptive_ifs;
| 122 tx_fifo_limit:3,
123 :1;
124 volatile u_int8_t adaptive_ifs;
|
125 volatile u_int8_t :8;
126 volatile u_int8_t rx_dma_bytecount:7,
| 125 volatile u_int :8;
126 volatile u_int rx_dma_bytecount:7,
|
127 :1;
| 127 :1;
|
128 volatile u_int8_t tx_dma_bytecount:7,
| 128 volatile u_int tx_dma_bytecount:7,
|
129 dma_bce:1;
| 129 dma_bce:1;
|
130 volatile u_int8_t late_scb:1,
| 130 volatile u_int late_scb:1,
|
131 :1,
132 tno_int:1,
133 ci_int:1,
134 :3,
135 save_bf:1;
| 131 :1,
132 tno_int:1,
133 ci_int:1,
134 :3,
135 save_bf:1;
|
136 volatile u_int8_t disc_short_rx:1,
| 136 volatile u_int disc_short_rx:1,
|
137 underrun_retry:2,
138 :5;
| 137 underrun_retry:2,
138 :5;
|
139 volatile u_int8_t mediatype:1,
| 139 volatile u_int mediatype:1,
|
140 :7;
| 140 :7;
|
141 volatile u_int8_t :8;
142 volatile u_int8_t :3,
| 141 volatile u_int :8;
142 volatile u_int :3,
|
143 nsai:1,
144 preamble_length:2,
145 loopback:2;
| 143 nsai:1,
144 preamble_length:2,
145 loopback:2;
|
146 volatile u_int8_t linear_priority:3,
| 146 volatile u_int linear_priority:3,
|
147 :5;
| 147 :5;
|
148 volatile u_int8_t linear_pri_mode:1,
| 148 volatile u_int linear_pri_mode:1,
|
149 :3,
150 interfrm_spacing:4;
| 149 :3,
150 interfrm_spacing:4;
|
151 volatile u_int8_t :8;
152 volatile u_int8_t :8;
153 volatile u_int8_t promiscuous:1,
| 151 volatile u_int :8;
152 volatile u_int :8;
153 volatile u_int promiscuous:1,
|
154 bcast_disable:1,
155 :5,
156 crscdt:1;
| 154 bcast_disable:1,
155 :5,
156 crscdt:1;
|
157 volatile u_int8_t :8;
158 volatile u_int8_t :8;
159 volatile u_int8_t stripping:1,
| 157 volatile u_int :8;
158 volatile u_int :8;
159 volatile u_int stripping:1,
|
160 padding:1,
161 rcv_crc_xfer:1,
162 :5;
| 160 padding:1,
161 rcv_crc_xfer:1,
162 :5;
|
163 volatile u_int8_t :6,
| 163 volatile u_int :6,
|
164 force_fdx:1,
165 fdx_pin_en:1;
| 164 force_fdx:1,
165 fdx_pin_en:1;
|
166 volatile u_int8_t :6,
| 166 volatile u_int :6,
|
167 multi_ia:1,
168 :1;
| 167 multi_ia:1,
168 :1;
|
169 volatile u_int8_t :3,
| 169 volatile u_int :3,
|
170 mc_all:1,
171 :4;
172};
173
174#define MAXMCADDR 80
175struct fxp_cb_mcs {
176 struct fxp_cb_tx *next;
177 struct mbuf *mb_head;
178 volatile u_int16_t cb_status;
179 volatile u_int16_t cb_command;
180 volatile u_int32_t link_addr;
181 volatile u_int16_t mc_cnt;
182 volatile u_int8_t mc_addr[MAXMCADDR][6];
183};
184
185/*
186 * Number of DMA segments in a TxCB. Note that this is carefully
187 * chosen to make the total struct size an even power of two. It's
188 * critical that no TxCB be split across a page boundry since
189 * no attempt is made to allocate physically contiguous memory.
190 *
191 */
192#ifdef __alpha__ /* XXX - should be conditional on pointer size */
193#define FXP_NTXSEG 28
194#else
195#define FXP_NTXSEG 29
196#endif
197
198struct fxp_tbd {
199 volatile u_int32_t tb_addr;
200 volatile u_int32_t tb_size;
201};
202struct fxp_cb_tx {
203 struct fxp_cb_tx *next;
204 struct mbuf *mb_head;
205 volatile u_int16_t cb_status;
206 volatile u_int16_t cb_command;
207 volatile u_int32_t link_addr;
208 volatile u_int32_t tbd_array_addr;
209 volatile u_int16_t byte_count;
210 volatile u_int8_t tx_threshold;
211 volatile u_int8_t tbd_number;
212 /*
213 * The following isn't actually part of the TxCB.
214 */
215 volatile struct fxp_tbd tbd[FXP_NTXSEG];
216};
217
218/*
219 * Control Block (CB) definitions
220 */
221
222/* status */
223#define FXP_CB_STATUS_OK 0x2000
224#define FXP_CB_STATUS_C 0x8000
225/* commands */
226#define FXP_CB_COMMAND_NOP 0x0
227#define FXP_CB_COMMAND_IAS 0x1
228#define FXP_CB_COMMAND_CONFIG 0x2
229#define FXP_CB_COMMAND_MCAS 0x3
230#define FXP_CB_COMMAND_XMIT 0x4
231#define FXP_CB_COMMAND_RESRV 0x5
232#define FXP_CB_COMMAND_DUMP 0x6
233#define FXP_CB_COMMAND_DIAG 0x7
234/* command flags */
235#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
236#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
237#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
238#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
239
240/*
241 * RFA definitions
242 */
243
244struct fxp_rfa {
245 volatile u_int16_t rfa_status;
246 volatile u_int16_t rfa_control;
247 volatile u_int32_t link_addr;
248 volatile u_int32_t rbd_addr;
249 volatile u_int16_t actual_size;
250 volatile u_int16_t size;
251};
252#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
253#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
254#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
255#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
256#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
257#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
258#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
259#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
260#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
261#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
262#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
263#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
264#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
265#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
266#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
267
268/*
269 * Statistics dump area definitions
270 */
271struct fxp_stats {
272 volatile u_int32_t tx_good;
273 volatile u_int32_t tx_maxcols;
274 volatile u_int32_t tx_latecols;
275 volatile u_int32_t tx_underruns;
276 volatile u_int32_t tx_lostcrs;
277 volatile u_int32_t tx_deffered;
278 volatile u_int32_t tx_single_collisions;
279 volatile u_int32_t tx_multiple_collisions;
280 volatile u_int32_t tx_total_collisions;
281 volatile u_int32_t rx_good;
282 volatile u_int32_t rx_crc_errors;
283 volatile u_int32_t rx_alignment_errors;
284 volatile u_int32_t rx_rnr_errors;
285 volatile u_int32_t rx_overrun_errors;
286 volatile u_int32_t rx_cdt_errors;
287 volatile u_int32_t rx_shortframes;
288 volatile u_int32_t completion_status;
289};
290#define FXP_STATS_DUMP_COMPLETE 0xa005
291#define FXP_STATS_DR_COMPLETE 0xa007
292
293/*
294 * Serial EEPROM control register bits
295 */
296/* shift clock */
297#define FXP_EEPROM_EESK 0x01
298/* chip select */
299#define FXP_EEPROM_EECS 0x02
300/* data in */
301#define FXP_EEPROM_EEDI 0x04
302/* data out */
303#define FXP_EEPROM_EEDO 0x08
304
305/*
306 * Serial EEPROM opcodes, including start bit
307 */
308#define FXP_EEPROM_OPC_ERASE 0x4
309#define FXP_EEPROM_OPC_WRITE 0x5
310#define FXP_EEPROM_OPC_READ 0x6
311
312/*
313 * Management Data Interface opcodes
314 */
315#define FXP_MDI_WRITE 0x1
316#define FXP_MDI_READ 0x2
317
318/*
319 * PHY device types
320 */
321#define FXP_PHY_NONE 0
322#define FXP_PHY_82553A 1
323#define FXP_PHY_82553C 2
324#define FXP_PHY_82503 3
325#define FXP_PHY_DP83840 4
326#define FXP_PHY_80C240 5
327#define FXP_PHY_80C24 6
328#define FXP_PHY_82555 7
329#define FXP_PHY_DP83840A 10
330#define FXP_PHY_82555B 11
331
332/*
333 * PHY BMCR Basic Mode Control Register
334 */
335#define FXP_PHY_BMCR 0x0
336#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
337#define FXP_PHY_BMCR_AUTOEN 0x1000
338#define FXP_PHY_BMCR_SPEED_100M 0x2000
339
340/*
341 * DP84830 PHY, PCS Configuration Register
342 */
343#define FXP_DP83840_PCR 0x17
344#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */
345#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */
346#define FXP_DP83840_PCR_BIT8 0x0100
347#define FXP_DP83840_PCR_BIT10 0x0400
| 170 mc_all:1,
171 :4;
172};
173
174#define MAXMCADDR 80
175struct fxp_cb_mcs {
176 struct fxp_cb_tx *next;
177 struct mbuf *mb_head;
178 volatile u_int16_t cb_status;
179 volatile u_int16_t cb_command;
180 volatile u_int32_t link_addr;
181 volatile u_int16_t mc_cnt;
182 volatile u_int8_t mc_addr[MAXMCADDR][6];
183};
184
185/*
186 * Number of DMA segments in a TxCB. Note that this is carefully
187 * chosen to make the total struct size an even power of two. It's
188 * critical that no TxCB be split across a page boundry since
189 * no attempt is made to allocate physically contiguous memory.
190 *
191 */
192#ifdef __alpha__ /* XXX - should be conditional on pointer size */
193#define FXP_NTXSEG 28
194#else
195#define FXP_NTXSEG 29
196#endif
197
198struct fxp_tbd {
199 volatile u_int32_t tb_addr;
200 volatile u_int32_t tb_size;
201};
202struct fxp_cb_tx {
203 struct fxp_cb_tx *next;
204 struct mbuf *mb_head;
205 volatile u_int16_t cb_status;
206 volatile u_int16_t cb_command;
207 volatile u_int32_t link_addr;
208 volatile u_int32_t tbd_array_addr;
209 volatile u_int16_t byte_count;
210 volatile u_int8_t tx_threshold;
211 volatile u_int8_t tbd_number;
212 /*
213 * The following isn't actually part of the TxCB.
214 */
215 volatile struct fxp_tbd tbd[FXP_NTXSEG];
216};
217
218/*
219 * Control Block (CB) definitions
220 */
221
222/* status */
223#define FXP_CB_STATUS_OK 0x2000
224#define FXP_CB_STATUS_C 0x8000
225/* commands */
226#define FXP_CB_COMMAND_NOP 0x0
227#define FXP_CB_COMMAND_IAS 0x1
228#define FXP_CB_COMMAND_CONFIG 0x2
229#define FXP_CB_COMMAND_MCAS 0x3
230#define FXP_CB_COMMAND_XMIT 0x4
231#define FXP_CB_COMMAND_RESRV 0x5
232#define FXP_CB_COMMAND_DUMP 0x6
233#define FXP_CB_COMMAND_DIAG 0x7
234/* command flags */
235#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
236#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
237#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
238#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
239
240/*
241 * RFA definitions
242 */
243
244struct fxp_rfa {
245 volatile u_int16_t rfa_status;
246 volatile u_int16_t rfa_control;
247 volatile u_int32_t link_addr;
248 volatile u_int32_t rbd_addr;
249 volatile u_int16_t actual_size;
250 volatile u_int16_t size;
251};
252#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
253#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
254#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
255#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
256#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
257#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
258#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
259#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
260#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
261#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
262#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
263#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
264#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
265#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
266#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
267
268/*
269 * Statistics dump area definitions
270 */
271struct fxp_stats {
272 volatile u_int32_t tx_good;
273 volatile u_int32_t tx_maxcols;
274 volatile u_int32_t tx_latecols;
275 volatile u_int32_t tx_underruns;
276 volatile u_int32_t tx_lostcrs;
277 volatile u_int32_t tx_deffered;
278 volatile u_int32_t tx_single_collisions;
279 volatile u_int32_t tx_multiple_collisions;
280 volatile u_int32_t tx_total_collisions;
281 volatile u_int32_t rx_good;
282 volatile u_int32_t rx_crc_errors;
283 volatile u_int32_t rx_alignment_errors;
284 volatile u_int32_t rx_rnr_errors;
285 volatile u_int32_t rx_overrun_errors;
286 volatile u_int32_t rx_cdt_errors;
287 volatile u_int32_t rx_shortframes;
288 volatile u_int32_t completion_status;
289};
290#define FXP_STATS_DUMP_COMPLETE 0xa005
291#define FXP_STATS_DR_COMPLETE 0xa007
292
293/*
294 * Serial EEPROM control register bits
295 */
296/* shift clock */
297#define FXP_EEPROM_EESK 0x01
298/* chip select */
299#define FXP_EEPROM_EECS 0x02
300/* data in */
301#define FXP_EEPROM_EEDI 0x04
302/* data out */
303#define FXP_EEPROM_EEDO 0x08
304
305/*
306 * Serial EEPROM opcodes, including start bit
307 */
308#define FXP_EEPROM_OPC_ERASE 0x4
309#define FXP_EEPROM_OPC_WRITE 0x5
310#define FXP_EEPROM_OPC_READ 0x6
311
312/*
313 * Management Data Interface opcodes
314 */
315#define FXP_MDI_WRITE 0x1
316#define FXP_MDI_READ 0x2
317
318/*
319 * PHY device types
320 */
321#define FXP_PHY_NONE 0
322#define FXP_PHY_82553A 1
323#define FXP_PHY_82553C 2
324#define FXP_PHY_82503 3
325#define FXP_PHY_DP83840 4
326#define FXP_PHY_80C240 5
327#define FXP_PHY_80C24 6
328#define FXP_PHY_82555 7
329#define FXP_PHY_DP83840A 10
330#define FXP_PHY_82555B 11
331
332/*
333 * PHY BMCR Basic Mode Control Register
334 */
335#define FXP_PHY_BMCR 0x0
336#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
337#define FXP_PHY_BMCR_AUTOEN 0x1000
338#define FXP_PHY_BMCR_SPEED_100M 0x2000
339
340/*
341 * DP84830 PHY, PCS Configuration Register
342 */
343#define FXP_DP83840_PCR 0x17
344#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */
345#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */
346#define FXP_DP83840_PCR_BIT8 0x0100
347#define FXP_DP83840_PCR_BIT10 0x0400
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