1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id$
28 */
29
30#define FXP_VENDORID_INTEL 0x8086
31#define FXP_DEVICEID_i82557 0x1229
32
33#define FXP_PCI_MMBA 0x10
34#define FXP_PCI_IOBA 0x14
35
36/*
37 * Control/status registers.
38 */
39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
44#define FXP_CSR_PORT 8 /* port (4 bytes) */
45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
48
49/*
50 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
51 *
52 * volatile u_int8_t :2,
53 * scb_rus:4,
54 * scb_cus:2;
55 */
56
57#define FXP_PORT_SOFTWARE_RESET 0
58#define FXP_PORT_SELFTEST 1
59#define FXP_PORT_SELECTIVE_RESET 2
60#define FXP_PORT_DUMP 3
61
62#define FXP_SCB_RUS_IDLE 0
63#define FXP_SCB_RUS_SUSPENDED 1
64#define FXP_SCB_RUS_NORESOURCES 2
65#define FXP_SCB_RUS_READY 4
66#define FXP_SCB_RUS_SUSP_NORBDS 9
67#define FXP_SCB_RUS_NORES_NORBDS 10
68#define FXP_SCB_RUS_READY_NORBDS 12
69
70#define FXP_SCB_CUS_IDLE 0
71#define FXP_SCB_CUS_SUSPENDED 1
72#define FXP_SCB_CUS_ACTIVE 2
73
74#define FXP_SCB_STATACK_SWI 0x04
75#define FXP_SCB_STATACK_MDI 0x08
76#define FXP_SCB_STATACK_RNR 0x10
77#define FXP_SCB_STATACK_CNA 0x20
78#define FXP_SCB_STATACK_FR 0x40
79#define FXP_SCB_STATACK_CXTNO 0x80
80
81#define FXP_SCB_COMMAND_MASK 0xff
82#define FXP_SCB_COMMAND_CU_NOP 0x00
83#define FXP_SCB_COMMAND_CU_START 0x10
84#define FXP_SCB_COMMAND_CU_RESUME 0x20
85#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
86#define FXP_SCB_COMMAND_CU_DUMP 0x50
87#define FXP_SCB_COMMAND_CU_BASE 0x60
88#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
89
90#define FXP_SCB_COMMAND_RU_NOP 0
91#define FXP_SCB_COMMAND_RU_START 1
92#define FXP_SCB_COMMAND_RU_RESUME 2
93#define FXP_SCB_COMMAND_RU_ABORT 4
94#define FXP_SCB_COMMAND_RU_LOADHDS 5
95#define FXP_SCB_COMMAND_RU_BASE 6
96#define FXP_SCB_COMMAND_RU_RBDRESUME 7
97
98/*
99 * Command block definitions
100 */
101struct fxp_cb_nop {
102 volatile u_int16_t cb_status;
103 volatile u_int16_t cb_command;
104 volatile u_int32_t link_addr;
105};
106struct fxp_cb_ias {
107 volatile u_int16_t cb_status;
108 volatile u_int16_t cb_command;
109 volatile u_int32_t link_addr;
110 volatile u_int8_t macaddr[6];
111};
112/* I hate bit-fields :-( */
113struct fxp_cb_config {
114 volatile u_int16_t cb_status;
115 volatile u_int16_t cb_command;
116 volatile u_int32_t link_addr;
117 volatile u_int8_t byte_count:6,
118 :2;
119 volatile u_int8_t rx_fifo_limit:4,
120 tx_fifo_limit:3,
121 :1;
122 volatile u_int8_t adaptive_ifs;
123 volatile u_int8_t :8;
124 volatile u_int8_t rx_dma_bytecount:7,
125 :1;
126 volatile u_int8_t tx_dma_bytecount:7,
127 dma_bce:1;
128 volatile u_int8_t late_scb:1,
129 :1,
130 tno_int:1,
131 ci_int:1,
132 :3,
133 save_bf:1;
134 volatile u_int8_t disc_short_rx:1,
135 underrun_retry:2,
136 :5;
137 volatile u_int8_t mediatype:1,
138 :7;
139 volatile u_int8_t :8;
140 volatile u_int8_t :3,
141 nsai:1,
142 preamble_length:2,
143 loopback:2;
144 volatile u_int8_t linear_priority:3,
145 :5;
146 volatile u_int8_t linear_pri_mode:1,
147 :3,
148 interfrm_spacing:4;
149 volatile u_int8_t :8;
150 volatile u_int8_t :8;
151 volatile u_int8_t promiscuous:1,
152 bcast_disable:1,
153 :5,
154 crscdt:1;
155 volatile u_int8_t :8;
156 volatile u_int8_t :8;
157 volatile u_int8_t stripping:1,
158 padding:1,
159 rcv_crc_xfer:1,
160 :5;
161 volatile u_int8_t :6,
162 force_fdx:1,
163 fdx_pin_en:1;
164 volatile u_int8_t :6,
165 multi_ia:1,
166 :1;
167 volatile u_int8_t :3,
168 mc_all:1,
169 :4;
170};
171struct fxp_tbd {
172 volatile u_int32_t tb_addr;
173 volatile u_int32_t tb_size;
174};
175
176struct fxp_cb_tx {
177 volatile u_int16_t cb_status;
178 volatile u_int16_t cb_command;
179 volatile u_int32_t link_addr;
180 volatile u_int32_t tbd_array_addr;
181 volatile u_int16_t byte_count;
182 volatile u_int8_t tx_threshold;
183 volatile u_int8_t tbd_number;
184 /*
185 * The following isn't actually part of the TxCB.
186 */
187 volatile struct fxp_tbd tbd[29];
188 struct mbuf *mb_head;
189 struct fxp_cb_tx *next;
190};
191
192/*
193 * Control Block (CB) definitions
194 */
195
196/* status */
197#define FXP_CB_STATUS_OK 0x2000
198#define FXP_CB_STATUS_C 0x8000
199/* commands */
200#define FXP_CB_COMMAND_NOP 0x0
201#define FXP_CB_COMMAND_IAS 0x1
202#define FXP_CB_COMMAND_CONFIG 0x2
203#define FXP_CB_COMMAND_MAS 0x3
204#define FXP_CB_COMMAND_XMIT 0x4
205#define FXP_CB_COMMAND_RESRV 0x5
206#define FXP_CB_COMMAND_DUMP 0x6
207#define FXP_CB_COMMAND_DIAG 0x7
208/* command flags */
209#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
210#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
211#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
212#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
213
214/*
215 * RFA definitions
216 */
217
218struct fxp_rfa {
219 volatile u_int16_t rfa_status;
220 volatile u_int16_t rfa_control;
221 volatile u_int32_t link_addr;
222 volatile u_int32_t rbd_addr;
223 volatile u_int16_t actual_size;
224 volatile u_int16_t size;
225};
226#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
227#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
228#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
229#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
230#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
231#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
232#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
233#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
234#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
235#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
236#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
237#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
238#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
239#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
240#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
241
242/*
243 * Statistics dump area definitions
244 */
245struct fxp_stats {
246 volatile u_int32_t tx_good;
247 volatile u_int32_t tx_maxcols;
248 volatile u_int32_t tx_latecols;
249 volatile u_int32_t tx_underruns;
250 volatile u_int32_t tx_lostcrs;
251 volatile u_int32_t tx_deffered;
252 volatile u_int32_t tx_single_collisions;
253 volatile u_int32_t tx_multiple_collisions;
254 volatile u_int32_t tx_total_collisions;
255 volatile u_int32_t rx_good;
256 volatile u_int32_t rx_crc_errors;
257 volatile u_int32_t rx_alignment_errors;
258 volatile u_int32_t rx_rnr_errors;
259 volatile u_int32_t rx_overrun_errors;
260 volatile u_int32_t rx_cdt_errors;
261 volatile u_int32_t rx_shortframes;
262 volatile u_int32_t completion_status;
263};
264#define FXP_STATS_DUMP_COMPLETE 0xa005
265#define FXP_STATS_DR_COMPLETE 0xa007
266
267/*
268 * Serial EEPROM control register bits
269 */
270/* shift clock */
271#define FXP_EEPROM_EESK 0x01
272/* chip select */
273#define FXP_EEPROM_EECS 0x02
274/* data in */
275#define FXP_EEPROM_EEDI 0x04
276/* data out */
277#define FXP_EEPROM_EEDO 0x08
278
279/*
280 * Serial EEPROM opcodes, including start bit
281 */
282#define FXP_EEPROM_OPC_ERASE 0x4
283#define FXP_EEPROM_OPC_WRITE 0x5
284#define FXP_EEPROM_OPC_READ 0x6
285
286/*
287 * Management Data Interface opcodes
288 */
289#define FXP_MDI_WRITE 0x1
290#define FXP_MDI_READ 0x2
291
292/*
293 * PHY device types
294 */
295#define FXP_PHY_NONE 0
296#define FXP_PHY_82553A 1
297#define FXP_PHY_82553C 2
298#define FXP_PHY_82503 3
299#define FXP_PHY_DP83840 4
300#define FXP_PHY_80C240 5
301#define FXP_PHY_80C24 6
302#define FXP_PHY_82555 7
303#define FXP_PHY_DP83840A 10
304
305/*
306 * PHY BMCR Basic Mode Control Register
307 */
308#define FXP_PHY_BMCR 0x0
309#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
310#define FXP_PHY_BMCR_AUTOEN 0x1000
311#define FXP_PHY_BMCR_SPEED_100M 0x2000
312
313/*
314 * DP84830 PHY, PCS Configuration Register
315 */
316#define FXP_DP83840_PCR 0x17
317#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */
318#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */
319#define FXP_DP83840_PCR_BIT8 0x0100
320#define FXP_DP83840_PCR_BIT10 0x0400
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id$
28 */
29
30#define FXP_VENDORID_INTEL 0x8086
31#define FXP_DEVICEID_i82557 0x1229
32
33#define FXP_PCI_MMBA 0x10
34#define FXP_PCI_IOBA 0x14
35
36/*
37 * Control/status registers.
38 */
39#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
40#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
41#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
42#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
44#define FXP_CSR_PORT 8 /* port (4 bytes) */
45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
48
49/*
50 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
51 *
52 * volatile u_int8_t :2,
53 * scb_rus:4,
54 * scb_cus:2;
55 */
56
57#define FXP_PORT_SOFTWARE_RESET 0
58#define FXP_PORT_SELFTEST 1
59#define FXP_PORT_SELECTIVE_RESET 2
60#define FXP_PORT_DUMP 3
61
62#define FXP_SCB_RUS_IDLE 0
63#define FXP_SCB_RUS_SUSPENDED 1
64#define FXP_SCB_RUS_NORESOURCES 2
65#define FXP_SCB_RUS_READY 4
66#define FXP_SCB_RUS_SUSP_NORBDS 9
67#define FXP_SCB_RUS_NORES_NORBDS 10
68#define FXP_SCB_RUS_READY_NORBDS 12
69
70#define FXP_SCB_CUS_IDLE 0
71#define FXP_SCB_CUS_SUSPENDED 1
72#define FXP_SCB_CUS_ACTIVE 2
73
74#define FXP_SCB_STATACK_SWI 0x04
75#define FXP_SCB_STATACK_MDI 0x08
76#define FXP_SCB_STATACK_RNR 0x10
77#define FXP_SCB_STATACK_CNA 0x20
78#define FXP_SCB_STATACK_FR 0x40
79#define FXP_SCB_STATACK_CXTNO 0x80
80
81#define FXP_SCB_COMMAND_MASK 0xff
82#define FXP_SCB_COMMAND_CU_NOP 0x00
83#define FXP_SCB_COMMAND_CU_START 0x10
84#define FXP_SCB_COMMAND_CU_RESUME 0x20
85#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
86#define FXP_SCB_COMMAND_CU_DUMP 0x50
87#define FXP_SCB_COMMAND_CU_BASE 0x60
88#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
89
90#define FXP_SCB_COMMAND_RU_NOP 0
91#define FXP_SCB_COMMAND_RU_START 1
92#define FXP_SCB_COMMAND_RU_RESUME 2
93#define FXP_SCB_COMMAND_RU_ABORT 4
94#define FXP_SCB_COMMAND_RU_LOADHDS 5
95#define FXP_SCB_COMMAND_RU_BASE 6
96#define FXP_SCB_COMMAND_RU_RBDRESUME 7
97
98/*
99 * Command block definitions
100 */
101struct fxp_cb_nop {
102 volatile u_int16_t cb_status;
103 volatile u_int16_t cb_command;
104 volatile u_int32_t link_addr;
105};
106struct fxp_cb_ias {
107 volatile u_int16_t cb_status;
108 volatile u_int16_t cb_command;
109 volatile u_int32_t link_addr;
110 volatile u_int8_t macaddr[6];
111};
112/* I hate bit-fields :-( */
113struct fxp_cb_config {
114 volatile u_int16_t cb_status;
115 volatile u_int16_t cb_command;
116 volatile u_int32_t link_addr;
117 volatile u_int8_t byte_count:6,
118 :2;
119 volatile u_int8_t rx_fifo_limit:4,
120 tx_fifo_limit:3,
121 :1;
122 volatile u_int8_t adaptive_ifs;
123 volatile u_int8_t :8;
124 volatile u_int8_t rx_dma_bytecount:7,
125 :1;
126 volatile u_int8_t tx_dma_bytecount:7,
127 dma_bce:1;
128 volatile u_int8_t late_scb:1,
129 :1,
130 tno_int:1,
131 ci_int:1,
132 :3,
133 save_bf:1;
134 volatile u_int8_t disc_short_rx:1,
135 underrun_retry:2,
136 :5;
137 volatile u_int8_t mediatype:1,
138 :7;
139 volatile u_int8_t :8;
140 volatile u_int8_t :3,
141 nsai:1,
142 preamble_length:2,
143 loopback:2;
144 volatile u_int8_t linear_priority:3,
145 :5;
146 volatile u_int8_t linear_pri_mode:1,
147 :3,
148 interfrm_spacing:4;
149 volatile u_int8_t :8;
150 volatile u_int8_t :8;
151 volatile u_int8_t promiscuous:1,
152 bcast_disable:1,
153 :5,
154 crscdt:1;
155 volatile u_int8_t :8;
156 volatile u_int8_t :8;
157 volatile u_int8_t stripping:1,
158 padding:1,
159 rcv_crc_xfer:1,
160 :5;
161 volatile u_int8_t :6,
162 force_fdx:1,
163 fdx_pin_en:1;
164 volatile u_int8_t :6,
165 multi_ia:1,
166 :1;
167 volatile u_int8_t :3,
168 mc_all:1,
169 :4;
170};
171struct fxp_tbd {
172 volatile u_int32_t tb_addr;
173 volatile u_int32_t tb_size;
174};
175
176struct fxp_cb_tx {
177 volatile u_int16_t cb_status;
178 volatile u_int16_t cb_command;
179 volatile u_int32_t link_addr;
180 volatile u_int32_t tbd_array_addr;
181 volatile u_int16_t byte_count;
182 volatile u_int8_t tx_threshold;
183 volatile u_int8_t tbd_number;
184 /*
185 * The following isn't actually part of the TxCB.
186 */
187 volatile struct fxp_tbd tbd[29];
188 struct mbuf *mb_head;
189 struct fxp_cb_tx *next;
190};
191
192/*
193 * Control Block (CB) definitions
194 */
195
196/* status */
197#define FXP_CB_STATUS_OK 0x2000
198#define FXP_CB_STATUS_C 0x8000
199/* commands */
200#define FXP_CB_COMMAND_NOP 0x0
201#define FXP_CB_COMMAND_IAS 0x1
202#define FXP_CB_COMMAND_CONFIG 0x2
203#define FXP_CB_COMMAND_MAS 0x3
204#define FXP_CB_COMMAND_XMIT 0x4
205#define FXP_CB_COMMAND_RESRV 0x5
206#define FXP_CB_COMMAND_DUMP 0x6
207#define FXP_CB_COMMAND_DIAG 0x7
208/* command flags */
209#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
210#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
211#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
212#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
213
214/*
215 * RFA definitions
216 */
217
218struct fxp_rfa {
219 volatile u_int16_t rfa_status;
220 volatile u_int16_t rfa_control;
221 volatile u_int32_t link_addr;
222 volatile u_int32_t rbd_addr;
223 volatile u_int16_t actual_size;
224 volatile u_int16_t size;
225};
226#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
227#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
228#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
229#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
230#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
231#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
232#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
233#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
234#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
235#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
236#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
237#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
238#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
239#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
240#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
241
242/*
243 * Statistics dump area definitions
244 */
245struct fxp_stats {
246 volatile u_int32_t tx_good;
247 volatile u_int32_t tx_maxcols;
248 volatile u_int32_t tx_latecols;
249 volatile u_int32_t tx_underruns;
250 volatile u_int32_t tx_lostcrs;
251 volatile u_int32_t tx_deffered;
252 volatile u_int32_t tx_single_collisions;
253 volatile u_int32_t tx_multiple_collisions;
254 volatile u_int32_t tx_total_collisions;
255 volatile u_int32_t rx_good;
256 volatile u_int32_t rx_crc_errors;
257 volatile u_int32_t rx_alignment_errors;
258 volatile u_int32_t rx_rnr_errors;
259 volatile u_int32_t rx_overrun_errors;
260 volatile u_int32_t rx_cdt_errors;
261 volatile u_int32_t rx_shortframes;
262 volatile u_int32_t completion_status;
263};
264#define FXP_STATS_DUMP_COMPLETE 0xa005
265#define FXP_STATS_DR_COMPLETE 0xa007
266
267/*
268 * Serial EEPROM control register bits
269 */
270/* shift clock */
271#define FXP_EEPROM_EESK 0x01
272/* chip select */
273#define FXP_EEPROM_EECS 0x02
274/* data in */
275#define FXP_EEPROM_EEDI 0x04
276/* data out */
277#define FXP_EEPROM_EEDO 0x08
278
279/*
280 * Serial EEPROM opcodes, including start bit
281 */
282#define FXP_EEPROM_OPC_ERASE 0x4
283#define FXP_EEPROM_OPC_WRITE 0x5
284#define FXP_EEPROM_OPC_READ 0x6
285
286/*
287 * Management Data Interface opcodes
288 */
289#define FXP_MDI_WRITE 0x1
290#define FXP_MDI_READ 0x2
291
292/*
293 * PHY device types
294 */
295#define FXP_PHY_NONE 0
296#define FXP_PHY_82553A 1
297#define FXP_PHY_82553C 2
298#define FXP_PHY_82503 3
299#define FXP_PHY_DP83840 4
300#define FXP_PHY_80C240 5
301#define FXP_PHY_80C24 6
302#define FXP_PHY_82555 7
303#define FXP_PHY_DP83840A 10
304
305/*
306 * PHY BMCR Basic Mode Control Register
307 */
308#define FXP_PHY_BMCR 0x0
309#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
310#define FXP_PHY_BMCR_AUTOEN 0x1000
311#define FXP_PHY_BMCR_SPEED_100M 0x2000
312
313/*
314 * DP84830 PHY, PCS Configuration Register
315 */
316#define FXP_DP83840_PCR 0x17
317#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */
318#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */
319#define FXP_DP83840_PCR_BIT8 0x0100
320#define FXP_DP83840_PCR_BIT10 0x0400