1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Modifications to support NetBSD and media selection:
6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
| 1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Modifications to support NetBSD and media selection:
6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
|
30 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 66006 2000-09-17 22:01:21Z cp $
| 30 * $FreeBSD: head/sys/dev/fxp/if_fxp.c 66007 2000-09-17 22:12:12Z dg $
|
31 */
32
33/*
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/mbuf.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/socket.h>
43
44#include <net/if.h>
45#include <net/if_dl.h>
46#include <net/if_media.h>
47
48#ifdef NS
49#include <netns/ns.h>
50#include <netns/ns_if.h>
51#endif
52
53#include <net/bpf.h>
54
55#if defined(__NetBSD__)
56
57#include <sys/ioctl.h>
58#include <sys/errno.h>
59#include <sys/device.h>
60
61#include <net/if_dl.h>
62#include <net/if_ether.h>
63
64#include <netinet/if_inarp.h>
65
66#include <vm/vm.h>
67
68#include <machine/cpu.h>
69#include <machine/bus.h>
70#include <machine/intr.h>
71
72#include <dev/pci/if_fxpreg.h>
73#include <dev/pci/if_fxpvar.h>
74
75#include <dev/pci/pcivar.h>
76#include <dev/pci/pcireg.h>
77#include <dev/pci/pcidevs.h>
78
79
80#else /* __FreeBSD__ */
81
82#include <sys/sockio.h>
83#include <sys/bus.h>
84#include <machine/bus.h>
85#include <sys/rman.h>
86#include <machine/resource.h>
87#include <sys/proc.h>
88#include <machine/mutex.h>
89
90#include <net/ethernet.h>
91#include <net/if_arp.h>
92
93#include <vm/vm.h> /* for vtophys */
94#include <vm/pmap.h> /* for vtophys */
95#include <machine/clock.h> /* for DELAY */
96
97#include <pci/pcivar.h>
98#include <pci/pcireg.h> /* for PCIM_CMD_xxx */
99#include <pci/if_fxpreg.h>
100#include <pci/if_fxpvar.h>
101
102#endif /* __NetBSD__ */
103
104#ifdef __alpha__ /* XXX */
105/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
106#undef vtophys
107#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
108#endif /* __alpha__ */
109
110/*
111 * NOTE! On the Alpha, we have an alignment constraint. The
112 * card DMAs the packet immediately following the RFA. However,
113 * the first thing in the packet is a 14-byte Ethernet header.
114 * This means that the packet is misaligned. To compensate,
115 * we actually offset the RFA 2 bytes into the cluster. This
116 * alignes the packet after the Ethernet header at a 32-bit
117 * boundary. HOWEVER! This means that the RFA is misaligned!
118 */
119#define RFA_ALIGNMENT_FUDGE 2
120
121/*
122 * Inline function to copy a 16-bit aligned 32-bit quantity.
123 */
124static __inline void fxp_lwcopy __P((volatile u_int32_t *,
125 volatile u_int32_t *));
126static __inline void
127fxp_lwcopy(src, dst)
128 volatile u_int32_t *src, *dst;
129{
130#ifdef __i386__
131 *dst = *src;
132#else
133 volatile u_int16_t *a = (volatile u_int16_t *)src;
134 volatile u_int16_t *b = (volatile u_int16_t *)dst;
135
136 b[0] = a[0];
137 b[1] = a[1];
138#endif
139}
140
141/*
142 * Template for default configuration parameters.
143 * See struct fxp_cb_config for the bit definitions.
144 */
145static u_char fxp_cb_config_template[] = {
146 0x0, 0x0, /* cb_status */
147 0x80, 0x2, /* cb_command */
148 0xff, 0xff, 0xff, 0xff, /* link_addr */
149 0x16, /* 0 */
150 0x8, /* 1 */
151 0x0, /* 2 */
152 0x0, /* 3 */
153 0x0, /* 4 */
154 0x80, /* 5 */
155 0xb2, /* 6 */
156 0x3, /* 7 */
157 0x1, /* 8 */
158 0x0, /* 9 */
159 0x26, /* 10 */
160 0x0, /* 11 */
161 0x60, /* 12 */
162 0x0, /* 13 */
163 0xf2, /* 14 */
164 0x48, /* 15 */
165 0x0, /* 16 */
166 0x40, /* 17 */
167 0xf3, /* 18 */
168 0x0, /* 19 */
169 0x3f, /* 20 */
170 0x5 /* 21 */
171};
172
173/* Supported media types. */
174struct fxp_supported_media {
175 const int fsm_phy; /* PHY type */
176 const int *fsm_media; /* the media array */
177 const int fsm_nmedia; /* the number of supported media */
178 const int fsm_defmedia; /* default media for this PHY */
179};
180
181static const int fxp_media_standard[] = {
182 IFM_ETHER|IFM_10_T,
183 IFM_ETHER|IFM_10_T|IFM_FDX,
184 IFM_ETHER|IFM_100_TX,
185 IFM_ETHER|IFM_100_TX|IFM_FDX,
186 IFM_ETHER|IFM_AUTO,
187};
188#define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO)
189
190static const int fxp_media_default[] = {
191 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */
192};
193#define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL)
194
195static const struct fxp_supported_media fxp_media[] = {
196 { FXP_PHY_DP83840, fxp_media_standard,
197 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
198 FXP_MEDIA_STANDARD_DEFMEDIA },
199 { FXP_PHY_DP83840A, fxp_media_standard,
200 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
201 FXP_MEDIA_STANDARD_DEFMEDIA },
202 { FXP_PHY_82553A, fxp_media_standard,
203 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
204 FXP_MEDIA_STANDARD_DEFMEDIA },
205 { FXP_PHY_82553C, fxp_media_standard,
206 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
207 FXP_MEDIA_STANDARD_DEFMEDIA },
208 { FXP_PHY_82555, fxp_media_standard,
209 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
210 FXP_MEDIA_STANDARD_DEFMEDIA },
211 { FXP_PHY_82555B, fxp_media_standard,
212 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
213 FXP_MEDIA_STANDARD_DEFMEDIA },
214 { FXP_PHY_80C24, fxp_media_default,
215 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]),
216 FXP_MEDIA_DEFAULT_DEFMEDIA },
217};
218#define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0]))
219
220static int fxp_mediachange __P((struct ifnet *));
221static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *));
222static void fxp_set_media __P((struct fxp_softc *, int));
223static __inline void fxp_scb_wait __P((struct fxp_softc *));
| 31 */
32
33/*
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/mbuf.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/socket.h>
43
44#include <net/if.h>
45#include <net/if_dl.h>
46#include <net/if_media.h>
47
48#ifdef NS
49#include <netns/ns.h>
50#include <netns/ns_if.h>
51#endif
52
53#include <net/bpf.h>
54
55#if defined(__NetBSD__)
56
57#include <sys/ioctl.h>
58#include <sys/errno.h>
59#include <sys/device.h>
60
61#include <net/if_dl.h>
62#include <net/if_ether.h>
63
64#include <netinet/if_inarp.h>
65
66#include <vm/vm.h>
67
68#include <machine/cpu.h>
69#include <machine/bus.h>
70#include <machine/intr.h>
71
72#include <dev/pci/if_fxpreg.h>
73#include <dev/pci/if_fxpvar.h>
74
75#include <dev/pci/pcivar.h>
76#include <dev/pci/pcireg.h>
77#include <dev/pci/pcidevs.h>
78
79
80#else /* __FreeBSD__ */
81
82#include <sys/sockio.h>
83#include <sys/bus.h>
84#include <machine/bus.h>
85#include <sys/rman.h>
86#include <machine/resource.h>
87#include <sys/proc.h>
88#include <machine/mutex.h>
89
90#include <net/ethernet.h>
91#include <net/if_arp.h>
92
93#include <vm/vm.h> /* for vtophys */
94#include <vm/pmap.h> /* for vtophys */
95#include <machine/clock.h> /* for DELAY */
96
97#include <pci/pcivar.h>
98#include <pci/pcireg.h> /* for PCIM_CMD_xxx */
99#include <pci/if_fxpreg.h>
100#include <pci/if_fxpvar.h>
101
102#endif /* __NetBSD__ */
103
104#ifdef __alpha__ /* XXX */
105/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
106#undef vtophys
107#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
108#endif /* __alpha__ */
109
110/*
111 * NOTE! On the Alpha, we have an alignment constraint. The
112 * card DMAs the packet immediately following the RFA. However,
113 * the first thing in the packet is a 14-byte Ethernet header.
114 * This means that the packet is misaligned. To compensate,
115 * we actually offset the RFA 2 bytes into the cluster. This
116 * alignes the packet after the Ethernet header at a 32-bit
117 * boundary. HOWEVER! This means that the RFA is misaligned!
118 */
119#define RFA_ALIGNMENT_FUDGE 2
120
121/*
122 * Inline function to copy a 16-bit aligned 32-bit quantity.
123 */
124static __inline void fxp_lwcopy __P((volatile u_int32_t *,
125 volatile u_int32_t *));
126static __inline void
127fxp_lwcopy(src, dst)
128 volatile u_int32_t *src, *dst;
129{
130#ifdef __i386__
131 *dst = *src;
132#else
133 volatile u_int16_t *a = (volatile u_int16_t *)src;
134 volatile u_int16_t *b = (volatile u_int16_t *)dst;
135
136 b[0] = a[0];
137 b[1] = a[1];
138#endif
139}
140
141/*
142 * Template for default configuration parameters.
143 * See struct fxp_cb_config for the bit definitions.
144 */
145static u_char fxp_cb_config_template[] = {
146 0x0, 0x0, /* cb_status */
147 0x80, 0x2, /* cb_command */
148 0xff, 0xff, 0xff, 0xff, /* link_addr */
149 0x16, /* 0 */
150 0x8, /* 1 */
151 0x0, /* 2 */
152 0x0, /* 3 */
153 0x0, /* 4 */
154 0x80, /* 5 */
155 0xb2, /* 6 */
156 0x3, /* 7 */
157 0x1, /* 8 */
158 0x0, /* 9 */
159 0x26, /* 10 */
160 0x0, /* 11 */
161 0x60, /* 12 */
162 0x0, /* 13 */
163 0xf2, /* 14 */
164 0x48, /* 15 */
165 0x0, /* 16 */
166 0x40, /* 17 */
167 0xf3, /* 18 */
168 0x0, /* 19 */
169 0x3f, /* 20 */
170 0x5 /* 21 */
171};
172
173/* Supported media types. */
174struct fxp_supported_media {
175 const int fsm_phy; /* PHY type */
176 const int *fsm_media; /* the media array */
177 const int fsm_nmedia; /* the number of supported media */
178 const int fsm_defmedia; /* default media for this PHY */
179};
180
181static const int fxp_media_standard[] = {
182 IFM_ETHER|IFM_10_T,
183 IFM_ETHER|IFM_10_T|IFM_FDX,
184 IFM_ETHER|IFM_100_TX,
185 IFM_ETHER|IFM_100_TX|IFM_FDX,
186 IFM_ETHER|IFM_AUTO,
187};
188#define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO)
189
190static const int fxp_media_default[] = {
191 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */
192};
193#define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL)
194
195static const struct fxp_supported_media fxp_media[] = {
196 { FXP_PHY_DP83840, fxp_media_standard,
197 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
198 FXP_MEDIA_STANDARD_DEFMEDIA },
199 { FXP_PHY_DP83840A, fxp_media_standard,
200 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
201 FXP_MEDIA_STANDARD_DEFMEDIA },
202 { FXP_PHY_82553A, fxp_media_standard,
203 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
204 FXP_MEDIA_STANDARD_DEFMEDIA },
205 { FXP_PHY_82553C, fxp_media_standard,
206 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
207 FXP_MEDIA_STANDARD_DEFMEDIA },
208 { FXP_PHY_82555, fxp_media_standard,
209 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
210 FXP_MEDIA_STANDARD_DEFMEDIA },
211 { FXP_PHY_82555B, fxp_media_standard,
212 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
213 FXP_MEDIA_STANDARD_DEFMEDIA },
214 { FXP_PHY_80C24, fxp_media_default,
215 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]),
216 FXP_MEDIA_DEFAULT_DEFMEDIA },
217};
218#define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0]))
219
220static int fxp_mediachange __P((struct ifnet *));
221static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *));
222static void fxp_set_media __P((struct fxp_softc *, int));
223static __inline void fxp_scb_wait __P((struct fxp_softc *));
|
| 224static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc));
|
224static FXP_INTR_TYPE fxp_intr __P((void *));
225static void fxp_start __P((struct ifnet *));
226static int fxp_ioctl __P((struct ifnet *,
227 FXP_IOCTLCMD_TYPE, caddr_t));
228static void fxp_init __P((void *));
229static void fxp_stop __P((struct fxp_softc *));
230static void fxp_watchdog __P((struct ifnet *));
231static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *));
232static int fxp_mdi_read __P((struct fxp_softc *, int, int));
233static void fxp_mdi_write __P((struct fxp_softc *, int, int, int));
234static void fxp_autosize_eeprom __P((struct fxp_softc *));
235static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *,
236 int, int));
237static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *));
238static void fxp_stats_update __P((void *));
239static void fxp_mc_setup __P((struct fxp_softc *));
240
241/*
242 * Set initial transmit threshold at 64 (512 bytes). This is
243 * increased by 64 (512 bytes) at a time, to maximum of 192
244 * (1536 bytes), if an underrun occurs.
245 */
246static int tx_threshold = 64;
247
248/*
249 * Number of transmit control blocks. This determines the number
250 * of transmit buffers that can be chained in the CB list.
251 * This must be a power of two.
252 */
253#define FXP_NTXCB 128
254
255/*
256 * Number of completed TX commands at which point an interrupt
257 * will be generated to garbage collect the attached buffers.
258 * Must be at least one less than FXP_NTXCB, and should be
259 * enough less so that the transmitter doesn't becomes idle
260 * during the buffer rundown (which would reduce performance).
261 */
262#define FXP_CXINT_THRESH 120
263
264/*
265 * TxCB list index mask. This is used to do list wrap-around.
266 */
267#define FXP_TXCB_MASK (FXP_NTXCB - 1)
268
269/*
270 * Number of receive frame area buffers. These are large so chose
271 * wisely.
272 */
273#define FXP_NRFABUFS 64
274
275/*
276 * Maximum number of seconds that the receiver can be idle before we
277 * assume it's dead and attempt to reset it by reprogramming the
278 * multicast filter. This is part of a work-around for a bug in the
279 * NIC. See fxp_stats_update().
280 */
281#define FXP_MAX_RX_IDLE 15
282
283/*
284 * Wait for the previous command to be accepted (but not necessarily
285 * completed).
286 */
287static __inline void
288fxp_scb_wait(sc)
289 struct fxp_softc *sc;
290{
291 int i = 10000;
292
| 225static FXP_INTR_TYPE fxp_intr __P((void *));
226static void fxp_start __P((struct ifnet *));
227static int fxp_ioctl __P((struct ifnet *,
228 FXP_IOCTLCMD_TYPE, caddr_t));
229static void fxp_init __P((void *));
230static void fxp_stop __P((struct fxp_softc *));
231static void fxp_watchdog __P((struct ifnet *));
232static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *));
233static int fxp_mdi_read __P((struct fxp_softc *, int, int));
234static void fxp_mdi_write __P((struct fxp_softc *, int, int, int));
235static void fxp_autosize_eeprom __P((struct fxp_softc *));
236static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *,
237 int, int));
238static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *));
239static void fxp_stats_update __P((void *));
240static void fxp_mc_setup __P((struct fxp_softc *));
241
242/*
243 * Set initial transmit threshold at 64 (512 bytes). This is
244 * increased by 64 (512 bytes) at a time, to maximum of 192
245 * (1536 bytes), if an underrun occurs.
246 */
247static int tx_threshold = 64;
248
249/*
250 * Number of transmit control blocks. This determines the number
251 * of transmit buffers that can be chained in the CB list.
252 * This must be a power of two.
253 */
254#define FXP_NTXCB 128
255
256/*
257 * Number of completed TX commands at which point an interrupt
258 * will be generated to garbage collect the attached buffers.
259 * Must be at least one less than FXP_NTXCB, and should be
260 * enough less so that the transmitter doesn't becomes idle
261 * during the buffer rundown (which would reduce performance).
262 */
263#define FXP_CXINT_THRESH 120
264
265/*
266 * TxCB list index mask. This is used to do list wrap-around.
267 */
268#define FXP_TXCB_MASK (FXP_NTXCB - 1)
269
270/*
271 * Number of receive frame area buffers. These are large so chose
272 * wisely.
273 */
274#define FXP_NRFABUFS 64
275
276/*
277 * Maximum number of seconds that the receiver can be idle before we
278 * assume it's dead and attempt to reset it by reprogramming the
279 * multicast filter. This is part of a work-around for a bug in the
280 * NIC. See fxp_stats_update().
281 */
282#define FXP_MAX_RX_IDLE 15
283
284/*
285 * Wait for the previous command to be accepted (but not necessarily
286 * completed).
287 */
288static __inline void
289fxp_scb_wait(sc)
290 struct fxp_softc *sc;
291{
292 int i = 10000;
293
|
293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i);
| 294 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
295 DELAY(2);
296 if (i == 0)
297 printf(FXP_FORMAT ": SCB timeout\n", FXP_ARGS(sc));
|
294}
295
| 298}
299
|
| 300static __inline void
301fxp_dma_wait(status, sc)
302 volatile u_int16_t *status;
303 struct fxp_softc *sc;
304{
305 int i = 10000;
306
307 while (!(*status & FXP_CB_STATUS_C) && --i)
308 DELAY(2);
309 if (i == 0)
310 printf(FXP_FORMAT ": DMA timeout\n", FXP_ARGS(sc));
311}
312
|
296/*************************************************************
297 * Operating system-specific autoconfiguration glue
298 *************************************************************/
299
300#if defined(__NetBSD__)
301
302#ifdef __BROKEN_INDIRECT_CONFIG
303static int fxp_match __P((struct device *, void *, void *));
304#else
305static int fxp_match __P((struct device *, struct cfdata *, void *));
306#endif
307static void fxp_attach __P((struct device *, struct device *, void *));
308
309static void fxp_shutdown __P((void *));
310
311/* Compensate for lack of a generic ether_ioctl() */
312static int fxp_ether_ioctl __P((struct ifnet *,
313 FXP_IOCTLCMD_TYPE, caddr_t));
314#define ether_ioctl fxp_ether_ioctl
315
316struct cfattach fxp_ca = {
317 sizeof(struct fxp_softc), fxp_match, fxp_attach
318};
319
320struct cfdriver fxp_cd = {
321 NULL, "fxp", DV_IFNET
322};
323
324/*
325 * Check if a device is an 82557.
326 */
327static int
328fxp_match(parent, match, aux)
329 struct device *parent;
330#ifdef __BROKEN_INDIRECT_CONFIG
331 void *match;
332#else
333 struct cfdata *match;
334#endif
335 void *aux;
336{
337 struct pci_attach_args *pa = aux;
338
339 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
340 return (0);
341
342 switch (PCI_PRODUCT(pa->pa_id)) {
343 case PCI_PRODUCT_INTEL_82557:
344 return (1);
345 }
346
347 return (0);
348}
349
350static void
351fxp_attach(parent, self, aux)
352 struct device *parent, *self;
353 void *aux;
354{
355 struct fxp_softc *sc = (struct fxp_softc *)self;
356 struct pci_attach_args *pa = aux;
357 pci_chipset_tag_t pc = pa->pa_pc;
358 pci_intr_handle_t ih;
359 const char *intrstr = NULL;
360 u_int8_t enaddr[6];
361 struct ifnet *ifp;
362
363 /*
364 * Map control/status registers.
365 */
366 if (pci_mapreg_map(pa, FXP_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
367 &sc->sc_st, &sc->sc_sh, NULL, NULL)) {
368 printf(": can't map registers\n");
369 return;
370 }
371 printf(": Intel EtherExpress Pro 10/100B Ethernet\n");
372
373 /*
374 * Allocate our interrupt.
375 */
376 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
377 pa->pa_intrline, &ih)) {
378 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
379 return;
380 }
381 intrstr = pci_intr_string(pc, ih);
382 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc);
383 if (sc->sc_ih == NULL) {
384 printf("%s: couldn't establish interrupt",
385 sc->sc_dev.dv_xname);
386 if (intrstr != NULL)
387 printf(" at %s", intrstr);
388 printf("\n");
389 return;
390 }
391 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
392
393 /* Do generic parts of attach. */
394 if (fxp_attach_common(sc, enaddr)) {
395 /* Failed! */
396 return;
397 }
398
399 printf("%s: Ethernet address %s%s\n", sc->sc_dev.dv_xname,
400 ether_sprintf(enaddr), sc->phy_10Mbps_only ? ", 10Mbps" : "");
401
402 ifp = &sc->sc_ethercom.ec_if;
403 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
404 ifp->if_softc = sc;
405 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
406 ifp->if_ioctl = fxp_ioctl;
407 ifp->if_start = fxp_start;
408 ifp->if_watchdog = fxp_watchdog;
409
410 /*
411 * Attach the interface.
412 */
413 if_attach(ifp);
414 /*
415 * Let the system queue as many packets as we have available
416 * TX descriptors.
417 */
418 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
419 ether_ifattach(ifp, enaddr);
420 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB,
421 sizeof(struct ether_header));
422
423 /*
424 * Add shutdown hook so that DMA is disabled prior to reboot. Not
425 * doing do could allow DMA to corrupt kernel memory during the
426 * reboot before the driver initializes.
427 */
428 shutdownhook_establish(fxp_shutdown, sc);
429}
430
431/*
432 * Device shutdown routine. Called at system shutdown after sync. The
433 * main purpose of this routine is to shut off receiver DMA so that
434 * kernel memory doesn't get clobbered during warmboot.
435 */
436static void
437fxp_shutdown(sc)
438 void *sc;
439{
440 fxp_stop((struct fxp_softc *) sc);
441}
442
443static int
444fxp_ether_ioctl(ifp, cmd, data)
445 struct ifnet *ifp;
446 FXP_IOCTLCMD_TYPE cmd;
447 caddr_t data;
448{
449 struct ifaddr *ifa = (struct ifaddr *) data;
450 struct fxp_softc *sc = ifp->if_softc;
451
452 switch (cmd) {
453 case SIOCSIFADDR:
454 ifp->if_flags |= IFF_UP;
455
456 switch (ifa->ifa_addr->sa_family) {
457#ifdef INET
458 case AF_INET:
459 fxp_init(sc);
460 arp_ifinit(ifp, ifa);
461 break;
462#endif
463#ifdef NS
464 case AF_NS:
465 {
466 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
467
468 if (ns_nullhost(*ina))
469 ina->x_host = *(union ns_host *)
470 LLADDR(ifp->if_sadl);
471 else
472 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
473 ifp->if_addrlen);
474 /* Set new address. */
475 fxp_init(sc);
476 break;
477 }
478#endif
479 default:
480 fxp_init(sc);
481 break;
482 }
483 break;
484
485 default:
486 return (EINVAL);
487 }
488
489 return (0);
490}
491
492#else /* __FreeBSD__ */
493
494/*
495 * Return identification string if this is device is ours.
496 */
497static int
498fxp_probe(device_t dev)
499{
500 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
501 switch (pci_get_device(dev)) {
502
503 case FXP_DEVICEID_i82557:
504 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet");
505 return 0;
506 case FXP_DEVICEID_i82559:
507 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet");
508 return 0;
509 case FXP_DEVICEID_i82559ER:
510 device_set_desc(dev, "Intel Embedded 10/100 Ethernet");
511 return 0;
512 default:
513 break;
514 }
515 }
516
517 return ENXIO;
518}
519
520static int
521fxp_attach(device_t dev)
522{
523 int error = 0;
524 struct fxp_softc *sc = device_get_softc(dev);
525 struct ifnet *ifp;
526 FXP_SPLVAR(s)
527 u_long val;
528 int rid;
529
530#if !defined(__NetBSD__)
531 mtx_init(&sc->sc_mtx, "fxp", MTX_DEF);
532#endif
533 callout_handle_init(&sc->stat_ch);
534
535 FXP_LOCK(sc, s);
536
537 /*
538 * Enable bus mastering.
539 */
540 val = pci_read_config(dev, PCIR_COMMAND, 2);
541 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
542 pci_write_config(dev, PCIR_COMMAND, val, 2);
543
544 /*
545 * Map control/status registers.
546 */
547 rid = FXP_PCI_MMBA;
548 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
549 0, ~0, 1, RF_ACTIVE);
550 if (!sc->mem) {
551 device_printf(dev, "could not map memory\n");
552 error = ENXIO;
553 goto fail;
554 }
555
556 sc->sc_st = rman_get_bustag(sc->mem);
557 sc->sc_sh = rman_get_bushandle(sc->mem);
558
559 /*
560 * Allocate our interrupt.
561 */
562 rid = 0;
563 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
564 RF_SHAREABLE | RF_ACTIVE);
565 if (sc->irq == NULL) {
566 device_printf(dev, "could not map interrupt\n");
567 error = ENXIO;
568 goto fail;
569 }
570
571 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
572 fxp_intr, sc, &sc->ih);
573 if (error) {
574 device_printf(dev, "could not setup irq\n");
575 goto fail;
576 }
577
578 /* Do generic parts of attach. */
579 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) {
580 /* Failed! */
581 bus_teardown_intr(dev, sc->irq, sc->ih);
582 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
583 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem);
584 error = ENXIO;
585 goto fail;
586 }
587
588 device_printf(dev, "Ethernet address %6D%s\n",
589 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : "");
590
591 ifp = &sc->arpcom.ac_if;
592 ifp->if_unit = device_get_unit(dev);
593 ifp->if_name = "fxp";
594 ifp->if_output = ether_output;
595 ifp->if_baudrate = 100000000;
596 ifp->if_init = fxp_init;
597 ifp->if_softc = sc;
598 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
599 ifp->if_ioctl = fxp_ioctl;
600 ifp->if_start = fxp_start;
601 ifp->if_watchdog = fxp_watchdog;
602
603 /*
604 * Attach the interface.
605 */
606 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
607 /*
608 * Let the system queue as many packets as we have available
609 * TX descriptors.
610 */
611 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
612
613 FXP_UNLOCK(sc, s);
614 return 0;
615
616 fail:
617 FXP_UNLOCK(sc, s);
618 mtx_destroy(&sc->sc_mtx);
619 return error;
620}
621
622/*
623 * Detach interface.
624 */
625static int
626fxp_detach(device_t dev)
627{
628 struct fxp_softc *sc = device_get_softc(dev);
629 FXP_SPLVAR(s)
630
631 FXP_LOCK(sc, s);
632
633 /*
634 * Close down routes etc.
635 */
636 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
637
638 /*
639 * Stop DMA and drop transmit queue.
640 */
641 fxp_stop(sc);
642
643 /*
644 * Deallocate resources.
645 */
646 bus_teardown_intr(dev, sc->irq, sc->ih);
647 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
648 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem);
649
650 /*
651 * Free all the receive buffers.
652 */
653 if (sc->rfa_headm != NULL)
654 m_freem(sc->rfa_headm);
655
656 /*
657 * Free all media structures.
658 */
659 ifmedia_removeall(&sc->sc_media);
660
661 /*
662 * Free anciliary structures.
663 */
664 free(sc->cbl_base, M_DEVBUF);
665 free(sc->fxp_stats, M_DEVBUF);
666 free(sc->mcsp, M_DEVBUF);
667
668 FXP_UNLOCK(sc, s);
669
670 return 0;
671}
672
673/*
674 * Device shutdown routine. Called at system shutdown after sync. The
675 * main purpose of this routine is to shut off receiver DMA so that
676 * kernel memory doesn't get clobbered during warmboot.
677 */
678static int
679fxp_shutdown(device_t dev)
680{
681 /*
682 * Make sure that DMA is disabled prior to reboot. Not doing
683 * do could allow DMA to corrupt kernel memory during the
684 * reboot before the driver initializes.
685 */
686 fxp_stop((struct fxp_softc *) device_get_softc(dev));
687 return 0;
688}
689
| 313/*************************************************************
314 * Operating system-specific autoconfiguration glue
315 *************************************************************/
316
317#if defined(__NetBSD__)
318
319#ifdef __BROKEN_INDIRECT_CONFIG
320static int fxp_match __P((struct device *, void *, void *));
321#else
322static int fxp_match __P((struct device *, struct cfdata *, void *));
323#endif
324static void fxp_attach __P((struct device *, struct device *, void *));
325
326static void fxp_shutdown __P((void *));
327
328/* Compensate for lack of a generic ether_ioctl() */
329static int fxp_ether_ioctl __P((struct ifnet *,
330 FXP_IOCTLCMD_TYPE, caddr_t));
331#define ether_ioctl fxp_ether_ioctl
332
333struct cfattach fxp_ca = {
334 sizeof(struct fxp_softc), fxp_match, fxp_attach
335};
336
337struct cfdriver fxp_cd = {
338 NULL, "fxp", DV_IFNET
339};
340
341/*
342 * Check if a device is an 82557.
343 */
344static int
345fxp_match(parent, match, aux)
346 struct device *parent;
347#ifdef __BROKEN_INDIRECT_CONFIG
348 void *match;
349#else
350 struct cfdata *match;
351#endif
352 void *aux;
353{
354 struct pci_attach_args *pa = aux;
355
356 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
357 return (0);
358
359 switch (PCI_PRODUCT(pa->pa_id)) {
360 case PCI_PRODUCT_INTEL_82557:
361 return (1);
362 }
363
364 return (0);
365}
366
367static void
368fxp_attach(parent, self, aux)
369 struct device *parent, *self;
370 void *aux;
371{
372 struct fxp_softc *sc = (struct fxp_softc *)self;
373 struct pci_attach_args *pa = aux;
374 pci_chipset_tag_t pc = pa->pa_pc;
375 pci_intr_handle_t ih;
376 const char *intrstr = NULL;
377 u_int8_t enaddr[6];
378 struct ifnet *ifp;
379
380 /*
381 * Map control/status registers.
382 */
383 if (pci_mapreg_map(pa, FXP_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
384 &sc->sc_st, &sc->sc_sh, NULL, NULL)) {
385 printf(": can't map registers\n");
386 return;
387 }
388 printf(": Intel EtherExpress Pro 10/100B Ethernet\n");
389
390 /*
391 * Allocate our interrupt.
392 */
393 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
394 pa->pa_intrline, &ih)) {
395 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
396 return;
397 }
398 intrstr = pci_intr_string(pc, ih);
399 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc);
400 if (sc->sc_ih == NULL) {
401 printf("%s: couldn't establish interrupt",
402 sc->sc_dev.dv_xname);
403 if (intrstr != NULL)
404 printf(" at %s", intrstr);
405 printf("\n");
406 return;
407 }
408 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
409
410 /* Do generic parts of attach. */
411 if (fxp_attach_common(sc, enaddr)) {
412 /* Failed! */
413 return;
414 }
415
416 printf("%s: Ethernet address %s%s\n", sc->sc_dev.dv_xname,
417 ether_sprintf(enaddr), sc->phy_10Mbps_only ? ", 10Mbps" : "");
418
419 ifp = &sc->sc_ethercom.ec_if;
420 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
421 ifp->if_softc = sc;
422 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
423 ifp->if_ioctl = fxp_ioctl;
424 ifp->if_start = fxp_start;
425 ifp->if_watchdog = fxp_watchdog;
426
427 /*
428 * Attach the interface.
429 */
430 if_attach(ifp);
431 /*
432 * Let the system queue as many packets as we have available
433 * TX descriptors.
434 */
435 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
436 ether_ifattach(ifp, enaddr);
437 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB,
438 sizeof(struct ether_header));
439
440 /*
441 * Add shutdown hook so that DMA is disabled prior to reboot. Not
442 * doing do could allow DMA to corrupt kernel memory during the
443 * reboot before the driver initializes.
444 */
445 shutdownhook_establish(fxp_shutdown, sc);
446}
447
448/*
449 * Device shutdown routine. Called at system shutdown after sync. The
450 * main purpose of this routine is to shut off receiver DMA so that
451 * kernel memory doesn't get clobbered during warmboot.
452 */
453static void
454fxp_shutdown(sc)
455 void *sc;
456{
457 fxp_stop((struct fxp_softc *) sc);
458}
459
460static int
461fxp_ether_ioctl(ifp, cmd, data)
462 struct ifnet *ifp;
463 FXP_IOCTLCMD_TYPE cmd;
464 caddr_t data;
465{
466 struct ifaddr *ifa = (struct ifaddr *) data;
467 struct fxp_softc *sc = ifp->if_softc;
468
469 switch (cmd) {
470 case SIOCSIFADDR:
471 ifp->if_flags |= IFF_UP;
472
473 switch (ifa->ifa_addr->sa_family) {
474#ifdef INET
475 case AF_INET:
476 fxp_init(sc);
477 arp_ifinit(ifp, ifa);
478 break;
479#endif
480#ifdef NS
481 case AF_NS:
482 {
483 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
484
485 if (ns_nullhost(*ina))
486 ina->x_host = *(union ns_host *)
487 LLADDR(ifp->if_sadl);
488 else
489 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
490 ifp->if_addrlen);
491 /* Set new address. */
492 fxp_init(sc);
493 break;
494 }
495#endif
496 default:
497 fxp_init(sc);
498 break;
499 }
500 break;
501
502 default:
503 return (EINVAL);
504 }
505
506 return (0);
507}
508
509#else /* __FreeBSD__ */
510
511/*
512 * Return identification string if this is device is ours.
513 */
514static int
515fxp_probe(device_t dev)
516{
517 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
518 switch (pci_get_device(dev)) {
519
520 case FXP_DEVICEID_i82557:
521 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet");
522 return 0;
523 case FXP_DEVICEID_i82559:
524 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet");
525 return 0;
526 case FXP_DEVICEID_i82559ER:
527 device_set_desc(dev, "Intel Embedded 10/100 Ethernet");
528 return 0;
529 default:
530 break;
531 }
532 }
533
534 return ENXIO;
535}
536
537static int
538fxp_attach(device_t dev)
539{
540 int error = 0;
541 struct fxp_softc *sc = device_get_softc(dev);
542 struct ifnet *ifp;
543 FXP_SPLVAR(s)
544 u_long val;
545 int rid;
546
547#if !defined(__NetBSD__)
548 mtx_init(&sc->sc_mtx, "fxp", MTX_DEF);
549#endif
550 callout_handle_init(&sc->stat_ch);
551
552 FXP_LOCK(sc, s);
553
554 /*
555 * Enable bus mastering.
556 */
557 val = pci_read_config(dev, PCIR_COMMAND, 2);
558 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
559 pci_write_config(dev, PCIR_COMMAND, val, 2);
560
561 /*
562 * Map control/status registers.
563 */
564 rid = FXP_PCI_MMBA;
565 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
566 0, ~0, 1, RF_ACTIVE);
567 if (!sc->mem) {
568 device_printf(dev, "could not map memory\n");
569 error = ENXIO;
570 goto fail;
571 }
572
573 sc->sc_st = rman_get_bustag(sc->mem);
574 sc->sc_sh = rman_get_bushandle(sc->mem);
575
576 /*
577 * Allocate our interrupt.
578 */
579 rid = 0;
580 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
581 RF_SHAREABLE | RF_ACTIVE);
582 if (sc->irq == NULL) {
583 device_printf(dev, "could not map interrupt\n");
584 error = ENXIO;
585 goto fail;
586 }
587
588 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
589 fxp_intr, sc, &sc->ih);
590 if (error) {
591 device_printf(dev, "could not setup irq\n");
592 goto fail;
593 }
594
595 /* Do generic parts of attach. */
596 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) {
597 /* Failed! */
598 bus_teardown_intr(dev, sc->irq, sc->ih);
599 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
600 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem);
601 error = ENXIO;
602 goto fail;
603 }
604
605 device_printf(dev, "Ethernet address %6D%s\n",
606 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : "");
607
608 ifp = &sc->arpcom.ac_if;
609 ifp->if_unit = device_get_unit(dev);
610 ifp->if_name = "fxp";
611 ifp->if_output = ether_output;
612 ifp->if_baudrate = 100000000;
613 ifp->if_init = fxp_init;
614 ifp->if_softc = sc;
615 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
616 ifp->if_ioctl = fxp_ioctl;
617 ifp->if_start = fxp_start;
618 ifp->if_watchdog = fxp_watchdog;
619
620 /*
621 * Attach the interface.
622 */
623 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
624 /*
625 * Let the system queue as many packets as we have available
626 * TX descriptors.
627 */
628 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
629
630 FXP_UNLOCK(sc, s);
631 return 0;
632
633 fail:
634 FXP_UNLOCK(sc, s);
635 mtx_destroy(&sc->sc_mtx);
636 return error;
637}
638
639/*
640 * Detach interface.
641 */
642static int
643fxp_detach(device_t dev)
644{
645 struct fxp_softc *sc = device_get_softc(dev);
646 FXP_SPLVAR(s)
647
648 FXP_LOCK(sc, s);
649
650 /*
651 * Close down routes etc.
652 */
653 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
654
655 /*
656 * Stop DMA and drop transmit queue.
657 */
658 fxp_stop(sc);
659
660 /*
661 * Deallocate resources.
662 */
663 bus_teardown_intr(dev, sc->irq, sc->ih);
664 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
665 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem);
666
667 /*
668 * Free all the receive buffers.
669 */
670 if (sc->rfa_headm != NULL)
671 m_freem(sc->rfa_headm);
672
673 /*
674 * Free all media structures.
675 */
676 ifmedia_removeall(&sc->sc_media);
677
678 /*
679 * Free anciliary structures.
680 */
681 free(sc->cbl_base, M_DEVBUF);
682 free(sc->fxp_stats, M_DEVBUF);
683 free(sc->mcsp, M_DEVBUF);
684
685 FXP_UNLOCK(sc, s);
686
687 return 0;
688}
689
690/*
691 * Device shutdown routine. Called at system shutdown after sync. The
692 * main purpose of this routine is to shut off receiver DMA so that
693 * kernel memory doesn't get clobbered during warmboot.
694 */
695static int
696fxp_shutdown(device_t dev)
697{
698 /*
699 * Make sure that DMA is disabled prior to reboot. Not doing
700 * do could allow DMA to corrupt kernel memory during the
701 * reboot before the driver initializes.
702 */
703 fxp_stop((struct fxp_softc *) device_get_softc(dev));
704 return 0;
705}
706
|
| 707/*
708 * Device suspend routine. Stop the interface and save some PCI
709 * settings in case the BIOS doesn't restore them properly on
710 * resume.
711 */
712static int
713fxp_suspend(device_t dev)
714{
715 struct fxp_softc *sc = device_get_softc(dev);
716 int i, s;
717
718 s = splimp();
719
720 fxp_stop(sc);
721
722 for (i=0; i<5; i++)
723 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4);
724 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
725 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
726 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
727 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
728
729 sc->suspended = 1;
730
731 splx(s);
732
733 return 0;
734}
735
736/*
737 * Device resume routine. Restore some PCI settings in case the BIOS
738 * doesn't, re-enable busmastering, and restart the interface if
739 * appropriate.
740 */
741static int
742fxp_resume(device_t dev)
743{
744 struct fxp_softc *sc = device_get_softc(dev);
745 struct ifnet *ifp = &sc->sc_if;
746 u_int16_t pci_command;
747 int i, s;
748
749 s = splimp();
750
751 /* better way to do this? */
752 for (i=0; i<5; i++)
753 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4);
754 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
755 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
756 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
757 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
758
759 /* reenable busmastering */
760 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
761 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
762 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
763
764 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
765 DELAY(10);
766
767 /* reinitialize interface if necessary */
768 if (ifp->if_flags & IFF_UP)
769 fxp_init(sc);
770
771 sc->suspended = 0;
772
773 splx(s);
774
775 return 0;
776}
777
|
690static device_method_t fxp_methods[] = {
691 /* Device interface */
692 DEVMETHOD(device_probe, fxp_probe),
693 DEVMETHOD(device_attach, fxp_attach),
694 DEVMETHOD(device_detach, fxp_detach),
695 DEVMETHOD(device_shutdown, fxp_shutdown),
| 778static device_method_t fxp_methods[] = {
779 /* Device interface */
780 DEVMETHOD(device_probe, fxp_probe),
781 DEVMETHOD(device_attach, fxp_attach),
782 DEVMETHOD(device_detach, fxp_detach),
783 DEVMETHOD(device_shutdown, fxp_shutdown),
|
| 784 DEVMETHOD(device_suspend, fxp_suspend),
785 DEVMETHOD(device_resume, fxp_resume),
|
696
697 { 0, 0 }
698};
699
700static driver_t fxp_driver = {
701 "fxp",
702 fxp_methods,
703 sizeof(struct fxp_softc),
704};
705
706static devclass_t fxp_devclass;
707
708DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
709
710#endif /* __NetBSD__ */
711
712/*************************************************************
713 * End of operating system-specific autoconfiguration glue
714 *************************************************************/
715
716/*
717 * Do generic parts of attach.
718 */
719static int
720fxp_attach_common(sc, enaddr)
721 struct fxp_softc *sc;
722 u_int8_t *enaddr;
723{
724 u_int16_t data;
725 int i, nmedia, defmedia;
726 const int *media;
727
728 /*
729 * Reset to a stable state.
730 */
731 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
732 DELAY(10);
733
734 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
735 M_DEVBUF, M_NOWAIT);
736 if (sc->cbl_base == NULL)
737 goto fail;
738 bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
739
740 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT);
741 if (sc->fxp_stats == NULL)
742 goto fail;
743 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
744
745 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
746 if (sc->mcsp == NULL)
747 goto fail;
748
749 /*
750 * Pre-allocate our receive buffers.
751 */
752 for (i = 0; i < FXP_NRFABUFS; i++) {
753 if (fxp_add_rfabuf(sc, NULL) != 0) {
754 goto fail;
755 }
756 }
757
758 /*
759 * Find out how large of an SEEPROM we have.
760 */
761 fxp_autosize_eeprom(sc);
762
763 /*
764 * Get info about the primary PHY
765 */
766 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1);
767 sc->phy_primary_addr = data & 0xff;
768 sc->phy_primary_device = (data >> 8) & 0x3f;
769 sc->phy_10Mbps_only = data >> 15;
770
771 /*
772 * Read MAC address.
773 */
774 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3);
775
776 /*
777 * Initialize the media structures.
778 */
779
780 media = fxp_media_default;
781 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]);
782 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA;
783
784 for (i = 0; i < NFXPMEDIA; i++) {
785 if (sc->phy_primary_device == fxp_media[i].fsm_phy) {
786 media = fxp_media[i].fsm_media;
787 nmedia = fxp_media[i].fsm_nmedia;
788 defmedia = fxp_media[i].fsm_defmedia;
789 }
790 }
791
792 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus);
793 for (i = 0; i < nmedia; i++) {
794 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only)
795 continue;
796 ifmedia_add(&sc->sc_media, media[i], 0, NULL);
797 }
798 ifmedia_set(&sc->sc_media, defmedia);
799
800 return (0);
801
802 fail:
803 printf(FXP_FORMAT ": Failed to malloc memory\n", FXP_ARGS(sc));
804 if (sc->cbl_base)
805 free(sc->cbl_base, M_DEVBUF);
806 if (sc->fxp_stats)
807 free(sc->fxp_stats, M_DEVBUF);
808 if (sc->mcsp)
809 free(sc->mcsp, M_DEVBUF);
810 /* frees entire chain */
811 if (sc->rfa_headm)
812 m_freem(sc->rfa_headm);
813
814 return (ENOMEM);
815}
816
817/*
818 * From NetBSD:
819 *
820 * Figure out EEPROM size.
821 *
822 * 559's can have either 64-word or 256-word EEPROMs, the 558
823 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
824 * talks about the existance of 16 to 256 word EEPROMs.
825 *
826 * The only known sizes are 64 and 256, where the 256 version is used
827 * by CardBus cards to store CIS information.
828 *
829 * The address is shifted in msb-to-lsb, and after the last
830 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
831 * after which follows the actual data. We try to detect this zero, by
832 * probing the data-out bit in the EEPROM control register just after
833 * having shifted in a bit. If the bit is zero, we assume we've
834 * shifted enough address bits. The data-out should be tri-state,
835 * before this, which should translate to a logical one.
836 *
837 * Other ways to do this would be to try to read a register with known
838 * contents with a varying number of address bits, but no such
839 * register seem to be available. The high bits of register 10 are 01
840 * on the 558 and 559, but apparently not on the 557.
841 *
842 * The Linux driver computes a checksum on the EEPROM data, but the
843 * value of this checksum is not very well documented.
844 */
845static void
846fxp_autosize_eeprom(sc)
847 struct fxp_softc *sc;
848{
849 u_int16_t reg;
850 int x;
851
852 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
853 /*
854 * Shift in read opcode.
855 */
856 for (x = 3; x > 0; x--) {
857 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
858 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
859 } else {
860 reg = FXP_EEPROM_EECS;
861 }
862 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
863 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
864 reg | FXP_EEPROM_EESK);
865 DELAY(1);
866 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
867 DELAY(1);
868 }
869 /*
870 * Shift in address.
871 * Wait for the dummy zero following a correct address shift.
872 */
873 for (x = 1; x <= 8; x++) {
874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
875 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
876 FXP_EEPROM_EECS | FXP_EEPROM_EESK);
877 DELAY(1);
878 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0)
879 break;
880 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
881 DELAY(1);
882 }
883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
884 DELAY(1);
885 sc->eeprom_size = x;
886}
887/*
888 * Read from the serial EEPROM. Basically, you manually shift in
889 * the read opcode (one bit at a time) and then shift in the address,
890 * and then you shift out the data (all of this one bit at a time).
891 * The word size is 16 bits, so you have to provide the address for
892 * every 16 bits of data.
893 */
894static void
895fxp_read_eeprom(sc, data, offset, words)
896 struct fxp_softc *sc;
897 u_short *data;
898 int offset;
899 int words;
900{
901 u_int16_t reg;
902 int i, x;
903
904 for (i = 0; i < words; i++) {
905 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
906 /*
907 * Shift in read opcode.
908 */
909 for (x = 3; x > 0; x--) {
910 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
911 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
912 } else {
913 reg = FXP_EEPROM_EECS;
914 }
915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
916 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
917 reg | FXP_EEPROM_EESK);
918 DELAY(1);
919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
920 DELAY(1);
921 }
922 /*
923 * Shift in address.
924 */
925 for (x = sc->eeprom_size; x > 0; x--) {
926 if ((i + offset) & (1 << (x - 1))) {
927 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
928 } else {
929 reg = FXP_EEPROM_EECS;
930 }
931 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
932 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
933 reg | FXP_EEPROM_EESK);
934 DELAY(1);
935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
936 DELAY(1);
937 }
938 reg = FXP_EEPROM_EECS;
939 data[i] = 0;
940 /*
941 * Shift out data.
942 */
943 for (x = 16; x > 0; x--) {
944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
945 reg | FXP_EEPROM_EESK);
946 DELAY(1);
947 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
948 FXP_EEPROM_EEDO)
949 data[i] |= (1 << (x - 1));
950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
951 DELAY(1);
952 }
953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
954 DELAY(1);
955 }
956}
957
958/*
959 * Start packet transmission on the interface.
960 */
961static void
962fxp_start(ifp)
963 struct ifnet *ifp;
964{
965 struct fxp_softc *sc = ifp->if_softc;
966 struct fxp_cb_tx *txp;
967
968#if !defined(__NetBSD__)
969 FXP_LOCK(sc, s);
970#endif
971 /*
972 * See if we need to suspend xmit until the multicast filter
973 * has been reprogrammed (which can only be done at the head
974 * of the command chain).
975 */
976 if (sc->need_mcsetup) {
977 FXP_UNLOCK(sc, s);
978 return;
979 }
980
981 txp = NULL;
982
983 /*
984 * We're finished if there is nothing more to add to the list or if
985 * we're all filled up with buffers to transmit.
986 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
987 * a NOP command when needed.
988 */
989 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
990 struct mbuf *m, *mb_head;
991 int segment;
992
993 /*
994 * Grab a packet to transmit.
995 */
996 IF_DEQUEUE(&ifp->if_snd, mb_head);
997
998 /*
999 * Get pointer to next available tx desc.
1000 */
1001 txp = sc->cbl_last->next;
1002
1003 /*
1004 * Go through each of the mbufs in the chain and initialize
1005 * the transmit buffer descriptors with the physical address
1006 * and size of the mbuf.
1007 */
1008tbdinit:
1009 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1010 if (m->m_len != 0) {
1011 if (segment == FXP_NTXSEG)
1012 break;
1013 txp->tbd[segment].tb_addr =
1014 vtophys(mtod(m, vm_offset_t));
1015 txp->tbd[segment].tb_size = m->m_len;
1016 segment++;
1017 }
1018 }
1019 if (m != NULL) {
1020 struct mbuf *mn;
1021
1022 /*
1023 * We ran out of segments. We have to recopy this mbuf
1024 * chain first. Bail out if we can't get the new buffers.
1025 */
1026 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1027 if (mn == NULL) {
1028 m_freem(mb_head);
1029 break;
1030 }
1031 if (mb_head->m_pkthdr.len > MHLEN) {
1032 MCLGET(mn, M_DONTWAIT);
1033 if ((mn->m_flags & M_EXT) == 0) {
1034 m_freem(mn);
1035 m_freem(mb_head);
1036 break;
1037 }
1038 }
1039 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1040 mtod(mn, caddr_t));
1041 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1042 m_freem(mb_head);
1043 mb_head = mn;
1044 goto tbdinit;
1045 }
1046
1047 txp->tbd_number = segment;
1048 txp->mb_head = mb_head;
1049 txp->cb_status = 0;
1050 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1051 txp->cb_command =
1052 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S;
1053 } else {
1054 txp->cb_command =
1055 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1056 /*
1057 * Set a 5 second timer just in case we don't hear from the
1058 * card again.
1059 */
1060 ifp->if_timer = 5;
1061 }
1062 txp->tx_threshold = tx_threshold;
1063
1064 /*
1065 * Advance the end of list forward.
1066 */
1067
1068#ifdef __alpha__
1069 /*
1070 * On platforms which can't access memory in 16-bit
1071 * granularities, we must prevent the card from DMA'ing
1072 * up the status while we update the command field.
1073 * This could cause us to overwrite the completion status.
1074 */
1075 atomic_clear_short(&sc->cbl_last->cb_command,
1076 FXP_CB_COMMAND_S);
1077#else
1078 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1079#endif /*__alpha__*/
1080 sc->cbl_last = txp;
1081
1082 /*
1083 * Advance the beginning of the list forward if there are
1084 * no other packets queued (when nothing is queued, cbl_first
1085 * sits on the last TxCB that was sent out).
1086 */
1087 if (sc->tx_queued == 0)
1088 sc->cbl_first = txp;
1089
1090 sc->tx_queued++;
1091
1092 /*
1093 * Pass packet to bpf if there is a listener.
1094 */
1095 if (ifp->if_bpf)
1096 bpf_mtap(FXP_BPFTAP_ARG(ifp), mb_head);
1097 }
1098
1099 /*
1100 * We're finished. If we added to the list, issue a RESUME to get DMA
1101 * going again if suspended.
1102 */
1103 if (txp != NULL) {
1104 fxp_scb_wait(sc);
1105 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
1106 }
1107#if !defined(__NetBSD__)
1108 FXP_UNLOCK(sc, s);
1109#endif
1110}
1111
1112/*
1113 * Process interface interrupts.
1114 */
1115static FXP_INTR_TYPE
1116fxp_intr(arg)
1117 void *arg;
1118{
1119 struct fxp_softc *sc = arg;
1120 struct ifnet *ifp = &sc->sc_if;
1121 u_int8_t statack;
1122#if defined(__NetBSD__)
1123 int claimed = 0;
1124#else
1125
1126 FXP_LOCK(sc, s);
1127#endif
1128
| 786
787 { 0, 0 }
788};
789
790static driver_t fxp_driver = {
791 "fxp",
792 fxp_methods,
793 sizeof(struct fxp_softc),
794};
795
796static devclass_t fxp_devclass;
797
798DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
799
800#endif /* __NetBSD__ */
801
802/*************************************************************
803 * End of operating system-specific autoconfiguration glue
804 *************************************************************/
805
806/*
807 * Do generic parts of attach.
808 */
809static int
810fxp_attach_common(sc, enaddr)
811 struct fxp_softc *sc;
812 u_int8_t *enaddr;
813{
814 u_int16_t data;
815 int i, nmedia, defmedia;
816 const int *media;
817
818 /*
819 * Reset to a stable state.
820 */
821 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
822 DELAY(10);
823
824 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
825 M_DEVBUF, M_NOWAIT);
826 if (sc->cbl_base == NULL)
827 goto fail;
828 bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
829
830 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT);
831 if (sc->fxp_stats == NULL)
832 goto fail;
833 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
834
835 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
836 if (sc->mcsp == NULL)
837 goto fail;
838
839 /*
840 * Pre-allocate our receive buffers.
841 */
842 for (i = 0; i < FXP_NRFABUFS; i++) {
843 if (fxp_add_rfabuf(sc, NULL) != 0) {
844 goto fail;
845 }
846 }
847
848 /*
849 * Find out how large of an SEEPROM we have.
850 */
851 fxp_autosize_eeprom(sc);
852
853 /*
854 * Get info about the primary PHY
855 */
856 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1);
857 sc->phy_primary_addr = data & 0xff;
858 sc->phy_primary_device = (data >> 8) & 0x3f;
859 sc->phy_10Mbps_only = data >> 15;
860
861 /*
862 * Read MAC address.
863 */
864 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3);
865
866 /*
867 * Initialize the media structures.
868 */
869
870 media = fxp_media_default;
871 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]);
872 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA;
873
874 for (i = 0; i < NFXPMEDIA; i++) {
875 if (sc->phy_primary_device == fxp_media[i].fsm_phy) {
876 media = fxp_media[i].fsm_media;
877 nmedia = fxp_media[i].fsm_nmedia;
878 defmedia = fxp_media[i].fsm_defmedia;
879 }
880 }
881
882 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus);
883 for (i = 0; i < nmedia; i++) {
884 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only)
885 continue;
886 ifmedia_add(&sc->sc_media, media[i], 0, NULL);
887 }
888 ifmedia_set(&sc->sc_media, defmedia);
889
890 return (0);
891
892 fail:
893 printf(FXP_FORMAT ": Failed to malloc memory\n", FXP_ARGS(sc));
894 if (sc->cbl_base)
895 free(sc->cbl_base, M_DEVBUF);
896 if (sc->fxp_stats)
897 free(sc->fxp_stats, M_DEVBUF);
898 if (sc->mcsp)
899 free(sc->mcsp, M_DEVBUF);
900 /* frees entire chain */
901 if (sc->rfa_headm)
902 m_freem(sc->rfa_headm);
903
904 return (ENOMEM);
905}
906
907/*
908 * From NetBSD:
909 *
910 * Figure out EEPROM size.
911 *
912 * 559's can have either 64-word or 256-word EEPROMs, the 558
913 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
914 * talks about the existance of 16 to 256 word EEPROMs.
915 *
916 * The only known sizes are 64 and 256, where the 256 version is used
917 * by CardBus cards to store CIS information.
918 *
919 * The address is shifted in msb-to-lsb, and after the last
920 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
921 * after which follows the actual data. We try to detect this zero, by
922 * probing the data-out bit in the EEPROM control register just after
923 * having shifted in a bit. If the bit is zero, we assume we've
924 * shifted enough address bits. The data-out should be tri-state,
925 * before this, which should translate to a logical one.
926 *
927 * Other ways to do this would be to try to read a register with known
928 * contents with a varying number of address bits, but no such
929 * register seem to be available. The high bits of register 10 are 01
930 * on the 558 and 559, but apparently not on the 557.
931 *
932 * The Linux driver computes a checksum on the EEPROM data, but the
933 * value of this checksum is not very well documented.
934 */
935static void
936fxp_autosize_eeprom(sc)
937 struct fxp_softc *sc;
938{
939 u_int16_t reg;
940 int x;
941
942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
943 /*
944 * Shift in read opcode.
945 */
946 for (x = 3; x > 0; x--) {
947 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
948 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
949 } else {
950 reg = FXP_EEPROM_EECS;
951 }
952 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
954 reg | FXP_EEPROM_EESK);
955 DELAY(1);
956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
957 DELAY(1);
958 }
959 /*
960 * Shift in address.
961 * Wait for the dummy zero following a correct address shift.
962 */
963 for (x = 1; x <= 8; x++) {
964 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
966 FXP_EEPROM_EECS | FXP_EEPROM_EESK);
967 DELAY(1);
968 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0)
969 break;
970 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
971 DELAY(1);
972 }
973 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
974 DELAY(1);
975 sc->eeprom_size = x;
976}
977/*
978 * Read from the serial EEPROM. Basically, you manually shift in
979 * the read opcode (one bit at a time) and then shift in the address,
980 * and then you shift out the data (all of this one bit at a time).
981 * The word size is 16 bits, so you have to provide the address for
982 * every 16 bits of data.
983 */
984static void
985fxp_read_eeprom(sc, data, offset, words)
986 struct fxp_softc *sc;
987 u_short *data;
988 int offset;
989 int words;
990{
991 u_int16_t reg;
992 int i, x;
993
994 for (i = 0; i < words; i++) {
995 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
996 /*
997 * Shift in read opcode.
998 */
999 for (x = 3; x > 0; x--) {
1000 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
1001 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1002 } else {
1003 reg = FXP_EEPROM_EECS;
1004 }
1005 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1006 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
1007 reg | FXP_EEPROM_EESK);
1008 DELAY(1);
1009 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1010 DELAY(1);
1011 }
1012 /*
1013 * Shift in address.
1014 */
1015 for (x = sc->eeprom_size; x > 0; x--) {
1016 if ((i + offset) & (1 << (x - 1))) {
1017 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1018 } else {
1019 reg = FXP_EEPROM_EECS;
1020 }
1021 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1022 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
1023 reg | FXP_EEPROM_EESK);
1024 DELAY(1);
1025 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1026 DELAY(1);
1027 }
1028 reg = FXP_EEPROM_EECS;
1029 data[i] = 0;
1030 /*
1031 * Shift out data.
1032 */
1033 for (x = 16; x > 0; x--) {
1034 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
1035 reg | FXP_EEPROM_EESK);
1036 DELAY(1);
1037 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
1038 FXP_EEPROM_EEDO)
1039 data[i] |= (1 << (x - 1));
1040 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1041 DELAY(1);
1042 }
1043 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1044 DELAY(1);
1045 }
1046}
1047
1048/*
1049 * Start packet transmission on the interface.
1050 */
1051static void
1052fxp_start(ifp)
1053 struct ifnet *ifp;
1054{
1055 struct fxp_softc *sc = ifp->if_softc;
1056 struct fxp_cb_tx *txp;
1057
1058#if !defined(__NetBSD__)
1059 FXP_LOCK(sc, s);
1060#endif
1061 /*
1062 * See if we need to suspend xmit until the multicast filter
1063 * has been reprogrammed (which can only be done at the head
1064 * of the command chain).
1065 */
1066 if (sc->need_mcsetup) {
1067 FXP_UNLOCK(sc, s);
1068 return;
1069 }
1070
1071 txp = NULL;
1072
1073 /*
1074 * We're finished if there is nothing more to add to the list or if
1075 * we're all filled up with buffers to transmit.
1076 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1077 * a NOP command when needed.
1078 */
1079 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1080 struct mbuf *m, *mb_head;
1081 int segment;
1082
1083 /*
1084 * Grab a packet to transmit.
1085 */
1086 IF_DEQUEUE(&ifp->if_snd, mb_head);
1087
1088 /*
1089 * Get pointer to next available tx desc.
1090 */
1091 txp = sc->cbl_last->next;
1092
1093 /*
1094 * Go through each of the mbufs in the chain and initialize
1095 * the transmit buffer descriptors with the physical address
1096 * and size of the mbuf.
1097 */
1098tbdinit:
1099 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1100 if (m->m_len != 0) {
1101 if (segment == FXP_NTXSEG)
1102 break;
1103 txp->tbd[segment].tb_addr =
1104 vtophys(mtod(m, vm_offset_t));
1105 txp->tbd[segment].tb_size = m->m_len;
1106 segment++;
1107 }
1108 }
1109 if (m != NULL) {
1110 struct mbuf *mn;
1111
1112 /*
1113 * We ran out of segments. We have to recopy this mbuf
1114 * chain first. Bail out if we can't get the new buffers.
1115 */
1116 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1117 if (mn == NULL) {
1118 m_freem(mb_head);
1119 break;
1120 }
1121 if (mb_head->m_pkthdr.len > MHLEN) {
1122 MCLGET(mn, M_DONTWAIT);
1123 if ((mn->m_flags & M_EXT) == 0) {
1124 m_freem(mn);
1125 m_freem(mb_head);
1126 break;
1127 }
1128 }
1129 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1130 mtod(mn, caddr_t));
1131 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1132 m_freem(mb_head);
1133 mb_head = mn;
1134 goto tbdinit;
1135 }
1136
1137 txp->tbd_number = segment;
1138 txp->mb_head = mb_head;
1139 txp->cb_status = 0;
1140 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1141 txp->cb_command =
1142 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S;
1143 } else {
1144 txp->cb_command =
1145 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1146 /*
1147 * Set a 5 second timer just in case we don't hear from the
1148 * card again.
1149 */
1150 ifp->if_timer = 5;
1151 }
1152 txp->tx_threshold = tx_threshold;
1153
1154 /*
1155 * Advance the end of list forward.
1156 */
1157
1158#ifdef __alpha__
1159 /*
1160 * On platforms which can't access memory in 16-bit
1161 * granularities, we must prevent the card from DMA'ing
1162 * up the status while we update the command field.
1163 * This could cause us to overwrite the completion status.
1164 */
1165 atomic_clear_short(&sc->cbl_last->cb_command,
1166 FXP_CB_COMMAND_S);
1167#else
1168 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1169#endif /*__alpha__*/
1170 sc->cbl_last = txp;
1171
1172 /*
1173 * Advance the beginning of the list forward if there are
1174 * no other packets queued (when nothing is queued, cbl_first
1175 * sits on the last TxCB that was sent out).
1176 */
1177 if (sc->tx_queued == 0)
1178 sc->cbl_first = txp;
1179
1180 sc->tx_queued++;
1181
1182 /*
1183 * Pass packet to bpf if there is a listener.
1184 */
1185 if (ifp->if_bpf)
1186 bpf_mtap(FXP_BPFTAP_ARG(ifp), mb_head);
1187 }
1188
1189 /*
1190 * We're finished. If we added to the list, issue a RESUME to get DMA
1191 * going again if suspended.
1192 */
1193 if (txp != NULL) {
1194 fxp_scb_wait(sc);
1195 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
1196 }
1197#if !defined(__NetBSD__)
1198 FXP_UNLOCK(sc, s);
1199#endif
1200}
1201
1202/*
1203 * Process interface interrupts.
1204 */
1205static FXP_INTR_TYPE
1206fxp_intr(arg)
1207 void *arg;
1208{
1209 struct fxp_softc *sc = arg;
1210 struct ifnet *ifp = &sc->sc_if;
1211 u_int8_t statack;
1212#if defined(__NetBSD__)
1213 int claimed = 0;
1214#else
1215
1216 FXP_LOCK(sc, s);
1217#endif
1218
|
1129 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
| 1219 while (!sc->suspended && (statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
|
1130#if defined(__NetBSD__)
1131 claimed = 1;
1132#endif
1133 /*
1134 * First ACK all the interrupts in this pass.
1135 */
1136 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1137
1138 /*
1139 * Free any finished transmit mbuf chains.
1140 *
1141 * Handle the CNA event likt a CXTNO event. It used to
1142 * be that this event (control unit not ready) was not
1143 * encountered, but it is now with the SMPng modifications.
1144 * The exact sequence of events that occur when the interface
1145 * is brought up are different now, and if this event
1146 * goes unhandled, the configuration/rxfilter setup sequence
1147 * can stall for several seconds. The result is that no
1148 * packets go out onto the wire for about 5 to 10 seconds
1149 * after the interface is ifconfig'ed for the first time.
1150 */
1151 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1152 struct fxp_cb_tx *txp;
1153
1154 for (txp = sc->cbl_first; sc->tx_queued &&
1155 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1156 txp = txp->next) {
1157 if (txp->mb_head != NULL) {
1158 m_freem(txp->mb_head);
1159 txp->mb_head = NULL;
1160 }
1161 sc->tx_queued--;
1162 }
1163 sc->cbl_first = txp;
1164 ifp->if_timer = 0;
1165 if (sc->tx_queued == 0) {
1166 if (sc->need_mcsetup)
1167 fxp_mc_setup(sc);
1168 }
1169 /*
1170 * Try to start more packets transmitting.
1171 */
1172 if (ifp->if_snd.ifq_head != NULL)
1173 fxp_start(ifp);
1174 }
1175 /*
1176 * Process receiver interrupts. If a no-resource (RNR)
1177 * condition exists, get whatever packets we can and
1178 * re-start the receiver.
1179 */
1180 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
1181 struct mbuf *m;
1182 struct fxp_rfa *rfa;
1183rcvloop:
1184 m = sc->rfa_headm;
1185 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1186 RFA_ALIGNMENT_FUDGE);
1187
1188 if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1189 /*
1190 * Remove first packet from the chain.
1191 */
1192 sc->rfa_headm = m->m_next;
1193 m->m_next = NULL;
1194
1195 /*
1196 * Add a new buffer to the receive chain.
1197 * If this fails, the old buffer is recycled
1198 * instead.
1199 */
1200 if (fxp_add_rfabuf(sc, m) == 0) {
1201 struct ether_header *eh;
1202 int total_len;
1203
1204 total_len = rfa->actual_size &
1205 (MCLBYTES - 1);
1206 if (total_len <
1207 sizeof(struct ether_header)) {
1208 m_freem(m);
1209 goto rcvloop;
1210 }
1211 m->m_pkthdr.rcvif = ifp;
1212 m->m_pkthdr.len = m->m_len = total_len;
1213 eh = mtod(m, struct ether_header *);
1214 m->m_data +=
1215 sizeof(struct ether_header);
1216 m->m_len -=
1217 sizeof(struct ether_header);
1218 m->m_pkthdr.len = m->m_len;
1219 ether_input(ifp, eh, m);
1220 }
1221 goto rcvloop;
1222 }
1223 if (statack & FXP_SCB_STATACK_RNR) {
1224 fxp_scb_wait(sc);
1225 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1226 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1227 RFA_ALIGNMENT_FUDGE);
1228 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
1229 FXP_SCB_COMMAND_RU_START);
1230 }
1231 }
1232 }
1233#if defined(__NetBSD__)
1234 return (claimed);
1235#else
1236 FXP_UNLOCK(sc, s);
1237#endif
1238}
1239
1240/*
1241 * Update packet in/out/collision statistics. The i82557 doesn't
1242 * allow you to access these counters without doing a fairly
1243 * expensive DMA to get _all_ of the statistics it maintains, so
1244 * we do this operation here only once per second. The statistics
1245 * counters in the kernel are updated from the previous dump-stats
1246 * DMA and then a new dump-stats DMA is started. The on-chip
1247 * counters are zeroed when the DMA completes. If we can't start
1248 * the DMA immediately, we don't wait - we just prepare to read
1249 * them again next time.
1250 */
1251static void
1252fxp_stats_update(arg)
1253 void *arg;
1254{
1255 struct fxp_softc *sc = arg;
1256 struct ifnet *ifp = &sc->sc_if;
1257 struct fxp_stats *sp = sc->fxp_stats;
1258 struct fxp_cb_tx *txp;
1259 FXP_SPLVAR(s)
1260
1261 ifp->if_opackets += sp->tx_good;
1262 ifp->if_collisions += sp->tx_total_collisions;
1263 if (sp->rx_good) {
1264 ifp->if_ipackets += sp->rx_good;
1265 sc->rx_idle_secs = 0;
1266 } else {
1267 /*
1268 * Receiver's been idle for another second.
1269 */
1270 sc->rx_idle_secs++;
1271 }
1272 ifp->if_ierrors +=
1273 sp->rx_crc_errors +
1274 sp->rx_alignment_errors +
1275 sp->rx_rnr_errors +
1276 sp->rx_overrun_errors;
1277 /*
1278 * If any transmit underruns occured, bump up the transmit
1279 * threshold by another 512 bytes (64 * 8).
1280 */
1281 if (sp->tx_underruns) {
1282 ifp->if_oerrors += sp->tx_underruns;
1283 if (tx_threshold < 192)
1284 tx_threshold += 64;
1285 }
1286 FXP_LOCK(sc, s);
1287 /*
1288 * Release any xmit buffers that have completed DMA. This isn't
1289 * strictly necessary to do here, but it's advantagous for mbufs
1290 * with external storage to be released in a timely manner rather
1291 * than being defered for a potentially long time. This limits
1292 * the delay to a maximum of one second.
1293 */
1294 for (txp = sc->cbl_first; sc->tx_queued &&
1295 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1296 txp = txp->next) {
1297 if (txp->mb_head != NULL) {
1298 m_freem(txp->mb_head);
1299 txp->mb_head = NULL;
1300 }
1301 sc->tx_queued--;
1302 }
1303 sc->cbl_first = txp;
1304 /*
1305 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1306 * then assume the receiver has locked up and attempt to clear
1307 * the condition by reprogramming the multicast filter. This is
1308 * a work-around for a bug in the 82557 where the receiver locks
1309 * up if it gets certain types of garbage in the syncronization
1310 * bits prior to the packet header. This bug is supposed to only
1311 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1312 * mode as well (perhaps due to a 10/100 speed transition).
1313 */
1314 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1315 sc->rx_idle_secs = 0;
1316 fxp_mc_setup(sc);
1317 }
1318 /*
1319 * If there is no pending command, start another stats
1320 * dump. Otherwise punt for now.
1321 */
1322 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1323 /*
1324 * Start another stats dump.
1325 */
1326 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
1327 FXP_SCB_COMMAND_CU_DUMPRESET);
1328 } else {
1329 /*
1330 * A previous command is still waiting to be accepted.
1331 * Just zero our copy of the stats and wait for the
1332 * next timer event to update them.
1333 */
1334 sp->tx_good = 0;
1335 sp->tx_underruns = 0;
1336 sp->tx_total_collisions = 0;
1337
1338 sp->rx_good = 0;
1339 sp->rx_crc_errors = 0;
1340 sp->rx_alignment_errors = 0;
1341 sp->rx_rnr_errors = 0;
1342 sp->rx_overrun_errors = 0;
1343 }
1344 FXP_UNLOCK(sc, s);
1345 /*
1346 * Schedule another timeout one second from now.
1347 */
1348 sc->stat_ch = timeout(fxp_stats_update, sc, hz);
1349}
1350
1351/*
1352 * Stop the interface. Cancels the statistics updater and resets
1353 * the interface.
1354 */
1355static void
1356fxp_stop(sc)
1357 struct fxp_softc *sc;
1358{
1359 struct ifnet *ifp = &sc->sc_if;
1360 struct fxp_cb_tx *txp;
1361 int i;
1362
1363#if !defined(__NetBSD__)
1364 FXP_LOCK(sc, s);
1365#endif
1366
| 1220#if defined(__NetBSD__)
1221 claimed = 1;
1222#endif
1223 /*
1224 * First ACK all the interrupts in this pass.
1225 */
1226 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1227
1228 /*
1229 * Free any finished transmit mbuf chains.
1230 *
1231 * Handle the CNA event likt a CXTNO event. It used to
1232 * be that this event (control unit not ready) was not
1233 * encountered, but it is now with the SMPng modifications.
1234 * The exact sequence of events that occur when the interface
1235 * is brought up are different now, and if this event
1236 * goes unhandled, the configuration/rxfilter setup sequence
1237 * can stall for several seconds. The result is that no
1238 * packets go out onto the wire for about 5 to 10 seconds
1239 * after the interface is ifconfig'ed for the first time.
1240 */
1241 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1242 struct fxp_cb_tx *txp;
1243
1244 for (txp = sc->cbl_first; sc->tx_queued &&
1245 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1246 txp = txp->next) {
1247 if (txp->mb_head != NULL) {
1248 m_freem(txp->mb_head);
1249 txp->mb_head = NULL;
1250 }
1251 sc->tx_queued--;
1252 }
1253 sc->cbl_first = txp;
1254 ifp->if_timer = 0;
1255 if (sc->tx_queued == 0) {
1256 if (sc->need_mcsetup)
1257 fxp_mc_setup(sc);
1258 }
1259 /*
1260 * Try to start more packets transmitting.
1261 */
1262 if (ifp->if_snd.ifq_head != NULL)
1263 fxp_start(ifp);
1264 }
1265 /*
1266 * Process receiver interrupts. If a no-resource (RNR)
1267 * condition exists, get whatever packets we can and
1268 * re-start the receiver.
1269 */
1270 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
1271 struct mbuf *m;
1272 struct fxp_rfa *rfa;
1273rcvloop:
1274 m = sc->rfa_headm;
1275 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1276 RFA_ALIGNMENT_FUDGE);
1277
1278 if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1279 /*
1280 * Remove first packet from the chain.
1281 */
1282 sc->rfa_headm = m->m_next;
1283 m->m_next = NULL;
1284
1285 /*
1286 * Add a new buffer to the receive chain.
1287 * If this fails, the old buffer is recycled
1288 * instead.
1289 */
1290 if (fxp_add_rfabuf(sc, m) == 0) {
1291 struct ether_header *eh;
1292 int total_len;
1293
1294 total_len = rfa->actual_size &
1295 (MCLBYTES - 1);
1296 if (total_len <
1297 sizeof(struct ether_header)) {
1298 m_freem(m);
1299 goto rcvloop;
1300 }
1301 m->m_pkthdr.rcvif = ifp;
1302 m->m_pkthdr.len = m->m_len = total_len;
1303 eh = mtod(m, struct ether_header *);
1304 m->m_data +=
1305 sizeof(struct ether_header);
1306 m->m_len -=
1307 sizeof(struct ether_header);
1308 m->m_pkthdr.len = m->m_len;
1309 ether_input(ifp, eh, m);
1310 }
1311 goto rcvloop;
1312 }
1313 if (statack & FXP_SCB_STATACK_RNR) {
1314 fxp_scb_wait(sc);
1315 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1316 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1317 RFA_ALIGNMENT_FUDGE);
1318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
1319 FXP_SCB_COMMAND_RU_START);
1320 }
1321 }
1322 }
1323#if defined(__NetBSD__)
1324 return (claimed);
1325#else
1326 FXP_UNLOCK(sc, s);
1327#endif
1328}
1329
1330/*
1331 * Update packet in/out/collision statistics. The i82557 doesn't
1332 * allow you to access these counters without doing a fairly
1333 * expensive DMA to get _all_ of the statistics it maintains, so
1334 * we do this operation here only once per second. The statistics
1335 * counters in the kernel are updated from the previous dump-stats
1336 * DMA and then a new dump-stats DMA is started. The on-chip
1337 * counters are zeroed when the DMA completes. If we can't start
1338 * the DMA immediately, we don't wait - we just prepare to read
1339 * them again next time.
1340 */
1341static void
1342fxp_stats_update(arg)
1343 void *arg;
1344{
1345 struct fxp_softc *sc = arg;
1346 struct ifnet *ifp = &sc->sc_if;
1347 struct fxp_stats *sp = sc->fxp_stats;
1348 struct fxp_cb_tx *txp;
1349 FXP_SPLVAR(s)
1350
1351 ifp->if_opackets += sp->tx_good;
1352 ifp->if_collisions += sp->tx_total_collisions;
1353 if (sp->rx_good) {
1354 ifp->if_ipackets += sp->rx_good;
1355 sc->rx_idle_secs = 0;
1356 } else {
1357 /*
1358 * Receiver's been idle for another second.
1359 */
1360 sc->rx_idle_secs++;
1361 }
1362 ifp->if_ierrors +=
1363 sp->rx_crc_errors +
1364 sp->rx_alignment_errors +
1365 sp->rx_rnr_errors +
1366 sp->rx_overrun_errors;
1367 /*
1368 * If any transmit underruns occured, bump up the transmit
1369 * threshold by another 512 bytes (64 * 8).
1370 */
1371 if (sp->tx_underruns) {
1372 ifp->if_oerrors += sp->tx_underruns;
1373 if (tx_threshold < 192)
1374 tx_threshold += 64;
1375 }
1376 FXP_LOCK(sc, s);
1377 /*
1378 * Release any xmit buffers that have completed DMA. This isn't
1379 * strictly necessary to do here, but it's advantagous for mbufs
1380 * with external storage to be released in a timely manner rather
1381 * than being defered for a potentially long time. This limits
1382 * the delay to a maximum of one second.
1383 */
1384 for (txp = sc->cbl_first; sc->tx_queued &&
1385 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1386 txp = txp->next) {
1387 if (txp->mb_head != NULL) {
1388 m_freem(txp->mb_head);
1389 txp->mb_head = NULL;
1390 }
1391 sc->tx_queued--;
1392 }
1393 sc->cbl_first = txp;
1394 /*
1395 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1396 * then assume the receiver has locked up and attempt to clear
1397 * the condition by reprogramming the multicast filter. This is
1398 * a work-around for a bug in the 82557 where the receiver locks
1399 * up if it gets certain types of garbage in the syncronization
1400 * bits prior to the packet header. This bug is supposed to only
1401 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1402 * mode as well (perhaps due to a 10/100 speed transition).
1403 */
1404 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1405 sc->rx_idle_secs = 0;
1406 fxp_mc_setup(sc);
1407 }
1408 /*
1409 * If there is no pending command, start another stats
1410 * dump. Otherwise punt for now.
1411 */
1412 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1413 /*
1414 * Start another stats dump.
1415 */
1416 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
1417 FXP_SCB_COMMAND_CU_DUMPRESET);
1418 } else {
1419 /*
1420 * A previous command is still waiting to be accepted.
1421 * Just zero our copy of the stats and wait for the
1422 * next timer event to update them.
1423 */
1424 sp->tx_good = 0;
1425 sp->tx_underruns = 0;
1426 sp->tx_total_collisions = 0;
1427
1428 sp->rx_good = 0;
1429 sp->rx_crc_errors = 0;
1430 sp->rx_alignment_errors = 0;
1431 sp->rx_rnr_errors = 0;
1432 sp->rx_overrun_errors = 0;
1433 }
1434 FXP_UNLOCK(sc, s);
1435 /*
1436 * Schedule another timeout one second from now.
1437 */
1438 sc->stat_ch = timeout(fxp_stats_update, sc, hz);
1439}
1440
1441/*
1442 * Stop the interface. Cancels the statistics updater and resets
1443 * the interface.
1444 */
1445static void
1446fxp_stop(sc)
1447 struct fxp_softc *sc;
1448{
1449 struct ifnet *ifp = &sc->sc_if;
1450 struct fxp_cb_tx *txp;
1451 int i;
1452
1453#if !defined(__NetBSD__)
1454 FXP_LOCK(sc, s);
1455#endif
1456
|
| 1457 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1458 ifp->if_timer = 0;
1459
|
1367 /*
1368 * Cancel stats updater.
1369 */
1370 untimeout(fxp_stats_update, sc, sc->stat_ch);
1371
1372 /*
1373 * Issue software reset
1374 */
1375 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1376 DELAY(10);
1377
1378 /*
1379 * Release any xmit buffers.
1380 */
1381 txp = sc->cbl_base;
1382 if (txp != NULL) {
1383 for (i = 0; i < FXP_NTXCB; i++) {
1384 if (txp[i].mb_head != NULL) {
1385 m_freem(txp[i].mb_head);
1386 txp[i].mb_head = NULL;
1387 }
1388 }
1389 }
1390 sc->tx_queued = 0;
1391
1392 /*
1393 * Free all the receive buffers then reallocate/reinitialize
1394 */
1395 if (sc->rfa_headm != NULL)
1396 m_freem(sc->rfa_headm);
1397 sc->rfa_headm = NULL;
1398 sc->rfa_tailm = NULL;
1399 for (i = 0; i < FXP_NRFABUFS; i++) {
1400 if (fxp_add_rfabuf(sc, NULL) != 0) {
1401 /*
1402 * This "can't happen" - we're at splimp()
1403 * and we just freed all the buffers we need
1404 * above.
1405 */
1406 panic("fxp_stop: no buffers!");
1407 }
1408 }
1409
| 1460 /*
1461 * Cancel stats updater.
1462 */
1463 untimeout(fxp_stats_update, sc, sc->stat_ch);
1464
1465 /*
1466 * Issue software reset
1467 */
1468 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1469 DELAY(10);
1470
1471 /*
1472 * Release any xmit buffers.
1473 */
1474 txp = sc->cbl_base;
1475 if (txp != NULL) {
1476 for (i = 0; i < FXP_NTXCB; i++) {
1477 if (txp[i].mb_head != NULL) {
1478 m_freem(txp[i].mb_head);
1479 txp[i].mb_head = NULL;
1480 }
1481 }
1482 }
1483 sc->tx_queued = 0;
1484
1485 /*
1486 * Free all the receive buffers then reallocate/reinitialize
1487 */
1488 if (sc->rfa_headm != NULL)
1489 m_freem(sc->rfa_headm);
1490 sc->rfa_headm = NULL;
1491 sc->rfa_tailm = NULL;
1492 for (i = 0; i < FXP_NRFABUFS; i++) {
1493 if (fxp_add_rfabuf(sc, NULL) != 0) {
1494 /*
1495 * This "can't happen" - we're at splimp()
1496 * and we just freed all the buffers we need
1497 * above.
1498 */
1499 panic("fxp_stop: no buffers!");
1500 }
1501 }
1502
|
1410 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1411 ifp->if_timer = 0;
| |
1412#if !defined(__NetBSD__)
1413 FXP_UNLOCK(sc, s);
1414#endif
1415}
1416
1417/*
1418 * Watchdog/transmission transmit timeout handler. Called when a
1419 * transmission is started on the interface, but no interrupt is
1420 * received before the timeout. This usually indicates that the
1421 * card has wedged for some reason.
1422 */
1423static void
1424fxp_watchdog(ifp)
1425 struct ifnet *ifp;
1426{
1427 struct fxp_softc *sc = ifp->if_softc;
1428
1429 printf(FXP_FORMAT ": device timeout\n", FXP_ARGS(sc));
1430 ifp->if_oerrors++;
1431
1432 fxp_init(sc);
1433}
1434
1435static void
1436fxp_init(xsc)
1437 void *xsc;
1438{
1439 struct fxp_softc *sc = xsc;
1440 struct ifnet *ifp = &sc->sc_if;
1441 struct fxp_cb_config *cbp;
1442 struct fxp_cb_ias *cb_ias;
1443 struct fxp_cb_tx *txp;
1444 int i, prm;
1445 FXP_SPLVAR(s)
1446
1447 FXP_LOCK(sc, s);
1448 /*
1449 * Cancel any pending I/O
1450 */
1451 fxp_stop(sc);
1452
1453 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1454
1455 /*
1456 * Initialize base of CBL and RFA memory. Loading with zero
1457 * sets it up for regular linear addressing.
1458 */
1459 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1460 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
1461
1462 fxp_scb_wait(sc);
1463 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
1464
1465 /*
1466 * Initialize base of dump-stats buffer.
1467 */
1468 fxp_scb_wait(sc);
1469 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1470 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR);
1471
1472 /*
1473 * We temporarily use memory that contains the TxCB list to
1474 * construct the config CB. The TxCB list memory is rebuilt
1475 * later.
1476 */
1477 cbp = (struct fxp_cb_config *) sc->cbl_base;
1478
1479 /*
1480 * This bcopy is kind of disgusting, but there are a bunch of must be
1481 * zero and must be one bits in this structure and this is the easiest
1482 * way to initialize them all to proper values.
1483 */
1484 bcopy(fxp_cb_config_template,
1485 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1486 sizeof(fxp_cb_config_template));
1487
1488 cbp->cb_status = 0;
1489 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1490 cbp->link_addr = -1; /* (no) next command */
1491 cbp->byte_count = 22; /* (22) bytes to config */
1492 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1493 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1494 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1495 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1496 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1497 cbp->dma_bce = 0; /* (disable) dma max counters */
1498 cbp->late_scb = 0; /* (don't) defer SCB update */
1499 cbp->tno_int = 0; /* (disable) tx not okay interrupt */
1500 cbp->ci_int = 1; /* interrupt on CU idle */
1501 cbp->save_bf = prm; /* save bad frames */
1502 cbp->disc_short_rx = !prm; /* discard short packets */
1503 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
1504 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */
1505 cbp->nsai = 1; /* (don't) disable source addr insert */
1506 cbp->preamble_length = 2; /* (7 byte) preamble */
1507 cbp->loopback = 0; /* (don't) loopback */
1508 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1509 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1510 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1511 cbp->promiscuous = prm; /* promiscuous mode */
1512 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1513 cbp->crscdt = 0; /* (CRS only) */
1514 cbp->stripping = !prm; /* truncate rx packet to byte count */
1515 cbp->padding = 1; /* (do) pad short tx packets */
1516 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1517 cbp->force_fdx = 0; /* (don't) force full duplex */
1518 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1519 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1520 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */
1521
1522 /*
1523 * Start the config command/DMA.
1524 */
1525 fxp_scb_wait(sc);
1526 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1527 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1528 /* ...and wait for it to complete. */
| 1503#if !defined(__NetBSD__)
1504 FXP_UNLOCK(sc, s);
1505#endif
1506}
1507
1508/*
1509 * Watchdog/transmission transmit timeout handler. Called when a
1510 * transmission is started on the interface, but no interrupt is
1511 * received before the timeout. This usually indicates that the
1512 * card has wedged for some reason.
1513 */
1514static void
1515fxp_watchdog(ifp)
1516 struct ifnet *ifp;
1517{
1518 struct fxp_softc *sc = ifp->if_softc;
1519
1520 printf(FXP_FORMAT ": device timeout\n", FXP_ARGS(sc));
1521 ifp->if_oerrors++;
1522
1523 fxp_init(sc);
1524}
1525
1526static void
1527fxp_init(xsc)
1528 void *xsc;
1529{
1530 struct fxp_softc *sc = xsc;
1531 struct ifnet *ifp = &sc->sc_if;
1532 struct fxp_cb_config *cbp;
1533 struct fxp_cb_ias *cb_ias;
1534 struct fxp_cb_tx *txp;
1535 int i, prm;
1536 FXP_SPLVAR(s)
1537
1538 FXP_LOCK(sc, s);
1539 /*
1540 * Cancel any pending I/O
1541 */
1542 fxp_stop(sc);
1543
1544 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1545
1546 /*
1547 * Initialize base of CBL and RFA memory. Loading with zero
1548 * sets it up for regular linear addressing.
1549 */
1550 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1551 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
1552
1553 fxp_scb_wait(sc);
1554 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
1555
1556 /*
1557 * Initialize base of dump-stats buffer.
1558 */
1559 fxp_scb_wait(sc);
1560 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1561 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR);
1562
1563 /*
1564 * We temporarily use memory that contains the TxCB list to
1565 * construct the config CB. The TxCB list memory is rebuilt
1566 * later.
1567 */
1568 cbp = (struct fxp_cb_config *) sc->cbl_base;
1569
1570 /*
1571 * This bcopy is kind of disgusting, but there are a bunch of must be
1572 * zero and must be one bits in this structure and this is the easiest
1573 * way to initialize them all to proper values.
1574 */
1575 bcopy(fxp_cb_config_template,
1576 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1577 sizeof(fxp_cb_config_template));
1578
1579 cbp->cb_status = 0;
1580 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1581 cbp->link_addr = -1; /* (no) next command */
1582 cbp->byte_count = 22; /* (22) bytes to config */
1583 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1584 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1585 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1586 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1587 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1588 cbp->dma_bce = 0; /* (disable) dma max counters */
1589 cbp->late_scb = 0; /* (don't) defer SCB update */
1590 cbp->tno_int = 0; /* (disable) tx not okay interrupt */
1591 cbp->ci_int = 1; /* interrupt on CU idle */
1592 cbp->save_bf = prm; /* save bad frames */
1593 cbp->disc_short_rx = !prm; /* discard short packets */
1594 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
1595 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */
1596 cbp->nsai = 1; /* (don't) disable source addr insert */
1597 cbp->preamble_length = 2; /* (7 byte) preamble */
1598 cbp->loopback = 0; /* (don't) loopback */
1599 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1600 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1601 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1602 cbp->promiscuous = prm; /* promiscuous mode */
1603 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1604 cbp->crscdt = 0; /* (CRS only) */
1605 cbp->stripping = !prm; /* truncate rx packet to byte count */
1606 cbp->padding = 1; /* (do) pad short tx packets */
1607 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1608 cbp->force_fdx = 0; /* (don't) force full duplex */
1609 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1610 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1611 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */
1612
1613 /*
1614 * Start the config command/DMA.
1615 */
1616 fxp_scb_wait(sc);
1617 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1618 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1619 /* ...and wait for it to complete. */
|
1529 while (!(cbp->cb_status & FXP_CB_STATUS_C));
| 1620 fxp_dma_wait(&cbp->cb_status, sc);
|
1530
1531 /*
1532 * Now initialize the station address. Temporarily use the TxCB
1533 * memory area like we did above for the config CB.
1534 */
1535 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1536 cb_ias->cb_status = 0;
1537 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1538 cb_ias->link_addr = -1;
1539#if defined(__NetBSD__)
1540 bcopy(LLADDR(ifp->if_sadl), (void *)cb_ias->macaddr, 6);
1541#else
1542 bcopy(sc->arpcom.ac_enaddr,
1543 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1544 sizeof(sc->arpcom.ac_enaddr));
1545#endif /* __NetBSD__ */
1546
1547 /*
1548 * Start the IAS (Individual Address Setup) command/DMA.
1549 */
1550 fxp_scb_wait(sc);
1551 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1552 /* ...and wait for it to complete. */
| 1621
1622 /*
1623 * Now initialize the station address. Temporarily use the TxCB
1624 * memory area like we did above for the config CB.
1625 */
1626 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1627 cb_ias->cb_status = 0;
1628 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1629 cb_ias->link_addr = -1;
1630#if defined(__NetBSD__)
1631 bcopy(LLADDR(ifp->if_sadl), (void *)cb_ias->macaddr, 6);
1632#else
1633 bcopy(sc->arpcom.ac_enaddr,
1634 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1635 sizeof(sc->arpcom.ac_enaddr));
1636#endif /* __NetBSD__ */
1637
1638 /*
1639 * Start the IAS (Individual Address Setup) command/DMA.
1640 */
1641 fxp_scb_wait(sc);
1642 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1643 /* ...and wait for it to complete. */
|
1553 while (!(cb_ias->cb_status & FXP_CB_STATUS_C));
| 1644 fxp_dma_wait(&cb_ias->cb_status, sc);
|
1554
1555 /*
1556 * Initialize transmit control block (TxCB) list.
1557 */
1558
1559 txp = sc->cbl_base;
1560 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1561 for (i = 0; i < FXP_NTXCB; i++) {
1562 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1563 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1564 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1565 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1566 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1567 }
1568 /*
1569 * Set the suspend flag on the first TxCB and start the control
1570 * unit. It will execute the NOP and then suspend.
1571 */
1572 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1573 sc->cbl_first = sc->cbl_last = txp;
1574 sc->tx_queued = 1;
1575
1576 fxp_scb_wait(sc);
1577 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1578
1579 /*
1580 * Initialize receiver buffer area - RFA.
1581 */
1582 fxp_scb_wait(sc);
1583 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1584 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1585 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
1586
1587 /*
1588 * Set current media.
1589 */
1590 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
1591
1592 ifp->if_flags |= IFF_RUNNING;
1593 ifp->if_flags &= ~IFF_OACTIVE;
1594 FXP_UNLOCK(sc, s);
1595
1596 /*
1597 * Start stats updater.
1598 */
1599 sc->stat_ch = timeout(fxp_stats_update, sc, hz);
1600}
1601
1602static void
1603fxp_set_media(sc, media)
1604 struct fxp_softc *sc;
1605 int media;
1606{
1607
1608 switch (sc->phy_primary_device) {
1609 case FXP_PHY_DP83840:
1610 case FXP_PHY_DP83840A:
1611 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
1612 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
1613 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
1614 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
1615 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
1616 /* fall through */
1617 case FXP_PHY_82553A:
1618 case FXP_PHY_82553C: /* untested */
1619 case FXP_PHY_82555:
1620 case FXP_PHY_82555B:
1621 if (IFM_SUBTYPE(media) != IFM_AUTO) {
1622 int flags;
1623
1624 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ?
1625 FXP_PHY_BMCR_SPEED_100M : 0;
1626 flags |= (media & IFM_FDX) ?
1627 FXP_PHY_BMCR_FULLDUPLEX : 0;
1628 fxp_mdi_write(sc, sc->phy_primary_addr,
1629 FXP_PHY_BMCR,
1630 (fxp_mdi_read(sc, sc->phy_primary_addr,
1631 FXP_PHY_BMCR) &
1632 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
1633 FXP_PHY_BMCR_FULLDUPLEX)) | flags);
1634 } else {
1635 fxp_mdi_write(sc, sc->phy_primary_addr,
1636 FXP_PHY_BMCR,
1637 (fxp_mdi_read(sc, sc->phy_primary_addr,
1638 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN));
1639 }
1640 break;
1641 /*
1642 * The Seeq 80c24 doesn't have a PHY programming interface, so do
1643 * nothing.
1644 */
1645 case FXP_PHY_80C24:
1646 break;
1647 default:
1648 printf(FXP_FORMAT
1649 ": warning: unsupported PHY, type = %d, addr = %d\n",
1650 FXP_ARGS(sc), sc->phy_primary_device,
1651 sc->phy_primary_addr);
1652 }
1653}
1654
1655/*
1656 * Change media according to request.
1657 */
1658int
1659fxp_mediachange(ifp)
1660 struct ifnet *ifp;
1661{
1662 struct fxp_softc *sc = ifp->if_softc;
1663 struct ifmedia *ifm = &sc->sc_media;
1664
1665 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1666 return (EINVAL);
1667
1668 fxp_set_media(sc, ifm->ifm_media);
1669 return (0);
1670}
1671
1672/*
1673 * Notify the world which media we're using.
1674 */
1675void
1676fxp_mediastatus(ifp, ifmr)
1677 struct ifnet *ifp;
1678 struct ifmediareq *ifmr;
1679{
1680 struct fxp_softc *sc = ifp->if_softc;
1681 int flags, stsflags;
1682
1683 switch (sc->phy_primary_device) {
1684 case FXP_PHY_82555:
1685 case FXP_PHY_82555B:
1686 case FXP_PHY_DP83840:
1687 case FXP_PHY_DP83840A:
1688 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */
1689 ifmr->ifm_active = IFM_ETHER;
1690 /*
1691 * the following is not an error.
1692 * You need to read this register twice to get current
1693 * status. This is correct documented behaviour, the
1694 * first read gets latched values.
1695 */
1696 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
1697 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
1698 if (stsflags & FXP_PHY_STS_LINK_STS)
1699 ifmr->ifm_status |= IFM_ACTIVE;
1700
1701 /*
1702 * If we are in auto mode, then try report the result.
1703 */
1704 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR);
1705 if (flags & FXP_PHY_BMCR_AUTOEN) {
1706 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */
1707 if (stsflags & FXP_PHY_STS_AUTO_DONE) {
1708 /*
1709 * Intel and National parts report
1710 * differently on what they found.
1711 */
1712 if ((sc->phy_primary_device == FXP_PHY_82555)
1713 || (sc->phy_primary_device == FXP_PHY_82555B)) {
1714 flags = fxp_mdi_read(sc,
1715 sc->phy_primary_addr,
1716 FXP_PHY_USC);
1717
1718 if (flags & FXP_PHY_USC_SPEED)
1719 ifmr->ifm_active |= IFM_100_TX;
1720 else
1721 ifmr->ifm_active |= IFM_10_T;
1722
1723 if (flags & FXP_PHY_USC_DUPLEX)
1724 ifmr->ifm_active |= IFM_FDX;
1725 } else { /* it's National. only know speed */
1726 flags = fxp_mdi_read(sc,
1727 sc->phy_primary_addr,
1728 FXP_DP83840_PAR);
1729
1730 if (flags & FXP_DP83840_PAR_SPEED_10)
1731 ifmr->ifm_active |= IFM_10_T;
1732 else
1733 ifmr->ifm_active |= IFM_100_TX;
1734 }
1735 }
1736 } else { /* in manual mode.. just report what we were set to */
1737 if (flags & FXP_PHY_BMCR_SPEED_100M)
1738 ifmr->ifm_active |= IFM_100_TX;
1739 else
1740 ifmr->ifm_active |= IFM_10_T;
1741
1742 if (flags & FXP_PHY_BMCR_FULLDUPLEX)
1743 ifmr->ifm_active |= IFM_FDX;
1744 }
1745 break;
1746
1747 case FXP_PHY_80C24:
1748 default:
1749 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */
1750 }
1751}
1752
1753/*
1754 * Add a buffer to the end of the RFA buffer list.
1755 * Return 0 if successful, 1 for failure. A failure results in
1756 * adding the 'oldm' (if non-NULL) on to the end of the list -
1757 * tossing out its old contents and recycling it.
1758 * The RFA struct is stuck at the beginning of mbuf cluster and the
1759 * data pointer is fixed up to point just past it.
1760 */
1761static int
1762fxp_add_rfabuf(sc, oldm)
1763 struct fxp_softc *sc;
1764 struct mbuf *oldm;
1765{
1766 u_int32_t v;
1767 struct mbuf *m;
1768 struct fxp_rfa *rfa, *p_rfa;
1769
1770 MGETHDR(m, M_DONTWAIT, MT_DATA);
1771 if (m != NULL) {
1772 MCLGET(m, M_DONTWAIT);
1773 if ((m->m_flags & M_EXT) == 0) {
1774 m_freem(m);
1775 if (oldm == NULL)
1776 return 1;
1777 m = oldm;
1778 m->m_data = m->m_ext.ext_buf;
1779 }
1780 } else {
1781 if (oldm == NULL)
1782 return 1;
1783 m = oldm;
1784 m->m_data = m->m_ext.ext_buf;
1785 }
1786
1787 /*
1788 * Move the data pointer up so that the incoming data packet
1789 * will be 32-bit aligned.
1790 */
1791 m->m_data += RFA_ALIGNMENT_FUDGE;
1792
1793 /*
1794 * Get a pointer to the base of the mbuf cluster and move
1795 * data start past it.
1796 */
1797 rfa = mtod(m, struct fxp_rfa *);
1798 m->m_data += sizeof(struct fxp_rfa);
1799 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1800
1801 /*
1802 * Initialize the rest of the RFA. Note that since the RFA
1803 * is misaligned, we cannot store values directly. Instead,
1804 * we use an optimized, inline copy.
1805 */
1806
1807 rfa->rfa_status = 0;
1808 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1809 rfa->actual_size = 0;
1810
1811 v = -1;
1812 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1813 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1814
1815 /*
1816 * If there are other buffers already on the list, attach this
1817 * one to the end by fixing up the tail to point to this one.
1818 */
1819 if (sc->rfa_headm != NULL) {
1820 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1821 RFA_ALIGNMENT_FUDGE);
1822 sc->rfa_tailm->m_next = m;
1823 v = vtophys(rfa);
1824 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1825 p_rfa->rfa_control = 0;
1826 } else {
1827 sc->rfa_headm = m;
1828 }
1829 sc->rfa_tailm = m;
1830
1831 return (m == oldm);
1832}
1833
1834static volatile int
1835fxp_mdi_read(sc, phy, reg)
1836 struct fxp_softc *sc;
1837 int phy;
1838 int reg;
1839{
1840 int count = 10000;
1841 int value;
1842
1843 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1844 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1845
1846 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1847 && count--)
1848 DELAY(10);
1849
1850 if (count <= 0)
1851 printf(FXP_FORMAT ": fxp_mdi_read: timed out\n",
1852 FXP_ARGS(sc));
1853
1854 return (value & 0xffff);
1855}
1856
1857static void
1858fxp_mdi_write(sc, phy, reg, value)
1859 struct fxp_softc *sc;
1860 int phy;
1861 int reg;
1862 int value;
1863{
1864 int count = 10000;
1865
1866 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1867 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1868 (value & 0xffff));
1869
1870 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1871 count--)
1872 DELAY(10);
1873
1874 if (count <= 0)
1875 printf(FXP_FORMAT ": fxp_mdi_write: timed out\n",
1876 FXP_ARGS(sc));
1877}
1878
1879static int
1880fxp_ioctl(ifp, command, data)
1881 struct ifnet *ifp;
1882 FXP_IOCTLCMD_TYPE command;
1883 caddr_t data;
1884{
1885 struct fxp_softc *sc = ifp->if_softc;
1886 struct ifreq *ifr = (struct ifreq *)data;
1887 FXP_SPLVAR(s)
1888 int error = 0;
1889
1890 FXP_LOCK(sc, s);
1891
1892 switch (command) {
1893
1894 case SIOCSIFADDR:
1895#if !defined(__NetBSD__)
1896 case SIOCGIFADDR:
1897 case SIOCSIFMTU:
1898#endif
1899 error = ether_ioctl(ifp, command, data);
1900 break;
1901
1902 case SIOCSIFFLAGS:
1903 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1904
1905 /*
1906 * If interface is marked up and not running, then start it.
1907 * If it is marked down and running, stop it.
1908 * XXX If it's up then re-initialize it. This is so flags
1909 * such as IFF_PROMISC are handled.
1910 */
1911 if (ifp->if_flags & IFF_UP) {
1912 fxp_init(sc);
1913 } else {
1914 if (ifp->if_flags & IFF_RUNNING)
1915 fxp_stop(sc);
1916 }
1917 break;
1918
1919 case SIOCADDMULTI:
1920 case SIOCDELMULTI:
1921 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1922#if defined(__NetBSD__)
1923 error = (command == SIOCADDMULTI) ?
1924 ether_addmulti(ifr, &sc->sc_ethercom) :
1925 ether_delmulti(ifr, &sc->sc_ethercom);
1926
1927 if (error == ENETRESET) {
1928 /*
1929 * Multicast list has changed; set the hardware
1930 * filter accordingly.
1931 */
1932 if (!sc->all_mcasts)
1933 fxp_mc_setup(sc);
1934 /*
1935 * fxp_mc_setup() can turn on all_mcasts if we run
1936 * out of space, so check it again rather than else {}.
1937 */
1938 if (sc->all_mcasts)
1939 fxp_init(sc);
1940 error = 0;
1941 }
1942#else /* __FreeBSD__ */
1943 /*
1944 * Multicast list has changed; set the hardware filter
1945 * accordingly.
1946 */
1947 if (!sc->all_mcasts)
1948 fxp_mc_setup(sc);
1949 /*
1950 * fxp_mc_setup() can turn on sc->all_mcasts, so check it
1951 * again rather than else {}.
1952 */
1953 if (sc->all_mcasts)
1954 fxp_init(sc);
1955 error = 0;
1956#endif /* __NetBSD__ */
1957 break;
1958
1959 case SIOCSIFMEDIA:
1960 case SIOCGIFMEDIA:
1961 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
1962 break;
1963
1964 default:
1965 error = EINVAL;
1966 }
1967 FXP_UNLOCK(sc, s);
1968 return (error);
1969}
1970
1971/*
1972 * Program the multicast filter.
1973 *
1974 * We have an artificial restriction that the multicast setup command
1975 * must be the first command in the chain, so we take steps to ensure
1976 * this. By requiring this, it allows us to keep up the performance of
1977 * the pre-initialized command ring (esp. link pointers) by not actually
1978 * inserting the mcsetup command in the ring - i.e. its link pointer
1979 * points to the TxCB ring, but the mcsetup descriptor itself is not part
1980 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
1981 * lead into the regular TxCB ring when it completes.
1982 *
1983 * This function must be called at splimp.
1984 */
1985static void
1986fxp_mc_setup(sc)
1987 struct fxp_softc *sc;
1988{
1989 struct fxp_cb_mcs *mcsp = sc->mcsp;
1990 struct ifnet *ifp = &sc->sc_if;
1991 struct ifmultiaddr *ifma;
1992 int nmcasts;
| 1645
1646 /*
1647 * Initialize transmit control block (TxCB) list.
1648 */
1649
1650 txp = sc->cbl_base;
1651 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1652 for (i = 0; i < FXP_NTXCB; i++) {
1653 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1654 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1655 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1656 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1657 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1658 }
1659 /*
1660 * Set the suspend flag on the first TxCB and start the control
1661 * unit. It will execute the NOP and then suspend.
1662 */
1663 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1664 sc->cbl_first = sc->cbl_last = txp;
1665 sc->tx_queued = 1;
1666
1667 fxp_scb_wait(sc);
1668 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1669
1670 /*
1671 * Initialize receiver buffer area - RFA.
1672 */
1673 fxp_scb_wait(sc);
1674 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1675 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1676 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
1677
1678 /*
1679 * Set current media.
1680 */
1681 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
1682
1683 ifp->if_flags |= IFF_RUNNING;
1684 ifp->if_flags &= ~IFF_OACTIVE;
1685 FXP_UNLOCK(sc, s);
1686
1687 /*
1688 * Start stats updater.
1689 */
1690 sc->stat_ch = timeout(fxp_stats_update, sc, hz);
1691}
1692
1693static void
1694fxp_set_media(sc, media)
1695 struct fxp_softc *sc;
1696 int media;
1697{
1698
1699 switch (sc->phy_primary_device) {
1700 case FXP_PHY_DP83840:
1701 case FXP_PHY_DP83840A:
1702 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
1703 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
1704 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
1705 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
1706 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
1707 /* fall through */
1708 case FXP_PHY_82553A:
1709 case FXP_PHY_82553C: /* untested */
1710 case FXP_PHY_82555:
1711 case FXP_PHY_82555B:
1712 if (IFM_SUBTYPE(media) != IFM_AUTO) {
1713 int flags;
1714
1715 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ?
1716 FXP_PHY_BMCR_SPEED_100M : 0;
1717 flags |= (media & IFM_FDX) ?
1718 FXP_PHY_BMCR_FULLDUPLEX : 0;
1719 fxp_mdi_write(sc, sc->phy_primary_addr,
1720 FXP_PHY_BMCR,
1721 (fxp_mdi_read(sc, sc->phy_primary_addr,
1722 FXP_PHY_BMCR) &
1723 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
1724 FXP_PHY_BMCR_FULLDUPLEX)) | flags);
1725 } else {
1726 fxp_mdi_write(sc, sc->phy_primary_addr,
1727 FXP_PHY_BMCR,
1728 (fxp_mdi_read(sc, sc->phy_primary_addr,
1729 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN));
1730 }
1731 break;
1732 /*
1733 * The Seeq 80c24 doesn't have a PHY programming interface, so do
1734 * nothing.
1735 */
1736 case FXP_PHY_80C24:
1737 break;
1738 default:
1739 printf(FXP_FORMAT
1740 ": warning: unsupported PHY, type = %d, addr = %d\n",
1741 FXP_ARGS(sc), sc->phy_primary_device,
1742 sc->phy_primary_addr);
1743 }
1744}
1745
1746/*
1747 * Change media according to request.
1748 */
1749int
1750fxp_mediachange(ifp)
1751 struct ifnet *ifp;
1752{
1753 struct fxp_softc *sc = ifp->if_softc;
1754 struct ifmedia *ifm = &sc->sc_media;
1755
1756 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1757 return (EINVAL);
1758
1759 fxp_set_media(sc, ifm->ifm_media);
1760 return (0);
1761}
1762
1763/*
1764 * Notify the world which media we're using.
1765 */
1766void
1767fxp_mediastatus(ifp, ifmr)
1768 struct ifnet *ifp;
1769 struct ifmediareq *ifmr;
1770{
1771 struct fxp_softc *sc = ifp->if_softc;
1772 int flags, stsflags;
1773
1774 switch (sc->phy_primary_device) {
1775 case FXP_PHY_82555:
1776 case FXP_PHY_82555B:
1777 case FXP_PHY_DP83840:
1778 case FXP_PHY_DP83840A:
1779 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */
1780 ifmr->ifm_active = IFM_ETHER;
1781 /*
1782 * the following is not an error.
1783 * You need to read this register twice to get current
1784 * status. This is correct documented behaviour, the
1785 * first read gets latched values.
1786 */
1787 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
1788 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
1789 if (stsflags & FXP_PHY_STS_LINK_STS)
1790 ifmr->ifm_status |= IFM_ACTIVE;
1791
1792 /*
1793 * If we are in auto mode, then try report the result.
1794 */
1795 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR);
1796 if (flags & FXP_PHY_BMCR_AUTOEN) {
1797 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */
1798 if (stsflags & FXP_PHY_STS_AUTO_DONE) {
1799 /*
1800 * Intel and National parts report
1801 * differently on what they found.
1802 */
1803 if ((sc->phy_primary_device == FXP_PHY_82555)
1804 || (sc->phy_primary_device == FXP_PHY_82555B)) {
1805 flags = fxp_mdi_read(sc,
1806 sc->phy_primary_addr,
1807 FXP_PHY_USC);
1808
1809 if (flags & FXP_PHY_USC_SPEED)
1810 ifmr->ifm_active |= IFM_100_TX;
1811 else
1812 ifmr->ifm_active |= IFM_10_T;
1813
1814 if (flags & FXP_PHY_USC_DUPLEX)
1815 ifmr->ifm_active |= IFM_FDX;
1816 } else { /* it's National. only know speed */
1817 flags = fxp_mdi_read(sc,
1818 sc->phy_primary_addr,
1819 FXP_DP83840_PAR);
1820
1821 if (flags & FXP_DP83840_PAR_SPEED_10)
1822 ifmr->ifm_active |= IFM_10_T;
1823 else
1824 ifmr->ifm_active |= IFM_100_TX;
1825 }
1826 }
1827 } else { /* in manual mode.. just report what we were set to */
1828 if (flags & FXP_PHY_BMCR_SPEED_100M)
1829 ifmr->ifm_active |= IFM_100_TX;
1830 else
1831 ifmr->ifm_active |= IFM_10_T;
1832
1833 if (flags & FXP_PHY_BMCR_FULLDUPLEX)
1834 ifmr->ifm_active |= IFM_FDX;
1835 }
1836 break;
1837
1838 case FXP_PHY_80C24:
1839 default:
1840 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */
1841 }
1842}
1843
1844/*
1845 * Add a buffer to the end of the RFA buffer list.
1846 * Return 0 if successful, 1 for failure. A failure results in
1847 * adding the 'oldm' (if non-NULL) on to the end of the list -
1848 * tossing out its old contents and recycling it.
1849 * The RFA struct is stuck at the beginning of mbuf cluster and the
1850 * data pointer is fixed up to point just past it.
1851 */
1852static int
1853fxp_add_rfabuf(sc, oldm)
1854 struct fxp_softc *sc;
1855 struct mbuf *oldm;
1856{
1857 u_int32_t v;
1858 struct mbuf *m;
1859 struct fxp_rfa *rfa, *p_rfa;
1860
1861 MGETHDR(m, M_DONTWAIT, MT_DATA);
1862 if (m != NULL) {
1863 MCLGET(m, M_DONTWAIT);
1864 if ((m->m_flags & M_EXT) == 0) {
1865 m_freem(m);
1866 if (oldm == NULL)
1867 return 1;
1868 m = oldm;
1869 m->m_data = m->m_ext.ext_buf;
1870 }
1871 } else {
1872 if (oldm == NULL)
1873 return 1;
1874 m = oldm;
1875 m->m_data = m->m_ext.ext_buf;
1876 }
1877
1878 /*
1879 * Move the data pointer up so that the incoming data packet
1880 * will be 32-bit aligned.
1881 */
1882 m->m_data += RFA_ALIGNMENT_FUDGE;
1883
1884 /*
1885 * Get a pointer to the base of the mbuf cluster and move
1886 * data start past it.
1887 */
1888 rfa = mtod(m, struct fxp_rfa *);
1889 m->m_data += sizeof(struct fxp_rfa);
1890 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1891
1892 /*
1893 * Initialize the rest of the RFA. Note that since the RFA
1894 * is misaligned, we cannot store values directly. Instead,
1895 * we use an optimized, inline copy.
1896 */
1897
1898 rfa->rfa_status = 0;
1899 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1900 rfa->actual_size = 0;
1901
1902 v = -1;
1903 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1904 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1905
1906 /*
1907 * If there are other buffers already on the list, attach this
1908 * one to the end by fixing up the tail to point to this one.
1909 */
1910 if (sc->rfa_headm != NULL) {
1911 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1912 RFA_ALIGNMENT_FUDGE);
1913 sc->rfa_tailm->m_next = m;
1914 v = vtophys(rfa);
1915 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1916 p_rfa->rfa_control = 0;
1917 } else {
1918 sc->rfa_headm = m;
1919 }
1920 sc->rfa_tailm = m;
1921
1922 return (m == oldm);
1923}
1924
1925static volatile int
1926fxp_mdi_read(sc, phy, reg)
1927 struct fxp_softc *sc;
1928 int phy;
1929 int reg;
1930{
1931 int count = 10000;
1932 int value;
1933
1934 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1935 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1936
1937 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1938 && count--)
1939 DELAY(10);
1940
1941 if (count <= 0)
1942 printf(FXP_FORMAT ": fxp_mdi_read: timed out\n",
1943 FXP_ARGS(sc));
1944
1945 return (value & 0xffff);
1946}
1947
1948static void
1949fxp_mdi_write(sc, phy, reg, value)
1950 struct fxp_softc *sc;
1951 int phy;
1952 int reg;
1953 int value;
1954{
1955 int count = 10000;
1956
1957 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1958 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1959 (value & 0xffff));
1960
1961 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1962 count--)
1963 DELAY(10);
1964
1965 if (count <= 0)
1966 printf(FXP_FORMAT ": fxp_mdi_write: timed out\n",
1967 FXP_ARGS(sc));
1968}
1969
1970static int
1971fxp_ioctl(ifp, command, data)
1972 struct ifnet *ifp;
1973 FXP_IOCTLCMD_TYPE command;
1974 caddr_t data;
1975{
1976 struct fxp_softc *sc = ifp->if_softc;
1977 struct ifreq *ifr = (struct ifreq *)data;
1978 FXP_SPLVAR(s)
1979 int error = 0;
1980
1981 FXP_LOCK(sc, s);
1982
1983 switch (command) {
1984
1985 case SIOCSIFADDR:
1986#if !defined(__NetBSD__)
1987 case SIOCGIFADDR:
1988 case SIOCSIFMTU:
1989#endif
1990 error = ether_ioctl(ifp, command, data);
1991 break;
1992
1993 case SIOCSIFFLAGS:
1994 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1995
1996 /*
1997 * If interface is marked up and not running, then start it.
1998 * If it is marked down and running, stop it.
1999 * XXX If it's up then re-initialize it. This is so flags
2000 * such as IFF_PROMISC are handled.
2001 */
2002 if (ifp->if_flags & IFF_UP) {
2003 fxp_init(sc);
2004 } else {
2005 if (ifp->if_flags & IFF_RUNNING)
2006 fxp_stop(sc);
2007 }
2008 break;
2009
2010 case SIOCADDMULTI:
2011 case SIOCDELMULTI:
2012 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
2013#if defined(__NetBSD__)
2014 error = (command == SIOCADDMULTI) ?
2015 ether_addmulti(ifr, &sc->sc_ethercom) :
2016 ether_delmulti(ifr, &sc->sc_ethercom);
2017
2018 if (error == ENETRESET) {
2019 /*
2020 * Multicast list has changed; set the hardware
2021 * filter accordingly.
2022 */
2023 if (!sc->all_mcasts)
2024 fxp_mc_setup(sc);
2025 /*
2026 * fxp_mc_setup() can turn on all_mcasts if we run
2027 * out of space, so check it again rather than else {}.
2028 */
2029 if (sc->all_mcasts)
2030 fxp_init(sc);
2031 error = 0;
2032 }
2033#else /* __FreeBSD__ */
2034 /*
2035 * Multicast list has changed; set the hardware filter
2036 * accordingly.
2037 */
2038 if (!sc->all_mcasts)
2039 fxp_mc_setup(sc);
2040 /*
2041 * fxp_mc_setup() can turn on sc->all_mcasts, so check it
2042 * again rather than else {}.
2043 */
2044 if (sc->all_mcasts)
2045 fxp_init(sc);
2046 error = 0;
2047#endif /* __NetBSD__ */
2048 break;
2049
2050 case SIOCSIFMEDIA:
2051 case SIOCGIFMEDIA:
2052 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2053 break;
2054
2055 default:
2056 error = EINVAL;
2057 }
2058 FXP_UNLOCK(sc, s);
2059 return (error);
2060}
2061
2062/*
2063 * Program the multicast filter.
2064 *
2065 * We have an artificial restriction that the multicast setup command
2066 * must be the first command in the chain, so we take steps to ensure
2067 * this. By requiring this, it allows us to keep up the performance of
2068 * the pre-initialized command ring (esp. link pointers) by not actually
2069 * inserting the mcsetup command in the ring - i.e. its link pointer
2070 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2071 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2072 * lead into the regular TxCB ring when it completes.
2073 *
2074 * This function must be called at splimp.
2075 */
2076static void
2077fxp_mc_setup(sc)
2078 struct fxp_softc *sc;
2079{
2080 struct fxp_cb_mcs *mcsp = sc->mcsp;
2081 struct ifnet *ifp = &sc->sc_if;
2082 struct ifmultiaddr *ifma;
2083 int nmcasts;
|
| 2084 int count;
|
1993
1994 /*
1995 * If there are queued commands, we must wait until they are all
1996 * completed. If we are already waiting, then add a NOP command
1997 * with interrupt option so that we're notified when all commands
1998 * have been completed - fxp_start() ensures that no additional
1999 * TX commands will be added when need_mcsetup is true.
2000 */
2001 if (sc->tx_queued) {
2002 struct fxp_cb_tx *txp;
2003
2004 /*
2005 * need_mcsetup will be true if we are already waiting for the
2006 * NOP command to be completed (see below). In this case, bail.
2007 */
2008 if (sc->need_mcsetup)
2009 return;
2010 sc->need_mcsetup = 1;
2011
2012 /*
2013 * Add a NOP command with interrupt so that we are notified when all
2014 * TX commands have been processed.
2015 */
2016 txp = sc->cbl_last->next;
2017 txp->mb_head = NULL;
2018 txp->cb_status = 0;
2019 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2020 /*
2021 * Advance the end of list forward.
2022 */
2023 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2024 sc->cbl_last = txp;
2025 sc->tx_queued++;
2026 /*
2027 * Issue a resume in case the CU has just suspended.
2028 */
2029 fxp_scb_wait(sc);
2030 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
2031 /*
2032 * Set a 5 second timer just in case we don't hear from the
2033 * card again.
2034 */
2035 ifp->if_timer = 5;
2036
2037 return;
2038 }
2039 sc->need_mcsetup = 0;
2040
2041 /*
2042 * Initialize multicast setup descriptor.
2043 */
2044 mcsp->next = sc->cbl_base;
2045 mcsp->mb_head = NULL;
2046 mcsp->cb_status = 0;
2047 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2048 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2049
2050 nmcasts = 0;
2051 if (!sc->all_mcasts) {
2052 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
2053 ifma = ifma->ifma_link.le_next) {
2054 if (ifma->ifma_addr->sa_family != AF_LINK)
2055 continue;
2056 if (nmcasts >= MAXMCADDR) {
2057 sc->all_mcasts = 1;
2058 nmcasts = 0;
2059 break;
2060 }
2061 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2062 (void *)(uintptr_t)(volatile void *)
2063 &sc->mcsp->mc_addr[nmcasts][0], 6);
2064 nmcasts++;
2065 }
2066 }
2067 mcsp->mc_cnt = nmcasts * 6;
2068 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2069 sc->tx_queued = 1;
2070
2071 /*
2072 * Wait until command unit is not active. This should never
2073 * be the case when nothing is queued, but make sure anyway.
2074 */
| 2085
2086 /*
2087 * If there are queued commands, we must wait until they are all
2088 * completed. If we are already waiting, then add a NOP command
2089 * with interrupt option so that we're notified when all commands
2090 * have been completed - fxp_start() ensures that no additional
2091 * TX commands will be added when need_mcsetup is true.
2092 */
2093 if (sc->tx_queued) {
2094 struct fxp_cb_tx *txp;
2095
2096 /*
2097 * need_mcsetup will be true if we are already waiting for the
2098 * NOP command to be completed (see below). In this case, bail.
2099 */
2100 if (sc->need_mcsetup)
2101 return;
2102 sc->need_mcsetup = 1;
2103
2104 /*
2105 * Add a NOP command with interrupt so that we are notified when all
2106 * TX commands have been processed.
2107 */
2108 txp = sc->cbl_last->next;
2109 txp->mb_head = NULL;
2110 txp->cb_status = 0;
2111 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2112 /*
2113 * Advance the end of list forward.
2114 */
2115 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2116 sc->cbl_last = txp;
2117 sc->tx_queued++;
2118 /*
2119 * Issue a resume in case the CU has just suspended.
2120 */
2121 fxp_scb_wait(sc);
2122 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
2123 /*
2124 * Set a 5 second timer just in case we don't hear from the
2125 * card again.
2126 */
2127 ifp->if_timer = 5;
2128
2129 return;
2130 }
2131 sc->need_mcsetup = 0;
2132
2133 /*
2134 * Initialize multicast setup descriptor.
2135 */
2136 mcsp->next = sc->cbl_base;
2137 mcsp->mb_head = NULL;
2138 mcsp->cb_status = 0;
2139 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2140 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2141
2142 nmcasts = 0;
2143 if (!sc->all_mcasts) {
2144 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
2145 ifma = ifma->ifma_link.le_next) {
2146 if (ifma->ifma_addr->sa_family != AF_LINK)
2147 continue;
2148 if (nmcasts >= MAXMCADDR) {
2149 sc->all_mcasts = 1;
2150 nmcasts = 0;
2151 break;
2152 }
2153 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2154 (void *)(uintptr_t)(volatile void *)
2155 &sc->mcsp->mc_addr[nmcasts][0], 6);
2156 nmcasts++;
2157 }
2158 }
2159 mcsp->mc_cnt = nmcasts * 6;
2160 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2161 sc->tx_queued = 1;
2162
2163 /*
2164 * Wait until command unit is not active. This should never
2165 * be the case when nothing is queued, but make sure anyway.
2166 */
|
| 2167 count = 100;
|
2075 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
| 2168 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
|
2076 FXP_SCB_CUS_ACTIVE) ;
| 2169 FXP_SCB_CUS_ACTIVE && --count)
2170 DELAY(10);
2171 if (count == 0) {
2172 printf(FXP_FORMAT ": command queue timeout\n", FXP_ARGS(sc));
2173 return;
2174 }
|
2077
2078 /*
2079 * Start the multicast setup command.
2080 */
2081 fxp_scb_wait(sc);
2082 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2083 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
2084
2085 ifp->if_timer = 2;
2086 return;
2087}
| 2175
2176 /*
2177 * Start the multicast setup command.
2178 */
2179 fxp_scb_wait(sc);
2180 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2181 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
2182
2183 ifp->if_timer = 2;
2184 return;
2185}
|