39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/endian.h>
43#include <sys/mbuf.h>
44 /* #include <sys/mutex.h> */
45#include <sys/kernel.h>
46#include <sys/socket.h>
47#include <sys/sysctl.h>
48
49#include <net/if.h>
50#include <net/if_dl.h>
51#include <net/if_media.h>
52
53#include <net/bpf.h>
54#include <sys/sockio.h>
55#include <sys/bus.h>
56#include <machine/bus.h>
57#include <sys/rman.h>
58#include <machine/resource.h>
59
60#include <net/ethernet.h>
61#include <net/if_arp.h>
62
63#include <machine/clock.h> /* for DELAY */
64
65#include <net/if_types.h>
66#include <net/if_vlan_var.h>
67
68#ifdef FXP_IP_CSUM_WAR
69#include <netinet/in.h>
70#include <netinet/in_systm.h>
71#include <netinet/ip.h>
72#include <machine/in_cksum.h>
73#endif
74
75#include <dev/pci/pcivar.h>
76#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77
78#include <dev/mii/mii.h>
79#include <dev/mii/miivar.h>
80
81#include <dev/fxp/if_fxpreg.h>
82#include <dev/fxp/if_fxpvar.h>
83#include <dev/fxp/rcvbundl.h>
84
85MODULE_DEPEND(fxp, pci, 1, 1, 1);
86MODULE_DEPEND(fxp, ether, 1, 1, 1);
87MODULE_DEPEND(fxp, miibus, 1, 1, 1);
88#include "miibus_if.h"
89
90/*
91 * NOTE! On the Alpha, we have an alignment constraint. The
92 * card DMAs the packet immediately following the RFA. However,
93 * the first thing in the packet is a 14-byte Ethernet header.
94 * This means that the packet is misaligned. To compensate,
95 * we actually offset the RFA 2 bytes into the cluster. This
96 * alignes the packet after the Ethernet header at a 32-bit
97 * boundary. HOWEVER! This means that the RFA is misaligned!
98 */
99#define RFA_ALIGNMENT_FUDGE 2
100
101/*
102 * Set initial transmit threshold at 64 (512 bytes). This is
103 * increased by 64 (512 bytes) at a time, to maximum of 192
104 * (1536 bytes), if an underrun occurs.
105 */
106static int tx_threshold = 64;
107
108/*
109 * The configuration byte map has several undefined fields which
110 * must be one or must be zero. Set up a template for these bits
111 * only, (assuming a 82557 chip) leaving the actual configuration
112 * to fxp_init.
113 *
114 * See struct fxp_cb_config for the bit definitions.
115 */
116static u_char fxp_cb_config_template[] = {
117 0x0, 0x0, /* cb_status */
118 0x0, 0x0, /* cb_command */
119 0x0, 0x0, 0x0, 0x0, /* link_addr */
120 0x0, /* 0 */
121 0x0, /* 1 */
122 0x0, /* 2 */
123 0x0, /* 3 */
124 0x0, /* 4 */
125 0x0, /* 5 */
126 0x32, /* 6 */
127 0x0, /* 7 */
128 0x0, /* 8 */
129 0x0, /* 9 */
130 0x6, /* 10 */
131 0x0, /* 11 */
132 0x0, /* 12 */
133 0x0, /* 13 */
134 0xf2, /* 14 */
135 0x48, /* 15 */
136 0x0, /* 16 */
137 0x40, /* 17 */
138 0xf0, /* 18 */
139 0x0, /* 19 */
140 0x3f, /* 20 */
141 0x5 /* 21 */
142};
143
144struct fxp_ident {
145 u_int16_t devid;
146 int16_t revid; /* -1 matches anything */
147 char *name;
148};
149
150/*
151 * Claim various Intel PCI device identifiers for this driver. The
152 * sub-vendor and sub-device field are extensively used to identify
153 * particular variants, but we don't currently differentiate between
154 * them.
155 */
156static struct fxp_ident fxp_ident_table[] = {
157 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
158 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
159 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
160 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
161 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
162 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
163 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
164 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
165 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
167 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
168 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
169 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
170 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
171 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
172 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
173 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
192 { 0, -1, NULL },
193};
194
195#ifdef FXP_IP_CSUM_WAR
196#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
197#else
198#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
199#endif
200
201static int fxp_probe(device_t dev);
202static int fxp_attach(device_t dev);
203static int fxp_detach(device_t dev);
204static int fxp_shutdown(device_t dev);
205static int fxp_suspend(device_t dev);
206static int fxp_resume(device_t dev);
207
208static void fxp_intr(void *xsc);
209static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
210 u_int8_t statack, int count);
211static void fxp_init(void *xsc);
212static void fxp_init_body(struct fxp_softc *sc);
213static void fxp_tick(void *xsc);
214#ifndef BURN_BRIDGES
215static void fxp_powerstate_d0(device_t dev);
216#endif
217static void fxp_start(struct ifnet *ifp);
218static void fxp_start_body(struct ifnet *ifp);
219static void fxp_stop(struct fxp_softc *sc);
220static void fxp_release(struct fxp_softc *sc);
221static int fxp_ioctl(struct ifnet *ifp, u_long command,
222 caddr_t data);
223static void fxp_watchdog(struct ifnet *ifp);
224static int fxp_add_rfabuf(struct fxp_softc *sc,
225 struct fxp_rx *rxp);
226static int fxp_mc_addrs(struct fxp_softc *sc);
227static void fxp_mc_setup(struct fxp_softc *sc);
228static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
229 int autosize);
230static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
231 u_int16_t data);
232static void fxp_autosize_eeprom(struct fxp_softc *sc);
233static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
234 int offset, int words);
235static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
236 int offset, int words);
237static int fxp_ifmedia_upd(struct ifnet *ifp);
238static void fxp_ifmedia_sts(struct ifnet *ifp,
239 struct ifmediareq *ifmr);
240static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
241static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
242 struct ifmediareq *ifmr);
243static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
244static void fxp_miibus_writereg(device_t dev, int phy, int reg,
245 int value);
246static void fxp_load_ucode(struct fxp_softc *sc);
247static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
248 int low, int high);
249static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
250static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
251static void fxp_scb_wait(struct fxp_softc *sc);
252static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
253static void fxp_dma_wait(struct fxp_softc *sc,
254 volatile u_int16_t *status, bus_dma_tag_t dmat,
255 bus_dmamap_t map);
256
257static device_method_t fxp_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, fxp_probe),
260 DEVMETHOD(device_attach, fxp_attach),
261 DEVMETHOD(device_detach, fxp_detach),
262 DEVMETHOD(device_shutdown, fxp_shutdown),
263 DEVMETHOD(device_suspend, fxp_suspend),
264 DEVMETHOD(device_resume, fxp_resume),
265
266 /* MII interface */
267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
269
270 { 0, 0 }
271};
272
273static driver_t fxp_driver = {
274 "fxp",
275 fxp_methods,
276 sizeof(struct fxp_softc),
277};
278
279static devclass_t fxp_devclass;
280
281DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
| 39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/endian.h>
43#include <sys/mbuf.h>
44 /* #include <sys/mutex.h> */
45#include <sys/kernel.h>
46#include <sys/socket.h>
47#include <sys/sysctl.h>
48
49#include <net/if.h>
50#include <net/if_dl.h>
51#include <net/if_media.h>
52
53#include <net/bpf.h>
54#include <sys/sockio.h>
55#include <sys/bus.h>
56#include <machine/bus.h>
57#include <sys/rman.h>
58#include <machine/resource.h>
59
60#include <net/ethernet.h>
61#include <net/if_arp.h>
62
63#include <machine/clock.h> /* for DELAY */
64
65#include <net/if_types.h>
66#include <net/if_vlan_var.h>
67
68#ifdef FXP_IP_CSUM_WAR
69#include <netinet/in.h>
70#include <netinet/in_systm.h>
71#include <netinet/ip.h>
72#include <machine/in_cksum.h>
73#endif
74
75#include <dev/pci/pcivar.h>
76#include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77
78#include <dev/mii/mii.h>
79#include <dev/mii/miivar.h>
80
81#include <dev/fxp/if_fxpreg.h>
82#include <dev/fxp/if_fxpvar.h>
83#include <dev/fxp/rcvbundl.h>
84
85MODULE_DEPEND(fxp, pci, 1, 1, 1);
86MODULE_DEPEND(fxp, ether, 1, 1, 1);
87MODULE_DEPEND(fxp, miibus, 1, 1, 1);
88#include "miibus_if.h"
89
90/*
91 * NOTE! On the Alpha, we have an alignment constraint. The
92 * card DMAs the packet immediately following the RFA. However,
93 * the first thing in the packet is a 14-byte Ethernet header.
94 * This means that the packet is misaligned. To compensate,
95 * we actually offset the RFA 2 bytes into the cluster. This
96 * alignes the packet after the Ethernet header at a 32-bit
97 * boundary. HOWEVER! This means that the RFA is misaligned!
98 */
99#define RFA_ALIGNMENT_FUDGE 2
100
101/*
102 * Set initial transmit threshold at 64 (512 bytes). This is
103 * increased by 64 (512 bytes) at a time, to maximum of 192
104 * (1536 bytes), if an underrun occurs.
105 */
106static int tx_threshold = 64;
107
108/*
109 * The configuration byte map has several undefined fields which
110 * must be one or must be zero. Set up a template for these bits
111 * only, (assuming a 82557 chip) leaving the actual configuration
112 * to fxp_init.
113 *
114 * See struct fxp_cb_config for the bit definitions.
115 */
116static u_char fxp_cb_config_template[] = {
117 0x0, 0x0, /* cb_status */
118 0x0, 0x0, /* cb_command */
119 0x0, 0x0, 0x0, 0x0, /* link_addr */
120 0x0, /* 0 */
121 0x0, /* 1 */
122 0x0, /* 2 */
123 0x0, /* 3 */
124 0x0, /* 4 */
125 0x0, /* 5 */
126 0x32, /* 6 */
127 0x0, /* 7 */
128 0x0, /* 8 */
129 0x0, /* 9 */
130 0x6, /* 10 */
131 0x0, /* 11 */
132 0x0, /* 12 */
133 0x0, /* 13 */
134 0xf2, /* 14 */
135 0x48, /* 15 */
136 0x0, /* 16 */
137 0x40, /* 17 */
138 0xf0, /* 18 */
139 0x0, /* 19 */
140 0x3f, /* 20 */
141 0x5 /* 21 */
142};
143
144struct fxp_ident {
145 u_int16_t devid;
146 int16_t revid; /* -1 matches anything */
147 char *name;
148};
149
150/*
151 * Claim various Intel PCI device identifiers for this driver. The
152 * sub-vendor and sub-device field are extensively used to identify
153 * particular variants, but we don't currently differentiate between
154 * them.
155 */
156static struct fxp_ident fxp_ident_table[] = {
157 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
158 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
159 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
160 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
161 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
162 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
163 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
164 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
165 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
167 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
168 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
169 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
170 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
171 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
172 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
173 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
175 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
176 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
177 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
178 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
179 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
180 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
181 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
182 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
183 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
184 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
185 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
186 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
187 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
188 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
189 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
190 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
191 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
192 { 0, -1, NULL },
193};
194
195#ifdef FXP_IP_CSUM_WAR
196#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
197#else
198#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
199#endif
200
201static int fxp_probe(device_t dev);
202static int fxp_attach(device_t dev);
203static int fxp_detach(device_t dev);
204static int fxp_shutdown(device_t dev);
205static int fxp_suspend(device_t dev);
206static int fxp_resume(device_t dev);
207
208static void fxp_intr(void *xsc);
209static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
210 u_int8_t statack, int count);
211static void fxp_init(void *xsc);
212static void fxp_init_body(struct fxp_softc *sc);
213static void fxp_tick(void *xsc);
214#ifndef BURN_BRIDGES
215static void fxp_powerstate_d0(device_t dev);
216#endif
217static void fxp_start(struct ifnet *ifp);
218static void fxp_start_body(struct ifnet *ifp);
219static void fxp_stop(struct fxp_softc *sc);
220static void fxp_release(struct fxp_softc *sc);
221static int fxp_ioctl(struct ifnet *ifp, u_long command,
222 caddr_t data);
223static void fxp_watchdog(struct ifnet *ifp);
224static int fxp_add_rfabuf(struct fxp_softc *sc,
225 struct fxp_rx *rxp);
226static int fxp_mc_addrs(struct fxp_softc *sc);
227static void fxp_mc_setup(struct fxp_softc *sc);
228static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
229 int autosize);
230static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
231 u_int16_t data);
232static void fxp_autosize_eeprom(struct fxp_softc *sc);
233static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
234 int offset, int words);
235static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
236 int offset, int words);
237static int fxp_ifmedia_upd(struct ifnet *ifp);
238static void fxp_ifmedia_sts(struct ifnet *ifp,
239 struct ifmediareq *ifmr);
240static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
241static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
242 struct ifmediareq *ifmr);
243static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
244static void fxp_miibus_writereg(device_t dev, int phy, int reg,
245 int value);
246static void fxp_load_ucode(struct fxp_softc *sc);
247static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
248 int low, int high);
249static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
250static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
251static void fxp_scb_wait(struct fxp_softc *sc);
252static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
253static void fxp_dma_wait(struct fxp_softc *sc,
254 volatile u_int16_t *status, bus_dma_tag_t dmat,
255 bus_dmamap_t map);
256
257static device_method_t fxp_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, fxp_probe),
260 DEVMETHOD(device_attach, fxp_attach),
261 DEVMETHOD(device_detach, fxp_detach),
262 DEVMETHOD(device_shutdown, fxp_shutdown),
263 DEVMETHOD(device_suspend, fxp_suspend),
264 DEVMETHOD(device_resume, fxp_resume),
265
266 /* MII interface */
267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
269
270 { 0, 0 }
271};
272
273static driver_t fxp_driver = {
274 "fxp",
275 fxp_methods,
276 sizeof(struct fxp_softc),
277};
278
279static devclass_t fxp_devclass;
280
281DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
|
282DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
283
284static int fxp_rnr;
285SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
286
287static int fxp_noflow;
288SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled");
289TUNABLE_INT("hw.fxp_noflow", &fxp_noflow);
290
291/*
292 * Wait for the previous command to be accepted (but not necessarily
293 * completed).
294 */
295static void
296fxp_scb_wait(struct fxp_softc *sc)
297{
298 int i = 10000;
299
300 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
301 DELAY(2);
302 if (i == 0)
303 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
304 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
305 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
306 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
307 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
308}
309
310static void
311fxp_scb_cmd(struct fxp_softc *sc, int cmd)
312{
313
314 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
315 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
316 fxp_scb_wait(sc);
317 }
318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
319}
320
321static void
322fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status,
323 bus_dma_tag_t dmat, bus_dmamap_t map)
324{
325 int i = 10000;
326
327 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
328 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) {
329 DELAY(2);
330 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
331 }
332 if (i == 0)
333 device_printf(sc->dev, "DMA timeout\n");
334}
335
336/*
337 * Return identification string if this device is ours.
338 */
339static int
340fxp_probe(device_t dev)
341{
342 u_int16_t devid;
343 u_int8_t revid;
344 struct fxp_ident *ident;
345
346 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
347 devid = pci_get_device(dev);
348 revid = pci_get_revid(dev);
349 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
350 if (ident->devid == devid &&
351 (ident->revid == revid || ident->revid == -1)) {
352 device_set_desc(dev, ident->name);
353 return (0);
354 }
355 }
356 }
357 return (ENXIO);
358}
359
360#ifndef BURN_BRIDGES
361static void
362fxp_powerstate_d0(device_t dev)
363{
364#if __FreeBSD_version >= 430002
365 u_int32_t iobase, membase, irq;
366
367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
368 /* Save important PCI config data. */
369 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
370 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
371 irq = pci_read_config(dev, PCIR_INTLINE, 4);
372
373 /* Reset the power state. */
374 device_printf(dev, "chip is in D%d power mode "
375 "-- setting to D0\n", pci_get_powerstate(dev));
376
377 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
378
379 /* Restore PCI config data. */
380 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
381 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
382 pci_write_config(dev, PCIR_INTLINE, irq, 4);
383 }
384#endif
385}
386#endif
387
388static void
389fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
390{
391 u_int32_t *addr;
392
393 if (error)
394 return;
395
396 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
397 addr = arg;
398 *addr = segs->ds_addr;
399}
400
401static int
402fxp_attach(device_t dev)
403{
404 int error = 0;
405 struct fxp_softc *sc = device_get_softc(dev);
406 struct ifnet *ifp;
407 struct fxp_rx *rxp;
408 u_int32_t val;
409 u_int16_t data, myea[ETHER_ADDR_LEN / 2];
410 int i, rid, m1, m2, prefer_iomap, maxtxseg;
411 int s, ipcbxmit_disable;
412
413 sc->dev = dev;
414 callout_init(&sc->stat_ch, CALLOUT_MPSAFE);
415 sysctl_ctx_init(&sc->sysctl_ctx);
416 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
417 MTX_DEF);
418 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
419 fxp_serial_ifmedia_sts);
420
421 s = splimp();
422
423 /*
424 * Enable bus mastering.
425 */
426 pci_enable_busmaster(dev);
427 val = pci_read_config(dev, PCIR_COMMAND, 2);
428#ifndef BURN_BRIDGES
429 fxp_powerstate_d0(dev);
430#endif
431 /*
432 * Figure out which we should try first - memory mapping or i/o mapping?
433 * We default to memory mapping. Then we accept an override from the
434 * command line. Then we check to see which one is enabled.
435 */
436 m1 = PCIM_CMD_MEMEN;
437 m2 = PCIM_CMD_PORTEN;
438 prefer_iomap = 0;
439 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
440 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
441 m1 = PCIM_CMD_PORTEN;
442 m2 = PCIM_CMD_MEMEN;
443 }
444
445 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
446 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
447 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
448 0, ~0, 1, RF_ACTIVE);
449 if (sc->mem == NULL) {
450 sc->rtp =
451 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
452 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
453 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
454 0, ~0, 1, RF_ACTIVE);
455 }
456
457 if (!sc->mem) {
458 error = ENXIO;
459 goto fail;
460 }
461 if (bootverbose) {
462 device_printf(dev, "using %s space register mapping\n",
463 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
464 }
465
466 sc->sc_st = rman_get_bustag(sc->mem);
467 sc->sc_sh = rman_get_bushandle(sc->mem);
468
469 /*
470 * Allocate our interrupt.
471 */
472 rid = 0;
473 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
474 RF_SHAREABLE | RF_ACTIVE);
475 if (sc->irq == NULL) {
476 device_printf(dev, "could not map interrupt\n");
477 error = ENXIO;
478 goto fail;
479 }
480
481 /*
482 * Reset to a stable state.
483 */
484 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
485 DELAY(10);
486
487 /*
488 * Find out how large of an SEEPROM we have.
489 */
490 fxp_autosize_eeprom(sc);
491
492 /*
493 * Determine whether we must use the 503 serial interface.
494 */
495 fxp_read_eeprom(sc, &data, 6, 1);
496 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
497 (data & FXP_PHY_SERIAL_ONLY))
498 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
499
500 /*
501 * Create the sysctl tree
502 */
503 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
504 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
505 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
506 if (sc->sysctl_tree == NULL) {
507 error = ENXIO;
508 goto fail;
509 }
510 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
511 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
512 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
513 "FXP driver receive interrupt microcode bundling delay");
514 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
515 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
516 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
517 "FXP driver receive interrupt microcode bundle size limit");
518
519 /*
520 * Pull in device tunables.
521 */
522 sc->tunable_int_delay = TUNABLE_INT_DELAY;
523 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
525 "int_delay", &sc->tunable_int_delay);
526 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
527 "bundle_max", &sc->tunable_bundle_max);
528
529 /*
530 * Find out the chip revision; lump all 82557 revs together.
531 */
532 fxp_read_eeprom(sc, &data, 5, 1);
533 if ((data >> 8) == 1)
534 sc->revision = FXP_REV_82557;
535 else
536 sc->revision = pci_get_revid(dev);
537
538 /*
539 * Enable workarounds for certain chip revision deficiencies.
540 *
541 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
542 * some systems based a normal 82559 design, have a defect where
543 * the chip can cause a PCI protocol violation if it receives
544 * a CU_RESUME command when it is entering the IDLE state. The
545 * workaround is to disable Dynamic Standby Mode, so the chip never
546 * deasserts CLKRUN#, and always remains in an active state.
547 *
548 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
549 */
550 i = pci_get_device(dev);
551 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
552 sc->revision >= FXP_REV_82559_A0) {
553 fxp_read_eeprom(sc, &data, 10, 1);
554 if (data & 0x02) { /* STB enable */
555 u_int16_t cksum;
556 int i;
557
558 device_printf(dev,
559 "Disabling dynamic standby mode in EEPROM\n");
560 data &= ~0x02;
561 fxp_write_eeprom(sc, &data, 10, 1);
562 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
563 cksum = 0;
564 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
565 fxp_read_eeprom(sc, &data, i, 1);
566 cksum += data;
567 }
568 i = (1 << sc->eeprom_size) - 1;
569 cksum = 0xBABA - cksum;
570 fxp_read_eeprom(sc, &data, i, 1);
571 fxp_write_eeprom(sc, &cksum, i, 1);
572 device_printf(dev,
573 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
574 i, data, cksum);
575#if 1
576 /*
577 * If the user elects to continue, try the software
578 * workaround, as it is better than nothing.
579 */
580 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
581#endif
582 }
583 }
584
585 /*
586 * If we are not a 82557 chip, we can enable extended features.
587 */
588 if (sc->revision != FXP_REV_82557) {
589 /*
590 * If MWI is enabled in the PCI configuration, and there
591 * is a valid cacheline size (8 or 16 dwords), then tell
592 * the board to turn on MWI.
593 */
594 if (val & PCIM_CMD_MWRICEN &&
595 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
596 sc->flags |= FXP_FLAG_MWI_ENABLE;
597
598 /* turn on the extended TxCB feature */
599 sc->flags |= FXP_FLAG_EXT_TXCB;
600
601 /* enable reception of long frames for VLAN */
602 sc->flags |= FXP_FLAG_LONG_PKT_EN;
603 }
604
605 /*
606 * Enable use of extended RFDs and TCBs for 82550
607 * and later chips. Note: we need extended TXCB support
608 * too, but that's already enabled by the code above.
609 * Be careful to do this only on the right devices.
610 *
611 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d"
612 * truncate packets that end with an mbuf containing 1 to 3 bytes
613 * when used with this feature enabled in the previous version of the
614 * driver. This problem appears to be fixed now that the driver
615 * always sets the hardware parse bit in the IPCB structure, which
616 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open
617 * Source Software Developer Manual" says is necessary in the
618 * cases where packet truncation was observed.
619 *
620 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable"
621 * allows this feature to be disabled at boot time.
622 *
623 * If fxp is not compiled into the kernel, this feature may also
624 * be disabled at run time:
625 * # kldunload fxp
626 * # kenv hint.fxp.0.ipcbxmit_disable=1
627 * # kldload fxp
628 */
629
630 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable",
631 &ipcbxmit_disable) != 0)
632 ipcbxmit_disable = 0;
633 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 ||
634 sc->revision == FXP_REV_82550_C)) {
635 sc->rfa_size = sizeof (struct fxp_rfa);
636 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
637 sc->flags |= FXP_FLAG_EXT_RFA;
638 } else {
639 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
640 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
641 }
642
643 /*
644 * Allocate DMA tags and DMA safe memory.
645 */
646 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG;
647 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT,
648 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg,
649 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag);
650 if (error) {
651 device_printf(dev, "could not allocate dma tag\n");
652 goto fail;
653 }
654
655 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
656 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1,
657 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant,
658 &sc->fxp_stag);
659 if (error) {
660 device_printf(dev, "could not allocate dma tag\n");
661 goto fail;
662 }
663
664 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
665 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
666 if (error)
667 goto fail;
668 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
669 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
670 if (error) {
671 device_printf(dev, "could not map the stats buffer\n");
672 goto fail;
673 }
674
675 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
676 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1,
677 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag);
678 if (error) {
679 device_printf(dev, "could not allocate dma tag\n");
680 goto fail;
681 }
682
683 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
684 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
685 if (error)
686 goto fail;
687
688 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
689 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
690 &sc->fxp_desc.cbl_addr, 0);
691 if (error) {
692 device_printf(dev, "could not map DMA memory\n");
693 goto fail;
694 }
695
696 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
697 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1,
698 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant,
699 &sc->mcs_tag);
700 if (error) {
701 device_printf(dev, "could not allocate dma tag\n");
702 goto fail;
703 }
704
705 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
706 BUS_DMA_NOWAIT, &sc->mcs_map);
707 if (error)
708 goto fail;
709 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
710 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
711 if (error) {
712 device_printf(dev, "can't map the multicast setup command\n");
713 goto fail;
714 }
715
716 /*
717 * Pre-allocate the TX DMA maps.
718 */
719 for (i = 0; i < FXP_NTXCB; i++) {
720 error = bus_dmamap_create(sc->fxp_mtag, 0,
721 &sc->fxp_desc.tx_list[i].tx_map);
722 if (error) {
723 device_printf(dev, "can't create DMA map for TX\n");
724 goto fail;
725 }
726 }
727 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
728 if (error) {
729 device_printf(dev, "can't create spare DMA map\n");
730 goto fail;
731 }
732
733 /*
734 * Pre-allocate our receive buffers.
735 */
736 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
737 for (i = 0; i < FXP_NRFABUFS; i++) {
738 rxp = &sc->fxp_desc.rx_list[i];
739 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
740 if (error) {
741 device_printf(dev, "can't create DMA map for RX\n");
742 goto fail;
743 }
744 if (fxp_add_rfabuf(sc, rxp) != 0) {
745 error = ENOMEM;
746 goto fail;
747 }
748 }
749
750 /*
751 * Read MAC address.
752 */
753 fxp_read_eeprom(sc, myea, 0, 3);
754 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff;
755 sc->arpcom.ac_enaddr[1] = myea[0] >> 8;
756 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff;
757 sc->arpcom.ac_enaddr[3] = myea[1] >> 8;
758 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff;
759 sc->arpcom.ac_enaddr[5] = myea[2] >> 8;
760 device_printf(dev, "Ethernet address %6D%s\n",
761 sc->arpcom.ac_enaddr, ":",
762 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
763 if (bootverbose) {
764 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
765 pci_get_vendor(dev), pci_get_device(dev),
766 pci_get_subvendor(dev), pci_get_subdevice(dev),
767 pci_get_revid(dev));
768 fxp_read_eeprom(sc, &data, 10, 1);
769 device_printf(dev, "Dynamic Standby mode is %s\n",
770 data & 0x02 ? "enabled" : "disabled");
771 }
772
773 /*
774 * If this is only a 10Mbps device, then there is no MII, and
775 * the PHY will use a serial interface instead.
776 *
777 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
778 * doesn't have a programming interface of any sort. The
779 * media is sensed automatically based on how the link partner
780 * is configured. This is, in essence, manual configuration.
781 */
782 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
783 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
784 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
785 } else {
786 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
787 fxp_ifmedia_sts)) {
788 device_printf(dev, "MII without any PHY!\n");
789 error = ENXIO;
790 goto fail;
791 }
792 }
793
794 ifp = &sc->arpcom.ac_if;
795 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
796 ifp->if_output = ether_output;
797 ifp->if_baudrate = 100000000;
798 ifp->if_init = fxp_init;
799 ifp->if_softc = sc;
800 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
801 ifp->if_ioctl = fxp_ioctl;
802 ifp->if_start = fxp_start;
803 ifp->if_watchdog = fxp_watchdog;
804
805 /* Enable checksum offload for 82550 or better chips */
806 if (sc->flags & FXP_FLAG_EXT_RFA) {
807 ifp->if_hwassist = FXP_CSUM_FEATURES;
808 ifp->if_capabilities = IFCAP_HWCSUM;
809 ifp->if_capenable = ifp->if_capabilities;
810 }
811
812 /*
813 * Attach the interface.
814 */
815 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
816
817 /*
818 * Tell the upper layer(s) we support long frames.
819 */
820 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
821 ifp->if_capabilities |= IFCAP_VLAN_MTU;
822
823 /*
824 * Let the system queue as many packets as we have available
825 * TX descriptors.
826 */
827 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
828
829 /*
830 * Hook our interrupt after all initialization is complete.
831 * XXX This driver has been tested with the INTR_MPSAFFE flag set
832 * however, ifp and its functions are not fully locked so MPSAFE
833 * should not be used unless you can handle potential data loss.
834 */
835 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
836 fxp_intr, sc, &sc->ih);
837 if (error) {
838 device_printf(dev, "could not setup irq\n");
839 ether_ifdetach(&sc->arpcom.ac_if);
840 goto fail;
841 }
842
843fail:
844 splx(s);
845 if (error)
846 fxp_release(sc);
847 return (error);
848}
849
850/*
851 * Release all resources. The softc lock should not be held and the
852 * interrupt should already be torn down.
853 */
854static void
855fxp_release(struct fxp_softc *sc)
856{
857 struct fxp_rx *rxp;
858 struct fxp_tx *txp;
859 int i;
860
861 mtx_assert(&sc->sc_mtx, MA_NOTOWNED);
862 if (sc->ih)
863 panic("fxp_release() called with intr handle still active");
864 if (sc->miibus)
865 device_delete_child(sc->dev, sc->miibus);
866 bus_generic_detach(sc->dev);
867 ifmedia_removeall(&sc->sc_media);
868 if (sc->fxp_desc.cbl_list) {
869 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
870 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
871 sc->cbl_map);
872 }
873 if (sc->fxp_stats) {
874 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
875 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
876 }
877 if (sc->mcsp) {
878 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
879 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
880 }
881 if (sc->irq)
882 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
883 if (sc->mem)
884 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
885 if (sc->fxp_mtag) {
886 for (i = 0; i < FXP_NRFABUFS; i++) {
887 rxp = &sc->fxp_desc.rx_list[i];
888 if (rxp->rx_mbuf != NULL) {
889 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
890 BUS_DMASYNC_POSTREAD);
891 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
892 m_freem(rxp->rx_mbuf);
893 }
894 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
895 }
896 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
897 bus_dma_tag_destroy(sc->fxp_mtag);
898 }
899 if (sc->fxp_stag) {
900 for (i = 0; i < FXP_NTXCB; i++) {
901 txp = &sc->fxp_desc.tx_list[i];
902 if (txp->tx_mbuf != NULL) {
903 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
904 BUS_DMASYNC_POSTWRITE);
905 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
906 m_freem(txp->tx_mbuf);
907 }
908 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
909 }
910 bus_dma_tag_destroy(sc->fxp_stag);
911 }
912 if (sc->cbl_tag)
913 bus_dma_tag_destroy(sc->cbl_tag);
914 if (sc->mcs_tag)
915 bus_dma_tag_destroy(sc->mcs_tag);
916
917 sysctl_ctx_free(&sc->sysctl_ctx);
918
919 mtx_destroy(&sc->sc_mtx);
920}
921
922/*
923 * Detach interface.
924 */
925static int
926fxp_detach(device_t dev)
927{
928 struct fxp_softc *sc = device_get_softc(dev);
929 int s;
930
931 FXP_LOCK(sc);
932 s = splimp();
933
934 sc->suspended = 1; /* Do same thing as we do for suspend */
935 /*
936 * Close down routes etc.
937 */
938 ether_ifdetach(&sc->arpcom.ac_if);
939
940 /*
941 * Stop DMA and drop transmit queue, but disable interrupts first.
942 */
943 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
944 fxp_stop(sc);
945 FXP_UNLOCK(sc);
946
947 /*
948 * Unhook interrupt before dropping lock. This is to prevent
949 * races with fxp_intr().
950 */
951 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
952 sc->ih = NULL;
953
954 splx(s);
955
956 /* Release our allocated resources. */
957 fxp_release(sc);
958 return (0);
959}
960
961/*
962 * Device shutdown routine. Called at system shutdown after sync. The
963 * main purpose of this routine is to shut off receiver DMA so that
964 * kernel memory doesn't get clobbered during warmboot.
965 */
966static int
967fxp_shutdown(device_t dev)
968{
969 /*
970 * Make sure that DMA is disabled prior to reboot. Not doing
971 * do could allow DMA to corrupt kernel memory during the
972 * reboot before the driver initializes.
973 */
974 fxp_stop((struct fxp_softc *) device_get_softc(dev));
975 return (0);
976}
977
978/*
979 * Device suspend routine. Stop the interface and save some PCI
980 * settings in case the BIOS doesn't restore them properly on
981 * resume.
982 */
983static int
984fxp_suspend(device_t dev)
985{
986 struct fxp_softc *sc = device_get_softc(dev);
987 int i, s;
988
989 FXP_LOCK(sc);
990 s = splimp();
991
992 fxp_stop(sc);
993
994 for (i = 0; i < 5; i++)
995 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
996 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
997 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
998 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
999 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1000
1001 sc->suspended = 1;
1002
1003 FXP_UNLOCK(sc);
1004 splx(s);
1005 return (0);
1006}
1007
1008/*
1009 * Device resume routine. Restore some PCI settings in case the BIOS
1010 * doesn't, re-enable busmastering, and restart the interface if
1011 * appropriate.
1012 */
1013static int
1014fxp_resume(device_t dev)
1015{
1016 struct fxp_softc *sc = device_get_softc(dev);
1017 struct ifnet *ifp = &sc->sc_if;
1018 u_int16_t pci_command;
1019 int i, s;
1020
1021 FXP_LOCK(sc);
1022 s = splimp();
1023#ifndef BURN_BRIDGES
1024 fxp_powerstate_d0(dev);
1025#endif
1026 /* better way to do this? */
1027 for (i = 0; i < 5; i++)
1028 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1029 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1030 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1031 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1032 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1033
1034 /* reenable busmastering */
1035 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
1036 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1037 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
1038
1039 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1040 DELAY(10);
1041
1042 /* reinitialize interface if necessary */
1043 if (ifp->if_flags & IFF_UP)
1044 fxp_init_body(sc);
1045
1046 sc->suspended = 0;
1047
1048 FXP_UNLOCK(sc);
1049 splx(s);
1050 return (0);
1051}
1052
1053static void
1054fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1055{
1056 u_int16_t reg;
1057 int x;
1058
1059 /*
1060 * Shift in data.
1061 */
1062 for (x = 1 << (length - 1); x; x >>= 1) {
1063 if (data & x)
1064 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1065 else
1066 reg = FXP_EEPROM_EECS;
1067 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1068 DELAY(1);
1069 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1070 DELAY(1);
1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1072 DELAY(1);
1073 }
1074}
1075
1076/*
1077 * Read from the serial EEPROM. Basically, you manually shift in
1078 * the read opcode (one bit at a time) and then shift in the address,
1079 * and then you shift out the data (all of this one bit at a time).
1080 * The word size is 16 bits, so you have to provide the address for
1081 * every 16 bits of data.
1082 */
1083static u_int16_t
1084fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1085{
1086 u_int16_t reg, data;
1087 int x;
1088
1089 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1090 /*
1091 * Shift in read opcode.
1092 */
1093 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1094 /*
1095 * Shift in address.
1096 */
1097 data = 0;
1098 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1099 if (offset & x)
1100 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1101 else
1102 reg = FXP_EEPROM_EECS;
1103 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1104 DELAY(1);
1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1106 DELAY(1);
1107 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1108 DELAY(1);
1109 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1110 data++;
1111 if (autosize && reg == 0) {
1112 sc->eeprom_size = data;
1113 break;
1114 }
1115 }
1116 /*
1117 * Shift out data.
1118 */
1119 data = 0;
1120 reg = FXP_EEPROM_EECS;
1121 for (x = 1 << 15; x; x >>= 1) {
1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1123 DELAY(1);
1124 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1125 data |= x;
1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1127 DELAY(1);
1128 }
1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1130 DELAY(1);
1131
1132 return (data);
1133}
1134
1135static void
1136fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1137{
1138 int i;
1139
1140 /*
1141 * Erase/write enable.
1142 */
1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1144 fxp_eeprom_shiftin(sc, 0x4, 3);
1145 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1147 DELAY(1);
1148 /*
1149 * Shift in write opcode, address, data.
1150 */
1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1152 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1153 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1154 fxp_eeprom_shiftin(sc, data, 16);
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1156 DELAY(1);
1157 /*
1158 * Wait for EEPROM to finish up.
1159 */
1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1161 DELAY(1);
1162 for (i = 0; i < 1000; i++) {
1163 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1164 break;
1165 DELAY(50);
1166 }
1167 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1168 DELAY(1);
1169 /*
1170 * Erase/write disable.
1171 */
1172 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1173 fxp_eeprom_shiftin(sc, 0x4, 3);
1174 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1175 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1176 DELAY(1);
1177}
1178
1179/*
1180 * From NetBSD:
1181 *
1182 * Figure out EEPROM size.
1183 *
1184 * 559's can have either 64-word or 256-word EEPROMs, the 558
1185 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1186 * talks about the existance of 16 to 256 word EEPROMs.
1187 *
1188 * The only known sizes are 64 and 256, where the 256 version is used
1189 * by CardBus cards to store CIS information.
1190 *
1191 * The address is shifted in msb-to-lsb, and after the last
1192 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1193 * after which follows the actual data. We try to detect this zero, by
1194 * probing the data-out bit in the EEPROM control register just after
1195 * having shifted in a bit. If the bit is zero, we assume we've
1196 * shifted enough address bits. The data-out should be tri-state,
1197 * before this, which should translate to a logical one.
1198 */
1199static void
1200fxp_autosize_eeprom(struct fxp_softc *sc)
1201{
1202
1203 /* guess maximum size of 256 words */
1204 sc->eeprom_size = 8;
1205
1206 /* autosize */
1207 (void) fxp_eeprom_getword(sc, 0, 1);
1208}
1209
1210static void
1211fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1212{
1213 int i;
1214
1215 for (i = 0; i < words; i++)
1216 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1217}
1218
1219static void
1220fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1221{
1222 int i;
1223
1224 for (i = 0; i < words; i++)
1225 fxp_eeprom_putword(sc, offset + i, data[i]);
1226}
1227
1228static void
1229fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
1230 bus_size_t mapsize, int error)
1231{
1232 struct fxp_softc *sc;
1233 struct fxp_cb_tx *txp;
1234 int i;
1235
1236 if (error)
1237 return;
1238
1239 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments"));
1240
1241 sc = arg;
1242 txp = sc->fxp_desc.tx_last->tx_next->tx_cb;
1243 for (i = 0; i < nseg; i++) {
1244 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
1245 /*
1246 * If this is an 82550/82551, then we're using extended
1247 * TxCBs _and_ we're using checksum offload. This means
1248 * that the TxCB is really an IPCB. One major difference
1249 * between the two is that with plain extended TxCBs,
1250 * the bottom half of the TxCB contains two entries from
1251 * the TBD array, whereas IPCBs contain just one entry:
1252 * one entry (8 bytes) has been sacrificed for the TCP/IP
1253 * checksum offload control bits. So to make things work
1254 * right, we have to start filling in the TBD array
1255 * starting from a different place depending on whether
1256 * the chip is an 82550/82551 or not.
1257 */
1258 if (sc->flags & FXP_FLAG_EXT_RFA) {
1259 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1260 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1261 } else {
1262 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1263 txp->tbd[i].tb_size = htole32(segs[i].ds_len);
1264 }
1265 }
1266 txp->tbd_number = nseg;
1267}
1268
1269/*
1270 * Grab the softc lock and call the real fxp_start_body() routine
1271 */
1272static void
1273fxp_start(struct ifnet *ifp)
1274{
1275 struct fxp_softc *sc = ifp->if_softc;
1276
1277 FXP_LOCK(sc);
1278 fxp_start_body(ifp);
1279 FXP_UNLOCK(sc);
1280}
1281
1282/*
1283 * Start packet transmission on the interface.
1284 * This routine must be called with the softc lock held, and is an
1285 * internal entry point only.
1286 */
1287static void
1288fxp_start_body(struct ifnet *ifp)
1289{
1290 struct fxp_softc *sc = ifp->if_softc;
1291 struct fxp_tx *txp;
1292 struct mbuf *mb_head;
1293 int error;
1294
1295 mtx_assert(&sc->sc_mtx, MA_OWNED);
1296 /*
1297 * See if we need to suspend xmit until the multicast filter
1298 * has been reprogrammed (which can only be done at the head
1299 * of the command chain).
1300 */
1301 if (sc->need_mcsetup) {
1302 return;
1303 }
1304
1305 txp = NULL;
1306
1307 /*
1308 * We're finished if there is nothing more to add to the list or if
1309 * we're all filled up with buffers to transmit.
1310 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1311 * a NOP command when needed.
1312 */
1313 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1314
1315 /*
1316 * Grab a packet to transmit.
1317 */
1318 IF_DEQUEUE(&ifp->if_snd, mb_head);
1319
1320 /*
1321 * Get pointer to next available tx desc.
1322 */
1323 txp = sc->fxp_desc.tx_last->tx_next;
1324
1325 /*
1326 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1327 * Ethernet Controller Family Open Source Software
1328 * Developer Manual says:
1329 * Using software parsing is only allowed with legal
1330 * TCP/IP or UDP/IP packets.
1331 * ...
1332 * For all other datagrams, hardware parsing must
1333 * be used.
1334 * Software parsing appears to truncate ICMP and
1335 * fragmented UDP packets that contain one to three
1336 * bytes in the second (and final) mbuf of the packet.
1337 */
1338 if (sc->flags & FXP_FLAG_EXT_RFA)
1339 txp->tx_cb->ipcb_ip_activation_high =
1340 FXP_IPCB_HARDWAREPARSING_ENABLE;
1341
1342 /*
1343 * Deal with TCP/IP checksum offload. Note that
1344 * in order for TCP checksum offload to work,
1345 * the pseudo header checksum must have already
1346 * been computed and stored in the checksum field
1347 * in the TCP header. The stack should have
1348 * already done this for us.
1349 */
1350
1351 if (mb_head->m_pkthdr.csum_flags) {
1352 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1353 txp->tx_cb->ipcb_ip_schedule =
1354 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1355 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP)
1356 txp->tx_cb->ipcb_ip_schedule |=
1357 FXP_IPCB_TCP_PACKET;
1358 }
1359#ifdef FXP_IP_CSUM_WAR
1360 /*
1361 * XXX The 82550 chip appears to have trouble
1362 * dealing with IP header checksums in very small
1363 * datagrams, namely fragments from 1 to 3 bytes
1364 * in size. For example, say you want to transmit
1365 * a UDP packet of 1473 bytes. The packet will be
1366 * fragmented over two IP datagrams, the latter
1367 * containing only one byte of data. The 82550 will
1368 * botch the header checksum on the 1-byte fragment.
1369 * As long as the datagram contains 4 or more bytes
1370 * of data, you're ok.
1371 *
1372 * The following code attempts to work around this
1373 * problem: if the datagram is less than 38 bytes
1374 * in size (14 bytes ether header, 20 bytes IP header,
1375 * plus 4 bytes of data), we punt and compute the IP
1376 * header checksum by hand. This workaround doesn't
1377 * work very well, however, since it can be fooled
1378 * by things like VLAN tags and IP options that make
1379 * the header sizes/offsets vary.
1380 */
1381
1382 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) {
1383 if (mb_head->m_pkthdr.len < 38) {
1384 struct ip *ip;
1385 mb_head->m_data += ETHER_HDR_LEN;
1386 ip = mtod(mb_head, struct ip *);
1387 ip->ip_sum = in_cksum(mb_head,
1388 ip->ip_hl << 2);
1389 mb_head->m_data -= ETHER_HDR_LEN;
1390 } else {
1391 txp->tx_cb->ipcb_ip_activation_high =
1392 FXP_IPCB_HARDWAREPARSING_ENABLE;
1393 txp->tx_cb->ipcb_ip_schedule |=
1394 FXP_IPCB_IP_CHECKSUM_ENABLE;
1395 }
1396 }
1397#endif
1398 }
1399
1400 /*
1401 * Go through each of the mbufs in the chain and initialize
1402 * the transmit buffer descriptors with the physical address
1403 * and size of the mbuf.
1404 */
1405 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1406 mb_head, fxp_dma_map_txbuf, sc, 0);
1407
1408 if (error && error != EFBIG) {
1409 device_printf(sc->dev, "can't map mbuf (error %d)\n",
1410 error);
1411 m_freem(mb_head);
1412 break;
1413 }
1414
1415 if (error) {
1416 struct mbuf *mn;
1417
1418 /*
1419 * We ran out of segments. We have to recopy this
1420 * mbuf chain first. Bail out if we can't get the
1421 * new buffers.
1422 */
1423 mn = m_defrag(mb_head, M_DONTWAIT);
1424 if (mn == NULL) {
1425 m_freem(mb_head);
1426 break;
1427 } else {
1428 mb_head = mn;
1429 }
1430 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1431 mb_head, fxp_dma_map_txbuf, sc, 0);
1432 if (error) {
1433 device_printf(sc->dev,
1434 "can't map mbuf (error %d)\n", error);
1435 m_freem(mb_head);
1436 break;
1437 }
1438 }
1439
1440 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1441 BUS_DMASYNC_PREWRITE);
1442
1443 txp->tx_mbuf = mb_head;
1444 txp->tx_cb->cb_status = 0;
1445 txp->tx_cb->byte_count = 0;
1446 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1447 txp->tx_cb->cb_command =
1448 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1449 FXP_CB_COMMAND_S);
1450 } else {
1451 txp->tx_cb->cb_command =
1452 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1453 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1454 /*
1455 * Set a 5 second timer just in case we don't hear
1456 * from the card again.
1457 */
1458 ifp->if_timer = 5;
1459 }
1460 txp->tx_cb->tx_threshold = tx_threshold;
1461
1462 /*
1463 * Advance the end of list forward.
1464 */
1465
1466#ifdef __alpha__
1467 /*
1468 * On platforms which can't access memory in 16-bit
1469 * granularities, we must prevent the card from DMA'ing
1470 * up the status while we update the command field.
1471 * This could cause us to overwrite the completion status.
1472 * XXX This is probably bogus and we're _not_ looking
1473 * for atomicity here.
1474 */
1475 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1476 htole16(FXP_CB_COMMAND_S));
1477#else
1478 sc->fxp_desc.tx_last->tx_cb->cb_command &=
1479 htole16(~FXP_CB_COMMAND_S);
1480#endif /*__alpha__*/
1481 sc->fxp_desc.tx_last = txp;
1482
1483 /*
1484 * Advance the beginning of the list forward if there are
1485 * no other packets queued (when nothing is queued, tx_first
1486 * sits on the last TxCB that was sent out).
1487 */
1488 if (sc->tx_queued == 0)
1489 sc->fxp_desc.tx_first = txp;
1490
1491 sc->tx_queued++;
1492
1493 /*
1494 * Pass packet to bpf if there is a listener.
1495 */
1496 BPF_MTAP(ifp, mb_head);
1497 }
1498 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1499
1500 /*
1501 * We're finished. If we added to the list, issue a RESUME to get DMA
1502 * going again if suspended.
1503 */
1504 if (txp != NULL) {
1505 fxp_scb_wait(sc);
1506 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1507 }
1508}
1509
1510#ifdef DEVICE_POLLING
1511static poll_handler_t fxp_poll;
1512
1513static void
1514fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1515{
1516 struct fxp_softc *sc = ifp->if_softc;
1517 u_int8_t statack;
1518
1519 FXP_LOCK(sc);
1520 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1521 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1522 FXP_UNLOCK(sc);
1523 return;
1524 }
1525 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1526 FXP_SCB_STATACK_FR;
1527 if (cmd == POLL_AND_CHECK_STATUS) {
1528 u_int8_t tmp;
1529
1530 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1531 if (tmp == 0xff || tmp == 0) {
1532 FXP_UNLOCK(sc);
1533 return; /* nothing to do */
1534 }
1535 tmp &= ~statack;
1536 /* ack what we can */
1537 if (tmp != 0)
1538 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1539 statack |= tmp;
1540 }
1541 fxp_intr_body(sc, ifp, statack, count);
1542 FXP_UNLOCK(sc);
1543}
1544#endif /* DEVICE_POLLING */
1545
1546/*
1547 * Process interface interrupts.
1548 */
1549static void
1550fxp_intr(void *xsc)
1551{
1552 struct fxp_softc *sc = xsc;
1553 struct ifnet *ifp = &sc->sc_if;
1554 u_int8_t statack;
1555
1556 FXP_LOCK(sc);
1557 if (sc->suspended) {
1558 FXP_UNLOCK(sc);
1559 return;
1560 }
1561
1562#ifdef DEVICE_POLLING
1563 if (ifp->if_flags & IFF_POLLING) {
1564 FXP_UNLOCK(sc);
1565 return;
1566 }
1567 if (ether_poll_register(fxp_poll, ifp)) {
1568 /* disable interrupts */
1569 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1570 FXP_UNLOCK(sc);
1571 fxp_poll(ifp, 0, 1);
1572 return;
1573 }
1574#endif
1575 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1576 /*
1577 * It should not be possible to have all bits set; the
1578 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1579 * all bits are set, this may indicate that the card has
1580 * been physically ejected, so ignore it.
1581 */
1582 if (statack == 0xff) {
1583 FXP_UNLOCK(sc);
1584 return;
1585 }
1586
1587 /*
1588 * First ACK all the interrupts in this pass.
1589 */
1590 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1591 fxp_intr_body(sc, ifp, statack, -1);
1592 }
1593 FXP_UNLOCK(sc);
1594}
1595
1596static void
1597fxp_txeof(struct fxp_softc *sc)
1598{
1599 struct fxp_tx *txp;
1600
1601 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1602 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1603 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1604 txp = txp->tx_next) {
1605 if (txp->tx_mbuf != NULL) {
1606 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1607 BUS_DMASYNC_POSTWRITE);
1608 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1609 m_freem(txp->tx_mbuf);
1610 txp->tx_mbuf = NULL;
1611 /* clear this to reset csum offload bits */
1612 txp->tx_cb->tbd[0].tb_addr = 0;
1613 }
1614 sc->tx_queued--;
1615 }
1616 sc->fxp_desc.tx_first = txp;
1617 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1618}
1619
1620static void
1621fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack,
1622 int count)
1623{
1624 struct mbuf *m;
1625 struct fxp_rx *rxp;
1626 struct fxp_rfa *rfa;
1627 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1628
1629 mtx_assert(&sc->sc_mtx, MA_OWNED);
1630 if (rnr)
1631 fxp_rnr++;
1632#ifdef DEVICE_POLLING
1633 /* Pick up a deferred RNR condition if `count' ran out last time. */
1634 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1635 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1636 rnr = 1;
1637 }
1638#endif
1639
1640 /*
1641 * Free any finished transmit mbuf chains.
1642 *
1643 * Handle the CNA event likt a CXTNO event. It used to
1644 * be that this event (control unit not ready) was not
1645 * encountered, but it is now with the SMPng modifications.
1646 * The exact sequence of events that occur when the interface
1647 * is brought up are different now, and if this event
1648 * goes unhandled, the configuration/rxfilter setup sequence
1649 * can stall for several seconds. The result is that no
1650 * packets go out onto the wire for about 5 to 10 seconds
1651 * after the interface is ifconfig'ed for the first time.
1652 */
1653 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1654 fxp_txeof(sc);
1655
1656 ifp->if_timer = 0;
1657 if (sc->tx_queued == 0) {
1658 if (sc->need_mcsetup)
1659 fxp_mc_setup(sc);
1660 }
1661 /*
1662 * Try to start more packets transmitting.
1663 */
1664 if (ifp->if_snd.ifq_head != NULL)
1665 fxp_start_body(ifp);
1666 }
1667
1668 /*
1669 * Just return if nothing happened on the receive side.
1670 */
1671 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1672 return;
1673
1674 /*
1675 * Process receiver interrupts. If a no-resource (RNR)
1676 * condition exists, get whatever packets we can and
1677 * re-start the receiver.
1678 *
1679 * When using polling, we do not process the list to completion,
1680 * so when we get an RNR interrupt we must defer the restart
1681 * until we hit the last buffer with the C bit set.
1682 * If we run out of cycles and rfa_headm has the C bit set,
1683 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1684 * that the info will be used in the subsequent polling cycle.
1685 */
1686 for (;;) {
1687 rxp = sc->fxp_desc.rx_head;
1688 m = rxp->rx_mbuf;
1689 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1690 RFA_ALIGNMENT_FUDGE);
1691 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1692 BUS_DMASYNC_POSTREAD);
1693
1694#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1695 if (count >= 0 && count-- == 0) {
1696 if (rnr) {
1697 /* Defer RNR processing until the next time. */
1698 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1699 rnr = 0;
1700 }
1701 break;
1702 }
1703#endif /* DEVICE_POLLING */
1704
1705 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0)
1706 break;
1707
1708 /*
1709 * Advance head forward.
1710 */
1711 sc->fxp_desc.rx_head = rxp->rx_next;
1712
1713 /*
1714 * Add a new buffer to the receive chain.
1715 * If this fails, the old buffer is recycled
1716 * instead.
1717 */
1718 if (fxp_add_rfabuf(sc, rxp) == 0) {
1719 int total_len;
1720
1721 /*
1722 * Fetch packet length (the top 2 bits of
1723 * actual_size are flags set by the controller
1724 * upon completion), and drop the packet in case
1725 * of bogus length or CRC errors.
1726 */
1727 total_len = le16toh(rfa->actual_size) & 0x3fff;
1728 if (total_len < sizeof(struct ether_header) ||
1729 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1730 sc->rfa_size ||
1731 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) {
1732 m_freem(m);
1733 continue;
1734 }
1735
1736 /* Do IP checksum checking. */
1737 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) {
1738 if (rfa->rfax_csum_sts &
1739 FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1740 m->m_pkthdr.csum_flags |=
1741 CSUM_IP_CHECKED;
1742 if (rfa->rfax_csum_sts &
1743 FXP_RFDX_CS_IP_CSUM_VALID)
1744 m->m_pkthdr.csum_flags |=
1745 CSUM_IP_VALID;
1746 if ((rfa->rfax_csum_sts &
1747 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1748 (rfa->rfax_csum_sts &
1749 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1750 m->m_pkthdr.csum_flags |=
1751 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1752 m->m_pkthdr.csum_data = 0xffff;
1753 }
1754 }
1755
1756 m->m_pkthdr.len = m->m_len = total_len;
1757 m->m_pkthdr.rcvif = ifp;
1758
1759 /*
1760 * Drop locks before calling if_input() since it
1761 * may re-enter fxp_start() in the netisr case.
1762 * This would result in a lock reversal. Better
1763 * performance might be obtained by chaining all
1764 * packets received, dropping the lock, and then
1765 * calling if_input() on each one.
1766 */
1767 FXP_UNLOCK(sc);
1768 (*ifp->if_input)(ifp, m);
1769 FXP_LOCK(sc);
1770 }
1771 }
1772 if (rnr) {
1773 fxp_scb_wait(sc);
1774 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1775 sc->fxp_desc.rx_head->rx_addr);
1776 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1777 }
1778}
1779
1780/*
1781 * Update packet in/out/collision statistics. The i82557 doesn't
1782 * allow you to access these counters without doing a fairly
1783 * expensive DMA to get _all_ of the statistics it maintains, so
1784 * we do this operation here only once per second. The statistics
1785 * counters in the kernel are updated from the previous dump-stats
1786 * DMA and then a new dump-stats DMA is started. The on-chip
1787 * counters are zeroed when the DMA completes. If we can't start
1788 * the DMA immediately, we don't wait - we just prepare to read
1789 * them again next time.
1790 */
1791static void
1792fxp_tick(void *xsc)
1793{
1794 struct fxp_softc *sc = xsc;
1795 struct ifnet *ifp = &sc->sc_if;
1796 struct fxp_stats *sp = sc->fxp_stats;
1797 int s;
1798
1799 FXP_LOCK(sc);
1800 s = splimp();
1801 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1802 ifp->if_opackets += le32toh(sp->tx_good);
1803 ifp->if_collisions += le32toh(sp->tx_total_collisions);
1804 if (sp->rx_good) {
1805 ifp->if_ipackets += le32toh(sp->rx_good);
1806 sc->rx_idle_secs = 0;
1807 } else {
1808 /*
1809 * Receiver's been idle for another second.
1810 */
1811 sc->rx_idle_secs++;
1812 }
1813 ifp->if_ierrors +=
1814 le32toh(sp->rx_crc_errors) +
1815 le32toh(sp->rx_alignment_errors) +
1816 le32toh(sp->rx_rnr_errors) +
1817 le32toh(sp->rx_overrun_errors);
1818 /*
1819 * If any transmit underruns occured, bump up the transmit
1820 * threshold by another 512 bytes (64 * 8).
1821 */
1822 if (sp->tx_underruns) {
1823 ifp->if_oerrors += le32toh(sp->tx_underruns);
1824 if (tx_threshold < 192)
1825 tx_threshold += 64;
1826 }
1827
1828 /*
1829 * Release any xmit buffers that have completed DMA. This isn't
1830 * strictly necessary to do here, but it's advantagous for mbufs
1831 * with external storage to be released in a timely manner rather
1832 * than being defered for a potentially long time. This limits
1833 * the delay to a maximum of one second.
1834 */
1835 fxp_txeof(sc);
1836
1837 /*
1838 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1839 * then assume the receiver has locked up and attempt to clear
1840 * the condition by reprogramming the multicast filter. This is
1841 * a work-around for a bug in the 82557 where the receiver locks
1842 * up if it gets certain types of garbage in the syncronization
1843 * bits prior to the packet header. This bug is supposed to only
1844 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1845 * mode as well (perhaps due to a 10/100 speed transition).
1846 */
1847 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1848 sc->rx_idle_secs = 0;
1849 fxp_mc_setup(sc);
1850 }
1851 /*
1852 * If there is no pending command, start another stats
1853 * dump. Otherwise punt for now.
1854 */
1855 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1856 /*
1857 * Start another stats dump.
1858 */
1859 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
1860 BUS_DMASYNC_PREREAD);
1861 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1862 } else {
1863 /*
1864 * A previous command is still waiting to be accepted.
1865 * Just zero our copy of the stats and wait for the
1866 * next timer event to update them.
1867 */
1868 sp->tx_good = 0;
1869 sp->tx_underruns = 0;
1870 sp->tx_total_collisions = 0;
1871
1872 sp->rx_good = 0;
1873 sp->rx_crc_errors = 0;
1874 sp->rx_alignment_errors = 0;
1875 sp->rx_rnr_errors = 0;
1876 sp->rx_overrun_errors = 0;
1877 }
1878 if (sc->miibus != NULL)
1879 mii_tick(device_get_softc(sc->miibus));
1880
1881 /*
1882 * Schedule another timeout one second from now.
1883 */
1884 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
1885 FXP_UNLOCK(sc);
1886 splx(s);
1887}
1888
1889/*
1890 * Stop the interface. Cancels the statistics updater and resets
1891 * the interface.
1892 */
1893static void
1894fxp_stop(struct fxp_softc *sc)
1895{
1896 struct ifnet *ifp = &sc->sc_if;
1897 struct fxp_tx *txp;
1898 int i;
1899
1900 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1901 ifp->if_timer = 0;
1902
1903#ifdef DEVICE_POLLING
1904 ether_poll_deregister(ifp);
1905#endif
1906 /*
1907 * Cancel stats updater.
1908 */
1909 callout_stop(&sc->stat_ch);
1910
1911 /*
1912 * Issue software reset, which also unloads the microcode.
1913 */
1914 sc->flags &= ~FXP_FLAG_UCODE;
1915 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1916 DELAY(50);
1917
1918 /*
1919 * Release any xmit buffers.
1920 */
1921 txp = sc->fxp_desc.tx_list;
1922 if (txp != NULL) {
1923 for (i = 0; i < FXP_NTXCB; i++) {
1924 if (txp[i].tx_mbuf != NULL) {
1925 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
1926 BUS_DMASYNC_POSTWRITE);
1927 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
1928 m_freem(txp[i].tx_mbuf);
1929 txp[i].tx_mbuf = NULL;
1930 /* clear this to reset csum offload bits */
1931 txp[i].tx_cb->tbd[0].tb_addr = 0;
1932 }
1933 }
1934 }
1935 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1936 sc->tx_queued = 0;
1937}
1938
1939/*
1940 * Watchdog/transmission transmit timeout handler. Called when a
1941 * transmission is started on the interface, but no interrupt is
1942 * received before the timeout. This usually indicates that the
1943 * card has wedged for some reason.
1944 */
1945static void
1946fxp_watchdog(struct ifnet *ifp)
1947{
1948 struct fxp_softc *sc = ifp->if_softc;
1949
1950 FXP_LOCK(sc);
1951 device_printf(sc->dev, "device timeout\n");
1952 ifp->if_oerrors++;
1953
1954 fxp_init_body(sc);
1955 FXP_UNLOCK(sc);
1956}
1957
1958/*
1959 * Acquire locks and then call the real initialization function. This
1960 * is necessary because ether_ioctl() calls if_init() and this would
1961 * result in mutex recursion if the mutex was held.
1962 */
1963static void
1964fxp_init(void *xsc)
1965{
1966 struct fxp_softc *sc = xsc;
1967
1968 FXP_LOCK(sc);
1969 fxp_init_body(sc);
1970 FXP_UNLOCK(sc);
1971}
1972
1973/*
1974 * Perform device initialization. This routine must be called with the
1975 * softc lock held.
1976 */
1977static void
1978fxp_init_body(struct fxp_softc *sc)
1979{
1980 struct ifnet *ifp = &sc->sc_if;
1981 struct fxp_cb_config *cbp;
1982 struct fxp_cb_ias *cb_ias;
1983 struct fxp_cb_tx *tcbp;
1984 struct fxp_tx *txp;
1985 struct fxp_cb_mcs *mcsp;
1986 int i, prm, s;
1987
1988 mtx_assert(&sc->sc_mtx, MA_OWNED);
1989 s = splimp();
1990 /*
1991 * Cancel any pending I/O
1992 */
1993 fxp_stop(sc);
1994
1995 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1996
1997 /*
1998 * Initialize base of CBL and RFA memory. Loading with zero
1999 * sets it up for regular linear addressing.
2000 */
2001 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2002 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2003
2004 fxp_scb_wait(sc);
2005 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2006
2007 /*
2008 * Initialize base of dump-stats buffer.
2009 */
2010 fxp_scb_wait(sc);
2011 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
2012 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2013 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2014
2015 /*
2016 * Attempt to load microcode if requested.
2017 */
2018 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
2019 fxp_load_ucode(sc);
2020
2021 /*
2022 * Initialize the multicast address list.
2023 */
2024 if (fxp_mc_addrs(sc)) {
2025 mcsp = sc->mcsp;
2026 mcsp->cb_status = 0;
2027 mcsp->cb_command =
2028 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2029 mcsp->link_addr = 0xffffffff;
2030 /*
2031 * Start the multicast setup command.
2032 */
2033 fxp_scb_wait(sc);
2034 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2035 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2036 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2037 /* ...and wait for it to complete. */
2038 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
2039 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
2040 BUS_DMASYNC_POSTWRITE);
2041 }
2042
2043 /*
2044 * We temporarily use memory that contains the TxCB list to
2045 * construct the config CB. The TxCB list memory is rebuilt
2046 * later.
2047 */
2048 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2049
2050 /*
2051 * This bcopy is kind of disgusting, but there are a bunch of must be
2052 * zero and must be one bits in this structure and this is the easiest
2053 * way to initialize them all to proper values.
2054 */
2055 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2056
2057 cbp->cb_status = 0;
2058 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2059 FXP_CB_COMMAND_EL);
2060 cbp->link_addr = 0xffffffff; /* (no) next command */
2061 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2062 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2063 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2064 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2065 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2066 cbp->type_enable = 0; /* actually reserved */
2067 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2068 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2069 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2070 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2071 cbp->dma_mbce = 0; /* (disable) dma max counters */
2072 cbp->late_scb = 0; /* (don't) defer SCB update */
2073 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2074 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2075 cbp->ci_int = 1; /* interrupt on CU idle */
2076 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2077 cbp->ext_stats_dis = 1; /* disable extended counters */
2078 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2079 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
2080 cbp->disc_short_rx = !prm; /* discard short packets */
2081 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2082 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2083 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
2084 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2085 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2086 cbp->csma_dis = 0; /* (don't) disable link */
2087 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
2088 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2089 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2090 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2091 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2092 cbp->nsai = 1; /* (don't) disable source addr insert */
2093 cbp->preamble_length = 2; /* (7 byte) preamble */
2094 cbp->loopback = 0; /* (don't) loopback */
2095 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2096 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2097 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2098 cbp->promiscuous = prm; /* promiscuous mode */
2099 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2100 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2101 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2102 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2103 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2104
2105 cbp->stripping = !prm; /* truncate rx packet to byte count */
2106 cbp->padding = 1; /* (do) pad short tx packets */
2107 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2108 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2109 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2110 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
2111 /* must set wake_en in PMCSR also */
2112 cbp->force_fdx = 0; /* (don't) force full duplex */
2113 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2114 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2115 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
2116 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2117
2118 if (fxp_noflow || sc->revision == FXP_REV_82557) {
2119 /*
2120 * The 82557 has no hardware flow control, the values
2121 * below are the defaults for the chip.
2122 */
2123 cbp->fc_delay_lsb = 0;
2124 cbp->fc_delay_msb = 0x40;
2125 cbp->pri_fc_thresh = 3;
2126 cbp->tx_fc_dis = 0;
2127 cbp->rx_fc_restop = 0;
2128 cbp->rx_fc_restart = 0;
2129 cbp->fc_filter = 0;
2130 cbp->pri_fc_loc = 1;
2131 } else {
2132 cbp->fc_delay_lsb = 0x1f;
2133 cbp->fc_delay_msb = 0x01;
2134 cbp->pri_fc_thresh = 3;
2135 cbp->tx_fc_dis = 0; /* enable transmit FC */
2136 cbp->rx_fc_restop = 1; /* enable FC restop frames */
2137 cbp->rx_fc_restart = 1; /* enable FC restart frames */
2138 cbp->fc_filter = !prm; /* drop FC frames to host */
2139 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2140 }
2141
2142 /*
2143 * Start the config command/DMA.
2144 */
2145 fxp_scb_wait(sc);
2146 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2147 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2149 /* ...and wait for it to complete. */
2150 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2151 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2152
2153 /*
2154 * Now initialize the station address. Temporarily use the TxCB
2155 * memory area like we did above for the config CB.
2156 */
2157 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2158 cb_ias->cb_status = 0;
2159 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2160 cb_ias->link_addr = 0xffffffff;
2161 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr,
2162 sizeof(sc->arpcom.ac_enaddr));
2163
2164 /*
2165 * Start the IAS (Individual Address Setup) command/DMA.
2166 */
2167 fxp_scb_wait(sc);
2168 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2170 /* ...and wait for it to complete. */
2171 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2172 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2173
2174 /*
2175 * Initialize transmit control block (TxCB) list.
2176 */
2177 txp = sc->fxp_desc.tx_list;
2178 tcbp = sc->fxp_desc.cbl_list;
2179 bzero(tcbp, FXP_TXCB_SZ);
2180 for (i = 0; i < FXP_NTXCB; i++) {
2181 txp[i].tx_cb = tcbp + i;
2182 txp[i].tx_mbuf = NULL;
2183 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2184 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2185 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2186 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2187 if (sc->flags & FXP_FLAG_EXT_TXCB)
2188 tcbp[i].tbd_array_addr =
2189 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2190 else
2191 tcbp[i].tbd_array_addr =
2192 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2193 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2194 }
2195 /*
2196 * Set the suspend flag on the first TxCB and start the control
2197 * unit. It will execute the NOP and then suspend.
2198 */
2199 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2200 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2201 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2202 sc->tx_queued = 1;
2203
2204 fxp_scb_wait(sc);
2205 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2206
2207 /*
2208 * Initialize receiver buffer area - RFA.
2209 */
2210 fxp_scb_wait(sc);
2211 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2212 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2213
2214 /*
2215 * Set current media.
2216 */
2217 if (sc->miibus != NULL)
2218 mii_mediachg(device_get_softc(sc->miibus));
2219
2220 ifp->if_flags |= IFF_RUNNING;
2221 ifp->if_flags &= ~IFF_OACTIVE;
2222
2223 /*
2224 * Enable interrupts.
2225 */
2226#ifdef DEVICE_POLLING
2227 /*
2228 * ... but only do that if we are not polling. And because (presumably)
2229 * the default is interrupts on, we need to disable them explicitly!
2230 */
2231 if ( ifp->if_flags & IFF_POLLING )
2232 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2233 else
2234#endif /* DEVICE_POLLING */
2235 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2236
2237 /*
2238 * Start stats updater.
2239 */
2240 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2241 splx(s);
2242}
2243
2244static int
2245fxp_serial_ifmedia_upd(struct ifnet *ifp)
2246{
2247
2248 return (0);
2249}
2250
2251static void
2252fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2253{
2254
2255 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2256}
2257
2258/*
2259 * Change media according to request.
2260 */
2261static int
2262fxp_ifmedia_upd(struct ifnet *ifp)
2263{
2264 struct fxp_softc *sc = ifp->if_softc;
2265 struct mii_data *mii;
2266
2267 mii = device_get_softc(sc->miibus);
2268 mii_mediachg(mii);
2269 return (0);
2270}
2271
2272/*
2273 * Notify the world which media we're using.
2274 */
2275static void
2276fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2277{
2278 struct fxp_softc *sc = ifp->if_softc;
2279 struct mii_data *mii;
2280
2281 mii = device_get_softc(sc->miibus);
2282 mii_pollstat(mii);
2283 ifmr->ifm_active = mii->mii_media_active;
2284 ifmr->ifm_status = mii->mii_media_status;
2285
2286 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
2287 sc->cu_resume_bug = 1;
2288 else
2289 sc->cu_resume_bug = 0;
2290}
2291
2292/*
2293 * Add a buffer to the end of the RFA buffer list.
2294 * Return 0 if successful, 1 for failure. A failure results in
2295 * adding the 'oldm' (if non-NULL) on to the end of the list -
2296 * tossing out its old contents and recycling it.
2297 * The RFA struct is stuck at the beginning of mbuf cluster and the
2298 * data pointer is fixed up to point just past it.
2299 */
2300static int
2301fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2302{
2303 struct mbuf *m;
2304 struct fxp_rfa *rfa, *p_rfa;
2305 struct fxp_rx *p_rx;
2306 bus_dmamap_t tmp_map;
2307 int error;
2308
2309 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2310 if (m == NULL)
2311 return (ENOBUFS);
2312
2313 /*
2314 * Move the data pointer up so that the incoming data packet
2315 * will be 32-bit aligned.
2316 */
2317 m->m_data += RFA_ALIGNMENT_FUDGE;
2318
2319 /*
2320 * Get a pointer to the base of the mbuf cluster and move
2321 * data start past it.
2322 */
2323 rfa = mtod(m, struct fxp_rfa *);
2324 m->m_data += sc->rfa_size;
2325 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2326
2327 rfa->rfa_status = 0;
2328 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2329 rfa->actual_size = 0;
2330
2331 /*
2332 * Initialize the rest of the RFA. Note that since the RFA
2333 * is misaligned, we cannot store values directly. We're thus
2334 * using the le32enc() function which handles endianness and
2335 * is also alignment-safe.
2336 */
2337 le32enc(&rfa->link_addr, 0xffffffff);
2338 le32enc(&rfa->rbd_addr, 0xffffffff);
2339
2340 /* Map the RFA into DMA memory. */
2341 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2342 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2343 &rxp->rx_addr, 0);
2344 if (error) {
2345 m_freem(m);
2346 return (error);
2347 }
2348
2349 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2350 tmp_map = sc->spare_map;
2351 sc->spare_map = rxp->rx_map;
2352 rxp->rx_map = tmp_map;
2353 rxp->rx_mbuf = m;
2354
2355 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2357
2358 /*
2359 * If there are other buffers already on the list, attach this
2360 * one to the end by fixing up the tail to point to this one.
2361 */
2362 if (sc->fxp_desc.rx_head != NULL) {
2363 p_rx = sc->fxp_desc.rx_tail;
2364 p_rfa = (struct fxp_rfa *)
2365 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2366 p_rx->rx_next = rxp;
2367 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2368 p_rfa->rfa_control = 0;
2369 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2370 BUS_DMASYNC_PREWRITE);
2371 } else {
2372 rxp->rx_next = NULL;
2373 sc->fxp_desc.rx_head = rxp;
2374 }
2375 sc->fxp_desc.rx_tail = rxp;
2376 return (0);
2377}
2378
2379static volatile int
2380fxp_miibus_readreg(device_t dev, int phy, int reg)
2381{
2382 struct fxp_softc *sc = device_get_softc(dev);
2383 int count = 10000;
2384 int value;
2385
2386 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2387 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2388
2389 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2390 && count--)
2391 DELAY(10);
2392
2393 if (count <= 0)
2394 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2395
2396 return (value & 0xffff);
2397}
2398
2399static void
2400fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2401{
2402 struct fxp_softc *sc = device_get_softc(dev);
2403 int count = 10000;
2404
2405 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2406 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2407 (value & 0xffff));
2408
2409 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2410 count--)
2411 DELAY(10);
2412
2413 if (count <= 0)
2414 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2415}
2416
2417static int
2418fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2419{
2420 struct fxp_softc *sc = ifp->if_softc;
2421 struct ifreq *ifr = (struct ifreq *)data;
2422 struct mii_data *mii;
2423 int s, error = 0;
2424
2425 /*
2426 * Detaching causes us to call ioctl with the mutex owned. Preclude
2427 * that by saying we're busy if the lock is already held.
2428 */
2429 if (mtx_owned(&sc->sc_mtx))
2430 return (EBUSY);
2431
2432 FXP_LOCK(sc);
2433 s = splimp();
2434
2435 switch (command) {
2436 case SIOCSIFFLAGS:
2437 if (ifp->if_flags & IFF_ALLMULTI)
2438 sc->flags |= FXP_FLAG_ALL_MCAST;
2439 else
2440 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2441
2442 /*
2443 * If interface is marked up and not running, then start it.
2444 * If it is marked down and running, stop it.
2445 * XXX If it's up then re-initialize it. This is so flags
2446 * such as IFF_PROMISC are handled.
2447 */
2448 if (ifp->if_flags & IFF_UP) {
2449 fxp_init_body(sc);
2450 } else {
2451 if (ifp->if_flags & IFF_RUNNING)
2452 fxp_stop(sc);
2453 }
2454 break;
2455
2456 case SIOCADDMULTI:
2457 case SIOCDELMULTI:
2458 if (ifp->if_flags & IFF_ALLMULTI)
2459 sc->flags |= FXP_FLAG_ALL_MCAST;
2460 else
2461 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2462 /*
2463 * Multicast list has changed; set the hardware filter
2464 * accordingly.
2465 */
2466 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2467 fxp_mc_setup(sc);
2468 /*
2469 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2470 * again rather than else {}.
2471 */
2472 if (sc->flags & FXP_FLAG_ALL_MCAST)
2473 fxp_init_body(sc);
2474 error = 0;
2475 break;
2476
2477 case SIOCSIFMEDIA:
2478 case SIOCGIFMEDIA:
2479 if (sc->miibus != NULL) {
2480 mii = device_get_softc(sc->miibus);
2481 error = ifmedia_ioctl(ifp, ifr,
2482 &mii->mii_media, command);
2483 } else {
2484 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2485 }
2486 break;
2487
2488 default:
2489 /*
2490 * ether_ioctl() will eventually call fxp_start() which
2491 * will result in mutex recursion so drop it first.
2492 */
2493 FXP_UNLOCK(sc);
2494 error = ether_ioctl(ifp, command, data);
2495 }
2496 if (mtx_owned(&sc->sc_mtx))
2497 FXP_UNLOCK(sc);
2498 splx(s);
2499 return (error);
2500}
2501
2502/*
2503 * Fill in the multicast address list and return number of entries.
2504 */
2505static int
2506fxp_mc_addrs(struct fxp_softc *sc)
2507{
2508 struct fxp_cb_mcs *mcsp = sc->mcsp;
2509 struct ifnet *ifp = &sc->sc_if;
2510 struct ifmultiaddr *ifma;
2511 int nmcasts;
2512
2513 nmcasts = 0;
2514 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2515#if __FreeBSD_version < 500000
2516 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2517#else
2518 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2519#endif
2520 if (ifma->ifma_addr->sa_family != AF_LINK)
2521 continue;
2522 if (nmcasts >= MAXMCADDR) {
2523 sc->flags |= FXP_FLAG_ALL_MCAST;
2524 nmcasts = 0;
2525 break;
2526 }
2527 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2528 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2529 nmcasts++;
2530 }
2531 }
2532 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2533 return (nmcasts);
2534}
2535
2536/*
2537 * Program the multicast filter.
2538 *
2539 * We have an artificial restriction that the multicast setup command
2540 * must be the first command in the chain, so we take steps to ensure
2541 * this. By requiring this, it allows us to keep up the performance of
2542 * the pre-initialized command ring (esp. link pointers) by not actually
2543 * inserting the mcsetup command in the ring - i.e. its link pointer
2544 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2545 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2546 * lead into the regular TxCB ring when it completes.
2547 *
2548 * This function must be called at splimp.
2549 */
2550static void
2551fxp_mc_setup(struct fxp_softc *sc)
2552{
2553 struct fxp_cb_mcs *mcsp = sc->mcsp;
2554 struct ifnet *ifp = &sc->sc_if;
2555 struct fxp_tx *txp;
2556 int count;
2557
2558 /*
2559 * If there are queued commands, we must wait until they are all
2560 * completed. If we are already waiting, then add a NOP command
2561 * with interrupt option so that we're notified when all commands
2562 * have been completed - fxp_start() ensures that no additional
2563 * TX commands will be added when need_mcsetup is true.
2564 */
2565 if (sc->tx_queued) {
2566 /*
2567 * need_mcsetup will be true if we are already waiting for the
2568 * NOP command to be completed (see below). In this case, bail.
2569 */
2570 if (sc->need_mcsetup)
2571 return;
2572 sc->need_mcsetup = 1;
2573
2574 /*
2575 * Add a NOP command with interrupt so that we are notified
2576 * when all TX commands have been processed.
2577 */
2578 txp = sc->fxp_desc.tx_last->tx_next;
2579 txp->tx_mbuf = NULL;
2580 txp->tx_cb->cb_status = 0;
2581 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2582 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2583 /*
2584 * Advance the end of list forward.
2585 */
2586 sc->fxp_desc.tx_last->tx_cb->cb_command &=
2587 htole16(~FXP_CB_COMMAND_S);
2588 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2589 sc->fxp_desc.tx_last = txp;
2590 sc->tx_queued++;
2591 /*
2592 * Issue a resume in case the CU has just suspended.
2593 */
2594 fxp_scb_wait(sc);
2595 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2596 /*
2597 * Set a 5 second timer just in case we don't hear from the
2598 * card again.
2599 */
2600 ifp->if_timer = 5;
2601
2602 return;
2603 }
2604 sc->need_mcsetup = 0;
2605
2606 /*
2607 * Initialize multicast setup descriptor.
2608 */
2609 mcsp->cb_status = 0;
2610 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2611 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2612 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2613 txp = &sc->fxp_desc.mcs_tx;
2614 txp->tx_mbuf = NULL;
2615 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2616 txp->tx_next = sc->fxp_desc.tx_list;
2617 (void) fxp_mc_addrs(sc);
2618 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2619 sc->tx_queued = 1;
2620
2621 /*
2622 * Wait until command unit is not active. This should never
2623 * be the case when nothing is queued, but make sure anyway.
2624 */
2625 count = 100;
2626 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2627 FXP_SCB_CUS_ACTIVE && --count)
2628 DELAY(10);
2629 if (count == 0) {
2630 device_printf(sc->dev, "command queue timeout\n");
2631 return;
2632 }
2633
2634 /*
2635 * Start the multicast setup command.
2636 */
2637 fxp_scb_wait(sc);
2638 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2639 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2640 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2641
2642 ifp->if_timer = 2;
2643 return;
2644}
2645
2646static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2647static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2648static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2649static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2650static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2651static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2652
2653#define UCODE(x) x, sizeof(x)
2654
2655struct ucode {
2656 u_int32_t revision;
2657 u_int32_t *ucode;
2658 int length;
2659 u_short int_delay_offset;
2660 u_short bundle_max_offset;
2661} ucode_table[] = {
2662 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2663 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2664 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2665 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2666 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2667 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2668 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2669 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2670 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2671 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2672 { 0, NULL, 0, 0, 0 }
2673};
2674
2675static void
2676fxp_load_ucode(struct fxp_softc *sc)
2677{
2678 struct ucode *uc;
2679 struct fxp_cb_ucode *cbp;
2680
2681 for (uc = ucode_table; uc->ucode != NULL; uc++)
2682 if (sc->revision == uc->revision)
2683 break;
2684 if (uc->ucode == NULL)
2685 return;
2686 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2687 cbp->cb_status = 0;
2688 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2689 cbp->link_addr = 0xffffffff; /* (no) next command */
2690 memcpy(cbp->ucode, uc->ucode, uc->length);
2691 if (uc->int_delay_offset)
2692 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] =
2693 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2694 if (uc->bundle_max_offset)
2695 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] =
2696 htole16(sc->tunable_bundle_max);
2697 /*
2698 * Download the ucode to the chip.
2699 */
2700 fxp_scb_wait(sc);
2701 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2702 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2703 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2704 /* ...and wait for it to complete. */
2705 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2706 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2707 device_printf(sc->dev,
2708 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2709 sc->tunable_int_delay,
2710 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2711 sc->flags |= FXP_FLAG_UCODE;
2712}
2713
2714static int
2715sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2716{
2717 int error, value;
2718
2719 value = *(int *)arg1;
2720 error = sysctl_handle_int(oidp, &value, 0, req);
2721 if (error || !req->newptr)
2722 return (error);
2723 if (value < low || value > high)
2724 return (EINVAL);
2725 *(int *)arg1 = value;
2726 return (0);
2727}
2728
2729/*
2730 * Interrupt delay is expressed in microseconds, a multiplier is used
2731 * to convert this to the appropriate clock ticks before using.
2732 */
2733static int
2734sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2735{
2736 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2737}
2738
2739static int
2740sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2741{
2742 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2743}
| 283DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
284
285static int fxp_rnr;
286SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
287
288static int fxp_noflow;
289SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled");
290TUNABLE_INT("hw.fxp_noflow", &fxp_noflow);
291
292/*
293 * Wait for the previous command to be accepted (but not necessarily
294 * completed).
295 */
296static void
297fxp_scb_wait(struct fxp_softc *sc)
298{
299 int i = 10000;
300
301 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
302 DELAY(2);
303 if (i == 0)
304 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
305 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
306 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
307 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
308 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
309}
310
311static void
312fxp_scb_cmd(struct fxp_softc *sc, int cmd)
313{
314
315 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
317 fxp_scb_wait(sc);
318 }
319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
320}
321
322static void
323fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status,
324 bus_dma_tag_t dmat, bus_dmamap_t map)
325{
326 int i = 10000;
327
328 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
329 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) {
330 DELAY(2);
331 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
332 }
333 if (i == 0)
334 device_printf(sc->dev, "DMA timeout\n");
335}
336
337/*
338 * Return identification string if this device is ours.
339 */
340static int
341fxp_probe(device_t dev)
342{
343 u_int16_t devid;
344 u_int8_t revid;
345 struct fxp_ident *ident;
346
347 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
348 devid = pci_get_device(dev);
349 revid = pci_get_revid(dev);
350 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
351 if (ident->devid == devid &&
352 (ident->revid == revid || ident->revid == -1)) {
353 device_set_desc(dev, ident->name);
354 return (0);
355 }
356 }
357 }
358 return (ENXIO);
359}
360
361#ifndef BURN_BRIDGES
362static void
363fxp_powerstate_d0(device_t dev)
364{
365#if __FreeBSD_version >= 430002
366 u_int32_t iobase, membase, irq;
367
368 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
369 /* Save important PCI config data. */
370 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
371 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
372 irq = pci_read_config(dev, PCIR_INTLINE, 4);
373
374 /* Reset the power state. */
375 device_printf(dev, "chip is in D%d power mode "
376 "-- setting to D0\n", pci_get_powerstate(dev));
377
378 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
379
380 /* Restore PCI config data. */
381 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
382 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
383 pci_write_config(dev, PCIR_INTLINE, irq, 4);
384 }
385#endif
386}
387#endif
388
389static void
390fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
391{
392 u_int32_t *addr;
393
394 if (error)
395 return;
396
397 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
398 addr = arg;
399 *addr = segs->ds_addr;
400}
401
402static int
403fxp_attach(device_t dev)
404{
405 int error = 0;
406 struct fxp_softc *sc = device_get_softc(dev);
407 struct ifnet *ifp;
408 struct fxp_rx *rxp;
409 u_int32_t val;
410 u_int16_t data, myea[ETHER_ADDR_LEN / 2];
411 int i, rid, m1, m2, prefer_iomap, maxtxseg;
412 int s, ipcbxmit_disable;
413
414 sc->dev = dev;
415 callout_init(&sc->stat_ch, CALLOUT_MPSAFE);
416 sysctl_ctx_init(&sc->sysctl_ctx);
417 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
418 MTX_DEF);
419 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
420 fxp_serial_ifmedia_sts);
421
422 s = splimp();
423
424 /*
425 * Enable bus mastering.
426 */
427 pci_enable_busmaster(dev);
428 val = pci_read_config(dev, PCIR_COMMAND, 2);
429#ifndef BURN_BRIDGES
430 fxp_powerstate_d0(dev);
431#endif
432 /*
433 * Figure out which we should try first - memory mapping or i/o mapping?
434 * We default to memory mapping. Then we accept an override from the
435 * command line. Then we check to see which one is enabled.
436 */
437 m1 = PCIM_CMD_MEMEN;
438 m2 = PCIM_CMD_PORTEN;
439 prefer_iomap = 0;
440 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
441 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
442 m1 = PCIM_CMD_PORTEN;
443 m2 = PCIM_CMD_MEMEN;
444 }
445
446 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
447 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
448 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
449 0, ~0, 1, RF_ACTIVE);
450 if (sc->mem == NULL) {
451 sc->rtp =
452 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
453 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
454 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
455 0, ~0, 1, RF_ACTIVE);
456 }
457
458 if (!sc->mem) {
459 error = ENXIO;
460 goto fail;
461 }
462 if (bootverbose) {
463 device_printf(dev, "using %s space register mapping\n",
464 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
465 }
466
467 sc->sc_st = rman_get_bustag(sc->mem);
468 sc->sc_sh = rman_get_bushandle(sc->mem);
469
470 /*
471 * Allocate our interrupt.
472 */
473 rid = 0;
474 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
475 RF_SHAREABLE | RF_ACTIVE);
476 if (sc->irq == NULL) {
477 device_printf(dev, "could not map interrupt\n");
478 error = ENXIO;
479 goto fail;
480 }
481
482 /*
483 * Reset to a stable state.
484 */
485 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
486 DELAY(10);
487
488 /*
489 * Find out how large of an SEEPROM we have.
490 */
491 fxp_autosize_eeprom(sc);
492
493 /*
494 * Determine whether we must use the 503 serial interface.
495 */
496 fxp_read_eeprom(sc, &data, 6, 1);
497 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
498 (data & FXP_PHY_SERIAL_ONLY))
499 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
500
501 /*
502 * Create the sysctl tree
503 */
504 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
505 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
506 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
507 if (sc->sysctl_tree == NULL) {
508 error = ENXIO;
509 goto fail;
510 }
511 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
512 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
513 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
514 "FXP driver receive interrupt microcode bundling delay");
515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
516 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
517 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
518 "FXP driver receive interrupt microcode bundle size limit");
519
520 /*
521 * Pull in device tunables.
522 */
523 sc->tunable_int_delay = TUNABLE_INT_DELAY;
524 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
525 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
526 "int_delay", &sc->tunable_int_delay);
527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
528 "bundle_max", &sc->tunable_bundle_max);
529
530 /*
531 * Find out the chip revision; lump all 82557 revs together.
532 */
533 fxp_read_eeprom(sc, &data, 5, 1);
534 if ((data >> 8) == 1)
535 sc->revision = FXP_REV_82557;
536 else
537 sc->revision = pci_get_revid(dev);
538
539 /*
540 * Enable workarounds for certain chip revision deficiencies.
541 *
542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
543 * some systems based a normal 82559 design, have a defect where
544 * the chip can cause a PCI protocol violation if it receives
545 * a CU_RESUME command when it is entering the IDLE state. The
546 * workaround is to disable Dynamic Standby Mode, so the chip never
547 * deasserts CLKRUN#, and always remains in an active state.
548 *
549 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
550 */
551 i = pci_get_device(dev);
552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
553 sc->revision >= FXP_REV_82559_A0) {
554 fxp_read_eeprom(sc, &data, 10, 1);
555 if (data & 0x02) { /* STB enable */
556 u_int16_t cksum;
557 int i;
558
559 device_printf(dev,
560 "Disabling dynamic standby mode in EEPROM\n");
561 data &= ~0x02;
562 fxp_write_eeprom(sc, &data, 10, 1);
563 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
564 cksum = 0;
565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
566 fxp_read_eeprom(sc, &data, i, 1);
567 cksum += data;
568 }
569 i = (1 << sc->eeprom_size) - 1;
570 cksum = 0xBABA - cksum;
571 fxp_read_eeprom(sc, &data, i, 1);
572 fxp_write_eeprom(sc, &cksum, i, 1);
573 device_printf(dev,
574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
575 i, data, cksum);
576#if 1
577 /*
578 * If the user elects to continue, try the software
579 * workaround, as it is better than nothing.
580 */
581 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
582#endif
583 }
584 }
585
586 /*
587 * If we are not a 82557 chip, we can enable extended features.
588 */
589 if (sc->revision != FXP_REV_82557) {
590 /*
591 * If MWI is enabled in the PCI configuration, and there
592 * is a valid cacheline size (8 or 16 dwords), then tell
593 * the board to turn on MWI.
594 */
595 if (val & PCIM_CMD_MWRICEN &&
596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
597 sc->flags |= FXP_FLAG_MWI_ENABLE;
598
599 /* turn on the extended TxCB feature */
600 sc->flags |= FXP_FLAG_EXT_TXCB;
601
602 /* enable reception of long frames for VLAN */
603 sc->flags |= FXP_FLAG_LONG_PKT_EN;
604 }
605
606 /*
607 * Enable use of extended RFDs and TCBs for 82550
608 * and later chips. Note: we need extended TXCB support
609 * too, but that's already enabled by the code above.
610 * Be careful to do this only on the right devices.
611 *
612 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d"
613 * truncate packets that end with an mbuf containing 1 to 3 bytes
614 * when used with this feature enabled in the previous version of the
615 * driver. This problem appears to be fixed now that the driver
616 * always sets the hardware parse bit in the IPCB structure, which
617 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open
618 * Source Software Developer Manual" says is necessary in the
619 * cases where packet truncation was observed.
620 *
621 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable"
622 * allows this feature to be disabled at boot time.
623 *
624 * If fxp is not compiled into the kernel, this feature may also
625 * be disabled at run time:
626 * # kldunload fxp
627 * # kenv hint.fxp.0.ipcbxmit_disable=1
628 * # kldload fxp
629 */
630
631 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable",
632 &ipcbxmit_disable) != 0)
633 ipcbxmit_disable = 0;
634 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 ||
635 sc->revision == FXP_REV_82550_C)) {
636 sc->rfa_size = sizeof (struct fxp_rfa);
637 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
638 sc->flags |= FXP_FLAG_EXT_RFA;
639 } else {
640 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
641 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
642 }
643
644 /*
645 * Allocate DMA tags and DMA safe memory.
646 */
647 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG;
648 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT,
649 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg,
650 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag);
651 if (error) {
652 device_printf(dev, "could not allocate dma tag\n");
653 goto fail;
654 }
655
656 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
657 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1,
658 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant,
659 &sc->fxp_stag);
660 if (error) {
661 device_printf(dev, "could not allocate dma tag\n");
662 goto fail;
663 }
664
665 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
666 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
667 if (error)
668 goto fail;
669 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
670 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
671 if (error) {
672 device_printf(dev, "could not map the stats buffer\n");
673 goto fail;
674 }
675
676 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
677 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1,
678 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag);
679 if (error) {
680 device_printf(dev, "could not allocate dma tag\n");
681 goto fail;
682 }
683
684 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
685 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
686 if (error)
687 goto fail;
688
689 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
690 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
691 &sc->fxp_desc.cbl_addr, 0);
692 if (error) {
693 device_printf(dev, "could not map DMA memory\n");
694 goto fail;
695 }
696
697 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
698 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1,
699 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant,
700 &sc->mcs_tag);
701 if (error) {
702 device_printf(dev, "could not allocate dma tag\n");
703 goto fail;
704 }
705
706 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
707 BUS_DMA_NOWAIT, &sc->mcs_map);
708 if (error)
709 goto fail;
710 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
711 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
712 if (error) {
713 device_printf(dev, "can't map the multicast setup command\n");
714 goto fail;
715 }
716
717 /*
718 * Pre-allocate the TX DMA maps.
719 */
720 for (i = 0; i < FXP_NTXCB; i++) {
721 error = bus_dmamap_create(sc->fxp_mtag, 0,
722 &sc->fxp_desc.tx_list[i].tx_map);
723 if (error) {
724 device_printf(dev, "can't create DMA map for TX\n");
725 goto fail;
726 }
727 }
728 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
729 if (error) {
730 device_printf(dev, "can't create spare DMA map\n");
731 goto fail;
732 }
733
734 /*
735 * Pre-allocate our receive buffers.
736 */
737 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
738 for (i = 0; i < FXP_NRFABUFS; i++) {
739 rxp = &sc->fxp_desc.rx_list[i];
740 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
741 if (error) {
742 device_printf(dev, "can't create DMA map for RX\n");
743 goto fail;
744 }
745 if (fxp_add_rfabuf(sc, rxp) != 0) {
746 error = ENOMEM;
747 goto fail;
748 }
749 }
750
751 /*
752 * Read MAC address.
753 */
754 fxp_read_eeprom(sc, myea, 0, 3);
755 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff;
756 sc->arpcom.ac_enaddr[1] = myea[0] >> 8;
757 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff;
758 sc->arpcom.ac_enaddr[3] = myea[1] >> 8;
759 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff;
760 sc->arpcom.ac_enaddr[5] = myea[2] >> 8;
761 device_printf(dev, "Ethernet address %6D%s\n",
762 sc->arpcom.ac_enaddr, ":",
763 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
764 if (bootverbose) {
765 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
766 pci_get_vendor(dev), pci_get_device(dev),
767 pci_get_subvendor(dev), pci_get_subdevice(dev),
768 pci_get_revid(dev));
769 fxp_read_eeprom(sc, &data, 10, 1);
770 device_printf(dev, "Dynamic Standby mode is %s\n",
771 data & 0x02 ? "enabled" : "disabled");
772 }
773
774 /*
775 * If this is only a 10Mbps device, then there is no MII, and
776 * the PHY will use a serial interface instead.
777 *
778 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
779 * doesn't have a programming interface of any sort. The
780 * media is sensed automatically based on how the link partner
781 * is configured. This is, in essence, manual configuration.
782 */
783 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
784 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
785 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
786 } else {
787 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
788 fxp_ifmedia_sts)) {
789 device_printf(dev, "MII without any PHY!\n");
790 error = ENXIO;
791 goto fail;
792 }
793 }
794
795 ifp = &sc->arpcom.ac_if;
796 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
797 ifp->if_output = ether_output;
798 ifp->if_baudrate = 100000000;
799 ifp->if_init = fxp_init;
800 ifp->if_softc = sc;
801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
802 ifp->if_ioctl = fxp_ioctl;
803 ifp->if_start = fxp_start;
804 ifp->if_watchdog = fxp_watchdog;
805
806 /* Enable checksum offload for 82550 or better chips */
807 if (sc->flags & FXP_FLAG_EXT_RFA) {
808 ifp->if_hwassist = FXP_CSUM_FEATURES;
809 ifp->if_capabilities = IFCAP_HWCSUM;
810 ifp->if_capenable = ifp->if_capabilities;
811 }
812
813 /*
814 * Attach the interface.
815 */
816 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
817
818 /*
819 * Tell the upper layer(s) we support long frames.
820 */
821 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
822 ifp->if_capabilities |= IFCAP_VLAN_MTU;
823
824 /*
825 * Let the system queue as many packets as we have available
826 * TX descriptors.
827 */
828 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
829
830 /*
831 * Hook our interrupt after all initialization is complete.
832 * XXX This driver has been tested with the INTR_MPSAFFE flag set
833 * however, ifp and its functions are not fully locked so MPSAFE
834 * should not be used unless you can handle potential data loss.
835 */
836 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
837 fxp_intr, sc, &sc->ih);
838 if (error) {
839 device_printf(dev, "could not setup irq\n");
840 ether_ifdetach(&sc->arpcom.ac_if);
841 goto fail;
842 }
843
844fail:
845 splx(s);
846 if (error)
847 fxp_release(sc);
848 return (error);
849}
850
851/*
852 * Release all resources. The softc lock should not be held and the
853 * interrupt should already be torn down.
854 */
855static void
856fxp_release(struct fxp_softc *sc)
857{
858 struct fxp_rx *rxp;
859 struct fxp_tx *txp;
860 int i;
861
862 mtx_assert(&sc->sc_mtx, MA_NOTOWNED);
863 if (sc->ih)
864 panic("fxp_release() called with intr handle still active");
865 if (sc->miibus)
866 device_delete_child(sc->dev, sc->miibus);
867 bus_generic_detach(sc->dev);
868 ifmedia_removeall(&sc->sc_media);
869 if (sc->fxp_desc.cbl_list) {
870 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
871 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
872 sc->cbl_map);
873 }
874 if (sc->fxp_stats) {
875 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
876 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
877 }
878 if (sc->mcsp) {
879 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
880 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
881 }
882 if (sc->irq)
883 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
884 if (sc->mem)
885 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
886 if (sc->fxp_mtag) {
887 for (i = 0; i < FXP_NRFABUFS; i++) {
888 rxp = &sc->fxp_desc.rx_list[i];
889 if (rxp->rx_mbuf != NULL) {
890 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
891 BUS_DMASYNC_POSTREAD);
892 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
893 m_freem(rxp->rx_mbuf);
894 }
895 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
896 }
897 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
898 bus_dma_tag_destroy(sc->fxp_mtag);
899 }
900 if (sc->fxp_stag) {
901 for (i = 0; i < FXP_NTXCB; i++) {
902 txp = &sc->fxp_desc.tx_list[i];
903 if (txp->tx_mbuf != NULL) {
904 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
905 BUS_DMASYNC_POSTWRITE);
906 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
907 m_freem(txp->tx_mbuf);
908 }
909 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
910 }
911 bus_dma_tag_destroy(sc->fxp_stag);
912 }
913 if (sc->cbl_tag)
914 bus_dma_tag_destroy(sc->cbl_tag);
915 if (sc->mcs_tag)
916 bus_dma_tag_destroy(sc->mcs_tag);
917
918 sysctl_ctx_free(&sc->sysctl_ctx);
919
920 mtx_destroy(&sc->sc_mtx);
921}
922
923/*
924 * Detach interface.
925 */
926static int
927fxp_detach(device_t dev)
928{
929 struct fxp_softc *sc = device_get_softc(dev);
930 int s;
931
932 FXP_LOCK(sc);
933 s = splimp();
934
935 sc->suspended = 1; /* Do same thing as we do for suspend */
936 /*
937 * Close down routes etc.
938 */
939 ether_ifdetach(&sc->arpcom.ac_if);
940
941 /*
942 * Stop DMA and drop transmit queue, but disable interrupts first.
943 */
944 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
945 fxp_stop(sc);
946 FXP_UNLOCK(sc);
947
948 /*
949 * Unhook interrupt before dropping lock. This is to prevent
950 * races with fxp_intr().
951 */
952 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
953 sc->ih = NULL;
954
955 splx(s);
956
957 /* Release our allocated resources. */
958 fxp_release(sc);
959 return (0);
960}
961
962/*
963 * Device shutdown routine. Called at system shutdown after sync. The
964 * main purpose of this routine is to shut off receiver DMA so that
965 * kernel memory doesn't get clobbered during warmboot.
966 */
967static int
968fxp_shutdown(device_t dev)
969{
970 /*
971 * Make sure that DMA is disabled prior to reboot. Not doing
972 * do could allow DMA to corrupt kernel memory during the
973 * reboot before the driver initializes.
974 */
975 fxp_stop((struct fxp_softc *) device_get_softc(dev));
976 return (0);
977}
978
979/*
980 * Device suspend routine. Stop the interface and save some PCI
981 * settings in case the BIOS doesn't restore them properly on
982 * resume.
983 */
984static int
985fxp_suspend(device_t dev)
986{
987 struct fxp_softc *sc = device_get_softc(dev);
988 int i, s;
989
990 FXP_LOCK(sc);
991 s = splimp();
992
993 fxp_stop(sc);
994
995 for (i = 0; i < 5; i++)
996 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
997 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
998 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
999 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1000 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1001
1002 sc->suspended = 1;
1003
1004 FXP_UNLOCK(sc);
1005 splx(s);
1006 return (0);
1007}
1008
1009/*
1010 * Device resume routine. Restore some PCI settings in case the BIOS
1011 * doesn't, re-enable busmastering, and restart the interface if
1012 * appropriate.
1013 */
1014static int
1015fxp_resume(device_t dev)
1016{
1017 struct fxp_softc *sc = device_get_softc(dev);
1018 struct ifnet *ifp = &sc->sc_if;
1019 u_int16_t pci_command;
1020 int i, s;
1021
1022 FXP_LOCK(sc);
1023 s = splimp();
1024#ifndef BURN_BRIDGES
1025 fxp_powerstate_d0(dev);
1026#endif
1027 /* better way to do this? */
1028 for (i = 0; i < 5; i++)
1029 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1030 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1031 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1032 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1033 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1034
1035 /* reenable busmastering */
1036 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
1037 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1038 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
1039
1040 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1041 DELAY(10);
1042
1043 /* reinitialize interface if necessary */
1044 if (ifp->if_flags & IFF_UP)
1045 fxp_init_body(sc);
1046
1047 sc->suspended = 0;
1048
1049 FXP_UNLOCK(sc);
1050 splx(s);
1051 return (0);
1052}
1053
1054static void
1055fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1056{
1057 u_int16_t reg;
1058 int x;
1059
1060 /*
1061 * Shift in data.
1062 */
1063 for (x = 1 << (length - 1); x; x >>= 1) {
1064 if (data & x)
1065 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1066 else
1067 reg = FXP_EEPROM_EECS;
1068 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1069 DELAY(1);
1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1071 DELAY(1);
1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1073 DELAY(1);
1074 }
1075}
1076
1077/*
1078 * Read from the serial EEPROM. Basically, you manually shift in
1079 * the read opcode (one bit at a time) and then shift in the address,
1080 * and then you shift out the data (all of this one bit at a time).
1081 * The word size is 16 bits, so you have to provide the address for
1082 * every 16 bits of data.
1083 */
1084static u_int16_t
1085fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1086{
1087 u_int16_t reg, data;
1088 int x;
1089
1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1091 /*
1092 * Shift in read opcode.
1093 */
1094 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1095 /*
1096 * Shift in address.
1097 */
1098 data = 0;
1099 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1100 if (offset & x)
1101 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1102 else
1103 reg = FXP_EEPROM_EECS;
1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1105 DELAY(1);
1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1107 DELAY(1);
1108 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1109 DELAY(1);
1110 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1111 data++;
1112 if (autosize && reg == 0) {
1113 sc->eeprom_size = data;
1114 break;
1115 }
1116 }
1117 /*
1118 * Shift out data.
1119 */
1120 data = 0;
1121 reg = FXP_EEPROM_EECS;
1122 for (x = 1 << 15; x; x >>= 1) {
1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1124 DELAY(1);
1125 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1126 data |= x;
1127 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1128 DELAY(1);
1129 }
1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1131 DELAY(1);
1132
1133 return (data);
1134}
1135
1136static void
1137fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1138{
1139 int i;
1140
1141 /*
1142 * Erase/write enable.
1143 */
1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1145 fxp_eeprom_shiftin(sc, 0x4, 3);
1146 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1148 DELAY(1);
1149 /*
1150 * Shift in write opcode, address, data.
1151 */
1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1153 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1154 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1155 fxp_eeprom_shiftin(sc, data, 16);
1156 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1157 DELAY(1);
1158 /*
1159 * Wait for EEPROM to finish up.
1160 */
1161 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1162 DELAY(1);
1163 for (i = 0; i < 1000; i++) {
1164 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1165 break;
1166 DELAY(50);
1167 }
1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1169 DELAY(1);
1170 /*
1171 * Erase/write disable.
1172 */
1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1174 fxp_eeprom_shiftin(sc, 0x4, 3);
1175 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1177 DELAY(1);
1178}
1179
1180/*
1181 * From NetBSD:
1182 *
1183 * Figure out EEPROM size.
1184 *
1185 * 559's can have either 64-word or 256-word EEPROMs, the 558
1186 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1187 * talks about the existance of 16 to 256 word EEPROMs.
1188 *
1189 * The only known sizes are 64 and 256, where the 256 version is used
1190 * by CardBus cards to store CIS information.
1191 *
1192 * The address is shifted in msb-to-lsb, and after the last
1193 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1194 * after which follows the actual data. We try to detect this zero, by
1195 * probing the data-out bit in the EEPROM control register just after
1196 * having shifted in a bit. If the bit is zero, we assume we've
1197 * shifted enough address bits. The data-out should be tri-state,
1198 * before this, which should translate to a logical one.
1199 */
1200static void
1201fxp_autosize_eeprom(struct fxp_softc *sc)
1202{
1203
1204 /* guess maximum size of 256 words */
1205 sc->eeprom_size = 8;
1206
1207 /* autosize */
1208 (void) fxp_eeprom_getword(sc, 0, 1);
1209}
1210
1211static void
1212fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1213{
1214 int i;
1215
1216 for (i = 0; i < words; i++)
1217 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1218}
1219
1220static void
1221fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1222{
1223 int i;
1224
1225 for (i = 0; i < words; i++)
1226 fxp_eeprom_putword(sc, offset + i, data[i]);
1227}
1228
1229static void
1230fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
1231 bus_size_t mapsize, int error)
1232{
1233 struct fxp_softc *sc;
1234 struct fxp_cb_tx *txp;
1235 int i;
1236
1237 if (error)
1238 return;
1239
1240 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments"));
1241
1242 sc = arg;
1243 txp = sc->fxp_desc.tx_last->tx_next->tx_cb;
1244 for (i = 0; i < nseg; i++) {
1245 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
1246 /*
1247 * If this is an 82550/82551, then we're using extended
1248 * TxCBs _and_ we're using checksum offload. This means
1249 * that the TxCB is really an IPCB. One major difference
1250 * between the two is that with plain extended TxCBs,
1251 * the bottom half of the TxCB contains two entries from
1252 * the TBD array, whereas IPCBs contain just one entry:
1253 * one entry (8 bytes) has been sacrificed for the TCP/IP
1254 * checksum offload control bits. So to make things work
1255 * right, we have to start filling in the TBD array
1256 * starting from a different place depending on whether
1257 * the chip is an 82550/82551 or not.
1258 */
1259 if (sc->flags & FXP_FLAG_EXT_RFA) {
1260 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1261 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1262 } else {
1263 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1264 txp->tbd[i].tb_size = htole32(segs[i].ds_len);
1265 }
1266 }
1267 txp->tbd_number = nseg;
1268}
1269
1270/*
1271 * Grab the softc lock and call the real fxp_start_body() routine
1272 */
1273static void
1274fxp_start(struct ifnet *ifp)
1275{
1276 struct fxp_softc *sc = ifp->if_softc;
1277
1278 FXP_LOCK(sc);
1279 fxp_start_body(ifp);
1280 FXP_UNLOCK(sc);
1281}
1282
1283/*
1284 * Start packet transmission on the interface.
1285 * This routine must be called with the softc lock held, and is an
1286 * internal entry point only.
1287 */
1288static void
1289fxp_start_body(struct ifnet *ifp)
1290{
1291 struct fxp_softc *sc = ifp->if_softc;
1292 struct fxp_tx *txp;
1293 struct mbuf *mb_head;
1294 int error;
1295
1296 mtx_assert(&sc->sc_mtx, MA_OWNED);
1297 /*
1298 * See if we need to suspend xmit until the multicast filter
1299 * has been reprogrammed (which can only be done at the head
1300 * of the command chain).
1301 */
1302 if (sc->need_mcsetup) {
1303 return;
1304 }
1305
1306 txp = NULL;
1307
1308 /*
1309 * We're finished if there is nothing more to add to the list or if
1310 * we're all filled up with buffers to transmit.
1311 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1312 * a NOP command when needed.
1313 */
1314 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1315
1316 /*
1317 * Grab a packet to transmit.
1318 */
1319 IF_DEQUEUE(&ifp->if_snd, mb_head);
1320
1321 /*
1322 * Get pointer to next available tx desc.
1323 */
1324 txp = sc->fxp_desc.tx_last->tx_next;
1325
1326 /*
1327 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1328 * Ethernet Controller Family Open Source Software
1329 * Developer Manual says:
1330 * Using software parsing is only allowed with legal
1331 * TCP/IP or UDP/IP packets.
1332 * ...
1333 * For all other datagrams, hardware parsing must
1334 * be used.
1335 * Software parsing appears to truncate ICMP and
1336 * fragmented UDP packets that contain one to three
1337 * bytes in the second (and final) mbuf of the packet.
1338 */
1339 if (sc->flags & FXP_FLAG_EXT_RFA)
1340 txp->tx_cb->ipcb_ip_activation_high =
1341 FXP_IPCB_HARDWAREPARSING_ENABLE;
1342
1343 /*
1344 * Deal with TCP/IP checksum offload. Note that
1345 * in order for TCP checksum offload to work,
1346 * the pseudo header checksum must have already
1347 * been computed and stored in the checksum field
1348 * in the TCP header. The stack should have
1349 * already done this for us.
1350 */
1351
1352 if (mb_head->m_pkthdr.csum_flags) {
1353 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1354 txp->tx_cb->ipcb_ip_schedule =
1355 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1356 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP)
1357 txp->tx_cb->ipcb_ip_schedule |=
1358 FXP_IPCB_TCP_PACKET;
1359 }
1360#ifdef FXP_IP_CSUM_WAR
1361 /*
1362 * XXX The 82550 chip appears to have trouble
1363 * dealing with IP header checksums in very small
1364 * datagrams, namely fragments from 1 to 3 bytes
1365 * in size. For example, say you want to transmit
1366 * a UDP packet of 1473 bytes. The packet will be
1367 * fragmented over two IP datagrams, the latter
1368 * containing only one byte of data. The 82550 will
1369 * botch the header checksum on the 1-byte fragment.
1370 * As long as the datagram contains 4 or more bytes
1371 * of data, you're ok.
1372 *
1373 * The following code attempts to work around this
1374 * problem: if the datagram is less than 38 bytes
1375 * in size (14 bytes ether header, 20 bytes IP header,
1376 * plus 4 bytes of data), we punt and compute the IP
1377 * header checksum by hand. This workaround doesn't
1378 * work very well, however, since it can be fooled
1379 * by things like VLAN tags and IP options that make
1380 * the header sizes/offsets vary.
1381 */
1382
1383 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) {
1384 if (mb_head->m_pkthdr.len < 38) {
1385 struct ip *ip;
1386 mb_head->m_data += ETHER_HDR_LEN;
1387 ip = mtod(mb_head, struct ip *);
1388 ip->ip_sum = in_cksum(mb_head,
1389 ip->ip_hl << 2);
1390 mb_head->m_data -= ETHER_HDR_LEN;
1391 } else {
1392 txp->tx_cb->ipcb_ip_activation_high =
1393 FXP_IPCB_HARDWAREPARSING_ENABLE;
1394 txp->tx_cb->ipcb_ip_schedule |=
1395 FXP_IPCB_IP_CHECKSUM_ENABLE;
1396 }
1397 }
1398#endif
1399 }
1400
1401 /*
1402 * Go through each of the mbufs in the chain and initialize
1403 * the transmit buffer descriptors with the physical address
1404 * and size of the mbuf.
1405 */
1406 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1407 mb_head, fxp_dma_map_txbuf, sc, 0);
1408
1409 if (error && error != EFBIG) {
1410 device_printf(sc->dev, "can't map mbuf (error %d)\n",
1411 error);
1412 m_freem(mb_head);
1413 break;
1414 }
1415
1416 if (error) {
1417 struct mbuf *mn;
1418
1419 /*
1420 * We ran out of segments. We have to recopy this
1421 * mbuf chain first. Bail out if we can't get the
1422 * new buffers.
1423 */
1424 mn = m_defrag(mb_head, M_DONTWAIT);
1425 if (mn == NULL) {
1426 m_freem(mb_head);
1427 break;
1428 } else {
1429 mb_head = mn;
1430 }
1431 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1432 mb_head, fxp_dma_map_txbuf, sc, 0);
1433 if (error) {
1434 device_printf(sc->dev,
1435 "can't map mbuf (error %d)\n", error);
1436 m_freem(mb_head);
1437 break;
1438 }
1439 }
1440
1441 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1442 BUS_DMASYNC_PREWRITE);
1443
1444 txp->tx_mbuf = mb_head;
1445 txp->tx_cb->cb_status = 0;
1446 txp->tx_cb->byte_count = 0;
1447 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1448 txp->tx_cb->cb_command =
1449 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1450 FXP_CB_COMMAND_S);
1451 } else {
1452 txp->tx_cb->cb_command =
1453 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1454 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1455 /*
1456 * Set a 5 second timer just in case we don't hear
1457 * from the card again.
1458 */
1459 ifp->if_timer = 5;
1460 }
1461 txp->tx_cb->tx_threshold = tx_threshold;
1462
1463 /*
1464 * Advance the end of list forward.
1465 */
1466
1467#ifdef __alpha__
1468 /*
1469 * On platforms which can't access memory in 16-bit
1470 * granularities, we must prevent the card from DMA'ing
1471 * up the status while we update the command field.
1472 * This could cause us to overwrite the completion status.
1473 * XXX This is probably bogus and we're _not_ looking
1474 * for atomicity here.
1475 */
1476 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1477 htole16(FXP_CB_COMMAND_S));
1478#else
1479 sc->fxp_desc.tx_last->tx_cb->cb_command &=
1480 htole16(~FXP_CB_COMMAND_S);
1481#endif /*__alpha__*/
1482 sc->fxp_desc.tx_last = txp;
1483
1484 /*
1485 * Advance the beginning of the list forward if there are
1486 * no other packets queued (when nothing is queued, tx_first
1487 * sits on the last TxCB that was sent out).
1488 */
1489 if (sc->tx_queued == 0)
1490 sc->fxp_desc.tx_first = txp;
1491
1492 sc->tx_queued++;
1493
1494 /*
1495 * Pass packet to bpf if there is a listener.
1496 */
1497 BPF_MTAP(ifp, mb_head);
1498 }
1499 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1500
1501 /*
1502 * We're finished. If we added to the list, issue a RESUME to get DMA
1503 * going again if suspended.
1504 */
1505 if (txp != NULL) {
1506 fxp_scb_wait(sc);
1507 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1508 }
1509}
1510
1511#ifdef DEVICE_POLLING
1512static poll_handler_t fxp_poll;
1513
1514static void
1515fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1516{
1517 struct fxp_softc *sc = ifp->if_softc;
1518 u_int8_t statack;
1519
1520 FXP_LOCK(sc);
1521 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1522 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1523 FXP_UNLOCK(sc);
1524 return;
1525 }
1526 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1527 FXP_SCB_STATACK_FR;
1528 if (cmd == POLL_AND_CHECK_STATUS) {
1529 u_int8_t tmp;
1530
1531 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1532 if (tmp == 0xff || tmp == 0) {
1533 FXP_UNLOCK(sc);
1534 return; /* nothing to do */
1535 }
1536 tmp &= ~statack;
1537 /* ack what we can */
1538 if (tmp != 0)
1539 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1540 statack |= tmp;
1541 }
1542 fxp_intr_body(sc, ifp, statack, count);
1543 FXP_UNLOCK(sc);
1544}
1545#endif /* DEVICE_POLLING */
1546
1547/*
1548 * Process interface interrupts.
1549 */
1550static void
1551fxp_intr(void *xsc)
1552{
1553 struct fxp_softc *sc = xsc;
1554 struct ifnet *ifp = &sc->sc_if;
1555 u_int8_t statack;
1556
1557 FXP_LOCK(sc);
1558 if (sc->suspended) {
1559 FXP_UNLOCK(sc);
1560 return;
1561 }
1562
1563#ifdef DEVICE_POLLING
1564 if (ifp->if_flags & IFF_POLLING) {
1565 FXP_UNLOCK(sc);
1566 return;
1567 }
1568 if (ether_poll_register(fxp_poll, ifp)) {
1569 /* disable interrupts */
1570 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1571 FXP_UNLOCK(sc);
1572 fxp_poll(ifp, 0, 1);
1573 return;
1574 }
1575#endif
1576 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1577 /*
1578 * It should not be possible to have all bits set; the
1579 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1580 * all bits are set, this may indicate that the card has
1581 * been physically ejected, so ignore it.
1582 */
1583 if (statack == 0xff) {
1584 FXP_UNLOCK(sc);
1585 return;
1586 }
1587
1588 /*
1589 * First ACK all the interrupts in this pass.
1590 */
1591 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1592 fxp_intr_body(sc, ifp, statack, -1);
1593 }
1594 FXP_UNLOCK(sc);
1595}
1596
1597static void
1598fxp_txeof(struct fxp_softc *sc)
1599{
1600 struct fxp_tx *txp;
1601
1602 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1603 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1604 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1605 txp = txp->tx_next) {
1606 if (txp->tx_mbuf != NULL) {
1607 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1608 BUS_DMASYNC_POSTWRITE);
1609 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1610 m_freem(txp->tx_mbuf);
1611 txp->tx_mbuf = NULL;
1612 /* clear this to reset csum offload bits */
1613 txp->tx_cb->tbd[0].tb_addr = 0;
1614 }
1615 sc->tx_queued--;
1616 }
1617 sc->fxp_desc.tx_first = txp;
1618 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1619}
1620
1621static void
1622fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack,
1623 int count)
1624{
1625 struct mbuf *m;
1626 struct fxp_rx *rxp;
1627 struct fxp_rfa *rfa;
1628 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1629
1630 mtx_assert(&sc->sc_mtx, MA_OWNED);
1631 if (rnr)
1632 fxp_rnr++;
1633#ifdef DEVICE_POLLING
1634 /* Pick up a deferred RNR condition if `count' ran out last time. */
1635 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1636 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1637 rnr = 1;
1638 }
1639#endif
1640
1641 /*
1642 * Free any finished transmit mbuf chains.
1643 *
1644 * Handle the CNA event likt a CXTNO event. It used to
1645 * be that this event (control unit not ready) was not
1646 * encountered, but it is now with the SMPng modifications.
1647 * The exact sequence of events that occur when the interface
1648 * is brought up are different now, and if this event
1649 * goes unhandled, the configuration/rxfilter setup sequence
1650 * can stall for several seconds. The result is that no
1651 * packets go out onto the wire for about 5 to 10 seconds
1652 * after the interface is ifconfig'ed for the first time.
1653 */
1654 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1655 fxp_txeof(sc);
1656
1657 ifp->if_timer = 0;
1658 if (sc->tx_queued == 0) {
1659 if (sc->need_mcsetup)
1660 fxp_mc_setup(sc);
1661 }
1662 /*
1663 * Try to start more packets transmitting.
1664 */
1665 if (ifp->if_snd.ifq_head != NULL)
1666 fxp_start_body(ifp);
1667 }
1668
1669 /*
1670 * Just return if nothing happened on the receive side.
1671 */
1672 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1673 return;
1674
1675 /*
1676 * Process receiver interrupts. If a no-resource (RNR)
1677 * condition exists, get whatever packets we can and
1678 * re-start the receiver.
1679 *
1680 * When using polling, we do not process the list to completion,
1681 * so when we get an RNR interrupt we must defer the restart
1682 * until we hit the last buffer with the C bit set.
1683 * If we run out of cycles and rfa_headm has the C bit set,
1684 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1685 * that the info will be used in the subsequent polling cycle.
1686 */
1687 for (;;) {
1688 rxp = sc->fxp_desc.rx_head;
1689 m = rxp->rx_mbuf;
1690 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1691 RFA_ALIGNMENT_FUDGE);
1692 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1693 BUS_DMASYNC_POSTREAD);
1694
1695#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1696 if (count >= 0 && count-- == 0) {
1697 if (rnr) {
1698 /* Defer RNR processing until the next time. */
1699 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1700 rnr = 0;
1701 }
1702 break;
1703 }
1704#endif /* DEVICE_POLLING */
1705
1706 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0)
1707 break;
1708
1709 /*
1710 * Advance head forward.
1711 */
1712 sc->fxp_desc.rx_head = rxp->rx_next;
1713
1714 /*
1715 * Add a new buffer to the receive chain.
1716 * If this fails, the old buffer is recycled
1717 * instead.
1718 */
1719 if (fxp_add_rfabuf(sc, rxp) == 0) {
1720 int total_len;
1721
1722 /*
1723 * Fetch packet length (the top 2 bits of
1724 * actual_size are flags set by the controller
1725 * upon completion), and drop the packet in case
1726 * of bogus length or CRC errors.
1727 */
1728 total_len = le16toh(rfa->actual_size) & 0x3fff;
1729 if (total_len < sizeof(struct ether_header) ||
1730 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1731 sc->rfa_size ||
1732 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) {
1733 m_freem(m);
1734 continue;
1735 }
1736
1737 /* Do IP checksum checking. */
1738 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) {
1739 if (rfa->rfax_csum_sts &
1740 FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1741 m->m_pkthdr.csum_flags |=
1742 CSUM_IP_CHECKED;
1743 if (rfa->rfax_csum_sts &
1744 FXP_RFDX_CS_IP_CSUM_VALID)
1745 m->m_pkthdr.csum_flags |=
1746 CSUM_IP_VALID;
1747 if ((rfa->rfax_csum_sts &
1748 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1749 (rfa->rfax_csum_sts &
1750 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1751 m->m_pkthdr.csum_flags |=
1752 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1753 m->m_pkthdr.csum_data = 0xffff;
1754 }
1755 }
1756
1757 m->m_pkthdr.len = m->m_len = total_len;
1758 m->m_pkthdr.rcvif = ifp;
1759
1760 /*
1761 * Drop locks before calling if_input() since it
1762 * may re-enter fxp_start() in the netisr case.
1763 * This would result in a lock reversal. Better
1764 * performance might be obtained by chaining all
1765 * packets received, dropping the lock, and then
1766 * calling if_input() on each one.
1767 */
1768 FXP_UNLOCK(sc);
1769 (*ifp->if_input)(ifp, m);
1770 FXP_LOCK(sc);
1771 }
1772 }
1773 if (rnr) {
1774 fxp_scb_wait(sc);
1775 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1776 sc->fxp_desc.rx_head->rx_addr);
1777 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1778 }
1779}
1780
1781/*
1782 * Update packet in/out/collision statistics. The i82557 doesn't
1783 * allow you to access these counters without doing a fairly
1784 * expensive DMA to get _all_ of the statistics it maintains, so
1785 * we do this operation here only once per second. The statistics
1786 * counters in the kernel are updated from the previous dump-stats
1787 * DMA and then a new dump-stats DMA is started. The on-chip
1788 * counters are zeroed when the DMA completes. If we can't start
1789 * the DMA immediately, we don't wait - we just prepare to read
1790 * them again next time.
1791 */
1792static void
1793fxp_tick(void *xsc)
1794{
1795 struct fxp_softc *sc = xsc;
1796 struct ifnet *ifp = &sc->sc_if;
1797 struct fxp_stats *sp = sc->fxp_stats;
1798 int s;
1799
1800 FXP_LOCK(sc);
1801 s = splimp();
1802 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1803 ifp->if_opackets += le32toh(sp->tx_good);
1804 ifp->if_collisions += le32toh(sp->tx_total_collisions);
1805 if (sp->rx_good) {
1806 ifp->if_ipackets += le32toh(sp->rx_good);
1807 sc->rx_idle_secs = 0;
1808 } else {
1809 /*
1810 * Receiver's been idle for another second.
1811 */
1812 sc->rx_idle_secs++;
1813 }
1814 ifp->if_ierrors +=
1815 le32toh(sp->rx_crc_errors) +
1816 le32toh(sp->rx_alignment_errors) +
1817 le32toh(sp->rx_rnr_errors) +
1818 le32toh(sp->rx_overrun_errors);
1819 /*
1820 * If any transmit underruns occured, bump up the transmit
1821 * threshold by another 512 bytes (64 * 8).
1822 */
1823 if (sp->tx_underruns) {
1824 ifp->if_oerrors += le32toh(sp->tx_underruns);
1825 if (tx_threshold < 192)
1826 tx_threshold += 64;
1827 }
1828
1829 /*
1830 * Release any xmit buffers that have completed DMA. This isn't
1831 * strictly necessary to do here, but it's advantagous for mbufs
1832 * with external storage to be released in a timely manner rather
1833 * than being defered for a potentially long time. This limits
1834 * the delay to a maximum of one second.
1835 */
1836 fxp_txeof(sc);
1837
1838 /*
1839 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1840 * then assume the receiver has locked up and attempt to clear
1841 * the condition by reprogramming the multicast filter. This is
1842 * a work-around for a bug in the 82557 where the receiver locks
1843 * up if it gets certain types of garbage in the syncronization
1844 * bits prior to the packet header. This bug is supposed to only
1845 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1846 * mode as well (perhaps due to a 10/100 speed transition).
1847 */
1848 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1849 sc->rx_idle_secs = 0;
1850 fxp_mc_setup(sc);
1851 }
1852 /*
1853 * If there is no pending command, start another stats
1854 * dump. Otherwise punt for now.
1855 */
1856 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1857 /*
1858 * Start another stats dump.
1859 */
1860 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
1861 BUS_DMASYNC_PREREAD);
1862 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1863 } else {
1864 /*
1865 * A previous command is still waiting to be accepted.
1866 * Just zero our copy of the stats and wait for the
1867 * next timer event to update them.
1868 */
1869 sp->tx_good = 0;
1870 sp->tx_underruns = 0;
1871 sp->tx_total_collisions = 0;
1872
1873 sp->rx_good = 0;
1874 sp->rx_crc_errors = 0;
1875 sp->rx_alignment_errors = 0;
1876 sp->rx_rnr_errors = 0;
1877 sp->rx_overrun_errors = 0;
1878 }
1879 if (sc->miibus != NULL)
1880 mii_tick(device_get_softc(sc->miibus));
1881
1882 /*
1883 * Schedule another timeout one second from now.
1884 */
1885 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
1886 FXP_UNLOCK(sc);
1887 splx(s);
1888}
1889
1890/*
1891 * Stop the interface. Cancels the statistics updater and resets
1892 * the interface.
1893 */
1894static void
1895fxp_stop(struct fxp_softc *sc)
1896{
1897 struct ifnet *ifp = &sc->sc_if;
1898 struct fxp_tx *txp;
1899 int i;
1900
1901 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1902 ifp->if_timer = 0;
1903
1904#ifdef DEVICE_POLLING
1905 ether_poll_deregister(ifp);
1906#endif
1907 /*
1908 * Cancel stats updater.
1909 */
1910 callout_stop(&sc->stat_ch);
1911
1912 /*
1913 * Issue software reset, which also unloads the microcode.
1914 */
1915 sc->flags &= ~FXP_FLAG_UCODE;
1916 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1917 DELAY(50);
1918
1919 /*
1920 * Release any xmit buffers.
1921 */
1922 txp = sc->fxp_desc.tx_list;
1923 if (txp != NULL) {
1924 for (i = 0; i < FXP_NTXCB; i++) {
1925 if (txp[i].tx_mbuf != NULL) {
1926 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
1927 BUS_DMASYNC_POSTWRITE);
1928 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
1929 m_freem(txp[i].tx_mbuf);
1930 txp[i].tx_mbuf = NULL;
1931 /* clear this to reset csum offload bits */
1932 txp[i].tx_cb->tbd[0].tb_addr = 0;
1933 }
1934 }
1935 }
1936 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1937 sc->tx_queued = 0;
1938}
1939
1940/*
1941 * Watchdog/transmission transmit timeout handler. Called when a
1942 * transmission is started on the interface, but no interrupt is
1943 * received before the timeout. This usually indicates that the
1944 * card has wedged for some reason.
1945 */
1946static void
1947fxp_watchdog(struct ifnet *ifp)
1948{
1949 struct fxp_softc *sc = ifp->if_softc;
1950
1951 FXP_LOCK(sc);
1952 device_printf(sc->dev, "device timeout\n");
1953 ifp->if_oerrors++;
1954
1955 fxp_init_body(sc);
1956 FXP_UNLOCK(sc);
1957}
1958
1959/*
1960 * Acquire locks and then call the real initialization function. This
1961 * is necessary because ether_ioctl() calls if_init() and this would
1962 * result in mutex recursion if the mutex was held.
1963 */
1964static void
1965fxp_init(void *xsc)
1966{
1967 struct fxp_softc *sc = xsc;
1968
1969 FXP_LOCK(sc);
1970 fxp_init_body(sc);
1971 FXP_UNLOCK(sc);
1972}
1973
1974/*
1975 * Perform device initialization. This routine must be called with the
1976 * softc lock held.
1977 */
1978static void
1979fxp_init_body(struct fxp_softc *sc)
1980{
1981 struct ifnet *ifp = &sc->sc_if;
1982 struct fxp_cb_config *cbp;
1983 struct fxp_cb_ias *cb_ias;
1984 struct fxp_cb_tx *tcbp;
1985 struct fxp_tx *txp;
1986 struct fxp_cb_mcs *mcsp;
1987 int i, prm, s;
1988
1989 mtx_assert(&sc->sc_mtx, MA_OWNED);
1990 s = splimp();
1991 /*
1992 * Cancel any pending I/O
1993 */
1994 fxp_stop(sc);
1995
1996 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1997
1998 /*
1999 * Initialize base of CBL and RFA memory. Loading with zero
2000 * sets it up for regular linear addressing.
2001 */
2002 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2003 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2004
2005 fxp_scb_wait(sc);
2006 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2007
2008 /*
2009 * Initialize base of dump-stats buffer.
2010 */
2011 fxp_scb_wait(sc);
2012 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
2013 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2014 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2015
2016 /*
2017 * Attempt to load microcode if requested.
2018 */
2019 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
2020 fxp_load_ucode(sc);
2021
2022 /*
2023 * Initialize the multicast address list.
2024 */
2025 if (fxp_mc_addrs(sc)) {
2026 mcsp = sc->mcsp;
2027 mcsp->cb_status = 0;
2028 mcsp->cb_command =
2029 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2030 mcsp->link_addr = 0xffffffff;
2031 /*
2032 * Start the multicast setup command.
2033 */
2034 fxp_scb_wait(sc);
2035 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2036 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2037 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2038 /* ...and wait for it to complete. */
2039 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
2040 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
2041 BUS_DMASYNC_POSTWRITE);
2042 }
2043
2044 /*
2045 * We temporarily use memory that contains the TxCB list to
2046 * construct the config CB. The TxCB list memory is rebuilt
2047 * later.
2048 */
2049 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2050
2051 /*
2052 * This bcopy is kind of disgusting, but there are a bunch of must be
2053 * zero and must be one bits in this structure and this is the easiest
2054 * way to initialize them all to proper values.
2055 */
2056 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2057
2058 cbp->cb_status = 0;
2059 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2060 FXP_CB_COMMAND_EL);
2061 cbp->link_addr = 0xffffffff; /* (no) next command */
2062 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2063 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2064 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2065 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2066 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2067 cbp->type_enable = 0; /* actually reserved */
2068 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2069 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2070 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2071 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2072 cbp->dma_mbce = 0; /* (disable) dma max counters */
2073 cbp->late_scb = 0; /* (don't) defer SCB update */
2074 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2075 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2076 cbp->ci_int = 1; /* interrupt on CU idle */
2077 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2078 cbp->ext_stats_dis = 1; /* disable extended counters */
2079 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2080 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
2081 cbp->disc_short_rx = !prm; /* discard short packets */
2082 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2083 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2084 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
2085 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2086 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2087 cbp->csma_dis = 0; /* (don't) disable link */
2088 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
2089 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2090 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2091 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2092 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2093 cbp->nsai = 1; /* (don't) disable source addr insert */
2094 cbp->preamble_length = 2; /* (7 byte) preamble */
2095 cbp->loopback = 0; /* (don't) loopback */
2096 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2097 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2098 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2099 cbp->promiscuous = prm; /* promiscuous mode */
2100 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2101 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2102 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2103 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2104 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2105
2106 cbp->stripping = !prm; /* truncate rx packet to byte count */
2107 cbp->padding = 1; /* (do) pad short tx packets */
2108 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2109 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2110 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2111 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
2112 /* must set wake_en in PMCSR also */
2113 cbp->force_fdx = 0; /* (don't) force full duplex */
2114 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2115 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2116 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
2117 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2118
2119 if (fxp_noflow || sc->revision == FXP_REV_82557) {
2120 /*
2121 * The 82557 has no hardware flow control, the values
2122 * below are the defaults for the chip.
2123 */
2124 cbp->fc_delay_lsb = 0;
2125 cbp->fc_delay_msb = 0x40;
2126 cbp->pri_fc_thresh = 3;
2127 cbp->tx_fc_dis = 0;
2128 cbp->rx_fc_restop = 0;
2129 cbp->rx_fc_restart = 0;
2130 cbp->fc_filter = 0;
2131 cbp->pri_fc_loc = 1;
2132 } else {
2133 cbp->fc_delay_lsb = 0x1f;
2134 cbp->fc_delay_msb = 0x01;
2135 cbp->pri_fc_thresh = 3;
2136 cbp->tx_fc_dis = 0; /* enable transmit FC */
2137 cbp->rx_fc_restop = 1; /* enable FC restop frames */
2138 cbp->rx_fc_restart = 1; /* enable FC restart frames */
2139 cbp->fc_filter = !prm; /* drop FC frames to host */
2140 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2141 }
2142
2143 /*
2144 * Start the config command/DMA.
2145 */
2146 fxp_scb_wait(sc);
2147 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2148 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2149 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2150 /* ...and wait for it to complete. */
2151 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2152 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2153
2154 /*
2155 * Now initialize the station address. Temporarily use the TxCB
2156 * memory area like we did above for the config CB.
2157 */
2158 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2159 cb_ias->cb_status = 0;
2160 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2161 cb_ias->link_addr = 0xffffffff;
2162 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr,
2163 sizeof(sc->arpcom.ac_enaddr));
2164
2165 /*
2166 * Start the IAS (Individual Address Setup) command/DMA.
2167 */
2168 fxp_scb_wait(sc);
2169 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2170 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2171 /* ...and wait for it to complete. */
2172 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2173 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2174
2175 /*
2176 * Initialize transmit control block (TxCB) list.
2177 */
2178 txp = sc->fxp_desc.tx_list;
2179 tcbp = sc->fxp_desc.cbl_list;
2180 bzero(tcbp, FXP_TXCB_SZ);
2181 for (i = 0; i < FXP_NTXCB; i++) {
2182 txp[i].tx_cb = tcbp + i;
2183 txp[i].tx_mbuf = NULL;
2184 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2185 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2186 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2187 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2188 if (sc->flags & FXP_FLAG_EXT_TXCB)
2189 tcbp[i].tbd_array_addr =
2190 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2191 else
2192 tcbp[i].tbd_array_addr =
2193 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2194 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2195 }
2196 /*
2197 * Set the suspend flag on the first TxCB and start the control
2198 * unit. It will execute the NOP and then suspend.
2199 */
2200 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2201 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2202 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2203 sc->tx_queued = 1;
2204
2205 fxp_scb_wait(sc);
2206 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2207
2208 /*
2209 * Initialize receiver buffer area - RFA.
2210 */
2211 fxp_scb_wait(sc);
2212 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2213 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2214
2215 /*
2216 * Set current media.
2217 */
2218 if (sc->miibus != NULL)
2219 mii_mediachg(device_get_softc(sc->miibus));
2220
2221 ifp->if_flags |= IFF_RUNNING;
2222 ifp->if_flags &= ~IFF_OACTIVE;
2223
2224 /*
2225 * Enable interrupts.
2226 */
2227#ifdef DEVICE_POLLING
2228 /*
2229 * ... but only do that if we are not polling. And because (presumably)
2230 * the default is interrupts on, we need to disable them explicitly!
2231 */
2232 if ( ifp->if_flags & IFF_POLLING )
2233 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2234 else
2235#endif /* DEVICE_POLLING */
2236 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2237
2238 /*
2239 * Start stats updater.
2240 */
2241 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2242 splx(s);
2243}
2244
2245static int
2246fxp_serial_ifmedia_upd(struct ifnet *ifp)
2247{
2248
2249 return (0);
2250}
2251
2252static void
2253fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2254{
2255
2256 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2257}
2258
2259/*
2260 * Change media according to request.
2261 */
2262static int
2263fxp_ifmedia_upd(struct ifnet *ifp)
2264{
2265 struct fxp_softc *sc = ifp->if_softc;
2266 struct mii_data *mii;
2267
2268 mii = device_get_softc(sc->miibus);
2269 mii_mediachg(mii);
2270 return (0);
2271}
2272
2273/*
2274 * Notify the world which media we're using.
2275 */
2276static void
2277fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2278{
2279 struct fxp_softc *sc = ifp->if_softc;
2280 struct mii_data *mii;
2281
2282 mii = device_get_softc(sc->miibus);
2283 mii_pollstat(mii);
2284 ifmr->ifm_active = mii->mii_media_active;
2285 ifmr->ifm_status = mii->mii_media_status;
2286
2287 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
2288 sc->cu_resume_bug = 1;
2289 else
2290 sc->cu_resume_bug = 0;
2291}
2292
2293/*
2294 * Add a buffer to the end of the RFA buffer list.
2295 * Return 0 if successful, 1 for failure. A failure results in
2296 * adding the 'oldm' (if non-NULL) on to the end of the list -
2297 * tossing out its old contents and recycling it.
2298 * The RFA struct is stuck at the beginning of mbuf cluster and the
2299 * data pointer is fixed up to point just past it.
2300 */
2301static int
2302fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2303{
2304 struct mbuf *m;
2305 struct fxp_rfa *rfa, *p_rfa;
2306 struct fxp_rx *p_rx;
2307 bus_dmamap_t tmp_map;
2308 int error;
2309
2310 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2311 if (m == NULL)
2312 return (ENOBUFS);
2313
2314 /*
2315 * Move the data pointer up so that the incoming data packet
2316 * will be 32-bit aligned.
2317 */
2318 m->m_data += RFA_ALIGNMENT_FUDGE;
2319
2320 /*
2321 * Get a pointer to the base of the mbuf cluster and move
2322 * data start past it.
2323 */
2324 rfa = mtod(m, struct fxp_rfa *);
2325 m->m_data += sc->rfa_size;
2326 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2327
2328 rfa->rfa_status = 0;
2329 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2330 rfa->actual_size = 0;
2331
2332 /*
2333 * Initialize the rest of the RFA. Note that since the RFA
2334 * is misaligned, we cannot store values directly. We're thus
2335 * using the le32enc() function which handles endianness and
2336 * is also alignment-safe.
2337 */
2338 le32enc(&rfa->link_addr, 0xffffffff);
2339 le32enc(&rfa->rbd_addr, 0xffffffff);
2340
2341 /* Map the RFA into DMA memory. */
2342 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2343 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2344 &rxp->rx_addr, 0);
2345 if (error) {
2346 m_freem(m);
2347 return (error);
2348 }
2349
2350 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2351 tmp_map = sc->spare_map;
2352 sc->spare_map = rxp->rx_map;
2353 rxp->rx_map = tmp_map;
2354 rxp->rx_mbuf = m;
2355
2356 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2357 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2358
2359 /*
2360 * If there are other buffers already on the list, attach this
2361 * one to the end by fixing up the tail to point to this one.
2362 */
2363 if (sc->fxp_desc.rx_head != NULL) {
2364 p_rx = sc->fxp_desc.rx_tail;
2365 p_rfa = (struct fxp_rfa *)
2366 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2367 p_rx->rx_next = rxp;
2368 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2369 p_rfa->rfa_control = 0;
2370 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2371 BUS_DMASYNC_PREWRITE);
2372 } else {
2373 rxp->rx_next = NULL;
2374 sc->fxp_desc.rx_head = rxp;
2375 }
2376 sc->fxp_desc.rx_tail = rxp;
2377 return (0);
2378}
2379
2380static volatile int
2381fxp_miibus_readreg(device_t dev, int phy, int reg)
2382{
2383 struct fxp_softc *sc = device_get_softc(dev);
2384 int count = 10000;
2385 int value;
2386
2387 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2388 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2389
2390 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2391 && count--)
2392 DELAY(10);
2393
2394 if (count <= 0)
2395 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2396
2397 return (value & 0xffff);
2398}
2399
2400static void
2401fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2402{
2403 struct fxp_softc *sc = device_get_softc(dev);
2404 int count = 10000;
2405
2406 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2407 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2408 (value & 0xffff));
2409
2410 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2411 count--)
2412 DELAY(10);
2413
2414 if (count <= 0)
2415 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2416}
2417
2418static int
2419fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2420{
2421 struct fxp_softc *sc = ifp->if_softc;
2422 struct ifreq *ifr = (struct ifreq *)data;
2423 struct mii_data *mii;
2424 int s, error = 0;
2425
2426 /*
2427 * Detaching causes us to call ioctl with the mutex owned. Preclude
2428 * that by saying we're busy if the lock is already held.
2429 */
2430 if (mtx_owned(&sc->sc_mtx))
2431 return (EBUSY);
2432
2433 FXP_LOCK(sc);
2434 s = splimp();
2435
2436 switch (command) {
2437 case SIOCSIFFLAGS:
2438 if (ifp->if_flags & IFF_ALLMULTI)
2439 sc->flags |= FXP_FLAG_ALL_MCAST;
2440 else
2441 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2442
2443 /*
2444 * If interface is marked up and not running, then start it.
2445 * If it is marked down and running, stop it.
2446 * XXX If it's up then re-initialize it. This is so flags
2447 * such as IFF_PROMISC are handled.
2448 */
2449 if (ifp->if_flags & IFF_UP) {
2450 fxp_init_body(sc);
2451 } else {
2452 if (ifp->if_flags & IFF_RUNNING)
2453 fxp_stop(sc);
2454 }
2455 break;
2456
2457 case SIOCADDMULTI:
2458 case SIOCDELMULTI:
2459 if (ifp->if_flags & IFF_ALLMULTI)
2460 sc->flags |= FXP_FLAG_ALL_MCAST;
2461 else
2462 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2463 /*
2464 * Multicast list has changed; set the hardware filter
2465 * accordingly.
2466 */
2467 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2468 fxp_mc_setup(sc);
2469 /*
2470 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2471 * again rather than else {}.
2472 */
2473 if (sc->flags & FXP_FLAG_ALL_MCAST)
2474 fxp_init_body(sc);
2475 error = 0;
2476 break;
2477
2478 case SIOCSIFMEDIA:
2479 case SIOCGIFMEDIA:
2480 if (sc->miibus != NULL) {
2481 mii = device_get_softc(sc->miibus);
2482 error = ifmedia_ioctl(ifp, ifr,
2483 &mii->mii_media, command);
2484 } else {
2485 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2486 }
2487 break;
2488
2489 default:
2490 /*
2491 * ether_ioctl() will eventually call fxp_start() which
2492 * will result in mutex recursion so drop it first.
2493 */
2494 FXP_UNLOCK(sc);
2495 error = ether_ioctl(ifp, command, data);
2496 }
2497 if (mtx_owned(&sc->sc_mtx))
2498 FXP_UNLOCK(sc);
2499 splx(s);
2500 return (error);
2501}
2502
2503/*
2504 * Fill in the multicast address list and return number of entries.
2505 */
2506static int
2507fxp_mc_addrs(struct fxp_softc *sc)
2508{
2509 struct fxp_cb_mcs *mcsp = sc->mcsp;
2510 struct ifnet *ifp = &sc->sc_if;
2511 struct ifmultiaddr *ifma;
2512 int nmcasts;
2513
2514 nmcasts = 0;
2515 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2516#if __FreeBSD_version < 500000
2517 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2518#else
2519 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2520#endif
2521 if (ifma->ifma_addr->sa_family != AF_LINK)
2522 continue;
2523 if (nmcasts >= MAXMCADDR) {
2524 sc->flags |= FXP_FLAG_ALL_MCAST;
2525 nmcasts = 0;
2526 break;
2527 }
2528 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2529 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2530 nmcasts++;
2531 }
2532 }
2533 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2534 return (nmcasts);
2535}
2536
2537/*
2538 * Program the multicast filter.
2539 *
2540 * We have an artificial restriction that the multicast setup command
2541 * must be the first command in the chain, so we take steps to ensure
2542 * this. By requiring this, it allows us to keep up the performance of
2543 * the pre-initialized command ring (esp. link pointers) by not actually
2544 * inserting the mcsetup command in the ring - i.e. its link pointer
2545 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2546 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2547 * lead into the regular TxCB ring when it completes.
2548 *
2549 * This function must be called at splimp.
2550 */
2551static void
2552fxp_mc_setup(struct fxp_softc *sc)
2553{
2554 struct fxp_cb_mcs *mcsp = sc->mcsp;
2555 struct ifnet *ifp = &sc->sc_if;
2556 struct fxp_tx *txp;
2557 int count;
2558
2559 /*
2560 * If there are queued commands, we must wait until they are all
2561 * completed. If we are already waiting, then add a NOP command
2562 * with interrupt option so that we're notified when all commands
2563 * have been completed - fxp_start() ensures that no additional
2564 * TX commands will be added when need_mcsetup is true.
2565 */
2566 if (sc->tx_queued) {
2567 /*
2568 * need_mcsetup will be true if we are already waiting for the
2569 * NOP command to be completed (see below). In this case, bail.
2570 */
2571 if (sc->need_mcsetup)
2572 return;
2573 sc->need_mcsetup = 1;
2574
2575 /*
2576 * Add a NOP command with interrupt so that we are notified
2577 * when all TX commands have been processed.
2578 */
2579 txp = sc->fxp_desc.tx_last->tx_next;
2580 txp->tx_mbuf = NULL;
2581 txp->tx_cb->cb_status = 0;
2582 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2583 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2584 /*
2585 * Advance the end of list forward.
2586 */
2587 sc->fxp_desc.tx_last->tx_cb->cb_command &=
2588 htole16(~FXP_CB_COMMAND_S);
2589 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2590 sc->fxp_desc.tx_last = txp;
2591 sc->tx_queued++;
2592 /*
2593 * Issue a resume in case the CU has just suspended.
2594 */
2595 fxp_scb_wait(sc);
2596 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2597 /*
2598 * Set a 5 second timer just in case we don't hear from the
2599 * card again.
2600 */
2601 ifp->if_timer = 5;
2602
2603 return;
2604 }
2605 sc->need_mcsetup = 0;
2606
2607 /*
2608 * Initialize multicast setup descriptor.
2609 */
2610 mcsp->cb_status = 0;
2611 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2612 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2613 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2614 txp = &sc->fxp_desc.mcs_tx;
2615 txp->tx_mbuf = NULL;
2616 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2617 txp->tx_next = sc->fxp_desc.tx_list;
2618 (void) fxp_mc_addrs(sc);
2619 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2620 sc->tx_queued = 1;
2621
2622 /*
2623 * Wait until command unit is not active. This should never
2624 * be the case when nothing is queued, but make sure anyway.
2625 */
2626 count = 100;
2627 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2628 FXP_SCB_CUS_ACTIVE && --count)
2629 DELAY(10);
2630 if (count == 0) {
2631 device_printf(sc->dev, "command queue timeout\n");
2632 return;
2633 }
2634
2635 /*
2636 * Start the multicast setup command.
2637 */
2638 fxp_scb_wait(sc);
2639 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2640 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2641 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2642
2643 ifp->if_timer = 2;
2644 return;
2645}
2646
2647static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2648static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2649static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2650static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2651static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2652static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2653
2654#define UCODE(x) x, sizeof(x)
2655
2656struct ucode {
2657 u_int32_t revision;
2658 u_int32_t *ucode;
2659 int length;
2660 u_short int_delay_offset;
2661 u_short bundle_max_offset;
2662} ucode_table[] = {
2663 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2664 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2665 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2666 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2667 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2668 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2669 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2670 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2671 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2672 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2673 { 0, NULL, 0, 0, 0 }
2674};
2675
2676static void
2677fxp_load_ucode(struct fxp_softc *sc)
2678{
2679 struct ucode *uc;
2680 struct fxp_cb_ucode *cbp;
2681
2682 for (uc = ucode_table; uc->ucode != NULL; uc++)
2683 if (sc->revision == uc->revision)
2684 break;
2685 if (uc->ucode == NULL)
2686 return;
2687 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2688 cbp->cb_status = 0;
2689 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2690 cbp->link_addr = 0xffffffff; /* (no) next command */
2691 memcpy(cbp->ucode, uc->ucode, uc->length);
2692 if (uc->int_delay_offset)
2693 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] =
2694 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2695 if (uc->bundle_max_offset)
2696 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] =
2697 htole16(sc->tunable_bundle_max);
2698 /*
2699 * Download the ucode to the chip.
2700 */
2701 fxp_scb_wait(sc);
2702 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2703 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2704 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2705 /* ...and wait for it to complete. */
2706 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2707 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2708 device_printf(sc->dev,
2709 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2710 sc->tunable_int_delay,
2711 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2712 sc->flags |= FXP_FLAG_UCODE;
2713}
2714
2715static int
2716sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2717{
2718 int error, value;
2719
2720 value = *(int *)arg1;
2721 error = sysctl_handle_int(oidp, &value, 0, req);
2722 if (error || !req->newptr)
2723 return (error);
2724 if (value < low || value > high)
2725 return (EINVAL);
2726 *(int *)arg1 = value;
2727 return (0);
2728}
2729
2730/*
2731 * Interrupt delay is expressed in microseconds, a multiplier is used
2732 * to convert this to the appropriate clock ticks before using.
2733 */
2734static int
2735sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2736{
2737 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2738}
2739
2740static int
2741sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2742{
2743 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2744}
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