1/*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30/*
31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/fxp/if_fxp.c 114269 2003-04-30 01:54:38Z imp $");
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/endian.h>
40#include <sys/mbuf.h>
41 /* #include <sys/mutex.h> */
42#include <sys/kernel.h>
43#include <sys/socket.h>
44#include <sys/sysctl.h>
45
46#include <net/if.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
49
50#include <net/bpf.h>
51#include <sys/sockio.h>
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56
57#include <net/ethernet.h>
58#include <net/if_arp.h>
59
60#include <machine/clock.h> /* for DELAY */
61
62#include <net/if_types.h>
63#include <net/if_vlan_var.h>
64
65#ifdef FXP_IP_CSUM_WAR
66#include <netinet/in.h>
67#include <netinet/in_systm.h>
68#include <netinet/ip.h>
69#include <machine/in_cksum.h>
70#endif
71
72#include <pci/pcivar.h>
73#include <pci/pcireg.h> /* for PCIM_CMD_xxx */
74
75#include <dev/mii/mii.h>
76#include <dev/mii/miivar.h>
77
78#include <dev/fxp/if_fxpreg.h>
79#include <dev/fxp/if_fxpvar.h>
80#include <dev/fxp/rcvbundl.h>
81
82MODULE_DEPEND(fxp, pci, 1, 1, 1);
83MODULE_DEPEND(fxp, ether, 1, 1, 1);
84MODULE_DEPEND(fxp, miibus, 1, 1, 1);
85#include "miibus_if.h"
86
87/*
88 * NOTE! On the Alpha, we have an alignment constraint. The
89 * card DMAs the packet immediately following the RFA. However,
90 * the first thing in the packet is a 14-byte Ethernet header.
91 * This means that the packet is misaligned. To compensate,
92 * we actually offset the RFA 2 bytes into the cluster. This
93 * alignes the packet after the Ethernet header at a 32-bit
94 * boundary. HOWEVER! This means that the RFA is misaligned!
95 */
96#define RFA_ALIGNMENT_FUDGE 2
97
98/*
99 * Set initial transmit threshold at 64 (512 bytes). This is
100 * increased by 64 (512 bytes) at a time, to maximum of 192
101 * (1536 bytes), if an underrun occurs.
102 */
103static int tx_threshold = 64;
104
105/*
106 * The configuration byte map has several undefined fields which
107 * must be one or must be zero. Set up a template for these bits
108 * only, (assuming a 82557 chip) leaving the actual configuration
109 * to fxp_init.
110 *
111 * See struct fxp_cb_config for the bit definitions.
112 */
113static u_char fxp_cb_config_template[] = {
114 0x0, 0x0, /* cb_status */
115 0x0, 0x0, /* cb_command */
116 0x0, 0x0, 0x0, 0x0, /* link_addr */
117 0x0, /* 0 */
118 0x0, /* 1 */
119 0x0, /* 2 */
120 0x0, /* 3 */
121 0x0, /* 4 */
122 0x0, /* 5 */
123 0x32, /* 6 */
124 0x0, /* 7 */
125 0x0, /* 8 */
126 0x0, /* 9 */
127 0x6, /* 10 */
128 0x0, /* 11 */
129 0x0, /* 12 */
130 0x0, /* 13 */
131 0xf2, /* 14 */
132 0x48, /* 15 */
133 0x0, /* 16 */
134 0x40, /* 17 */
135 0xf0, /* 18 */
136 0x0, /* 19 */
137 0x3f, /* 20 */
138 0x5 /* 21 */
139};
140
141struct fxp_ident {
142 u_int16_t devid;
143 char *name;
144};
145
146/*
147 * Claim various Intel PCI device identifiers for this driver. The
148 * sub-vendor and sub-device field are extensively used to identify
149 * particular variants, but we don't currently differentiate between
150 * them.
151 */
152static struct fxp_ident fxp_ident_table[] = {
153 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" },
154 { 0x1030, "Intel 82559 Pro/100 Ethernet" },
155 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
156 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
157 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
158 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
159 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
160 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
161 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
162 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
163 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
164 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
165 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
166 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
167 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
168 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
169 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" },
170 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" },
171 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" },
172 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
173 { 0, NULL },
174};
175
176#ifdef FXP_IP_CSUM_WAR
177#define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
178#else
179#define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
180#endif
181
182static int fxp_probe(device_t dev);
183static int fxp_attach(device_t dev);
184static int fxp_detach(device_t dev);
185static int fxp_shutdown(device_t dev);
186static int fxp_suspend(device_t dev);
187static int fxp_resume(device_t dev);
188
189static void fxp_intr(void *xsc);
190static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
191 u_int8_t statack, int count);
192static void fxp_init(void *xsc);
193static void fxp_init_body(struct fxp_softc *sc);
194static void fxp_tick(void *xsc);
195static void fxp_powerstate_d0(device_t dev);
196static void fxp_start(struct ifnet *ifp);
197static void fxp_start_body(struct ifnet *ifp);
198static void fxp_stop(struct fxp_softc *sc);
199static void fxp_release(struct fxp_softc *sc);
200static int fxp_ioctl(struct ifnet *ifp, u_long command,
201 caddr_t data);
202static void fxp_watchdog(struct ifnet *ifp);
203static int fxp_add_rfabuf(struct fxp_softc *sc,
204 struct fxp_rx *rxp);
205static int fxp_mc_addrs(struct fxp_softc *sc);
206static void fxp_mc_setup(struct fxp_softc *sc);
207static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
208 int autosize);
209static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
210 u_int16_t data);
211static void fxp_autosize_eeprom(struct fxp_softc *sc);
212static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
213 int offset, int words);
214static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
215 int offset, int words);
216static int fxp_ifmedia_upd(struct ifnet *ifp);
217static void fxp_ifmedia_sts(struct ifnet *ifp,
218 struct ifmediareq *ifmr);
219static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
220static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
221 struct ifmediareq *ifmr);
222static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
223static void fxp_miibus_writereg(device_t dev, int phy, int reg,
224 int value);
225static void fxp_load_ucode(struct fxp_softc *sc);
226static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
227 int low, int high);
228static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
229static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
230static __inline void fxp_scb_wait(struct fxp_softc *sc);
231static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
232static __inline void fxp_dma_wait(struct fxp_softc *sc,
233 volatile u_int16_t *status, bus_dma_tag_t dmat,
234 bus_dmamap_t map);
235
236static device_method_t fxp_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, fxp_probe),
239 DEVMETHOD(device_attach, fxp_attach),
240 DEVMETHOD(device_detach, fxp_detach),
241 DEVMETHOD(device_shutdown, fxp_shutdown),
242 DEVMETHOD(device_suspend, fxp_suspend),
243 DEVMETHOD(device_resume, fxp_resume),
244
245 /* MII interface */
246 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
247 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
248
249 { 0, 0 }
250};
251
252static driver_t fxp_driver = {
253 "fxp",
254 fxp_methods,
255 sizeof(struct fxp_softc),
256};
257
258static devclass_t fxp_devclass;
259
260DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
261DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
262DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
263
264static int fxp_rnr;
265SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
266
267/*
268 * Wait for the previous command to be accepted (but not necessarily
269 * completed).
270 */
271static __inline void
272fxp_scb_wait(struct fxp_softc *sc)
273{
274 int i = 10000;
275
276 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
277 DELAY(2);
278 if (i == 0)
279 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
280 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
281 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
282 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
283 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
284}
285
286static __inline void
287fxp_scb_cmd(struct fxp_softc *sc, int cmd)
288{
289
290 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
291 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
292 fxp_scb_wait(sc);
293 }
294 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
295}
296
297static __inline void
298fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status,
299 bus_dma_tag_t dmat, bus_dmamap_t map)
300{
301 int i = 10000;
302
303 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
304 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) {
305 DELAY(2);
306 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
307 }
308 if (i == 0)
309 device_printf(sc->dev, "DMA timeout\n");
310}
311
312/*
313 * Return identification string if this is device is ours.
314 */
315static int
316fxp_probe(device_t dev)
317{
318 u_int16_t devid;
319 struct fxp_ident *ident;
320
321 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
322 devid = pci_get_device(dev);
323 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
324 if (ident->devid == devid) {
325 device_set_desc(dev, ident->name);
326 return (0);
327 }
328 }
329 }
330 return (ENXIO);
331}
332
333static void
334fxp_powerstate_d0(device_t dev)
335{
336#if __FreeBSD_version >= 430002
337 u_int32_t iobase, membase, irq;
338
339 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
340 /* Save important PCI config data. */
341 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
342 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
343 irq = pci_read_config(dev, PCIR_INTLINE, 4);
344
345 /* Reset the power state. */
346 device_printf(dev, "chip is in D%d power mode "
347 "-- setting to D0\n", pci_get_powerstate(dev));
348
349 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
350
351 /* Restore PCI config data. */
352 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
353 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
354 pci_write_config(dev, PCIR_INTLINE, irq, 4);
355 }
356#endif
357}
358
359static void
360fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
361{
362 u_int32_t *addr;
363
364 if (error)
365 return;
366
367 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
368 addr = arg;
369 *addr = segs->ds_addr;
370}
371
372static int
373fxp_attach(device_t dev)
374{
375 int error = 0;
376 struct fxp_softc *sc = device_get_softc(dev);
377 struct ifnet *ifp;
378 struct fxp_rx *rxp;
379 u_int32_t val;
380 u_int16_t data, myea[ETHER_ADDR_LEN / 2];
381 int i, rid, m1, m2, prefer_iomap, maxtxseg;
382 int s;
383
384 sc->dev = dev;
385 callout_handle_init(&sc->stat_ch);
386 sysctl_ctx_init(&sc->sysctl_ctx);
387 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
388 MTX_DEF);
389 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
390 fxp_serial_ifmedia_sts);
391
392 s = splimp();
393
394 /*
395 * Enable bus mastering.
396 */
397 pci_enable_busmaster(dev);
398 val = pci_read_config(dev, PCIR_COMMAND, 2);
399
400 fxp_powerstate_d0(dev);
401
402 /*
403 * Figure out which we should try first - memory mapping or i/o mapping?
404 * We default to memory mapping. Then we accept an override from the
405 * command line. Then we check to see which one is enabled.
406 */
407 m1 = PCIM_CMD_MEMEN;
408 m2 = PCIM_CMD_PORTEN;
409 prefer_iomap = 0;
410 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
411 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
412 m1 = PCIM_CMD_PORTEN;
413 m2 = PCIM_CMD_MEMEN;
414 }
415
416 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
417 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
418 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
419 0, ~0, 1, RF_ACTIVE);
420 if (sc->mem == NULL) {
421 sc->rtp =
422 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
423 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
424 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
425 0, ~0, 1, RF_ACTIVE);
426 }
427
428 if (!sc->mem) {
429 error = ENXIO;
430 goto fail;
431 }
432 if (bootverbose) {
433 device_printf(dev, "using %s space register mapping\n",
434 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
435 }
436
437 sc->sc_st = rman_get_bustag(sc->mem);
438 sc->sc_sh = rman_get_bushandle(sc->mem);
439
440 /*
441 * Allocate our interrupt.
442 */
443 rid = 0;
444 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
445 RF_SHAREABLE | RF_ACTIVE);
446 if (sc->irq == NULL) {
447 device_printf(dev, "could not map interrupt\n");
448 error = ENXIO;
449 goto fail;
450 }
451
452 /*
453 * Reset to a stable state.
454 */
455 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
456 DELAY(10);
457
458 /*
459 * Find out how large of an SEEPROM we have.
460 */
461 fxp_autosize_eeprom(sc);
462
463 /*
464 * Determine whether we must use the 503 serial interface.
465 */
466 fxp_read_eeprom(sc, &data, 6, 1);
467 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
468 (data & FXP_PHY_SERIAL_ONLY))
469 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
470
471 /*
472 * Create the sysctl tree
473 */
474 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
475 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
476 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
477 if (sc->sysctl_tree == NULL) {
478 error = ENXIO;
479 goto fail;
480 }
481 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
482 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
483 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
484 "FXP driver receive interrupt microcode bundling delay");
485 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
486 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
487 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
488 "FXP driver receive interrupt microcode bundle size limit");
489
490 /*
491 * Pull in device tunables.
492 */
493 sc->tunable_int_delay = TUNABLE_INT_DELAY;
494 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
495 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
496 "int_delay", &sc->tunable_int_delay);
497 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
498 "bundle_max", &sc->tunable_bundle_max);
499
500 /*
501 * Find out the chip revision; lump all 82557 revs together.
502 */
503 fxp_read_eeprom(sc, &data, 5, 1);
504 if ((data >> 8) == 1)
505 sc->revision = FXP_REV_82557;
506 else
507 sc->revision = pci_get_revid(dev);
508
509 /*
510 * Enable workarounds for certain chip revision deficiencies.
511 *
512 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
513 * some systems based a normal 82559 design, have a defect where
514 * the chip can cause a PCI protocol violation if it receives
515 * a CU_RESUME command when it is entering the IDLE state. The
516 * workaround is to disable Dynamic Standby Mode, so the chip never
517 * deasserts CLKRUN#, and always remains in an active state.
518 *
519 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
520 */
521 i = pci_get_device(dev);
522 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
523 sc->revision >= FXP_REV_82559_A0) {
524 fxp_read_eeprom(sc, &data, 10, 1);
525 if (data & 0x02) { /* STB enable */
526 u_int16_t cksum;
527 int i;
528
529 device_printf(dev,
530 "Disabling dynamic standby mode in EEPROM\n");
531 data &= ~0x02;
532 fxp_write_eeprom(sc, &data, 10, 1);
533 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
534 cksum = 0;
535 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
536 fxp_read_eeprom(sc, &data, i, 1);
537 cksum += data;
538 }
539 i = (1 << sc->eeprom_size) - 1;
540 cksum = 0xBABA - cksum;
541 fxp_read_eeprom(sc, &data, i, 1);
542 fxp_write_eeprom(sc, &cksum, i, 1);
543 device_printf(dev,
544 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
545 i, data, cksum);
546#if 1
547 /*
548 * If the user elects to continue, try the software
549 * workaround, as it is better than nothing.
550 */
551 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
552#endif
553 }
554 }
555
556 /*
557 * If we are not a 82557 chip, we can enable extended features.
558 */
559 if (sc->revision != FXP_REV_82557) {
560 /*
561 * If MWI is enabled in the PCI configuration, and there
562 * is a valid cacheline size (8 or 16 dwords), then tell
563 * the board to turn on MWI.
564 */
565 if (val & PCIM_CMD_MWRICEN &&
566 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
567 sc->flags |= FXP_FLAG_MWI_ENABLE;
568
569 /* turn on the extended TxCB feature */
570 sc->flags |= FXP_FLAG_EXT_TXCB;
571
572 /* enable reception of long frames for VLAN */
573 sc->flags |= FXP_FLAG_LONG_PKT_EN;
574 }
575
576 /*
577 * Enable use of extended RFDs and TCBs for 82550
578 * and later chips. Note: we need extended TXCB support
579 * too, but that's already enabled by the code above.
580 * Be careful to do this only on the right devices.
581 */
582
583 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) {
584 sc->rfa_size = sizeof (struct fxp_rfa);
585 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
586 sc->flags |= FXP_FLAG_EXT_RFA;
587 } else {
588 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
589 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
590 }
591
592 /*
593 * Allocate DMA tags and DMA safe memory.
594 */
595 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG;
596 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT,
597 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg,
598 maxtxseg, MCLBYTES, 0, &sc->fxp_mtag);
599 if (error) {
600 device_printf(dev, "could not allocate dma tag\n");
601 goto fail;
602 }
603
604 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
605 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1,
606 sizeof(struct fxp_stats), 0, &sc->fxp_stag);
607 if (error) {
608 device_printf(dev, "could not allocate dma tag\n");
609 goto fail;
610 }
611
612 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
613 BUS_DMA_NOWAIT, &sc->fxp_smap);
614 if (error)
615 goto fail;
616 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
617 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
618 if (error) {
619 device_printf(dev, "could not map the stats buffer\n");
620 goto fail;
621 }
622 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
623
624 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
625 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1,
626 FXP_TXCB_SZ, 0, &sc->cbl_tag);
627 if (error) {
628 device_printf(dev, "could not allocate dma tag\n");
629 goto fail;
630 }
631
632 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
633 BUS_DMA_NOWAIT, &sc->cbl_map);
634 if (error)
635 goto fail;
636 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ);
637
638 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
639 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
640 &sc->fxp_desc.cbl_addr, 0);
641 if (error) {
642 device_printf(dev, "could not map DMA memory\n");
643 goto fail;
644 }
645
646 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
647 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1,
648 sizeof(struct fxp_cb_mcs), 0, &sc->mcs_tag);
649 if (error) {
650 device_printf(dev, "could not allocate dma tag\n");
651 goto fail;
652 }
653
654 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
655 BUS_DMA_NOWAIT, &sc->mcs_map);
656 if (error)
657 goto fail;
658 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
659 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
660 if (error) {
661 device_printf(dev, "can't map the multicast setup command\n");
662 goto fail;
663 }
664
665 /*
666 * Pre-allocate the TX DMA maps.
667 */
668 for (i = 0; i < FXP_NTXCB; i++) {
669 error = bus_dmamap_create(sc->fxp_mtag, 0,
670 &sc->fxp_desc.tx_list[i].tx_map);
671 if (error) {
672 device_printf(dev, "can't create DMA map for TX\n");
673 goto fail;
674 }
675 }
676 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
677 if (error) {
678 device_printf(dev, "can't create spare DMA map\n");
679 goto fail;
680 }
681
682 /*
683 * Pre-allocate our receive buffers.
684 */
685 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
686 for (i = 0; i < FXP_NRFABUFS; i++) {
687 rxp = &sc->fxp_desc.rx_list[i];
688 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
689 if (error) {
690 device_printf(dev, "can't create DMA map for RX\n");
691 goto fail;
692 }
693 if (fxp_add_rfabuf(sc, rxp) != 0) {
694 error = ENOMEM;
695 goto fail;
696 }
697 }
698
699 /*
700 * Read MAC address.
701 */
702 fxp_read_eeprom(sc, myea, 0, 3);
703 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff;
704 sc->arpcom.ac_enaddr[1] = myea[0] >> 8;
705 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff;
706 sc->arpcom.ac_enaddr[3] = myea[1] >> 8;
707 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff;
708 sc->arpcom.ac_enaddr[5] = myea[2] >> 8;
709 device_printf(dev, "Ethernet address %6D%s\n",
710 sc->arpcom.ac_enaddr, ":",
711 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
712 if (bootverbose) {
713 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
714 pci_get_vendor(dev), pci_get_device(dev),
715 pci_get_subvendor(dev), pci_get_subdevice(dev),
716 pci_get_revid(dev));
717 fxp_read_eeprom(sc, &data, 10, 1);
718 device_printf(dev, "Dynamic Standby mode is %s\n",
719 data & 0x02 ? "enabled" : "disabled");
720 }
721
722 /*
723 * If this is only a 10Mbps device, then there is no MII, and
724 * the PHY will use a serial interface instead.
725 *
726 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
727 * doesn't have a programming interface of any sort. The
728 * media is sensed automatically based on how the link partner
729 * is configured. This is, in essence, manual configuration.
730 */
731 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
732 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
733 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
734 } else {
735 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
736 fxp_ifmedia_sts)) {
737 device_printf(dev, "MII without any PHY!\n");
738 error = ENXIO;
739 goto fail;
740 }
741 }
742
743 ifp = &sc->arpcom.ac_if;
744 ifp->if_unit = device_get_unit(dev);
745 ifp->if_name = "fxp";
746 ifp->if_output = ether_output;
747 ifp->if_baudrate = 100000000;
748 ifp->if_init = fxp_init;
749 ifp->if_softc = sc;
750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
751 ifp->if_ioctl = fxp_ioctl;
752 ifp->if_start = fxp_start;
753 ifp->if_watchdog = fxp_watchdog;
754
755 /* Enable checksum offload for 82550 or better chips */
756 if (sc->flags & FXP_FLAG_EXT_RFA) {
757 ifp->if_hwassist = FXP_CSUM_FEATURES;
758 ifp->if_capabilities = IFCAP_HWCSUM;
759 ifp->if_capenable = ifp->if_capabilities;
760 }
761
762 /*
763 * Attach the interface.
764 */
765 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
766
767 /*
768 * Tell the upper layer(s) we support long frames.
769 */
770 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
771 ifp->if_capabilities |= IFCAP_VLAN_MTU;
772
773 /*
774 * Let the system queue as many packets as we have available
775 * TX descriptors.
776 */
777 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
778
779 /*
780 * Hook our interrupt after all initialization is complete.
781 * XXX This driver has been tested with the INTR_MPSAFFE flag set
782 * however, ifp and its functions are not fully locked so MPSAFE
783 * should not be used unless you can handle potential data loss.
784 */
785 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/,
786 fxp_intr, sc, &sc->ih);
787 if (error) {
788 device_printf(dev, "could not setup irq\n");
789 ether_ifdetach(&sc->arpcom.ac_if);
790 goto fail;
791 }
792
793fail:
794 splx(s);
795 if (error)
796 fxp_release(sc);
797 return (error);
798}
799
800/*
801 * Release all resources. The softc lock should not be held and the
802 * interrupt should already be torn down.
803 */
804static void
805fxp_release(struct fxp_softc *sc)
806{
807 struct fxp_rx *rxp;
808 struct fxp_tx *txp;
809 int i;
810
811 mtx_assert(&sc->sc_mtx, MA_NOTOWNED);
812 if (sc->ih)
813 panic("fxp_release() called with intr handle still active");
814 if (sc->miibus)
815 device_delete_child(sc->dev, sc->miibus);
816 bus_generic_detach(sc->dev);
817 ifmedia_removeall(&sc->sc_media);
818 if (sc->fxp_desc.cbl_list) {
819 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
820 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
821 sc->cbl_map);
822 }
823 if (sc->fxp_stats) {
824 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
825 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
826 }
827 if (sc->mcsp) {
828 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
829 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
830 }
831 if (sc->irq)
832 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
833 if (sc->mem)
834 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
835 if (sc->fxp_mtag) {
836 for (i = 0; i < FXP_NRFABUFS; i++) {
837 rxp = &sc->fxp_desc.rx_list[i];
838 if (rxp->rx_mbuf != NULL) {
839 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
840 BUS_DMASYNC_POSTREAD);
841 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
842 m_freem(rxp->rx_mbuf);
843 }
844 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
845 }
846 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
847 bus_dma_tag_destroy(sc->fxp_mtag);
848 }
849 if (sc->fxp_stag) {
850 for (i = 0; i < FXP_NTXCB; i++) {
851 txp = &sc->fxp_desc.tx_list[i];
852 if (txp->tx_mbuf != NULL) {
853 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
854 BUS_DMASYNC_POSTWRITE);
855 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
856 m_freem(txp->tx_mbuf);
857 }
858 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
859 }
860 bus_dma_tag_destroy(sc->fxp_stag);
861 }
862 if (sc->cbl_tag)
863 bus_dma_tag_destroy(sc->cbl_tag);
864 if (sc->mcs_tag)
865 bus_dma_tag_destroy(sc->mcs_tag);
866
867 sysctl_ctx_free(&sc->sysctl_ctx);
868
869 mtx_destroy(&sc->sc_mtx);
870}
871
872/*
873 * Detach interface.
874 */
875static int
876fxp_detach(device_t dev)
877{
878 struct fxp_softc *sc = device_get_softc(dev);
879 int s;
880
881 FXP_LOCK(sc);
882 s = splimp();
883
884 sc->suspend = 1; /* Do same thing as we do for suspend */
885 /*
886 * Close down routes etc.
887 */
888 ether_ifdetach(&sc->arpcom.ac_if);
889
890 /*
891 * Stop DMA and drop transmit queue, but disable interrupts first.
892 */
893 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
894 fxp_stop(sc);
895 FXP_UNLOCK(sc);
896
897 /*
898 * Unhook interrupt before dropping lock. This is to prevent
899 * races with fxp_intr().
900 */
901 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
902 sc->ih = NULL;
903
904 splx(s);
905
906 /* Release our allocated resources. */
907 fxp_release(sc);
908 return (0);
909}
910
911/*
912 * Device shutdown routine. Called at system shutdown after sync. The
913 * main purpose of this routine is to shut off receiver DMA so that
914 * kernel memory doesn't get clobbered during warmboot.
915 */
916static int
917fxp_shutdown(device_t dev)
918{
919 /*
920 * Make sure that DMA is disabled prior to reboot. Not doing
921 * do could allow DMA to corrupt kernel memory during the
922 * reboot before the driver initializes.
923 */
924 fxp_stop((struct fxp_softc *) device_get_softc(dev));
925 return (0);
926}
927
928/*
929 * Device suspend routine. Stop the interface and save some PCI
930 * settings in case the BIOS doesn't restore them properly on
931 * resume.
932 */
933static int
934fxp_suspend(device_t dev)
935{
936 struct fxp_softc *sc = device_get_softc(dev);
937 int i, s;
938
939 FXP_LOCK(sc);
940 s = splimp();
941
942 fxp_stop(sc);
943
944 for (i = 0; i < 5; i++)
945 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
946 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
947 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
948 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
949 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
950
951 sc->suspended = 1;
952
953 FXP_UNLOCK(sc);
954 splx(s);
955 return (0);
956}
957
958/*
959 * Device resume routine. Restore some PCI settings in case the BIOS
960 * doesn't, re-enable busmastering, and restart the interface if
961 * appropriate.
962 */
963static int
964fxp_resume(device_t dev)
965{
966 struct fxp_softc *sc = device_get_softc(dev);
967 struct ifnet *ifp = &sc->sc_if;
968 u_int16_t pci_command;
969 int i, s;
970
971 FXP_LOCK(sc);
972 s = splimp();
973
974 fxp_powerstate_d0(dev);
975
976 /* better way to do this? */
977 for (i = 0; i < 5; i++)
978 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
979 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
980 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
981 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
982 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
983
984 /* reenable busmastering */
985 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
986 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
987 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
988
989 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
990 DELAY(10);
991
992 /* reinitialize interface if necessary */
993 if (ifp->if_flags & IFF_UP)
994 fxp_init_body(sc);
995
996 sc->suspended = 0;
997
998 FXP_UNLOCK(sc);
999 splx(s);
1000 return (0);
1001}
1002
1003static void
1004fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1005{
1006 u_int16_t reg;
1007 int x;
1008
1009 /*
1010 * Shift in data.
1011 */
1012 for (x = 1 << (length - 1); x; x >>= 1) {
1013 if (data & x)
1014 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1015 else
1016 reg = FXP_EEPROM_EECS;
1017 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1018 DELAY(1);
1019 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1020 DELAY(1);
1021 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1022 DELAY(1);
1023 }
1024}
1025
1026/*
1027 * Read from the serial EEPROM. Basically, you manually shift in
1028 * the read opcode (one bit at a time) and then shift in the address,
1029 * and then you shift out the data (all of this one bit at a time).
1030 * The word size is 16 bits, so you have to provide the address for
1031 * every 16 bits of data.
1032 */
1033static u_int16_t
1034fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1035{
1036 u_int16_t reg, data;
1037 int x;
1038
1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1040 /*
1041 * Shift in read opcode.
1042 */
1043 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1044 /*
1045 * Shift in address.
1046 */
1047 data = 0;
1048 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1049 if (offset & x)
1050 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1051 else
1052 reg = FXP_EEPROM_EECS;
1053 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1054 DELAY(1);
1055 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1056 DELAY(1);
1057 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1058 DELAY(1);
1059 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1060 data++;
1061 if (autosize && reg == 0) {
1062 sc->eeprom_size = data;
1063 break;
1064 }
1065 }
1066 /*
1067 * Shift out data.
1068 */
1069 data = 0;
1070 reg = FXP_EEPROM_EECS;
1071 for (x = 1 << 15; x; x >>= 1) {
1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1073 DELAY(1);
1074 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1075 data |= x;
1076 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1077 DELAY(1);
1078 }
1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1080 DELAY(1);
1081
1082 return (data);
1083}
1084
1085static void
1086fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1087{
1088 int i;
1089
1090 /*
1091 * Erase/write enable.
1092 */
1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1094 fxp_eeprom_shiftin(sc, 0x4, 3);
1095 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1097 DELAY(1);
1098 /*
1099 * Shift in write opcode, address, data.
1100 */
1101 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1102 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1103 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1104 fxp_eeprom_shiftin(sc, data, 16);
1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1106 DELAY(1);
1107 /*
1108 * Wait for EEPROM to finish up.
1109 */
1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1111 DELAY(1);
1112 for (i = 0; i < 1000; i++) {
1113 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1114 break;
1115 DELAY(50);
1116 }
1117 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1118 DELAY(1);
1119 /*
1120 * Erase/write disable.
1121 */
1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1123 fxp_eeprom_shiftin(sc, 0x4, 3);
1124 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1125 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1126 DELAY(1);
1127}
1128
1129/*
1130 * From NetBSD:
1131 *
1132 * Figure out EEPROM size.
1133 *
1134 * 559's can have either 64-word or 256-word EEPROMs, the 558
1135 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1136 * talks about the existance of 16 to 256 word EEPROMs.
1137 *
1138 * The only known sizes are 64 and 256, where the 256 version is used
1139 * by CardBus cards to store CIS information.
1140 *
1141 * The address is shifted in msb-to-lsb, and after the last
1142 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1143 * after which follows the actual data. We try to detect this zero, by
1144 * probing the data-out bit in the EEPROM control register just after
1145 * having shifted in a bit. If the bit is zero, we assume we've
1146 * shifted enough address bits. The data-out should be tri-state,
1147 * before this, which should translate to a logical one.
1148 */
1149static void
1150fxp_autosize_eeprom(struct fxp_softc *sc)
1151{
1152
1153 /* guess maximum size of 256 words */
1154 sc->eeprom_size = 8;
1155
1156 /* autosize */
1157 (void) fxp_eeprom_getword(sc, 0, 1);
1158}
1159
1160static void
1161fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1162{
1163 int i;
1164
1165 for (i = 0; i < words; i++)
1166 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1167}
1168
1169static void
1170fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1171{
1172 int i;
1173
1174 for (i = 0; i < words; i++)
1175 fxp_eeprom_putword(sc, offset + i, data[i]);
1176}
1177
1178static void
1179fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
1180 bus_size_t mapsize, int error)
1181{
1182 struct fxp_softc *sc;
1183 struct fxp_cb_tx *txp;
1184 int i;
1185
1186 if (error)
1187 return;
1188
1189 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments"));
1190
1191 sc = arg;
1192 txp = sc->fxp_desc.tx_last->tx_next->tx_cb;
1193 for (i = 0; i < nseg; i++) {
1194 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
1195 /*
1196 * If this is an 82550/82551, then we're using extended
1197 * TxCBs _and_ we're using checksum offload. This means
1198 * that the TxCB is really an IPCB. One major difference
1199 * between the two is that with plain extended TxCBs,
1200 * the bottom half of the TxCB contains two entries from
1201 * the TBD array, whereas IPCBs contain just one entry:
1202 * one entry (8 bytes) has been sacrificed for the TCP/IP
1203 * checksum offload control bits. So to make things work
1204 * right, we have to start filling in the TBD array
1205 * starting from a different place depending on whether
1206 * the chip is an 82550/82551 or not.
1207 */
1208 if (sc->flags & FXP_FLAG_EXT_RFA) {
1209 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1210 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1211 } else {
1212 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1213 txp->tbd[i].tb_size = htole32(segs[i].ds_len);
1214 }
1215 }
1216 txp->tbd_number = nseg;
1217}
1218
1219/*
1220 * Grab the softc lock and call the real fxp_start_body() routine
1221 */
1222static void
1223fxp_start(struct ifnet *ifp)
1224{
1225 struct fxp_softc *sc = ifp->if_softc;
1226
1227 FXP_LOCK(sc);
1228 fxp_start_body(ifp);
1229 FXP_UNLOCK(sc);
1230}
1231
1232/*
1233 * Start packet transmission on the interface.
1234 * This routine must be called with the softc lock held, and is an
1235 * internal entry point only.
1236 */
1237static void
1238fxp_start_body(struct ifnet *ifp)
1239{
1240 struct fxp_softc *sc = ifp->if_softc;
1241 struct fxp_tx *txp;
1242 struct mbuf *mb_head;
1243 int error;
1244
1245 mtx_assert(&sc->sc_mtx, MA_OWNED);
1246 /*
1247 * See if we need to suspend xmit until the multicast filter
1248 * has been reprogrammed (which can only be done at the head
1249 * of the command chain).
1250 */
1251 if (sc->need_mcsetup) {
1252 return;
1253 }
1254
1255 txp = NULL;
1256
1257 /*
1258 * We're finished if there is nothing more to add to the list or if
1259 * we're all filled up with buffers to transmit.
1260 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1261 * a NOP command when needed.
1262 */
1263 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1264
1265 /*
1266 * Grab a packet to transmit.
1267 */
1268 IF_DEQUEUE(&ifp->if_snd, mb_head);
1269
1270 /*
1271 * Get pointer to next available tx desc.
1272 */
1273 txp = sc->fxp_desc.tx_last->tx_next;
1274
1275 /*
1276 * Deal with TCP/IP checksum offload. Note that
1277 * in order for TCP checksum offload to work,
1278 * the pseudo header checksum must have already
1279 * been computed and stored in the checksum field
1280 * in the TCP header. The stack should have
1281 * already done this for us.
1282 */
1283
1284 if (mb_head->m_pkthdr.csum_flags) {
1285 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1286 txp->tx_cb->ipcb_ip_activation_high =
1287 FXP_IPCB_HARDWAREPARSING_ENABLE;
1288 txp->tx_cb->ipcb_ip_schedule =
1289 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1290 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP)
1291 txp->tx_cb->ipcb_ip_schedule |=
1292 FXP_IPCB_TCP_PACKET;
1293 }
1294#ifdef FXP_IP_CSUM_WAR
1295 /*
1296 * XXX The 82550 chip appears to have trouble
1297 * dealing with IP header checksums in very small
1298 * datagrams, namely fragments from 1 to 3 bytes
1299 * in size. For example, say you want to transmit
1300 * a UDP packet of 1473 bytes. The packet will be
1301 * fragmented over two IP datagrams, the latter
1302 * containing only one byte of data. The 82550 will
1303 * botch the header checksum on the 1-byte fragment.
1304 * As long as the datagram contains 4 or more bytes
1305 * of data, you're ok.
1306 *
1307 * The following code attempts to work around this
1308 * problem: if the datagram is less than 38 bytes
1309 * in size (14 bytes ether header, 20 bytes IP header,
1310 * plus 4 bytes of data), we punt and compute the IP
1311 * header checksum by hand. This workaround doesn't
1312 * work very well, however, since it can be fooled
1313 * by things like VLAN tags and IP options that make
1314 * the header sizes/offsets vary.
1315 */
1316
1317 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) {
1318 if (mb_head->m_pkthdr.len < 38) {
1319 struct ip *ip;
1320 mb_head->m_data += ETHER_HDR_LEN;
1321 ip = mtod(mb_head, struct ip *);
1322 ip->ip_sum = in_cksum(mb_head,
1323 ip->ip_hl << 2);
1324 mb_head->m_data -= ETHER_HDR_LEN;
1325 } else {
1326 txp->tx_cb->ipcb_ip_activation_high =
1327 FXP_IPCB_HARDWAREPARSING_ENABLE;
1328 txp->tx_cb->ipcb_ip_schedule |=
1329 FXP_IPCB_IP_CHECKSUM_ENABLE;
1330 }
1331 }
1332#endif
1333 }
1334
1335 /*
1336 * Go through each of the mbufs in the chain and initialize
1337 * the transmit buffer descriptors with the physical address
1338 * and size of the mbuf.
1339 */
1340 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1341 mb_head, fxp_dma_map_txbuf, sc, 0);
1342
1343 if (error && error != EFBIG) {
1344 device_printf(sc->dev, "can't map mbuf (error %d)\n",
1345 error);
1346 m_freem(mb_head);
1347 break;
1348 }
1349
1350 if (error) {
1351 struct mbuf *mn;
1352
1353 /*
1354 * We ran out of segments. We have to recopy this
1355 * mbuf chain first. Bail out if we can't get the
1356 * new buffers.
1357 */
1358 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1359 if (mn == NULL) {
1360 m_freem(mb_head);
1361 break;
1362 }
1363 if (mb_head->m_pkthdr.len > MHLEN) {
1364 MCLGET(mn, M_DONTWAIT);
1365 if ((mn->m_flags & M_EXT) == 0) {
1366 m_freem(mn);
1367 m_freem(mb_head);
1368 break;
1369 }
1370 }
1371 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1372 mtod(mn, caddr_t));
1373 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1374 m_freem(mb_head);
1375 mb_head = mn;
1376 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map,
1377 mb_head, fxp_dma_map_txbuf, sc, 0);
1378 if (error) {
1379 device_printf(sc->dev,
1380 "can't map mbuf (error %d)\n", error);
1381 m_freem(mb_head);
1382 break;
1383 }
1384 }
1385
1386 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1387 BUS_DMASYNC_PREWRITE);
1388
1389 txp->tx_mbuf = mb_head;
1390 txp->tx_cb->cb_status = 0;
1391 txp->tx_cb->byte_count = 0;
1392 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1393 txp->tx_cb->cb_command =
1394 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1395 FXP_CB_COMMAND_S);
1396 } else {
1397 txp->tx_cb->cb_command =
1398 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1399 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1400 /*
1401 * Set a 5 second timer just in case we don't hear
1402 * from the card again.
1403 */
1404 ifp->if_timer = 5;
1405 }
1406 txp->tx_cb->tx_threshold = tx_threshold;
1407
1408 /*
1409 * Advance the end of list forward.
1410 */
1411
1412#ifdef __alpha__
1413 /*
1414 * On platforms which can't access memory in 16-bit
1415 * granularities, we must prevent the card from DMA'ing
1416 * up the status while we update the command field.
1417 * This could cause us to overwrite the completion status.
1418 * XXX This is probably bogus and we're _not_ looking
1419 * for atomicity here.
1420 */
1421 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1422 htole16(FXP_CB_COMMAND_S));
1423#else
1424 sc->fxp_desc.tx_last->tx_cb->cb_command &=
1425 htole16(~FXP_CB_COMMAND_S);
1426#endif /*__alpha__*/
1427 sc->fxp_desc.tx_last = txp;
1428
1429 /*
1430 * Advance the beginning of the list forward if there are
1431 * no other packets queued (when nothing is queued, tx_first
1432 * sits on the last TxCB that was sent out).
1433 */
1434 if (sc->tx_queued == 0)
1435 sc->fxp_desc.tx_first = txp;
1436
1437 sc->tx_queued++;
1438
1439 /*
1440 * Pass packet to bpf if there is a listener.
1441 */
1442 BPF_MTAP(ifp, mb_head);
1443 }
1444 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1445
1446 /*
1447 * We're finished. If we added to the list, issue a RESUME to get DMA
1448 * going again if suspended.
1449 */
1450 if (txp != NULL) {
1451 fxp_scb_wait(sc);
1452 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1453 }
1454}
1455
1456#ifdef DEVICE_POLLING
1457static poll_handler_t fxp_poll;
1458
1459static void
1460fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1461{
1462 struct fxp_softc *sc = ifp->if_softc;
1463 u_int8_t statack;
1464
1465 FXP_LOCK(sc);
1466 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1467 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1468 FXP_UNLOCK(sc);
1469 return;
1470 }
1471 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1472 FXP_SCB_STATACK_FR;
1473 if (cmd == POLL_AND_CHECK_STATUS) {
1474 u_int8_t tmp;
1475
1476 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1477 if (tmp == 0xff || tmp == 0) {
1478 FXP_UNLOCK(sc);
1479 return; /* nothing to do */
1480 }
1481 tmp &= ~statack;
1482 /* ack what we can */
1483 if (tmp != 0)
1484 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1485 statack |= tmp;
1486 }
1487 fxp_intr_body(sc, ifp, statack, count);
1488 FXP_UNLOCK(sc);
1489}
1490#endif /* DEVICE_POLLING */
1491
1492/*
1493 * Process interface interrupts.
1494 */
1495static void
1496fxp_intr(void *xsc)
1497{
1498 struct fxp_softc *sc = xsc;
1499 struct ifnet *ifp = &sc->sc_if;
1500 u_int8_t statack;
1501
1502 FXP_LOCK(sc);
1503 if (sc->suspended) {
1504 FXP_UNLOCK(sc);
1505 return;
1506 }
1507
1508#ifdef DEVICE_POLLING
1509 if (ifp->if_flags & IFF_POLLING) {
1510 FXP_UNLOCK(sc);
1511 return;
1512 }
1513 if (ether_poll_register(fxp_poll, ifp)) {
1514 /* disable interrupts */
1515 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1516 fxp_poll(ifp, 0, 1);
1517 FXP_UNLOCK(sc);
1518 return;
1519 }
1520#endif
1521 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1522 /*
1523 * It should not be possible to have all bits set; the
1524 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1525 * all bits are set, this may indicate that the card has
1526 * been physically ejected, so ignore it.
1527 */
1528 if (statack == 0xff) {
1529 FXP_UNLOCK(sc);
1530 return;
1531 }
1532
1533 /*
1534 * First ACK all the interrupts in this pass.
1535 */
1536 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1537 fxp_intr_body(sc, ifp, statack, -1);
1538 }
1539 FXP_UNLOCK(sc);
1540}
1541
1542static void
1543fxp_txeof(struct fxp_softc *sc)
1544{
1545 struct fxp_tx *txp;
1546
1547 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1548 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1549 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1550 txp = txp->tx_next) {
1551 if (txp->tx_mbuf != NULL) {
1552 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1553 BUS_DMASYNC_POSTWRITE);
1554 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1555 m_freem(txp->tx_mbuf);
1556 txp->tx_mbuf = NULL;
1557 /* clear this to reset csum offload bits */
1558 txp->tx_cb->tbd[0].tb_addr = 0;
1559 }
1560 sc->tx_queued--;
1561 }
1562 sc->fxp_desc.tx_first = txp;
1563 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1564}
1565
1566static void
1567fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack,
1568 int count)
1569{
1570 struct mbuf *m;
1571 struct fxp_rx *rxp;
1572 struct fxp_rfa *rfa;
1573 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1574
1575 mtx_assert(&sc->sc_mtx, MA_OWNED);
1576 if (rnr)
1577 fxp_rnr++;
1578#ifdef DEVICE_POLLING
1579 /* Pick up a deferred RNR condition if `count' ran out last time. */
1580 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1581 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1582 rnr = 1;
1583 }
1584#endif
1585
1586 /*
1587 * Free any finished transmit mbuf chains.
1588 *
1589 * Handle the CNA event likt a CXTNO event. It used to
1590 * be that this event (control unit not ready) was not
1591 * encountered, but it is now with the SMPng modifications.
1592 * The exact sequence of events that occur when the interface
1593 * is brought up are different now, and if this event
1594 * goes unhandled, the configuration/rxfilter setup sequence
1595 * can stall for several seconds. The result is that no
1596 * packets go out onto the wire for about 5 to 10 seconds
1597 * after the interface is ifconfig'ed for the first time.
1598 */
1599 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1600 fxp_txeof(sc);
1601
1602 ifp->if_timer = 0;
1603 if (sc->tx_queued == 0) {
1604 if (sc->need_mcsetup)
1605 fxp_mc_setup(sc);
1606 }
1607 /*
1608 * Try to start more packets transmitting.
1609 */
1610 if (ifp->if_snd.ifq_head != NULL)
1611 fxp_start_body(ifp);
1612 }
1613
1614 /*
1615 * Just return if nothing happened on the receive side.
1616 */
1617 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1618 return;
1619
1620 /*
1621 * Process receiver interrupts. If a no-resource (RNR)
1622 * condition exists, get whatever packets we can and
1623 * re-start the receiver.
1624 *
1625 * When using polling, we do not process the list to completion,
1626 * so when we get an RNR interrupt we must defer the restart
1627 * until we hit the last buffer with the C bit set.
1628 * If we run out of cycles and rfa_headm has the C bit set,
1629 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1630 * that the info will be used in the subsequent polling cycle.
1631 */
1632 for (;;) {
1633 rxp = sc->fxp_desc.rx_head;
1634 m = rxp->rx_mbuf;
1635 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1636 RFA_ALIGNMENT_FUDGE);
1637 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1638 BUS_DMASYNC_POSTREAD);
1639
1640#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1641 if (count >= 0 && count-- == 0) {
1642 if (rnr) {
1643 /* Defer RNR processing until the next time. */
1644 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1645 rnr = 0;
1646 }
1647 break;
1648 }
1649#endif /* DEVICE_POLLING */
1650
1651 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0)
1652 break;
1653
1654 /*
1655 * Advance head forward.
1656 */
1657 sc->fxp_desc.rx_head = rxp->rx_next;
1658
1659 /*
1660 * Add a new buffer to the receive chain.
1661 * If this fails, the old buffer is recycled
1662 * instead.
1663 */
1664 if (fxp_add_rfabuf(sc, rxp) == 0) {
1665 int total_len;
1666
1667 /*
1668 * Fetch packet length (the top 2 bits of
1669 * actual_size are flags set by the controller
1670 * upon completion), and drop the packet in case
1671 * of bogus length or CRC errors.
1672 */
1673 total_len = le16toh(rfa->actual_size) & 0x3fff;
1674 if (total_len < sizeof(struct ether_header) ||
1675 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1676 sc->rfa_size ||
1677 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) {
1678 m_freem(m);
1679 continue;
1680 }
1681
1682 /* Do IP checksum checking. */
1683 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) {
1684 if (rfa->rfax_csum_sts &
1685 FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1686 m->m_pkthdr.csum_flags |=
1687 CSUM_IP_CHECKED;
1688 if (rfa->rfax_csum_sts &
1689 FXP_RFDX_CS_IP_CSUM_VALID)
1690 m->m_pkthdr.csum_flags |=
1691 CSUM_IP_VALID;
1692 if ((rfa->rfax_csum_sts &
1693 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1694 (rfa->rfax_csum_sts &
1695 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1696 m->m_pkthdr.csum_flags |=
1697 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1698 m->m_pkthdr.csum_data = 0xffff;
1699 }
1700 }
1701
1702 m->m_pkthdr.len = m->m_len = total_len;
1703 m->m_pkthdr.rcvif = ifp;
1704
1705 (*ifp->if_input)(ifp, m);
1706 }
1707 }
1708 if (rnr) {
1709 fxp_scb_wait(sc);
1710 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1711 sc->fxp_desc.rx_head->rx_addr);
1712 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1713 }
1714}
1715
1716/*
1717 * Update packet in/out/collision statistics. The i82557 doesn't
1718 * allow you to access these counters without doing a fairly
1719 * expensive DMA to get _all_ of the statistics it maintains, so
1720 * we do this operation here only once per second. The statistics
1721 * counters in the kernel are updated from the previous dump-stats
1722 * DMA and then a new dump-stats DMA is started. The on-chip
1723 * counters are zeroed when the DMA completes. If we can't start
1724 * the DMA immediately, we don't wait - we just prepare to read
1725 * them again next time.
1726 */
1727static void
1728fxp_tick(void *xsc)
1729{
1730 struct fxp_softc *sc = xsc;
1731 struct ifnet *ifp = &sc->sc_if;
1732 struct fxp_stats *sp = sc->fxp_stats;
1733 int s;
1734
1735 FXP_LOCK(sc);
1736 s = splimp();
1737 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1738 ifp->if_opackets += le32toh(sp->tx_good);
1739 ifp->if_collisions += le32toh(sp->tx_total_collisions);
1740 if (sp->rx_good) {
1741 ifp->if_ipackets += le32toh(sp->rx_good);
1742 sc->rx_idle_secs = 0;
1743 } else {
1744 /*
1745 * Receiver's been idle for another second.
1746 */
1747 sc->rx_idle_secs++;
1748 }
1749 ifp->if_ierrors +=
1750 le32toh(sp->rx_crc_errors) +
1751 le32toh(sp->rx_alignment_errors) +
1752 le32toh(sp->rx_rnr_errors) +
1753 le32toh(sp->rx_overrun_errors);
1754 /*
1755 * If any transmit underruns occured, bump up the transmit
1756 * threshold by another 512 bytes (64 * 8).
1757 */
1758 if (sp->tx_underruns) {
1759 ifp->if_oerrors += le32toh(sp->tx_underruns);
1760 if (tx_threshold < 192)
1761 tx_threshold += 64;
1762 }
1763
1764 /*
1765 * Release any xmit buffers that have completed DMA. This isn't
1766 * strictly necessary to do here, but it's advantagous for mbufs
1767 * with external storage to be released in a timely manner rather
1768 * than being defered for a potentially long time. This limits
1769 * the delay to a maximum of one second.
1770 */
1771 fxp_txeof(sc);
1772
1773 /*
1774 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1775 * then assume the receiver has locked up and attempt to clear
1776 * the condition by reprogramming the multicast filter. This is
1777 * a work-around for a bug in the 82557 where the receiver locks
1778 * up if it gets certain types of garbage in the syncronization
1779 * bits prior to the packet header. This bug is supposed to only
1780 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1781 * mode as well (perhaps due to a 10/100 speed transition).
1782 */
1783 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1784 sc->rx_idle_secs = 0;
1785 fxp_mc_setup(sc);
1786 }
1787 /*
1788 * If there is no pending command, start another stats
1789 * dump. Otherwise punt for now.
1790 */
1791 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1792 /*
1793 * Start another stats dump.
1794 */
1795 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
1796 BUS_DMASYNC_PREREAD);
1797 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1798 } else {
1799 /*
1800 * A previous command is still waiting to be accepted.
1801 * Just zero our copy of the stats and wait for the
1802 * next timer event to update them.
1803 */
1804 sp->tx_good = 0;
1805 sp->tx_underruns = 0;
1806 sp->tx_total_collisions = 0;
1807
1808 sp->rx_good = 0;
1809 sp->rx_crc_errors = 0;
1810 sp->rx_alignment_errors = 0;
1811 sp->rx_rnr_errors = 0;
1812 sp->rx_overrun_errors = 0;
1813 }
1814 if (sc->miibus != NULL)
1815 mii_tick(device_get_softc(sc->miibus));
1816
1817 /*
1818 * Schedule another timeout one second from now.
1819 */
1820 sc->stat_ch = timeout(fxp_tick, sc, hz);
1821 FXP_UNLOCK(sc);
1822 splx(s);
1823}
1824
1825/*
1826 * Stop the interface. Cancels the statistics updater and resets
1827 * the interface.
1828 */
1829static void
1830fxp_stop(struct fxp_softc *sc)
1831{
1832 struct ifnet *ifp = &sc->sc_if;
1833 struct fxp_tx *txp;
1834 int i;
1835
1836 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1837 ifp->if_timer = 0;
1838
1839#ifdef DEVICE_POLLING
1840 ether_poll_deregister(ifp);
1841#endif
1842 /*
1843 * Cancel stats updater.
1844 */
1845 untimeout(fxp_tick, sc, sc->stat_ch);
1846
1847 /*
1848 * Issue software reset, which also unloads the microcode.
1849 */
1850 sc->flags &= ~FXP_FLAG_UCODE;
1851 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1852 DELAY(50);
1853
1854 /*
1855 * Release any xmit buffers.
1856 */
1857 txp = sc->fxp_desc.tx_list;
1858 if (txp != NULL) {
1859 for (i = 0; i < FXP_NTXCB; i++) {
1860 if (txp[i].tx_mbuf != NULL) {
1861 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
1862 BUS_DMASYNC_POSTWRITE);
1863 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
1864 m_freem(txp[i].tx_mbuf);
1865 txp[i].tx_mbuf = NULL;
1866 /* clear this to reset csum offload bits */
1867 txp[i].tx_cb->tbd[0].tb_addr = 0;
1868 }
1869 }
1870 }
1871 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1872 sc->tx_queued = 0;
1873}
1874
1875/*
1876 * Watchdog/transmission transmit timeout handler. Called when a
1877 * transmission is started on the interface, but no interrupt is
1878 * received before the timeout. This usually indicates that the
1879 * card has wedged for some reason.
1880 */
1881static void
1882fxp_watchdog(struct ifnet *ifp)
1883{
1884 struct fxp_softc *sc = ifp->if_softc;
1885
1886 FXP_LOCK(sc);
1887 device_printf(sc->dev, "device timeout\n");
1888 ifp->if_oerrors++;
1889
1890 fxp_init_body(sc);
1891 FXP_UNLOCK(sc);
1892}
1893
1894/*
1895 * Acquire locks and then call the real initialization function. This
1896 * is necessary because ether_ioctl() calls if_init() and this would
1897 * result in mutex recursion if the mutex was held.
1898 */
1899static void
1900fxp_init(void *xsc)
1901{
1902 struct fxp_softc *sc = xsc;
1903
1904 FXP_LOCK(sc);
1905 fxp_init_body(sc);
1906 FXP_UNLOCK(sc);
1907}
1908
1909/*
1910 * Perform device initialization. This routine must be called with the
1911 * softc lock held.
1912 */
1913static void
1914fxp_init_body(struct fxp_softc *sc)
1915{
1916 struct ifnet *ifp = &sc->sc_if;
1917 struct fxp_cb_config *cbp;
1918 struct fxp_cb_ias *cb_ias;
1919 struct fxp_cb_tx *tcbp;
1920 struct fxp_tx *txp;
1921 struct fxp_cb_mcs *mcsp;
1922 int i, prm, s;
1923
1924 mtx_assert(&sc->sc_mtx, MA_OWNED);
1925 s = splimp();
1926 /*
1927 * Cancel any pending I/O
1928 */
1929 fxp_stop(sc);
1930
1931 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1932
1933 /*
1934 * Initialize base of CBL and RFA memory. Loading with zero
1935 * sets it up for regular linear addressing.
1936 */
1937 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1938 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1939
1940 fxp_scb_wait(sc);
1941 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1942
1943 /*
1944 * Initialize base of dump-stats buffer.
1945 */
1946 fxp_scb_wait(sc);
1947 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
1948 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
1949 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1950
1951 /*
1952 * Attempt to load microcode if requested.
1953 */
1954 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1955 fxp_load_ucode(sc);
1956
1957 /*
1958 * Initialize the multicast address list.
1959 */
1960 if (fxp_mc_addrs(sc)) {
1961 mcsp = sc->mcsp;
1962 mcsp->cb_status = 0;
1963 mcsp->cb_command =
1964 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
1965 mcsp->link_addr = 0xffffffff;
1966 /*
1967 * Start the multicast setup command.
1968 */
1969 fxp_scb_wait(sc);
1970 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
1971 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
1972 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1973 /* ...and wait for it to complete. */
1974 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
1975 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
1976 BUS_DMASYNC_POSTWRITE);
1977 }
1978
1979 /*
1980 * We temporarily use memory that contains the TxCB list to
1981 * construct the config CB. The TxCB list memory is rebuilt
1982 * later.
1983 */
1984 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
1985
1986 /*
1987 * This bcopy is kind of disgusting, but there are a bunch of must be
1988 * zero and must be one bits in this structure and this is the easiest
1989 * way to initialize them all to proper values.
1990 */
1991 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
1992
1993 cbp->cb_status = 0;
1994 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
1995 FXP_CB_COMMAND_EL);
1996 cbp->link_addr = 0xffffffff; /* (no) next command */
1997 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
1998 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1999 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2000 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2001 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2002 cbp->type_enable = 0; /* actually reserved */
2003 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2004 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2005 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2006 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2007 cbp->dma_mbce = 0; /* (disable) dma max counters */
2008 cbp->late_scb = 0; /* (don't) defer SCB update */
2009 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2010 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2011 cbp->ci_int = 1; /* interrupt on CU idle */
2012 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2013 cbp->ext_stats_dis = 1; /* disable extended counters */
2014 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2015 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
2016 cbp->disc_short_rx = !prm; /* discard short packets */
2017 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2018 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2019 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
2020 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2021 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2022 cbp->csma_dis = 0; /* (don't) disable link */
2023 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
2024 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2025 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2026 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2027 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2028 cbp->nsai = 1; /* (don't) disable source addr insert */
2029 cbp->preamble_length = 2; /* (7 byte) preamble */
2030 cbp->loopback = 0; /* (don't) loopback */
2031 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2032 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2033 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2034 cbp->promiscuous = prm; /* promiscuous mode */
2035 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2036 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2037 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2038 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2039 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2040
2041 cbp->stripping = !prm; /* truncate rx packet to byte count */
2042 cbp->padding = 1; /* (do) pad short tx packets */
2043 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2044 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2045 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2046 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
2047 /* must set wake_en in PMCSR also */
2048 cbp->force_fdx = 0; /* (don't) force full duplex */
2049 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2050 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2051 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
2052 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2053
2054 if (sc->revision == FXP_REV_82557) {
2055 /*
2056 * The 82557 has no hardware flow control, the values
2057 * below are the defaults for the chip.
2058 */
2059 cbp->fc_delay_lsb = 0;
2060 cbp->fc_delay_msb = 0x40;
2061 cbp->pri_fc_thresh = 3;
2062 cbp->tx_fc_dis = 0;
2063 cbp->rx_fc_restop = 0;
2064 cbp->rx_fc_restart = 0;
2065 cbp->fc_filter = 0;
2066 cbp->pri_fc_loc = 1;
2067 } else {
2068 cbp->fc_delay_lsb = 0x1f;
2069 cbp->fc_delay_msb = 0x01;
2070 cbp->pri_fc_thresh = 3;
2071 cbp->tx_fc_dis = 0; /* enable transmit FC */
2072 cbp->rx_fc_restop = 1; /* enable FC restop frames */
2073 cbp->rx_fc_restart = 1; /* enable FC restart frames */
2074 cbp->fc_filter = !prm; /* drop FC frames to host */
2075 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2076 }
2077
2078 /*
2079 * Start the config command/DMA.
2080 */
2081 fxp_scb_wait(sc);
2082 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2083 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2084 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2085 /* ...and wait for it to complete. */
2086 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2087 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2088
2089 /*
2090 * Now initialize the station address. Temporarily use the TxCB
2091 * memory area like we did above for the config CB.
2092 */
2093 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2094 cb_ias->cb_status = 0;
2095 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2096 cb_ias->link_addr = 0xffffffff;
2097 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr,
2098 sizeof(sc->arpcom.ac_enaddr));
2099
2100 /*
2101 * Start the IAS (Individual Address Setup) command/DMA.
2102 */
2103 fxp_scb_wait(sc);
2104 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2105 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2106 /* ...and wait for it to complete. */
2107 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2108 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2109
2110 /*
2111 * Initialize transmit control block (TxCB) list.
2112 */
2113 txp = sc->fxp_desc.tx_list;
2114 tcbp = sc->fxp_desc.cbl_list;
2115 bzero(tcbp, FXP_TXCB_SZ);
2116 for (i = 0; i < FXP_NTXCB; i++) {
2117 txp[i].tx_cb = tcbp + i;
2118 txp[i].tx_mbuf = NULL;
2119 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2120 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2121 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2122 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2123 if (sc->flags & FXP_FLAG_EXT_TXCB)
2124 tcbp[i].tbd_array_addr =
2125 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2126 else
2127 tcbp[i].tbd_array_addr =
2128 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2129 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2130 }
2131 /*
2132 * Set the suspend flag on the first TxCB and start the control
2133 * unit. It will execute the NOP and then suspend.
2134 */
2135 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2136 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2137 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2138 sc->tx_queued = 1;
2139
2140 fxp_scb_wait(sc);
2141 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2142
2143 /*
2144 * Initialize receiver buffer area - RFA.
2145 */
2146 fxp_scb_wait(sc);
2147 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2149
2150 /*
2151 * Set current media.
2152 */
2153 if (sc->miibus != NULL)
2154 mii_mediachg(device_get_softc(sc->miibus));
2155
2156 ifp->if_flags |= IFF_RUNNING;
2157 ifp->if_flags &= ~IFF_OACTIVE;
2158
2159 /*
2160 * Enable interrupts.
2161 */
2162#ifdef DEVICE_POLLING
2163 /*
2164 * ... but only do that if we are not polling. And because (presumably)
2165 * the default is interrupts on, we need to disable them explicitly!
2166 */
2167 if ( ifp->if_flags & IFF_POLLING )
2168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2169 else
2170#endif /* DEVICE_POLLING */
2171 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2172
2173 /*
2174 * Start stats updater.
2175 */
2176 sc->stat_ch = timeout(fxp_tick, sc, hz);
2177 splx(s);
2178}
2179
2180static int
2181fxp_serial_ifmedia_upd(struct ifnet *ifp)
2182{
2183
2184 return (0);
2185}
2186
2187static void
2188fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2189{
2190
2191 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2192}
2193
2194/*
2195 * Change media according to request.
2196 */
2197static int
2198fxp_ifmedia_upd(struct ifnet *ifp)
2199{
2200 struct fxp_softc *sc = ifp->if_softc;
2201 struct mii_data *mii;
2202
2203 mii = device_get_softc(sc->miibus);
2204 mii_mediachg(mii);
2205 return (0);
2206}
2207
2208/*
2209 * Notify the world which media we're using.
2210 */
2211static void
2212fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2213{
2214 struct fxp_softc *sc = ifp->if_softc;
2215 struct mii_data *mii;
2216
2217 mii = device_get_softc(sc->miibus);
2218 mii_pollstat(mii);
2219 ifmr->ifm_active = mii->mii_media_active;
2220 ifmr->ifm_status = mii->mii_media_status;
2221
2222 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
2223 sc->cu_resume_bug = 1;
2224 else
2225 sc->cu_resume_bug = 0;
2226}
2227
2228/*
2229 * Add a buffer to the end of the RFA buffer list.
2230 * Return 0 if successful, 1 for failure. A failure results in
2231 * adding the 'oldm' (if non-NULL) on to the end of the list -
2232 * tossing out its old contents and recycling it.
2233 * The RFA struct is stuck at the beginning of mbuf cluster and the
2234 * data pointer is fixed up to point just past it.
2235 */
2236static int
2237fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2238{
2239 struct mbuf *m;
2240 struct fxp_rfa *rfa, *p_rfa;
2241 struct fxp_rx *p_rx;
2242 bus_dmamap_t tmp_map;
2243 int error;
2244
2245 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2246 if (m == NULL)
2247 return (ENOBUFS);
2248
2249 /*
2250 * Move the data pointer up so that the incoming data packet
2251 * will be 32-bit aligned.
2252 */
2253 m->m_data += RFA_ALIGNMENT_FUDGE;
2254
2255 /*
2256 * Get a pointer to the base of the mbuf cluster and move
2257 * data start past it.
2258 */
2259 rfa = mtod(m, struct fxp_rfa *);
2260 m->m_data += sc->rfa_size;
2261 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2262
2263 /*
2264 * Initialize the rest of the RFA. Note that since the RFA
2265 * is misaligned, we cannot store values directly. Instead,
2266 * we use an optimized, inline copy.
2267 */
2268
2269 rfa->rfa_status = 0;
2270 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2271 rfa->actual_size = 0;
2272
2273 le32enc(&rfa->link_addr, 0xffffffff);
2274 le32enc(&rfa->rbd_addr, 0xffffffff);
2275
2276 /* Map the RFA into DMA memory. */
2277 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2278 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2279 &rxp->rx_addr, 0);
2280 if (error) {
2281 m_freem(m);
2282 return (error);
2283 }
2284
2285 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2286 tmp_map = sc->spare_map;
2287 sc->spare_map = rxp->rx_map;
2288 rxp->rx_map = tmp_map;
2289 rxp->rx_mbuf = m;
2290
2291 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2292 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2293
2294 /*
2295 * If there are other buffers already on the list, attach this
2296 * one to the end by fixing up the tail to point to this one.
2297 */
2298 if (sc->fxp_desc.rx_head != NULL) {
2299 p_rx = sc->fxp_desc.rx_tail;
2300 p_rfa = (struct fxp_rfa *)
2301 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2302 p_rx->rx_next = rxp;
2303 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2304 p_rfa->rfa_control = 0;
2305 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2306 BUS_DMASYNC_PREWRITE);
2307 } else {
2308 rxp->rx_next = NULL;
2309 sc->fxp_desc.rx_head = rxp;
2310 }
2311 sc->fxp_desc.rx_tail = rxp;
2312 return (0);
2313}
2314
2315static volatile int
2316fxp_miibus_readreg(device_t dev, int phy, int reg)
2317{
2318 struct fxp_softc *sc = device_get_softc(dev);
2319 int count = 10000;
2320 int value;
2321
2322 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2323 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2324
2325 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2326 && count--)
2327 DELAY(10);
2328
2329 if (count <= 0)
2330 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2331
2332 return (value & 0xffff);
2333}
2334
2335static void
2336fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2337{
2338 struct fxp_softc *sc = device_get_softc(dev);
2339 int count = 10000;
2340
2341 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2342 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2343 (value & 0xffff));
2344
2345 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2346 count--)
2347 DELAY(10);
2348
2349 if (count <= 0)
2350 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2351}
2352
2353static int
2354fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2355{
2356 struct fxp_softc *sc = ifp->if_softc;
2357 struct ifreq *ifr = (struct ifreq *)data;
2358 struct mii_data *mii;
2359 int s, error = 0;
2360
2361 /*
2362 * Detaching causes us to call ioctl with the mutex owned. Preclude
2363 * that by saying we're busy if the lock is already held.
2364 */
2365 if (mtx_owned(&sc->sc_mtx))
2366 return (EBUSY);
2367
2368 FXP_LOCK(sc);
2369 s = splimp();
2370
2371 switch (command) {
2372 case SIOCSIFFLAGS:
2373 if (ifp->if_flags & IFF_ALLMULTI)
2374 sc->flags |= FXP_FLAG_ALL_MCAST;
2375 else
2376 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2377
2378 /*
2379 * If interface is marked up and not running, then start it.
2380 * If it is marked down and running, stop it.
2381 * XXX If it's up then re-initialize it. This is so flags
2382 * such as IFF_PROMISC are handled.
2383 */
2384 if (ifp->if_flags & IFF_UP) {
2385 fxp_init_body(sc);
2386 } else {
2387 if (ifp->if_flags & IFF_RUNNING)
2388 fxp_stop(sc);
2389 }
2390 break;
2391
2392 case SIOCADDMULTI:
2393 case SIOCDELMULTI:
2394 if (ifp->if_flags & IFF_ALLMULTI)
2395 sc->flags |= FXP_FLAG_ALL_MCAST;
2396 else
2397 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2398 /*
2399 * Multicast list has changed; set the hardware filter
2400 * accordingly.
2401 */
2402 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2403 fxp_mc_setup(sc);
2404 /*
2405 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2406 * again rather than else {}.
2407 */
2408 if (sc->flags & FXP_FLAG_ALL_MCAST)
2409 fxp_init_body(sc);
2410 error = 0;
2411 break;
2412
2413 case SIOCSIFMEDIA:
2414 case SIOCGIFMEDIA:
2415 if (sc->miibus != NULL) {
2416 mii = device_get_softc(sc->miibus);
2417 error = ifmedia_ioctl(ifp, ifr,
2418 &mii->mii_media, command);
2419 } else {
2420 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2421 }
2422 break;
2423
2424 default:
2425 /*
2426 * ether_ioctl() will eventually call fxp_start() which
2427 * will result in mutex recursion so drop it first.
2428 */
2429 FXP_UNLOCK(sc);
2430 error = ether_ioctl(ifp, command, data);
2431 }
2432 if (mtx_owned(&sc->sc_mtx))
2433 FXP_UNLOCK(sc);
2434 splx(s);
2435 return (error);
2436}
2437
2438/*
2439 * Fill in the multicast address list and return number of entries.
2440 */
2441static int
2442fxp_mc_addrs(struct fxp_softc *sc)
2443{
2444 struct fxp_cb_mcs *mcsp = sc->mcsp;
2445 struct ifnet *ifp = &sc->sc_if;
2446 struct ifmultiaddr *ifma;
2447 int nmcasts;
2448
2449 nmcasts = 0;
2450 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2451#if __FreeBSD_version < 500000
2452 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2453#else
2454 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2455#endif
2456 if (ifma->ifma_addr->sa_family != AF_LINK)
2457 continue;
2458 if (nmcasts >= MAXMCADDR) {
2459 sc->flags |= FXP_FLAG_ALL_MCAST;
2460 nmcasts = 0;
2461 break;
2462 }
2463 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2464 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2465 nmcasts++;
2466 }
2467 }
2468 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2469 return (nmcasts);
2470}
2471
2472/*
2473 * Program the multicast filter.
2474 *
2475 * We have an artificial restriction that the multicast setup command
2476 * must be the first command in the chain, so we take steps to ensure
2477 * this. By requiring this, it allows us to keep up the performance of
2478 * the pre-initialized command ring (esp. link pointers) by not actually
2479 * inserting the mcsetup command in the ring - i.e. its link pointer
2480 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2481 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2482 * lead into the regular TxCB ring when it completes.
2483 *
2484 * This function must be called at splimp.
2485 */
2486static void
2487fxp_mc_setup(struct fxp_softc *sc)
2488{
2489 struct fxp_cb_mcs *mcsp = sc->mcsp;
2490 struct ifnet *ifp = &sc->sc_if;
2491 struct fxp_tx *txp;
2492 int count;
2493
2494 /*
2495 * If there are queued commands, we must wait until they are all
2496 * completed. If we are already waiting, then add a NOP command
2497 * with interrupt option so that we're notified when all commands
2498 * have been completed - fxp_start() ensures that no additional
2499 * TX commands will be added when need_mcsetup is true.
2500 */
2501 if (sc->tx_queued) {
2502 /*
2503 * need_mcsetup will be true if we are already waiting for the
2504 * NOP command to be completed (see below). In this case, bail.
2505 */
2506 if (sc->need_mcsetup)
2507 return;
2508 sc->need_mcsetup = 1;
2509
2510 /*
2511 * Add a NOP command with interrupt so that we are notified
2512 * when all TX commands have been processed.
2513 */
2514 txp = sc->fxp_desc.tx_last->tx_next;
2515 txp->tx_mbuf = NULL;
2516 txp->tx_cb->cb_status = 0;
2517 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2518 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2519 /*
2520 * Advance the end of list forward.
2521 */
2522 sc->fxp_desc.tx_last->tx_cb->cb_command &=
2523 htole16(~FXP_CB_COMMAND_S);
2524 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2525 sc->fxp_desc.tx_last = txp;
2526 sc->tx_queued++;
2527 /*
2528 * Issue a resume in case the CU has just suspended.
2529 */
2530 fxp_scb_wait(sc);
2531 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2532 /*
2533 * Set a 5 second timer just in case we don't hear from the
2534 * card again.
2535 */
2536 ifp->if_timer = 5;
2537
2538 return;
2539 }
2540 sc->need_mcsetup = 0;
2541
2542 /*
2543 * Initialize multicast setup descriptor.
2544 */
2545 mcsp->cb_status = 0;
2546 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2547 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2548 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2549 txp = &sc->fxp_desc.mcs_tx;
2550 txp->tx_mbuf = NULL;
2551 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2552 txp->tx_next = sc->fxp_desc.tx_list;
2553 (void) fxp_mc_addrs(sc);
2554 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2555 sc->tx_queued = 1;
2556
2557 /*
2558 * Wait until command unit is not active. This should never
2559 * be the case when nothing is queued, but make sure anyway.
2560 */
2561 count = 100;
2562 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2563 FXP_SCB_CUS_ACTIVE && --count)
2564 DELAY(10);
2565 if (count == 0) {
2566 device_printf(sc->dev, "command queue timeout\n");
2567 return;
2568 }
2569
2570 /*
2571 * Start the multicast setup command.
2572 */
2573 fxp_scb_wait(sc);
2574 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2575 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2576 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2577
2578 ifp->if_timer = 2;
2579 return;
2580}
2581
2582static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2583static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2584static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2585static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2586static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2587static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2588
2589#define UCODE(x) x, sizeof(x)
2590
2591struct ucode {
2592 u_int32_t revision;
2593 u_int32_t *ucode;
2594 int length;
2595 u_short int_delay_offset;
2596 u_short bundle_max_offset;
2597} ucode_table[] = {
2598 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2599 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2600 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2601 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2602 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2603 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2604 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2605 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2606 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2607 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2608 { 0, NULL, 0, 0, 0 }
2609};
2610
2611static void
2612fxp_load_ucode(struct fxp_softc *sc)
2613{
2614 struct ucode *uc;
2615 struct fxp_cb_ucode *cbp;
2616
2617 for (uc = ucode_table; uc->ucode != NULL; uc++)
2618 if (sc->revision == uc->revision)
2619 break;
2620 if (uc->ucode == NULL)
2621 return;
2622 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2623 cbp->cb_status = 0;
2624 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2625 cbp->link_addr = 0xffffffff; /* (no) next command */
2626 memcpy(cbp->ucode, uc->ucode, uc->length);
2627 if (uc->int_delay_offset)
2628 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] =
2629 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2630 if (uc->bundle_max_offset)
2631 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] =
2632 htole16(sc->tunable_bundle_max);
2633 /*
2634 * Download the ucode to the chip.
2635 */
2636 fxp_scb_wait(sc);
2637 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2638 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2639 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2640 /* ...and wait for it to complete. */
2641 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2642 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2643 device_printf(sc->dev,
2644 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2645 sc->tunable_int_delay,
2646 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2647 sc->flags |= FXP_FLAG_UCODE;
2648}
2649
2650static int
2651sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2652{
2653 int error, value;
2654
2655 value = *(int *)arg1;
2656 error = sysctl_handle_int(oidp, &value, 0, req);
2657 if (error || !req->newptr)
2658 return (error);
2659 if (value < low || value > high)
2660 return (EINVAL);
2661 *(int *)arg1 = value;
2662 return (0);
2663}
2664
2665/*
2666 * Interrupt delay is expressed in microseconds, a multiplier is used
2667 * to convert this to the appropriate clock ticks before using.
2668 */
2669static int
2670sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2671{
2672 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2673}
2674
2675static int
2676sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2677{
2678 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2679}