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fwohci.c (129541) fwohci.c (129585)
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 129541 2004-05-21 09:12:07Z dfr $
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 129585 2004-05-22 16:14:17Z dfr $
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

--- 46 unchanged lines hidden (view full) ---

89 "Undef","Undef","unknown event","flushed",
90 "Undef","ack complete","ack pend","Undef",
91 "ack busy_X","ack busy_A","ack busy_B","Undef",
92 "Undef","Undef","Undef","ack tardy",
93 "Undef","ack data_err","ack type_err",""};
94
95#define MAX_SPEED 3
96extern char *linkspeed[];
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

--- 46 unchanged lines hidden (view full) ---

89 "Undef","Undef","unknown event","flushed",
90 "Undef","ack complete","ack pend","Undef",
91 "ack busy_X","ack busy_A","ack busy_B","Undef",
92 "Undef","Undef","Undef","ack tardy",
93 "Undef","ack data_err","ack type_err",""};
94
95#define MAX_SPEED 3
96extern char *linkspeed[];
97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
97uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
98
99static struct tcode_info tinfo[] = {
100/* hdr_len block flag*/
101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
103/* 2 WRES */ {12, FWTI_RES},
104/* 3 XXX */ { 0, 0},
105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},

--- 19 unchanged lines hidden (view full) ---

125static void fwohci_ibr (struct firewire_comm *);
126static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
127static void fwohci_db_free (struct fwohci_dbch *);
128static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
129static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
130static void fwohci_start_atq (struct firewire_comm *);
131static void fwohci_start_ats (struct firewire_comm *);
132static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
98
99static struct tcode_info tinfo[] = {
100/* hdr_len block flag*/
101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
103/* 2 WRES */ {12, FWTI_RES},
104/* 3 XXX */ { 0, 0},
105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},

--- 19 unchanged lines hidden (view full) ---

125static void fwohci_ibr (struct firewire_comm *);
126static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
127static void fwohci_db_free (struct fwohci_dbch *);
128static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
129static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
130static void fwohci_start_atq (struct firewire_comm *);
131static void fwohci_start_ats (struct firewire_comm *);
132static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
133static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t);
134static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t);
133static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
134static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
135static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
136static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
137static int fwohci_irx_enable (struct firewire_comm *, int);
138static int fwohci_irx_disable (struct firewire_comm *, int);
139#if BYTE_ORDER == BIG_ENDIAN
135static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
136static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
137static int fwohci_irx_enable (struct firewire_comm *, int);
138static int fwohci_irx_disable (struct firewire_comm *, int);
139#if BYTE_ORDER == BIG_ENDIAN
140static void fwohci_irx_post (struct firewire_comm *, u_int32_t *);
140static void fwohci_irx_post (struct firewire_comm *, uint32_t *);
141#endif
142static int fwohci_itxbuf_enable (struct firewire_comm *, int);
143static int fwohci_itx_disable (struct firewire_comm *, int);
144static void fwohci_timeout (void *);
145static void fwohci_set_intr (struct firewire_comm *, int);
146
147static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
148static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
141#endif
142static int fwohci_itxbuf_enable (struct firewire_comm *, int);
143static int fwohci_itx_disable (struct firewire_comm *, int);
144static void fwohci_timeout (void *);
145static void fwohci_set_intr (struct firewire_comm *, int);
146
147static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
148static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
149static void dump_db (struct fwohci_softc *, u_int32_t);
150static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t);
151static void dump_dma (struct fwohci_softc *, u_int32_t);
152static u_int32_t fwohci_cyctimer (struct firewire_comm *);
149static void dump_db (struct fwohci_softc *, uint32_t);
150static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
151static void dump_dma (struct fwohci_softc *, uint32_t);
152static uint32_t fwohci_cyctimer (struct firewire_comm *);
153static void fwohci_rbuf_update (struct fwohci_softc *, int);
154static void fwohci_tbuf_update (struct fwohci_softc *, int);
155void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
156#if FWOHCI_TASKQUEUE
157static void fwohci_complete(void *, int);
158#endif
159
160/*

--- 92 unchanged lines hidden (view full) ---

253#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
254#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
255
256d_ioctl_t fwohci_ioctl;
257
258/*
259 * Communication with PHY device
260 */
153static void fwohci_rbuf_update (struct fwohci_softc *, int);
154static void fwohci_tbuf_update (struct fwohci_softc *, int);
155void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
156#if FWOHCI_TASKQUEUE
157static void fwohci_complete(void *, int);
158#endif
159
160/*

--- 92 unchanged lines hidden (view full) ---

253#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
254#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
255
256d_ioctl_t fwohci_ioctl;
257
258/*
259 * Communication with PHY device
260 */
261static u_int32_t
262fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
261static uint32_t
262fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
263{
263{
264 u_int32_t fun;
264 uint32_t fun;
265
266 addr &= 0xf;
267 data &= 0xff;
268
269 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
270 OWRITE(sc, OHCI_PHYACCESS, fun);
271 DELAY(100);
272
273 return(fwphy_rddata( sc, addr));
274}
275
265
266 addr &= 0xf;
267 data &= 0xff;
268
269 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
270 OWRITE(sc, OHCI_PHYACCESS, fun);
271 DELAY(100);
272
273 return(fwphy_rddata( sc, addr));
274}
275
276static u_int32_t
276static uint32_t
277fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
278{
279 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
280 int i;
277fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
278{
279 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
280 int i;
281 u_int32_t bm;
281 uint32_t bm;
282
283#define OHCI_CSR_DATA 0x0c
284#define OHCI_CSR_COMP 0x10
285#define OHCI_CSR_CONT 0x14
286#define OHCI_BUS_MANAGER_ID 0
287
288 OWRITE(sc, OHCI_CSR_DATA, node);
289 OWRITE(sc, OHCI_CSR_COMP, 0x3f);

--- 5 unchanged lines hidden (view full) ---

295 bm = node;
296 if (bootverbose)
297 device_printf(sc->fc.dev,
298 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
299
300 return(bm);
301}
302
282
283#define OHCI_CSR_DATA 0x0c
284#define OHCI_CSR_COMP 0x10
285#define OHCI_CSR_CONT 0x14
286#define OHCI_BUS_MANAGER_ID 0
287
288 OWRITE(sc, OHCI_CSR_DATA, node);
289 OWRITE(sc, OHCI_CSR_COMP, 0x3f);

--- 5 unchanged lines hidden (view full) ---

295 bm = node;
296 if (bootverbose)
297 device_printf(sc->fc.dev,
298 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
299
300 return(bm);
301}
302
303static u_int32_t
303static uint32_t
304fwphy_rddata(struct fwohci_softc *sc, u_int addr)
305{
304fwphy_rddata(struct fwohci_softc *sc, u_int addr)
305{
306 u_int32_t fun, stat;
306 uint32_t fun, stat;
307 u_int i, retry = 0;
308
309 addr &= 0xf;
310#define MAX_RETRY 100
311again:
312 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
313 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
314 OWRITE(sc, OHCI_PHYACCESS, fun);

--- 32 unchanged lines hidden (view full) ---

347int
348fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
349{
350 struct firewire_softc *sc;
351 struct fwohci_softc *fc;
352 int unit = DEV2UNIT(dev);
353 int err = 0;
354 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
307 u_int i, retry = 0;
308
309 addr &= 0xf;
310#define MAX_RETRY 100
311again:
312 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
313 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
314 OWRITE(sc, OHCI_PHYACCESS, fun);

--- 32 unchanged lines hidden (view full) ---

347int
348fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
349{
350 struct firewire_softc *sc;
351 struct fwohci_softc *fc;
352 int unit = DEV2UNIT(dev);
353 int err = 0;
354 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
355 u_int32_t *dmach = (u_int32_t *) data;
355 uint32_t *dmach = (uint32_t *) data;
356
357 sc = devclass_get_softc(firewire_devclass, unit);
358 if(sc == NULL){
359 return(EINVAL);
360 }
361 fc = (struct fwohci_softc *)sc->fc;
362
363 if (!data)

--- 44 unchanged lines hidden (view full) ---

408 break;
409 }
410 return err;
411}
412
413static int
414fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
415{
356
357 sc = devclass_get_softc(firewire_devclass, unit);
358 if(sc == NULL){
359 return(EINVAL);
360 }
361 fc = (struct fwohci_softc *)sc->fc;
362
363 if (!data)

--- 44 unchanged lines hidden (view full) ---

408 break;
409 }
410 return err;
411}
412
413static int
414fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
415{
416 u_int32_t reg, reg2;
416 uint32_t reg, reg2;
417 int e1394a = 1;
418/*
419 * probe PHY parameters
420 * 0. to prove PHY version, whether compliance of 1394a.
421 * 1. to probe maximum speed supported by the PHY and
422 * number of port supported by core-logic.
423 * It is not actually available port on your PC .
424 */

--- 58 unchanged lines hidden (view full) ---

483 return 0;
484}
485
486
487void
488fwohci_reset(struct fwohci_softc *sc, device_t dev)
489{
490 int i, max_rec, speed;
417 int e1394a = 1;
418/*
419 * probe PHY parameters
420 * 0. to prove PHY version, whether compliance of 1394a.
421 * 1. to probe maximum speed supported by the PHY and
422 * number of port supported by core-logic.
423 * It is not actually available port on your PC .
424 */

--- 58 unchanged lines hidden (view full) ---

483 return 0;
484}
485
486
487void
488fwohci_reset(struct fwohci_softc *sc, device_t dev)
489{
490 int i, max_rec, speed;
491 u_int32_t reg, reg2;
491 uint32_t reg, reg2;
492 struct fwohcidb_tr *db_tr;
493
494 /* Disable interrupts */
495 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
496
497 /* Now stopping all DMA channels */
498 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
499 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);

--- 89 unchanged lines hidden (view full) ---

589 fwohci_set_intr(&sc->fc, 1);
590
591}
592
593int
594fwohci_init(struct fwohci_softc *sc, device_t dev)
595{
596 int i, mver;
492 struct fwohcidb_tr *db_tr;
493
494 /* Disable interrupts */
495 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
496
497 /* Now stopping all DMA channels */
498 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
499 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);

--- 89 unchanged lines hidden (view full) ---

589 fwohci_set_intr(&sc->fc, 1);
590
591}
592
593int
594fwohci_init(struct fwohci_softc *sc, device_t dev)
595{
596 int i, mver;
597 u_int32_t reg;
598 u_int8_t ui[8];
597 uint32_t reg;
598 uint8_t ui[8];
599
600#if FWOHCI_TASKQUEUE
601 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
602#endif
603
604/* OHCI version */
605 reg = OREAD(sc, OHCI_VERSION);
606 mver = (reg >> 16) & 0xff;

--- 89 unchanged lines hidden (view full) ---

696#define OHCI_SIDSIZE (1 << 11)
697 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
698 &sc->sid_dma, BUS_DMA_WAITOK);
699 if (sc->sid_buf == NULL) {
700 device_printf(dev, "sid_buf alloc failed.");
701 return ENOMEM;
702 }
703
599
600#if FWOHCI_TASKQUEUE
601 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
602#endif
603
604/* OHCI version */
605 reg = OREAD(sc, OHCI_VERSION);
606 mver = (reg >> 16) & 0xff;

--- 89 unchanged lines hidden (view full) ---

696#define OHCI_SIDSIZE (1 << 11)
697 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
698 &sc->sid_dma, BUS_DMA_WAITOK);
699 if (sc->sid_buf == NULL) {
700 device_printf(dev, "sid_buf alloc failed.");
701 return ENOMEM;
702 }
703
704 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
704 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
705 &sc->dummy_dma, BUS_DMA_WAITOK);
706
707 if (sc->dummy_dma.v_addr == NULL) {
708 device_printf(dev, "dummy_dma alloc failed.");
709 return ENOMEM;
710 }
711
712 fwohci_db_init(sc, &sc->arrq);

--- 49 unchanged lines hidden (view full) ---

762void
763fwohci_timeout(void *arg)
764{
765 struct fwohci_softc *sc;
766
767 sc = (struct fwohci_softc *)arg;
768}
769
705 &sc->dummy_dma, BUS_DMA_WAITOK);
706
707 if (sc->dummy_dma.v_addr == NULL) {
708 device_printf(dev, "dummy_dma alloc failed.");
709 return ENOMEM;
710 }
711
712 fwohci_db_init(sc, &sc->arrq);

--- 49 unchanged lines hidden (view full) ---

762void
763fwohci_timeout(void *arg)
764{
765 struct fwohci_softc *sc;
766
767 sc = (struct fwohci_softc *)arg;
768}
769
770u_int32_t
770uint32_t
771fwohci_cyctimer(struct firewire_comm *fc)
772{
773 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
774 return(OREAD(sc, OHCI_CYCLETIMER));
775}
776
777int
778fwohci_detach(struct fwohci_softc *sc, device_t dev)

--- 58 unchanged lines hidden (view full) ---

837}
838
839static void
840fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
841{
842 int i, s;
843 int tcode, hdr_len, pl_off;
844 int fsegment = -1;
771fwohci_cyctimer(struct firewire_comm *fc)
772{
773 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
774 return(OREAD(sc, OHCI_CYCLETIMER));
775}
776
777int
778fwohci_detach(struct fwohci_softc *sc, device_t dev)

--- 58 unchanged lines hidden (view full) ---

837}
838
839static void
840fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
841{
842 int i, s;
843 int tcode, hdr_len, pl_off;
844 int fsegment = -1;
845 u_int32_t off;
845 uint32_t off;
846 struct fw_xfer *xfer;
847 struct fw_pkt *fp;
848 struct fwohci_txpkthdr *ohcifp;
849 struct fwohcidb_tr *db_tr;
850 struct fwohcidb *db;
846 struct fw_xfer *xfer;
847 struct fw_pkt *fp;
848 struct fwohci_txpkthdr *ohcifp;
849 struct fwohcidb_tr *db_tr;
850 struct fwohcidb *db;
851 u_int32_t *ld;
851 uint32_t *ld;
852 struct tcode_info *info;
853 static int maxdesc=0;
854
855 if(&sc->atrq == dbch){
856 off = OHCI_ATQOFF;
857 }else if(&sc->atrs == dbch){
858 off = OHCI_ATSOFF;
859 }else{

--- 172 unchanged lines hidden (view full) ---

1032
1033void
1034fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1035{
1036 int s, ch, err = 0;
1037 struct fwohcidb_tr *tr;
1038 struct fwohcidb *db;
1039 struct fw_xfer *xfer;
852 struct tcode_info *info;
853 static int maxdesc=0;
854
855 if(&sc->atrq == dbch){
856 off = OHCI_ATQOFF;
857 }else if(&sc->atrs == dbch){
858 off = OHCI_ATSOFF;
859 }else{

--- 172 unchanged lines hidden (view full) ---

1032
1033void
1034fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1035{
1036 int s, ch, err = 0;
1037 struct fwohcidb_tr *tr;
1038 struct fwohcidb *db;
1039 struct fw_xfer *xfer;
1040 u_int32_t off;
1040 uint32_t off;
1041 u_int stat, status;
1042 int packets;
1043 struct firewire_comm *fc = (struct firewire_comm *)sc;
1044
1045 if(&sc->atrq == dbch){
1046 off = OHCI_ATQOFF;
1047 ch = ATRQ_CH;
1048 }else if(&sc->atrs == dbch){

--- 257 unchanged lines hidden (view full) ---

1306 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1307 fwohci_db_free(&sc->ir[dmach]);
1308 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1309 return 0;
1310}
1311
1312#if BYTE_ORDER == BIG_ENDIAN
1313static void
1041 u_int stat, status;
1042 int packets;
1043 struct firewire_comm *fc = (struct firewire_comm *)sc;
1044
1045 if(&sc->atrq == dbch){
1046 off = OHCI_ATQOFF;
1047 ch = ATRQ_CH;
1048 }else if(&sc->atrs == dbch){

--- 257 unchanged lines hidden (view full) ---

1306 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1307 fwohci_db_free(&sc->ir[dmach]);
1308 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1309 return 0;
1310}
1311
1312#if BYTE_ORDER == BIG_ENDIAN
1313static void
1314fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1314fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1315{
1316 qld[0] = FWOHCI_DMA_READ(qld[0]);
1317 return;
1318}
1319#endif
1320
1321static int
1322fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1323{
1324 int err = 0;
1325 int idb, z, i, dmach = 0, ldesc;
1315{
1316 qld[0] = FWOHCI_DMA_READ(qld[0]);
1317 return;
1318}
1319#endif
1320
1321static int
1322fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1323{
1324 int err = 0;
1325 int idb, z, i, dmach = 0, ldesc;
1326 u_int32_t off = 0;
1326 uint32_t off = 0;
1327 struct fwohcidb_tr *db_tr;
1328 struct fwohcidb *db;
1329
1330 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1331 err = EINVAL;
1332 return err;
1333 }
1334 z = dbch->ndesc;

--- 42 unchanged lines hidden (view full) ---

1377 return err;
1378}
1379
1380static int
1381fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1382{
1383 int err = 0;
1384 int idb, z, i, dmach = 0, ldesc;
1327 struct fwohcidb_tr *db_tr;
1328 struct fwohcidb *db;
1329
1330 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1331 err = EINVAL;
1332 return err;
1333 }
1334 z = dbch->ndesc;

--- 42 unchanged lines hidden (view full) ---

1377 return err;
1378}
1379
1380static int
1381fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1382{
1383 int err = 0;
1384 int idb, z, i, dmach = 0, ldesc;
1385 u_int32_t off = 0;
1385 uint32_t off = 0;
1386 struct fwohcidb_tr *db_tr;
1387 struct fwohcidb *db;
1388
1389 z = dbch->ndesc;
1390 if(&sc->arrq == dbch){
1391 off = OHCI_ARQOFF;
1392 }else if(&sc->arrs == dbch){
1393 off = OHCI_ARSOFF;

--- 92 unchanged lines hidden (view full) ---

1486static int
1487fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1488{
1489 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1490 int err = 0;
1491 unsigned short tag, ich;
1492 struct fwohci_dbch *dbch;
1493 int cycle_match, cycle_now, s, ldesc;
1386 struct fwohcidb_tr *db_tr;
1387 struct fwohcidb *db;
1388
1389 z = dbch->ndesc;
1390 if(&sc->arrq == dbch){
1391 off = OHCI_ARQOFF;
1392 }else if(&sc->arrs == dbch){
1393 off = OHCI_ARSOFF;

--- 92 unchanged lines hidden (view full) ---

1486static int
1487fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1488{
1489 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1490 int err = 0;
1491 unsigned short tag, ich;
1492 struct fwohci_dbch *dbch;
1493 int cycle_match, cycle_now, s, ldesc;
1494 u_int32_t stat;
1494 uint32_t stat;
1495 struct fw_bulkxfer *first, *chunk, *prev;
1496 struct fw_xferq *it;
1497
1498 dbch = &sc->it[dmach];
1499 it = &dbch->xferq;
1500
1501 tag = (it->flag >> 6) & 3;
1502 ich = it->flag & 0x3f;

--- 99 unchanged lines hidden (view full) ---

1602}
1603
1604static int
1605fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1606{
1607 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1608 int err = 0, s, ldesc;
1609 unsigned short tag, ich;
1495 struct fw_bulkxfer *first, *chunk, *prev;
1496 struct fw_xferq *it;
1497
1498 dbch = &sc->it[dmach];
1499 it = &dbch->xferq;
1500
1501 tag = (it->flag >> 6) & 3;
1502 ich = it->flag & 0x3f;

--- 99 unchanged lines hidden (view full) ---

1602}
1603
1604static int
1605fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1606{
1607 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1608 int err = 0, s, ldesc;
1609 unsigned short tag, ich;
1610 u_int32_t stat;
1610 uint32_t stat;
1611 struct fwohci_dbch *dbch;
1612 struct fwohcidb_tr *db_tr;
1613 struct fw_bulkxfer *first, *prev, *chunk;
1614 struct fw_xferq *ir;
1615
1616 dbch = &sc->ir[dmach];
1617 ir = &dbch->xferq;
1618

--- 138 unchanged lines hidden (view full) ---

1757
1758 bus_generic_resume(dev);
1759 sc->fc.ibr(&sc->fc);
1760 return 0;
1761}
1762
1763#define ACK_ALL
1764static void
1611 struct fwohci_dbch *dbch;
1612 struct fwohcidb_tr *db_tr;
1613 struct fw_bulkxfer *first, *prev, *chunk;
1614 struct fw_xferq *ir;
1615
1616 dbch = &sc->ir[dmach];
1617 ir = &dbch->xferq;
1618

--- 138 unchanged lines hidden (view full) ---

1757
1758 bus_generic_resume(dev);
1759 sc->fc.ibr(&sc->fc);
1760 return 0;
1761}
1762
1763#define ACK_ALL
1764static void
1765fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1765fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
1766{
1766{
1767 u_int32_t irstat, itstat;
1767 uint32_t irstat, itstat;
1768 u_int i;
1769 struct firewire_comm *fc = (struct firewire_comm *)sc;
1770
1771#ifdef OHCI_DEBUG
1772 if(stat & OREAD(sc, FWOHCI_INTMASK))
1773 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1774 stat & OHCI_INT_EN ? "DMA_EN ":"",
1775 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",

--- 99 unchanged lines hidden (view full) ---

1875#endif
1876#if 0
1877 dump_dma(sc, ARRQ_CH);
1878 dump_db(sc, ARRQ_CH);
1879#endif
1880 fwohci_arcv(sc, &sc->arrq, count);
1881 }
1882 if(stat & OHCI_INT_PHY_SID){
1768 u_int i;
1769 struct firewire_comm *fc = (struct firewire_comm *)sc;
1770
1771#ifdef OHCI_DEBUG
1772 if(stat & OREAD(sc, FWOHCI_INTMASK))
1773 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1774 stat & OHCI_INT_EN ? "DMA_EN ":"",
1775 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",

--- 99 unchanged lines hidden (view full) ---

1875#endif
1876#if 0
1877 dump_dma(sc, ARRQ_CH);
1878 dump_db(sc, ARRQ_CH);
1879#endif
1880 fwohci_arcv(sc, &sc->arrq, count);
1881 }
1882 if(stat & OHCI_INT_PHY_SID){
1883 u_int32_t *buf, node_id;
1883 uint32_t *buf, node_id;
1884 int plen;
1885
1886#ifndef ACK_ALL
1887 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1888#endif
1889 /* Enable bus reset interrupt */
1890 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1891 /* Allow async. request to us */

--- 33 unchanged lines hidden (view full) ---

1925 goto sidout;
1926 }
1927 plen &= OHCI_SID_CNT_MASK;
1928 if (plen < 4 || plen > OHCI_SIDSIZE) {
1929 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1930 goto sidout;
1931 }
1932 plen -= 4; /* chop control info */
1884 int plen;
1885
1886#ifndef ACK_ALL
1887 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1888#endif
1889 /* Enable bus reset interrupt */
1890 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1891 /* Allow async. request to us */

--- 33 unchanged lines hidden (view full) ---

1925 goto sidout;
1926 }
1927 plen &= OHCI_SID_CNT_MASK;
1928 if (plen < 4 || plen > OHCI_SIDSIZE) {
1929 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1930 goto sidout;
1931 }
1932 plen -= 4; /* chop control info */
1933 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
1933 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
1934 if (buf == NULL) {
1935 device_printf(fc->dev, "malloc failed\n");
1936 goto sidout;
1937 }
1938 for (i = 0; i < plen / 4; i ++)
1939 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1940#if 1 /* XXX needed?? */
1941 /* pending all pre-bus_reset packets */

--- 41 unchanged lines hidden (view full) ---

1983 return;
1984}
1985
1986#if FWOHCI_TASKQUEUE
1987static void
1988fwohci_complete(void *arg, int pending)
1989{
1990 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1934 if (buf == NULL) {
1935 device_printf(fc->dev, "malloc failed\n");
1936 goto sidout;
1937 }
1938 for (i = 0; i < plen / 4; i ++)
1939 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1940#if 1 /* XXX needed?? */
1941 /* pending all pre-bus_reset packets */

--- 41 unchanged lines hidden (view full) ---

1983 return;
1984}
1985
1986#if FWOHCI_TASKQUEUE
1987static void
1988fwohci_complete(void *arg, int pending)
1989{
1990 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1991 u_int32_t stat;
1991 uint32_t stat;
1992
1993again:
1994 stat = atomic_readandclear_int(&sc->intstat);
1995 if (stat)
1996 fwohci_intr_body(sc, stat, -1);
1997 else
1998 return;
1999 goto again;
2000}
2001#endif
2002
1992
1993again:
1994 stat = atomic_readandclear_int(&sc->intstat);
1995 if (stat)
1996 fwohci_intr_body(sc, stat, -1);
1997 else
1998 return;
1999 goto again;
2000}
2001#endif
2002
2003static u_int32_t
2003static uint32_t
2004fwochi_check_stat(struct fwohci_softc *sc)
2005{
2004fwochi_check_stat(struct fwohci_softc *sc)
2005{
2006 u_int32_t stat, irstat, itstat;
2006 uint32_t stat, irstat, itstat;
2007
2008 stat = OREAD(sc, FWOHCI_INTSTAT);
2009 if (stat == 0xffffffff) {
2010 device_printf(sc->fc.dev,
2011 "device physically ejected?\n");
2012 return(stat);
2013 }
2014#ifdef ACK_ALL

--- 12 unchanged lines hidden (view full) ---

2027 }
2028 return(stat);
2029}
2030
2031void
2032fwohci_intr(void *arg)
2033{
2034 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2007
2008 stat = OREAD(sc, FWOHCI_INTSTAT);
2009 if (stat == 0xffffffff) {
2010 device_printf(sc->fc.dev,
2011 "device physically ejected?\n");
2012 return(stat);
2013 }
2014#ifdef ACK_ALL

--- 12 unchanged lines hidden (view full) ---

2027 }
2028 return(stat);
2029}
2030
2031void
2032fwohci_intr(void *arg)
2033{
2034 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2035 u_int32_t stat;
2035 uint32_t stat;
2036#if !FWOHCI_TASKQUEUE
2036#if !FWOHCI_TASKQUEUE
2037 u_int32_t bus_reset = 0;
2037 uint32_t bus_reset = 0;
2038#endif
2039
2040 if (!(sc->intmask & OHCI_INT_EN)) {
2041 /* polling mode */
2042 return;
2043 }
2044
2045#if !FWOHCI_TASKQUEUE

--- 16 unchanged lines hidden (view full) ---

2062 goto again;
2063#endif
2064}
2065
2066void
2067fwohci_poll(struct firewire_comm *fc, int quick, int count)
2068{
2069 int s;
2038#endif
2039
2040 if (!(sc->intmask & OHCI_INT_EN)) {
2041 /* polling mode */
2042 return;
2043 }
2044
2045#if !FWOHCI_TASKQUEUE

--- 16 unchanged lines hidden (view full) ---

2062 goto again;
2063#endif
2064}
2065
2066void
2067fwohci_poll(struct firewire_comm *fc, int quick, int count)
2068{
2069 int s;
2070 u_int32_t stat;
2070 uint32_t stat;
2071 struct fwohci_softc *sc;
2072
2073
2074 sc = (struct fwohci_softc *)fc;
2075 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2076 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2077 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2078#if 0

--- 29 unchanged lines hidden (view full) ---

2108
2109static void
2110fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2111{
2112 struct firewire_comm *fc = &sc->fc;
2113 struct fwohcidb *db;
2114 struct fw_bulkxfer *chunk;
2115 struct fw_xferq *it;
2071 struct fwohci_softc *sc;
2072
2073
2074 sc = (struct fwohci_softc *)fc;
2075 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2076 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2077 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2078#if 0

--- 29 unchanged lines hidden (view full) ---

2108
2109static void
2110fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2111{
2112 struct firewire_comm *fc = &sc->fc;
2113 struct fwohcidb *db;
2114 struct fw_bulkxfer *chunk;
2115 struct fw_xferq *it;
2116 u_int32_t stat, count;
2116 uint32_t stat, count;
2117 int s, w=0, ldesc;
2118
2119 it = fc->it[dmach];
2120 ldesc = sc->it[dmach].ndesc - 1;
2121 s = splfw(); /* unnecessary ? */
2122 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2123 if (firewire_debug)
2124 dump_db(sc, ITX_CH + dmach);

--- 29 unchanged lines hidden (view full) ---

2154
2155static void
2156fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2157{
2158 struct firewire_comm *fc = &sc->fc;
2159 struct fwohcidb_tr *db_tr;
2160 struct fw_bulkxfer *chunk;
2161 struct fw_xferq *ir;
2117 int s, w=0, ldesc;
2118
2119 it = fc->it[dmach];
2120 ldesc = sc->it[dmach].ndesc - 1;
2121 s = splfw(); /* unnecessary ? */
2122 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2123 if (firewire_debug)
2124 dump_db(sc, ITX_CH + dmach);

--- 29 unchanged lines hidden (view full) ---

2154
2155static void
2156fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2157{
2158 struct firewire_comm *fc = &sc->fc;
2159 struct fwohcidb_tr *db_tr;
2160 struct fw_bulkxfer *chunk;
2161 struct fw_xferq *ir;
2162 u_int32_t stat;
2162 uint32_t stat;
2163 int s, w=0, ldesc;
2164
2165 ir = fc->ir[dmach];
2166 ldesc = sc->ir[dmach].ndesc - 1;
2167#if 0
2168 dump_db(sc, dmach);
2169#endif
2170 s = splfw();

--- 36 unchanged lines hidden (view full) ---

2207 if (ir->flag & FWXFERQ_HANDLER)
2208 ir->hand(ir);
2209 else
2210 wakeup(ir);
2211 }
2212}
2213
2214void
2163 int s, w=0, ldesc;
2164
2165 ir = fc->ir[dmach];
2166 ldesc = sc->ir[dmach].ndesc - 1;
2167#if 0
2168 dump_db(sc, dmach);
2169#endif
2170 s = splfw();

--- 36 unchanged lines hidden (view full) ---

2207 if (ir->flag & FWXFERQ_HANDLER)
2208 ir->hand(ir);
2209 else
2210 wakeup(ir);
2211 }
2212}
2213
2214void
2215dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2215dump_dma(struct fwohci_softc *sc, uint32_t ch)
2216{
2216{
2217 u_int32_t off, cntl, stat, cmd, match;
2217 uint32_t off, cntl, stat, cmd, match;
2218
2219 if(ch == 0){
2220 off = OHCI_ATQOFF;
2221 }else if(ch == 1){
2222 off = OHCI_ATSOFF;
2223 }else if(ch == 2){
2224 off = OHCI_ARQOFF;
2225 }else if(ch == 3){

--- 26 unchanged lines hidden (view full) ---

2252 stat & 0x1f
2253 );
2254 }else{
2255 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2256 }
2257}
2258
2259void
2218
2219 if(ch == 0){
2220 off = OHCI_ATQOFF;
2221 }else if(ch == 1){
2222 off = OHCI_ATSOFF;
2223 }else if(ch == 2){
2224 off = OHCI_ARQOFF;
2225 }else if(ch == 3){

--- 26 unchanged lines hidden (view full) ---

2252 stat & 0x1f
2253 );
2254 }else{
2255 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2256 }
2257}
2258
2259void
2260dump_db(struct fwohci_softc *sc, u_int32_t ch)
2260dump_db(struct fwohci_softc *sc, uint32_t ch)
2261{
2262 struct fwohci_dbch *dbch;
2263 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2264 struct fwohcidb *curr = NULL, *prev, *next = NULL;
2265 int idb, jdb;
2261{
2262 struct fwohci_dbch *dbch;
2263 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2264 struct fwohcidb *curr = NULL, *prev, *next = NULL;
2265 int idb, jdb;
2266 u_int32_t cmd, off;
2266 uint32_t cmd, off;
2267 if(ch == 0){
2268 off = OHCI_ATQOFF;
2269 dbch = &sc->atrq;
2270 }else if(ch == 1){
2271 off = OHCI_ATSOFF;
2272 dbch = &sc->atrs;
2273 }else if(ch == 2){
2274 off = OHCI_ARQOFF;

--- 56 unchanged lines hidden (view full) ---

2331 }else{
2332 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2333 }
2334 return;
2335}
2336
2337void
2338print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2267 if(ch == 0){
2268 off = OHCI_ATQOFF;
2269 dbch = &sc->atrq;
2270 }else if(ch == 1){
2271 off = OHCI_ATSOFF;
2272 dbch = &sc->atrs;
2273 }else if(ch == 2){
2274 off = OHCI_ARQOFF;

--- 56 unchanged lines hidden (view full) ---

2331 }else{
2332 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2333 }
2334 return;
2335}
2336
2337void
2338print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2339 u_int32_t ch, u_int32_t max)
2339 uint32_t ch, uint32_t max)
2340{
2341 fwohcireg_t stat;
2342 int i, key;
2340{
2341 fwohcireg_t stat;
2342 int i, key;
2343 u_int32_t cmd, res;
2343 uint32_t cmd, res;
2344
2345 if(db == NULL){
2346 printf("No Descriptor is found\n");
2347 return;
2348 }
2349
2350 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2351 ch,

--- 70 unchanged lines hidden (view full) ---

2422 }
2423 return;
2424}
2425
2426void
2427fwohci_ibr(struct firewire_comm *fc)
2428{
2429 struct fwohci_softc *sc;
2344
2345 if(db == NULL){
2346 printf("No Descriptor is found\n");
2347 return;
2348 }
2349
2350 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2351 ch,

--- 70 unchanged lines hidden (view full) ---

2422 }
2423 return;
2424}
2425
2426void
2427fwohci_ibr(struct firewire_comm *fc)
2428{
2429 struct fwohci_softc *sc;
2430 u_int32_t fun;
2430 uint32_t fun;
2431
2432 device_printf(fc->dev, "Initiate bus reset\n");
2433 sc = (struct fwohci_softc *)fc;
2434
2435 /*
2436 * Set root hold-off bit so that non cyclemaster capable node
2437 * shouldn't became the root node.
2438 */

--- 90 unchanged lines hidden (view full) ---

2529 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2530 db_tr->dbcnt = 3;
2531
2532 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2533 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2534 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2535 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2536 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2431
2432 device_printf(fc->dev, "Initiate bus reset\n");
2433 sc = (struct fwohci_softc *)fc;
2434
2435 /*
2436 * Set root hold-off bit so that non cyclemaster capable node
2437 * shouldn't became the root node.
2438 */

--- 90 unchanged lines hidden (view full) ---

2529 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2530 db_tr->dbcnt = 3;
2531
2532 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2533 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2534 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2535 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2536 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2537 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2537 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t));
2538
2539 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2540 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2541#if 1
2542 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2543 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2544#endif
2545 return 0;

--- 17 unchanged lines hidden (view full) ---

2563 return(ENOMEM);
2564 db_tr->dbcnt = 1;
2565 dsiz[0] = ir->psize;
2566 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2567 BUS_DMASYNC_PREREAD);
2568 } else {
2569 db_tr->dbcnt = 0;
2570 if (dummy_dma != NULL) {
2538
2539 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2540 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2541#if 1
2542 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2543 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2544#endif
2545 return 0;

--- 17 unchanged lines hidden (view full) ---

2563 return(ENOMEM);
2564 db_tr->dbcnt = 1;
2565 dsiz[0] = ir->psize;
2566 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2567 BUS_DMASYNC_PREREAD);
2568 } else {
2569 db_tr->dbcnt = 0;
2570 if (dummy_dma != NULL) {
2571 dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2571 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2572 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2573 }
2574 dsiz[db_tr->dbcnt] = ir->psize;
2575 if (ir->buf != NULL) {
2576 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2577 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2578 }
2579 db_tr->dbcnt++;

--- 14 unchanged lines hidden (view full) ---

2594 return 0;
2595}
2596
2597
2598static int
2599fwohci_arcv_swap(struct fw_pkt *fp, int len)
2600{
2601 struct fw_pkt *fp0;
2572 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2573 }
2574 dsiz[db_tr->dbcnt] = ir->psize;
2575 if (ir->buf != NULL) {
2576 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2577 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2578 }
2579 db_tr->dbcnt++;

--- 14 unchanged lines hidden (view full) ---

2594 return 0;
2595}
2596
2597
2598static int
2599fwohci_arcv_swap(struct fw_pkt *fp, int len)
2600{
2601 struct fw_pkt *fp0;
2602 u_int32_t ld0;
2602 uint32_t ld0;
2603 int slen, hlen;
2604#if BYTE_ORDER == BIG_ENDIAN
2605 int i;
2606#endif
2607
2608 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2609#if 0
2610 printf("ld0: x%08x\n", ld0);

--- 34 unchanged lines hidden (view full) ---

2645
2646static int
2647fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2648{
2649 struct tcode_info *info;
2650 int r;
2651
2652 info = &tinfo[fp->mode.common.tcode];
2603 int slen, hlen;
2604#if BYTE_ORDER == BIG_ENDIAN
2605 int i;
2606#endif
2607
2608 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2609#if 0
2610 printf("ld0: x%08x\n", ld0);

--- 34 unchanged lines hidden (view full) ---

2645
2646static int
2647fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2648{
2649 struct tcode_info *info;
2650 int r;
2651
2652 info = &tinfo[fp->mode.common.tcode];
2653 r = info->hdr_len + sizeof(u_int32_t);
2653 r = info->hdr_len + sizeof(uint32_t);
2654 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2654 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2655 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t));
2655 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
2656
2656
2657 if (r == sizeof(u_int32_t))
2657 if (r == sizeof(uint32_t))
2658 /* XXX */
2659 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2660 fp->mode.common.tcode);
2661
2662 if (r > dbch->xferq.psize) {
2663 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2664 /* panic ? */
2665 }

--- 16 unchanged lines hidden (view full) ---

2682static void
2683fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2684{
2685 struct fwohcidb_tr *db_tr;
2686 struct iovec vec[2];
2687 struct fw_pkt pktbuf;
2688 int nvec;
2689 struct fw_pkt *fp;
2658 /* XXX */
2659 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2660 fp->mode.common.tcode);
2661
2662 if (r > dbch->xferq.psize) {
2663 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2664 /* panic ? */
2665 }

--- 16 unchanged lines hidden (view full) ---

2682static void
2683fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2684{
2685 struct fwohcidb_tr *db_tr;
2686 struct iovec vec[2];
2687 struct fw_pkt pktbuf;
2688 int nvec;
2689 struct fw_pkt *fp;
2690 u_int8_t *ld;
2691 u_int32_t stat, off, status;
2690 uint8_t *ld;
2691 uint32_t stat, off, status;
2692 u_int spd;
2693 int len, plen, hlen, pcnt, offset;
2694 int s;
2695 caddr_t buf;
2696 int resCount;
2697
2698 if(&sc->arrq == dbch){
2699 off = OHCI_ARQOFF;

--- 11 unchanged lines hidden (view full) ---

2711 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2712 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2713 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2714#if 0
2715 printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2716#endif
2717 while (status & OHCI_CNTL_DMA_ACTIVE) {
2718 len = dbch->xferq.psize - resCount;
2692 u_int spd;
2693 int len, plen, hlen, pcnt, offset;
2694 int s;
2695 caddr_t buf;
2696 int resCount;
2697
2698 if(&sc->arrq == dbch){
2699 off = OHCI_ARQOFF;

--- 11 unchanged lines hidden (view full) ---

2711 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2712 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2713 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2714#if 0
2715 printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2716#endif
2717 while (status & OHCI_CNTL_DMA_ACTIVE) {
2718 len = dbch->xferq.psize - resCount;
2719 ld = (u_int8_t *)db_tr->buf;
2719 ld = (uint8_t *)db_tr->buf;
2720 if (dbch->pdb_tr == NULL) {
2721 len -= dbch->buf_offset;
2722 ld += dbch->buf_offset;
2723 }
2724 if (len > 0)
2725 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2726 BUS_DMASYNC_POSTREAD);
2727 while (len > 0 ) {

--- 82 unchanged lines hidden (view full) ---

2810 /* XXX clear pdb_tr */
2811 goto out;
2812 }
2813 vec[nvec].iov_base = ld;
2814 vec[nvec].iov_len = plen;
2815 nvec ++;
2816 ld += plen;
2817 }
2720 if (dbch->pdb_tr == NULL) {
2721 len -= dbch->buf_offset;
2722 ld += dbch->buf_offset;
2723 }
2724 if (len > 0)
2725 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2726 BUS_DMASYNC_POSTREAD);
2727 while (len > 0 ) {

--- 82 unchanged lines hidden (view full) ---

2810 /* XXX clear pdb_tr */
2811 goto out;
2812 }
2813 vec[nvec].iov_base = ld;
2814 vec[nvec].iov_len = plen;
2815 nvec ++;
2816 ld += plen;
2817 }
2818 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2818 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2819 if (nvec == 0)
2820 printf("nvec == 0\n");
2821
2822/* DMA result-code will be written at the tail of packet */
2823#if BYTE_ORDER == BIG_ENDIAN
2824 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2825#else
2826 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;

--- 73 unchanged lines hidden --- 		2819 if (nvec == 0)
2820 printf("nvec == 0\n");
2821
2822/* DMA result-code will be written at the tail of packet */
2823#if BYTE_ORDER == BIG_ENDIAN
2824 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2825#else
2826 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;

--- 73 unchanged lines hidden ---