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firewire.h (127468) firewire.h (129585)
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/firewire.h 127468 2004-03-26 23:17:10Z simokawa $
34 * $FreeBSD: head/sys/dev/firewire/firewire.h 129585 2004-05-22 16:14:17Z dfr $
35 *
36 */
37
38#ifndef _FIREWIRE_H
39#define _FIREWIRE_H 1
40
41#define DEV_DEF 0
42#define DEV_DV 2

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50 struct fw_bufspec {
51 unsigned int nchunk;
52 unsigned int npacket;
53 unsigned int psize;
54 } tx, rx;
55};
56
57struct fw_addr {
35 *
36 */
37
38#ifndef _FIREWIRE_H
39#define _FIREWIRE_H 1
40
41#define DEV_DEF 0
42#define DEV_DV 2

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50 struct fw_bufspec {
51 unsigned int nchunk;
52 unsigned int npacket;
53 unsigned int psize;
54 } tx, rx;
55};
56
57struct fw_addr {
58 unsigned long hi;
59 unsigned long lo;
58 uint32_t hi;
59 uint32_t lo;
60};
61
62struct fw_asybindreq {
63 struct fw_addr start;
64 unsigned long len;
65};
66
67struct fw_reg_req_t {
60};
61
62struct fw_asybindreq {
63 struct fw_addr start;
64 unsigned long len;
65};
66
67struct fw_reg_req_t {
68 unsigned long addr;
69 unsigned long data;
68 uint32_t addr;
69 uint32_t data;
70};
71
72#define MAXREC(x) (2 << (x))
73#define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */
74#define FWMAXQUEUE 128
75
76#define FWLOCALBUS 0xffc0
77

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101
102#define FWSPD_S100 0
103#define FWSPD_S200 1
104#define FWSPD_S400 2
105
106#define FWP_TL_VALID (1 << 7)
107
108struct fw_isohdr {
70};
71
72#define MAXREC(x) (2 << (x))
73#define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */
74#define FWMAXQUEUE 128
75
76#define FWLOCALBUS 0xffc0
77

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101
102#define FWSPD_S100 0
103#define FWSPD_S200 1
104#define FWSPD_S400 2
105
106#define FWP_TL_VALID (1 << 7)
107
108struct fw_isohdr {
109 u_int32_t hdr[1];
109 uint32_t hdr[1];
110};
111
112struct fw_asyhdr {
110};
111
112struct fw_asyhdr {
113 u_int32_t hdr[4];
113 uint32_t hdr[4];
114};
115
116#if BYTE_ORDER == BIG_ENDIAN
114};
115
116#if BYTE_ORDER == BIG_ENDIAN
117#define BIT4x2(x,y) u_int8_t x:4, y:4
118#define BIT16x2(x,y) u_int32_t x:16, y:16
117#define BIT4x2(x,y) uint8_t x:4, y:4
118#define BIT16x2(x,y) uint32_t x:16, y:16
119#else
119#else
120#define BIT4x2(x,y) u_int8_t y:4, x:4
121#define BIT16x2(x,y) u_int32_t y:16, x:16
120#define BIT4x2(x,y) uint8_t y:4, x:4
121#define BIT16x2(x,y) uint32_t y:16, x:16
122#endif
123
124
125#if BYTE_ORDER == BIG_ENDIAN
122#endif
123
124
125#if BYTE_ORDER == BIG_ENDIAN
126#define COMMON_HDR(a,b,c,d) u_int32_t a:16,b:8,c:4,d:4
127#define COMMON_RES(a,b,c,d) u_int32_t a:16,b:4,c:4,d:8
126#define COMMON_HDR(a,b,c,d) uint32_t a:16,b:8,c:4,d:4
127#define COMMON_RES(a,b,c,d) uint32_t a:16,b:4,c:4,d:8
128#else
128#else
129#define COMMON_HDR(a,b,c,d) u_int32_t d:4,c:4,b:8,a:16
130#define COMMON_RES(a,b,c,d) u_int32_t d:8,c:4,b:4,a:16
129#define COMMON_HDR(a,b,c,d) uint32_t d:4,c:4,b:8,a:16
130#define COMMON_RES(a,b,c,d) uint32_t d:8,c:4,b:4,a:16
131#endif
132
133struct fw_pkt {
134 union {
131#endif
132
133struct fw_pkt {
134 union {
135 u_int32_t ld[0];
135 uint32_t ld[0];
136 struct {
137 COMMON_HDR(, , tcode, );
138 } common;
139 struct {
140 COMMON_HDR(len, chtag, tcode, sy);
136 struct {
137 COMMON_HDR(, , tcode, );
138 } common;
139 struct {
140 COMMON_HDR(len, chtag, tcode, sy);
141 u_int32_t payload[0];
141 uint32_t payload[0];
142 } stream;
143 struct {
144 COMMON_HDR(dst, tlrt, tcode, pri);
145 BIT16x2(src, );
146 } hdr;
147 struct {
148 COMMON_HDR(dst, tlrt, tcode, pri);
149 BIT16x2(src, dest_hi);
142 } stream;
143 struct {
144 COMMON_HDR(dst, tlrt, tcode, pri);
145 BIT16x2(src, );
146 } hdr;
147 struct {
148 COMMON_HDR(dst, tlrt, tcode, pri);
149 BIT16x2(src, dest_hi);
150 u_int32_t dest_lo;
150 uint32_t dest_lo;
151 } rreqq;
152 struct {
153 COMMON_HDR(dst, tlrt, tcode, pri);
154 COMMON_RES(src, rtcode, , );
151 } rreqq;
152 struct {
153 COMMON_HDR(dst, tlrt, tcode, pri);
154 COMMON_RES(src, rtcode, , );
155 u_int32_t :32;
155 uint32_t :32;
156 } wres;
157 struct {
158 COMMON_HDR(dst, tlrt, tcode, pri);
159 BIT16x2(src, dest_hi);
156 } wres;
157 struct {
158 COMMON_HDR(dst, tlrt, tcode, pri);
159 BIT16x2(src, dest_hi);
160 u_int32_t dest_lo;
160 uint32_t dest_lo;
161 BIT16x2(len, extcode);
162 } rreqb;
163 struct {
164 COMMON_HDR(dst, tlrt, tcode, pri);
165 BIT16x2(src, dest_hi);
161 BIT16x2(len, extcode);
162 } rreqb;
163 struct {
164 COMMON_HDR(dst, tlrt, tcode, pri);
165 BIT16x2(src, dest_hi);
166 u_int32_t dest_lo;
167 u_int32_t data;
166 uint32_t dest_lo;
167 uint32_t data;
168 } wreqq;
169 struct {
170 COMMON_HDR(dst, tlrt, tcode, pri);
171 BIT16x2(src, dest_hi);
168 } wreqq;
169 struct {
170 COMMON_HDR(dst, tlrt, tcode, pri);
171 BIT16x2(src, dest_hi);
172 u_int32_t dest_lo;
173 u_int32_t data;
172 uint32_t dest_lo;
173 uint32_t data;
174 } cyc;
175 struct {
176 COMMON_HDR(dst, tlrt, tcode, pri);
177 COMMON_RES(src, rtcode, , );
174 } cyc;
175 struct {
176 COMMON_HDR(dst, tlrt, tcode, pri);
177 COMMON_RES(src, rtcode, , );
178 u_int32_t :32;
179 u_int32_t data;
178 uint32_t :32;
179 uint32_t data;
180 } rresq;
181 struct {
182 COMMON_HDR(dst, tlrt, tcode, pri);
183 BIT16x2(src, dest_hi);
180 } rresq;
181 struct {
182 COMMON_HDR(dst, tlrt, tcode, pri);
183 BIT16x2(src, dest_hi);
184 u_int32_t dest_lo;
184 uint32_t dest_lo;
185 BIT16x2(len, extcode);
185 BIT16x2(len, extcode);
186 u_int32_t payload[0];
186 uint32_t payload[0];
187 } wreqb;
188 struct {
189 COMMON_HDR(dst, tlrt, tcode, pri);
190 BIT16x2(src, dest_hi);
187 } wreqb;
188 struct {
189 COMMON_HDR(dst, tlrt, tcode, pri);
190 BIT16x2(src, dest_hi);
191 u_int32_t dest_lo;
191 uint32_t dest_lo;
192 BIT16x2(len, extcode);
192 BIT16x2(len, extcode);
193 u_int32_t payload[0];
193 uint32_t payload[0];
194 } lreq;
195 struct {
196 COMMON_HDR(dst, tlrt, tcode, pri);
197 COMMON_RES(src, rtcode, , );
194 } lreq;
195 struct {
196 COMMON_HDR(dst, tlrt, tcode, pri);
197 COMMON_RES(src, rtcode, , );
198 u_int32_t :32;
198 uint32_t :32;
199 BIT16x2(len, extcode);
199 BIT16x2(len, extcode);
200 u_int32_t payload[0];
200 uint32_t payload[0];
201 } rresb;
202 struct {
203 COMMON_HDR(dst, tlrt, tcode, pri);
204 COMMON_RES(src, rtcode, , );
201 } rresb;
202 struct {
203 COMMON_HDR(dst, tlrt, tcode, pri);
204 COMMON_RES(src, rtcode, , );
205 u_int32_t :32;
205 uint32_t :32;
206 BIT16x2(len, extcode);
206 BIT16x2(len, extcode);
207 u_int32_t payload[0];
207 uint32_t payload[0];
208 } lres;
209 } mode;
210};
211
212/*
213 * Response code (rtcode)
214 */
215/* The node has successfully completed the command. */

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232#define EXTCODE_MASK_SWAP 1
233#define EXTCODE_CMP_SWAP 2
234#define EXTCODE_FETCH_ADD 3
235#define EXTCODE_LITTLE_ADD 4
236#define EXTCODE_BOUNDED_ADD 5
237#define EXTCODE_WRAP_ADD 6
238
239struct fw_eui64 {
208 } lres;
209 } mode;
210};
211
212/*
213 * Response code (rtcode)
214 */
215/* The node has successfully completed the command. */

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232#define EXTCODE_MASK_SWAP 1
233#define EXTCODE_CMP_SWAP 2
234#define EXTCODE_FETCH_ADD 3
235#define EXTCODE_LITTLE_ADD 4
236#define EXTCODE_BOUNDED_ADD 5
237#define EXTCODE_WRAP_ADD 6
238
239struct fw_eui64 {
240 u_int32_t hi, lo;
240 uint32_t hi, lo;
241};
242#define FW_EUI64_BYTE(eui, x) \
243 ((((x)<4)? \
244 ((eui)->hi >> (8*(3-(x)))): \
245 ((eui)->lo >> (8*(7-(x)))) \
246 ) & 0xff)
247#define FW_EUI64_EQUAL(x, y) \
248 ((x).hi == (y).hi && (x).lo == (y).lo)

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256#define FWASRESTL 2
257#define FWASREQSTREAM 3
258 unsigned short len;
259 union {
260 struct fw_eui64 eui;
261 }dst;
262 }req;
263 struct fw_pkt pkt;
241};
242#define FW_EUI64_BYTE(eui, x) \
243 ((((x)<4)? \
244 ((eui)->hi >> (8*(3-(x)))): \
245 ((eui)->lo >> (8*(7-(x)))) \
246 ) & 0xff)
247#define FW_EUI64_EQUAL(x, y) \
248 ((x).hi == (y).hi && (x).lo == (y).lo)

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256#define FWASRESTL 2
257#define FWASREQSTREAM 3
258 unsigned short len;
259 union {
260 struct fw_eui64 eui;
261 }dst;
262 }req;
263 struct fw_pkt pkt;
264 u_int32_t data[512];
264 uint32_t data[512];
265};
266
267struct fw_devinfo {
268 struct fw_eui64 eui;
265};
266
267struct fw_devinfo {
268 struct fw_eui64 eui;
269 u_int16_t dst;
270 u_int16_t status;
269 uint16_t dst;
270 uint16_t status;
271};
272
273#define FW_MAX_DEVLST 70
274struct fw_devlstreq {
271};
272
273#define FW_MAX_DEVLST 70
274struct fw_devlstreq {
275 u_int16_t n;
276 u_int16_t info_len;
275 uint16_t n;
276 uint16_t info_len;
277 struct fw_devinfo dev[FW_MAX_DEVLST];
278};
279
280#define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
281#define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
282#define FW_SELF_ID_PORT_NOT_CONNECTED 1
283#define FW_SELF_ID_PORT_NOT_EXISTS 0
284#if BYTE_ORDER == BIG_ENDIAN
285union fw_self_id {
286 struct {
277 struct fw_devinfo dev[FW_MAX_DEVLST];
278};
279
280#define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
281#define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
282#define FW_SELF_ID_PORT_NOT_CONNECTED 1
283#define FW_SELF_ID_PORT_NOT_EXISTS 0
284#if BYTE_ORDER == BIG_ENDIAN
285union fw_self_id {
286 struct {
287 u_int32_t id:2,
287 uint32_t id:2,
288 phy_id:6,
289 sequel:1,
290 link_active:1,
291 gap_count:6,
292 phy_speed:2,
293 phy_delay:2,
294 contender:1,
295 power_class:3,
296 port0:2,
297 port1:2,
298 port2:2,
299 initiated_reset:1,
300 more_packets:1;
301 } p0;
302 struct {
288 phy_id:6,
289 sequel:1,
290 link_active:1,
291 gap_count:6,
292 phy_speed:2,
293 phy_delay:2,
294 contender:1,
295 power_class:3,
296 port0:2,
297 port1:2,
298 port2:2,
299 initiated_reset:1,
300 more_packets:1;
301 } p0;
302 struct {
303 u_int32_t
303 uint32_t
304 id:2,
305 phy_id:6,
306 sequel:1,
307 sequence_num:3,
308 :2,
309 porta:2,
310 portb:2,
311 portc:2,

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316 porth:2,
317 :1,
318 more_packets:1;
319 } p1;
320};
321#else
322union fw_self_id {
323 struct {
304 id:2,
305 phy_id:6,
306 sequel:1,
307 sequence_num:3,
308 :2,
309 porta:2,
310 portb:2,
311 portc:2,

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316 porth:2,
317 :1,
318 more_packets:1;
319 } p1;
320};
321#else
322union fw_self_id {
323 struct {
324 u_int32_t more_packets:1,
324 uint32_t more_packets:1,
325 initiated_reset:1,
326 port2:2,
327 port1:2,
328 port0:2,
329 power_class:3,
330 contender:1,
331 phy_delay:2,
332 phy_speed:2,
333 gap_count:6,
334 link_active:1,
335 sequel:1,
336 phy_id:6,
337 id:2;
338 } p0;
339 struct {
325 initiated_reset:1,
326 port2:2,
327 port1:2,
328 port0:2,
329 power_class:3,
330 contender:1,
331 phy_delay:2,
332 phy_speed:2,
333 gap_count:6,
334 link_active:1,
335 sequel:1,
336 phy_id:6,
337 id:2;
338 } p0;
339 struct {
340 u_int32_t more_packets:1,
340 uint32_t more_packets:1,
341 reserved1:1,
342 porth:2,
343 portg:2,
344 portf:2,
345 porte:2,
346 portd:2,
347 portc:2,
348 portb:2,

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353 phy_id:6,
354 id:2;
355 } p1;
356};
357#endif
358
359
360struct fw_topology_map {
341 reserved1:1,
342 porth:2,
343 portg:2,
344 portf:2,
345 porte:2,
346 portd:2,
347 portc:2,
348 portb:2,

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353 phy_id:6,
354 id:2;
355 } p1;
356};
357#endif
358
359
360struct fw_topology_map {
361 u_int32_t crc:16,
362 crc_len:16;
363 u_int32_t generation;
364 u_int32_t self_id_count:16,
365 node_count:16;
361 uint32_t crc:16,
362 crc_len:16;
363 uint32_t generation;
364 uint32_t self_id_count:16,
365 node_count:16;
366 union fw_self_id self_id[4*64];
367};
368
369struct fw_speed_map {
366 union fw_self_id self_id[4*64];
367};
368
369struct fw_speed_map {
370 u_int32_t crc:16,
371 crc_len:16;
372 u_int32_t generation;
373 u_int8_t speed[64][64];
370 uint32_t crc:16,
371 crc_len:16;
372 uint32_t generation;
373 uint8_t speed[64][64];
374};
375
376struct fw_crom_buf {
377 struct fw_eui64 eui;
378 int len;
379 void *ptr;
380};
381

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400#define FW_SDEUI64 _IOW('S', 20, struct fw_eui64)
401#define FW_GDEUI64 _IOR('S', 21, struct fw_eui64)
402
403#define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t)
404#define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t)
405#define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t)
406#define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t)
407
374};
375
376struct fw_crom_buf {
377 struct fw_eui64 eui;
378 int len;
379 void *ptr;
380};
381

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400#define FW_SDEUI64 _IOW('S', 20, struct fw_eui64)
401#define FW_GDEUI64 _IOR('S', 21, struct fw_eui64)
402
403#define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t)
404#define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t)
405#define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t)
406#define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t)
407
408#define DUMPDMA _IOWR('S', 82, u_int32_t)
408#define DUMPDMA _IOWR('S', 82, uint32_t)
409
410#ifdef _KERNEL
411
412#define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
413
414#if defined(__DragonFly__) || __FreeBSD_version < 500000
415#define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8))
416#define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff))
417#endif
418
419#define MAKEMINOR(f, u, s) \
420 unit2minor((f) | (((u) & 0xff) << 8) | (s & 0xff))
421#define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8)
422#define DEV2SUB(x) (dev2unit(x) & 0xff)
423
424#define FWMEM_FLAG 0x10000
425#define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG)
426#endif
427#endif
409
410#ifdef _KERNEL
411
412#define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
413
414#if defined(__DragonFly__) || __FreeBSD_version < 500000
415#define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8))
416#define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff))
417#endif
418
419#define MAKEMINOR(f, u, s) \
420 unit2minor((f) | (((u) & 0xff) << 8) | (s & 0xff))
421#define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8)
422#define DEV2SUB(x) (dev2unit(x) & 0xff)
423
424#define FWMEM_FLAG 0x10000
425#define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG)
426#endif
427#endif