1/*-
2 * Copyright (c) 2011-2012 Stefan Bethke.
3 * Copyright (c) 2012 Adrian Chadd.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/etherswitch/arswitch/arswitch_phy.c 235288 2012-05-11 20:53:20Z adrian $
28 */
29
30#include <sys/param.h>
31#include <sys/bus.h>
32#include <sys/errno.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/socket.h>
36#include <sys/sockio.h>
37#include <sys/sysctl.h>
38#include <sys/systm.h>
39
40#include <net/if.h>
41#include <net/if_arp.h>
42#include <net/ethernet.h>
43#include <net/if_dl.h>
44#include <net/if_media.h>
45#include <net/if_types.h>
46
47#include <machine/bus.h>
48#include <dev/iicbus/iic.h>
49#include <dev/iicbus/iiconf.h>
50#include <dev/iicbus/iicbus.h>
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include <dev/etherswitch/mdio.h>
54
55#include <dev/etherswitch/etherswitch.h>
56
57#include <dev/etherswitch/arswitch/arswitchreg.h>
58#include <dev/etherswitch/arswitch/arswitchvar.h>
59
60#include <dev/etherswitch/arswitch/arswitch_reg.h>
61#include <dev/etherswitch/arswitch/arswitch_phy.h>
62
63#include "mdio_if.h"
64#include "miibus_if.h"
65#include "etherswitch_if.h"
66
67#if defined(DEBUG)
68static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch");
69#endif
70
71/*
72 * access PHYs integrated into the switch chip through the switch's MDIO
73 * control register.
74 */
75int
76arswitch_readphy(device_t dev, int phy, int reg)
77{
78 uint32_t data = 0, ctrl;
79 int err, timeout;
80
81 if (phy < 0 || phy >= 32)
82 return (ENXIO);
83 if (reg < 0 || reg >= 32)
84 return (ENXIO);
85 err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
86 AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
87 AR8X16_MDIO_CTRL_CMD_READ |
88 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
89 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
90 DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
91 if (err != 0)
92 return (-1);
93 for (timeout = 100; timeout--; ) {
94 ctrl = arswitch_readreg_msb(dev, AR8X16_REG_MDIO_CTRL);
95 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
96 break;
97 }
98 if (timeout < 0)
99 err = EIO;
100 data = arswitch_readreg_lsb(dev, AR8X16_REG_MDIO_CTRL) &
101 AR8X16_MDIO_CTRL_DATA_MASK;
102 return (data);
103}
104
105int
106arswitch_writephy(device_t dev, int phy, int reg, int data)
107{
108 uint32_t ctrl;
109 int err, timeout;
110
111 if (reg < 0 || reg >= 32)
112 return (ENXIO);
113 err = arswitch_writereg_lsb(dev, AR8X16_REG_MDIO_CTRL,
114 (data & AR8X16_MDIO_CTRL_DATA_MASK));
115 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
116 if (err != 0)
117 return (err);
118 err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
119 AR8X16_MDIO_CTRL_BUSY |
120 AR8X16_MDIO_CTRL_MASTER_EN |
121 AR8X16_MDIO_CTRL_CMD_WRITE |
122 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
123 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
124 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
125 if (err != 0)
126 return (err);
127 for (timeout = 100; timeout--; ) {
128 ctrl = arswitch_readreg(dev, AR8X16_REG_MDIO_CTRL);
129 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
130 break;
131 }
132 if (timeout < 0)
133 err = EIO;
134 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
135 return (err);
136}