1/*-
2 * Copyright (c) 2011-2012 Stefan Bethke.
3 * Copyright (c) 2012 Adrian Chadd.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/etherswitch/arswitch/arswitch_phy.c 235288 2012-05-11 20:53:20Z adrian $
28 */
29
30#include <sys/param.h>
31#include <sys/bus.h>
32#include <sys/errno.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/socket.h>

--- 34 unchanged lines hidden (view full) ---

70
71/*
72 * access PHYs integrated into the switch chip through the switch's MDIO
73 * control register.
74 */
75int
76arswitch_readphy(device_t dev, int phy, int reg)
77{
78 uint32_t data = 0, ctrl;
79 int err, timeout;
80
81 if (phy < 0 || phy >= 32)
82 return (ENXIO);
83 if (reg < 0 || reg >= 32)
84 return (ENXIO);
85 err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
86 AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
87 AR8X16_MDIO_CTRL_CMD_READ |
88 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
89 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
90 DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
91 if (err != 0)
92 return (-1);
93 for (timeout = 100; timeout--; ) {
94 ctrl = arswitch_readreg_msb(dev, AR8X16_REG_MDIO_CTRL);
95 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
96 break;
97 }
98 if (timeout < 0)
99 err = EIO;
100 data = arswitch_readreg_lsb(dev, AR8X16_REG_MDIO_CTRL) &
101 AR8X16_MDIO_CTRL_DATA_MASK;
102 return (data);
103}
104
105int
106arswitch_writephy(device_t dev, int phy, int reg, int data)
107{
108 uint32_t ctrl;
109 int err, timeout;
110
111 if (reg < 0 || reg >= 32)
112 return (ENXIO);
113 err = arswitch_writereg_lsb(dev, AR8X16_REG_MDIO_CTRL,
114 (data & AR8X16_MDIO_CTRL_DATA_MASK));
115 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
116 if (err != 0)
117 return (err);
118 err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
119 AR8X16_MDIO_CTRL_BUSY |
120 AR8X16_MDIO_CTRL_MASTER_EN |
121 AR8X16_MDIO_CTRL_CMD_WRITE |
122 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
123 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
124 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
125 if (err != 0)
126 return (err);
127 for (timeout = 100; timeout--; ) {
128 ctrl = arswitch_readreg(dev, AR8X16_REG_MDIO_CTRL);
129 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
130 break;
131 }
132 if (timeout < 0)
133 err = EIO;
134 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
135 return (err);
136}