1/*-
2 * Copyright (c) 2011-2012 Stefan Bethke.
3 * Copyright (c) 2012 Adrian Chadd.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/etherswitch/arswitch/arswitch_phy.c 241578 2012-10-15 12:20:40Z ray $
28 */
29
30#include <sys/param.h>
31#include <sys/bus.h>
32#include <sys/errno.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/socket.h>

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70
71/*
72 * access PHYs integrated into the switch chip through the switch's MDIO
73 * control register.
74 */
75int
76arswitch_readphy(device_t dev, int phy, int reg)
77{
78 struct arswitch_softc *sc;
79 uint32_t data = 0, ctrl;
80 int err, timeout;
81
82 sc = device_get_softc(dev);
83 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
84
85 if (phy < 0 || phy >= 32)
86 return (ENXIO);
87 if (reg < 0 || reg >= 32)
88 return (ENXIO);
89
90 ARSWITCH_LOCK(sc);
91 err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
92 AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
93 AR8X16_MDIO_CTRL_CMD_READ |
94 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
95 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
96 DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
97 if (err != 0)
98 goto fail;
99 for (timeout = 100; timeout--; ) {
100 ctrl = arswitch_readreg_msb(dev, AR8X16_REG_MDIO_CTRL);
101 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
102 break;
103 }
104 if (timeout < 0)
105 goto fail;
106 data = arswitch_readreg_lsb(dev, AR8X16_REG_MDIO_CTRL) &
107 AR8X16_MDIO_CTRL_DATA_MASK;
108 ARSWITCH_UNLOCK(sc);
109 return (data);
110
111fail:
112 ARSWITCH_UNLOCK(sc);
113 return (-1);
114}
115
116int
117arswitch_writephy(device_t dev, int phy, int reg, int data)
118{
119 struct arswitch_softc *sc;
120 uint32_t ctrl;
121 int err, timeout;
122
123 sc = device_get_softc(dev);
124 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
125
126 if (reg < 0 || reg >= 32)
127 return (ENXIO);
128
129 ARSWITCH_LOCK(sc);
130 err = arswitch_writereg_lsb(dev, AR8X16_REG_MDIO_CTRL,
131 (data & AR8X16_MDIO_CTRL_DATA_MASK));
132 if (err != 0)
133 goto out;
134 err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
135 AR8X16_MDIO_CTRL_BUSY |
136 AR8X16_MDIO_CTRL_MASTER_EN |
137 AR8X16_MDIO_CTRL_CMD_WRITE |
138 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
139 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
140 if (err != 0)
141 goto out;
142 for (timeout = 100; timeout--; ) {
143 ctrl = arswitch_readreg(dev, AR8X16_REG_MDIO_CTRL);
144 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
145 break;
146 }
147 if (timeout < 0)
148 err = EIO;
149out:
150 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
151 ARSWITCH_UNLOCK(sc);
152 return (err);
153}