| ncr53c9xvar.h (226381) | ncr53c9xvar.h (226947) |
|---|---|
| 1/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, --- 52 unchanged lines hidden (view full) --- 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 | 1/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, --- 52 unchanged lines hidden (view full) --- 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 |
| 69/* $FreeBSD: head/sys/dev/esp/ncr53c9xvar.h 226381 2011-10-15 09:29:43Z marius $ */ | 69/* $FreeBSD: head/sys/dev/esp/ncr53c9xvar.h 226947 2011-10-30 21:17:42Z marius $ */ |
| 70 | 70 |
| 71#ifndef _DEV_IC_NCR53C9XVAR_H_ 72#define _DEV_IC_NCR53C9XVAR_H_ | 71#ifndef _NCR53C9XVAR_H_ 72#define _NCR53C9XVAR_H_ |
| 73 74#include <sys/lock.h> 75 76/* Set this to 1 for normal debug, or 2 for per-target tracing. */ 77/* #define NCR53C9X_DEBUG 2 */ 78 79/* Wide or differential can have 16 targets */ 80#define NCR_NLUN 8 --- 29 unchanged lines hidden (view full) --- 110 * ECB. Holds additional information for each SCSI command Comments: We 111 * need a separate scsi command block because we may need to overwrite it 112 * with a request sense command. Basicly, we refrain from fiddling with 113 * the ccb union (except do the expected updating of return values). 114 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid, 115 * scsi_status,sense_data}. 116 */ 117struct ncr53c9x_ecb { | 73 74#include <sys/lock.h> 75 76/* Set this to 1 for normal debug, or 2 for per-target tracing. */ 77/* #define NCR53C9X_DEBUG 2 */ 78 79/* Wide or differential can have 16 targets */ 80#define NCR_NLUN 8 --- 29 unchanged lines hidden (view full) --- 110 * ECB. Holds additional information for each SCSI command Comments: We 111 * need a separate scsi command block because we may need to overwrite it 112 * with a request sense command. Basicly, we refrain from fiddling with 113 * the ccb union (except do the expected updating of return values). 114 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid, 115 * scsi_status,sense_data}. 116 */ 117struct ncr53c9x_ecb { |
| 118 /* These fields are preserved between alloc and free */ | 118 /* These fields are preserved between alloc and free. */ 119 struct callout ch; |
| 119 struct ncr53c9x_softc *sc; 120 int tag_id; 121 int flags; 122 123 union ccb *ccb; /* SCSI xfer ctrl block from above */ 124 TAILQ_ENTRY(ncr53c9x_ecb) free_links; 125 TAILQ_ENTRY(ncr53c9x_ecb) chain; 126#define ECB_ALLOC 0x01 127#define ECB_READY 0x02 128#define ECB_SENSE 0x04 129#define ECB_ABORT 0x40 130#define ECB_RESET 0x80 131#define ECB_TENTATIVE_DONE 0x100 132 int timeout; | 120 struct ncr53c9x_softc *sc; 121 int tag_id; 122 int flags; 123 124 union ccb *ccb; /* SCSI xfer ctrl block from above */ 125 TAILQ_ENTRY(ncr53c9x_ecb) free_links; 126 TAILQ_ENTRY(ncr53c9x_ecb) chain; 127#define ECB_ALLOC 0x01 128#define ECB_READY 0x02 129#define ECB_SENSE 0x04 130#define ECB_ABORT 0x40 131#define ECB_RESET 0x80 132#define ECB_TENTATIVE_DONE 0x100 133 int timeout; |
| 133 struct callout ch; | |
| 134 135 struct { 136 uint8_t msg[3]; /* Selection Id msg and tags */ 137 struct scsi_generic cmd; /* SCSI command block */ 138 } cmd; 139 uint8_t *daddr; /* Saved data pointer */ 140 int clen; /* Size of command in cmd.cmd */ 141 int dleft; /* Residue */ --- 143 unchanged lines hidden (view full) --- 285#define NCR_MSGS(str) 286#endif 287 288#define NCR_MAX_MSG_LEN 8 289 290struct ncr53c9x_softc; 291 292/* | 134 135 struct { 136 uint8_t msg[3]; /* Selection Id msg and tags */ 137 struct scsi_generic cmd; /* SCSI command block */ 138 } cmd; 139 uint8_t *daddr; /* Saved data pointer */ 140 int clen; /* Size of command in cmd.cmd */ 141 int dleft; /* Residue */ --- 143 unchanged lines hidden (view full) --- 285#define NCR_MSGS(str) 286#endif 287 288#define NCR_MAX_MSG_LEN 8 289 290struct ncr53c9x_softc; 291 292/* |
| 293 * Function switch used as glue to MD code. | 293 * Function switch used as glue to MD code |
| 294 */ 295struct ncr53c9x_glue { 296 /* Mandatory entry points. */ 297 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int); 298 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t); 299 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 300 void (*gl_dma_reset)(struct ncr53c9x_softc *); 301 int (*gl_dma_intr)(struct ncr53c9x_softc *); 302 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *, 303 int, size_t *); 304 void (*gl_dma_go)(struct ncr53c9x_softc *); 305 void (*gl_dma_stop)(struct ncr53c9x_softc *); 306 int (*gl_dma_isactive)(struct ncr53c9x_softc *); | 294 */ 295struct ncr53c9x_glue { 296 /* Mandatory entry points. */ 297 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int); 298 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t); 299 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 300 void (*gl_dma_reset)(struct ncr53c9x_softc *); 301 int (*gl_dma_intr)(struct ncr53c9x_softc *); 302 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *, 303 int, size_t *); 304 void (*gl_dma_go)(struct ncr53c9x_softc *); 305 void (*gl_dma_stop)(struct ncr53c9x_softc *); 306 int (*gl_dma_isactive)(struct ncr53c9x_softc *); |
| 307 308 /* Optional entry points. */ 309 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *); | |
| 310}; 311 312struct ncr53c9x_softc { 313 device_t sc_dev; /* us as a device */ 314 315 struct cam_sim *sc_sim; /* our scsi adapter */ 316 struct cam_path *sc_path; /* our scsi channel */ 317 struct callout sc_watchdog; /* periodic timer */ --- 7 unchanged lines hidden (view full) --- 325 uint8_t sc_cfg2; /* Config 2, not ESP100 */ 326 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */ 327 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 328 uint8_t sc_cfg4; /* Config 4, only ESP200 */ 329 uint8_t sc_cfg5; /* Config 5, only ESP200 */ 330 uint8_t sc_ccf; /* Clock Conversion */ 331 uint8_t sc_timeout; 332 | 307}; 308 309struct ncr53c9x_softc { 310 device_t sc_dev; /* us as a device */ 311 312 struct cam_sim *sc_sim; /* our scsi adapter */ 313 struct cam_path *sc_path; /* our scsi channel */ 314 struct callout sc_watchdog; /* periodic timer */ --- 7 unchanged lines hidden (view full) --- 322 uint8_t sc_cfg2; /* Config 2, not ESP100 */ 323 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */ 324 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 325 uint8_t sc_cfg4; /* Config 4, only ESP200 */ 326 uint8_t sc_cfg5; /* Config 5, only ESP200 */ 327 uint8_t sc_ccf; /* Clock Conversion */ 328 uint8_t sc_timeout; 329 |
| 333 /* register copies, see espreadregs() */ | 330 /* register copies, see ncr53c9x_readregs() */ |
| 334 uint8_t sc_espintr; 335 uint8_t sc_espstat; 336 uint8_t sc_espstep; 337 uint8_t sc_espstat2; 338 uint8_t sc_espfflags; 339 340 /* Lists of command blocks */ 341 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list; --- 68 unchanged lines hidden (view full) --- 410#define NCR_ATN 0x10 /* ATN asserted */ 411#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */ 412 413/* values for sc_features */ 414#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 415#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 416#define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 417#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ | 331 uint8_t sc_espintr; 332 uint8_t sc_espstat; 333 uint8_t sc_espstep; 334 uint8_t sc_espstat2; 335 uint8_t sc_espfflags; 336 337 /* Lists of command blocks */ 338 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list; --- 68 unchanged lines hidden (view full) --- 407#define NCR_ATN 0x10 /* ATN asserted */ 408#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */ 409 410/* values for sc_features */ 411#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 412#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 413#define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 414#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ |
| 415#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */ |
|
| 418 419/* values for sc_msgout */ 420#define SEND_DEV_RESET 0x0001 421#define SEND_PARITY_ERROR 0x0002 422#define SEND_INIT_DET_ERR 0x0004 423#define SEND_REJECT 0x0008 424#define SEND_IDENTIFY 0x0010 425#define SEND_ABORT 0x0020 --- 68 unchanged lines hidden (view full) --- 494 495/* 496 * Macro to convert the chip register Clock Per Byte value to 497 * Synchronous Transfer Period. 498 */ 499#define ncr53c9x_cpb2stp(sc, cpb) \ 500 ((250 * (cpb)) / (sc)->sc_freq) 501 | 416 417/* values for sc_msgout */ 418#define SEND_DEV_RESET 0x0001 419#define SEND_PARITY_ERROR 0x0002 420#define SEND_INIT_DET_ERR 0x0004 421#define SEND_REJECT 0x0008 422#define SEND_IDENTIFY 0x0010 423#define SEND_ABORT 0x0020 --- 68 unchanged lines hidden (view full) --- 492 493/* 494 * Macro to convert the chip register Clock Per Byte value to 495 * Synchronous Transfer Period. 496 */ 497#define ncr53c9x_cpb2stp(sc, cpb) \ 498 ((250 * (cpb)) / (sc)->sc_freq) 499 |
| 500extern devclass_t esp_devclass; 501 |
|
| 502int ncr53c9x_attach(struct ncr53c9x_softc *sc); 503int ncr53c9x_detach(struct ncr53c9x_softc *sc); 504void ncr53c9x_intr(void *arg); 505 | 502int ncr53c9x_attach(struct ncr53c9x_softc *sc); 503int ncr53c9x_detach(struct ncr53c9x_softc *sc); 504void ncr53c9x_intr(void *arg); 505 |
| 506#endif /* _DEV_IC_NCR53C9XVAR_H_ */ | 506#endif /* _NCR53C9XVAR_H_ */ |