1/*-
2 * Copyright (c) 2004 Scott Long
3 * Copyright (c) 2005, 2008 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29/* $NetBSD: ncr53c9x.c,v 1.143 2011/07/31 18:39:00 jakllsch Exp $ */
30
31/*-
32 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
33 * All rights reserved.
34 *
35 * This code is derived from software contributed to The NetBSD Foundation
36 * by Charles M. Hannum.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
57 * POSSIBILITY OF SUCH DAMAGE.
58 */
59
60/*-
61 * Copyright (c) 1994 Peter Galbavy
62 * Copyright (c) 1995 Paul Kranenburg
63 * All rights reserved.
64 *
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
67 * are met:
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
73 * 3. All advertising materials mentioning features or use of this software
74 * must display the following acknowledgement:
75 * This product includes software developed by Peter Galbavy
76 * 4. The name of the author may not be used to endorse or promote products
77 * derived from this software without specific prior written permission.
78 *
79 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
80 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
81 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
82 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
83 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
84 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
87 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
88 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
89 * POSSIBILITY OF SUCH DAMAGE.
90 */
91
92/*
93 * Based on aic6360 by Jarle Greipsland
94 *
95 * Acknowledgements: Many of the algorithms used in this driver are
96 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and
97 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
98 */
99
100#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2004 Scott Long
3 * Copyright (c) 2005, 2008 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29/* $NetBSD: ncr53c9x.c,v 1.143 2011/07/31 18:39:00 jakllsch Exp $ */
30
31/*-
32 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
33 * All rights reserved.
34 *
35 * This code is derived from software contributed to The NetBSD Foundation
36 * by Charles M. Hannum.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
57 * POSSIBILITY OF SUCH DAMAGE.
58 */
59
60/*-
61 * Copyright (c) 1994 Peter Galbavy
62 * Copyright (c) 1995 Paul Kranenburg
63 * All rights reserved.
64 *
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
67 * are met:
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
73 * 3. All advertising materials mentioning features or use of this software
74 * must display the following acknowledgement:
75 * This product includes software developed by Peter Galbavy
76 * 4. The name of the author may not be used to endorse or promote products
77 * derived from this software without specific prior written permission.
78 *
79 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
80 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
81 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
82 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
83 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
84 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
87 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
88 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
89 * POSSIBILITY OF SUCH DAMAGE.
90 */
91
92/*
93 * Based on aic6360 by Jarle Greipsland
94 *
95 * Acknowledgements: Many of the algorithms used in this driver are
96 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and
97 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
98 */
99
100#include <sys/cdefs.h>
|
101__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 226381 2011-10-15 09:29:43Z marius $");
| 101__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 226947 2011-10-30 21:17:42Z marius $");
|
102
103#include <sys/param.h>
104#include <sys/systm.h>
105#include <sys/bus.h>
106#include <sys/kernel.h>
107#include <sys/malloc.h>
108#include <sys/lock.h>
109#include <sys/module.h>
110#include <sys/mutex.h>
111#include <sys/queue.h>
112#include <sys/time.h>
113#include <sys/callout.h>
114
115#include <cam/cam.h>
116#include <cam/cam_ccb.h>
117#include <cam/cam_debug.h>
118#include <cam/cam_sim.h>
119#include <cam/cam_xpt_sim.h>
120#include <cam/scsi/scsi_all.h>
121#include <cam/scsi/scsi_message.h>
122
123#include <dev/esp/ncr53c9xreg.h>
124#include <dev/esp/ncr53c9xvar.h>
125
| 102
103#include <sys/param.h>
104#include <sys/systm.h>
105#include <sys/bus.h>
106#include <sys/kernel.h>
107#include <sys/malloc.h>
108#include <sys/lock.h>
109#include <sys/module.h>
110#include <sys/mutex.h>
111#include <sys/queue.h>
112#include <sys/time.h>
113#include <sys/callout.h>
114
115#include <cam/cam.h>
116#include <cam/cam_ccb.h>
117#include <cam/cam_debug.h>
118#include <cam/cam_sim.h>
119#include <cam/cam_xpt_sim.h>
120#include <cam/scsi/scsi_all.h>
121#include <cam/scsi/scsi_message.h>
122
123#include <dev/esp/ncr53c9xreg.h>
124#include <dev/esp/ncr53c9xvar.h>
125
|
| 126devclass_t esp_devclass;
127
|
126MODULE_DEPEND(esp, cam, 1, 1, 1);
127
128#ifdef NCR53C9X_DEBUG
129int ncr53c9x_debug =
130 NCR_SHOWMISC /* | NCR_SHOWPHASE | NCR_SHOWTRAC | NCR_SHOWCMDS */;
131#endif
132
133static void ncr53c9x_abort(struct ncr53c9x_softc *sc,
134 struct ncr53c9x_ecb *ecb);
135static void ncr53c9x_action(struct cam_sim *sim, union ccb *ccb);
136static void ncr53c9x_async(void *cbarg, uint32_t code,
137 struct cam_path *path, void *arg);
138static void ncr53c9x_callout(void *arg);
139static void ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result);
140static void ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target,
141 cam_status result);
142static void ncr53c9x_dequeue(struct ncr53c9x_softc *sc,
143 struct ncr53c9x_ecb *ecb);
144static void ncr53c9x_done(struct ncr53c9x_softc *sc,
145 struct ncr53c9x_ecb *ecb);
146static void ncr53c9x_free_ecb(struct ncr53c9x_softc *sc,
147 struct ncr53c9x_ecb *ecb);
148static void ncr53c9x_msgin(struct ncr53c9x_softc *sc);
149static void ncr53c9x_msgout(struct ncr53c9x_softc *sc);
150static void ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset);
151static void ncr53c9x_intr1(struct ncr53c9x_softc *sc);
152static void ncr53c9x_poll(struct cam_sim *sim);
153static int ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how);
154static int ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message,
155 int tagtype, int tagid);
156static void ncr53c9x_reset(struct ncr53c9x_softc *sc);
157static void ncr53c9x_sense(struct ncr53c9x_softc *sc,
158 struct ncr53c9x_ecb *ecb);
159static void ncr53c9x_sched(struct ncr53c9x_softc *sc);
160static void ncr53c9x_select(struct ncr53c9x_softc *sc,
161 struct ncr53c9x_ecb *ecb);
162static void ncr53c9x_watch(void *arg);
163static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, uint8_t *p,
164 int len);
165
166static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *sc);
167static struct ncr53c9x_linfo *ncr53c9x_lunsearch(struct ncr53c9x_tinfo *sc,
168 int64_t lun);
169
170static inline void ncr53c9x_readregs(struct ncr53c9x_softc *sc);
171static inline void ncr53c9x_setsync(struct ncr53c9x_softc *sc,
172 struct ncr53c9x_tinfo *ti);
173static inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc,
174 int period);
175
176#define NCR_RDFIFO_START 0
177#define NCR_RDFIFO_CONTINUE 1
178
179#define NCR_SET_COUNT(sc, size) do { \
180 NCR_WRITE_REG((sc), NCR_TCL, (size)); \
181 NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \
| 128MODULE_DEPEND(esp, cam, 1, 1, 1);
129
130#ifdef NCR53C9X_DEBUG
131int ncr53c9x_debug =
132 NCR_SHOWMISC /* | NCR_SHOWPHASE | NCR_SHOWTRAC | NCR_SHOWCMDS */;
133#endif
134
135static void ncr53c9x_abort(struct ncr53c9x_softc *sc,
136 struct ncr53c9x_ecb *ecb);
137static void ncr53c9x_action(struct cam_sim *sim, union ccb *ccb);
138static void ncr53c9x_async(void *cbarg, uint32_t code,
139 struct cam_path *path, void *arg);
140static void ncr53c9x_callout(void *arg);
141static void ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result);
142static void ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target,
143 cam_status result);
144static void ncr53c9x_dequeue(struct ncr53c9x_softc *sc,
145 struct ncr53c9x_ecb *ecb);
146static void ncr53c9x_done(struct ncr53c9x_softc *sc,
147 struct ncr53c9x_ecb *ecb);
148static void ncr53c9x_free_ecb(struct ncr53c9x_softc *sc,
149 struct ncr53c9x_ecb *ecb);
150static void ncr53c9x_msgin(struct ncr53c9x_softc *sc);
151static void ncr53c9x_msgout(struct ncr53c9x_softc *sc);
152static void ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset);
153static void ncr53c9x_intr1(struct ncr53c9x_softc *sc);
154static void ncr53c9x_poll(struct cam_sim *sim);
155static int ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how);
156static int ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message,
157 int tagtype, int tagid);
158static void ncr53c9x_reset(struct ncr53c9x_softc *sc);
159static void ncr53c9x_sense(struct ncr53c9x_softc *sc,
160 struct ncr53c9x_ecb *ecb);
161static void ncr53c9x_sched(struct ncr53c9x_softc *sc);
162static void ncr53c9x_select(struct ncr53c9x_softc *sc,
163 struct ncr53c9x_ecb *ecb);
164static void ncr53c9x_watch(void *arg);
165static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, uint8_t *p,
166 int len);
167
168static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *sc);
169static struct ncr53c9x_linfo *ncr53c9x_lunsearch(struct ncr53c9x_tinfo *sc,
170 int64_t lun);
171
172static inline void ncr53c9x_readregs(struct ncr53c9x_softc *sc);
173static inline void ncr53c9x_setsync(struct ncr53c9x_softc *sc,
174 struct ncr53c9x_tinfo *ti);
175static inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc,
176 int period);
177
178#define NCR_RDFIFO_START 0
179#define NCR_RDFIFO_CONTINUE 1
180
181#define NCR_SET_COUNT(sc, size) do { \
182 NCR_WRITE_REG((sc), NCR_TCL, (size)); \
183 NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \
|
182 if ((sc->sc_cfg2 & NCRCFG2_FE) || \
183 (sc->sc_rev == NCR_VARIANT_FAS366)) \
| 184 if ((sc->sc_features & NCR_F_LARGEXFER) != 0) \
|
184 NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \
185 if (sc->sc_rev == NCR_VARIANT_FAS366) \
186 NCR_WRITE_REG(sc, NCR_RCH, 0); \
187} while (/* CONSTCOND */0)
188
189#ifndef mstohz
190#define mstohz(ms) \
191 (((ms) < 0x20000) ? \
192 ((ms +0u) / 1000u) * hz : \
193 ((ms +0u) * hz) /1000u)
194#endif
195
196/*
197 * Names for the NCR53c9x variants, corresponding to the variant tags
198 * in ncr53c9xvar.h.
199 */
200static const char *ncr53c9x_variant_names[] = {
201 "ESP100",
202 "ESP100A",
203 "ESP200",
204 "NCR53C94",
205 "NCR53C96",
206 "ESP406",
207 "FAS408",
208 "FAS216",
209 "AM53C974",
210 "FAS366/HME",
211 "NCR53C90 (86C01)",
212 "FAS100A",
213 "FAS236",
214};
215
216/*
217 * Search linked list for LUN info by LUN id.
218 */
219static struct ncr53c9x_linfo *
220ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun)
221{
222 struct ncr53c9x_linfo *li;
223
224 LIST_FOREACH(li, &ti->luns, link)
225 if (li->lun == lun)
226 return (li);
227 return (NULL);
228}
229
230/*
231 * Attach this instance, and then all the sub-devices.
232 */
233int
234ncr53c9x_attach(struct ncr53c9x_softc *sc)
235{
236 struct cam_devq *devq;
237 struct cam_sim *sim;
238 struct cam_path *path;
239 struct ncr53c9x_ecb *ecb;
240 int error, i;
241
242 if (NCR_LOCK_INITIALIZED(sc) == 0) {
243 device_printf(sc->sc_dev, "mutex not initialized\n");
244 return (ENXIO);
245 }
246
247 callout_init_mtx(&sc->sc_watchdog, &sc->sc_lock, 0);
248
249 /*
250 * Note, the front-end has set us up to print the chip variation.
251 */
252 if (sc->sc_rev >= NCR_VARIANT_MAX) {
253 device_printf(sc->sc_dev, "unknown variant %d, devices not "
254 "attached\n", sc->sc_rev);
255 return (EINVAL);
256 }
257
258 device_printf(sc->sc_dev, "%s, %dMHz, SCSI ID %d\n",
259 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id);
260
261 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8;
262
263 /*
264 * Allocate SCSI message buffers.
265 * Front-ends can override allocation to avoid alignment
266 * handling in the DMA engines. Note that ncr53c9x_msgout()
267 * can request a 1 byte DMA transfer.
268 */
269 if (sc->sc_omess == NULL) {
270 sc->sc_omess_self = 1;
271 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT);
272 if (sc->sc_omess == NULL) {
273 device_printf(sc->sc_dev,
274 "cannot allocate MSGOUT buffer\n");
275 return (ENOMEM);
276 }
277 } else
278 sc->sc_omess_self = 0;
279
280 if (sc->sc_imess == NULL) {
281 sc->sc_imess_self = 1;
282 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT);
283 if (sc->sc_imess == NULL) {
284 device_printf(sc->sc_dev,
285 "cannot allocate MSGIN buffer\n");
286 error = ENOMEM;
287 goto fail_omess;
288 }
289 } else
290 sc->sc_imess_self = 0;
291
292 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]),
293 M_DEVBUF, M_NOWAIT | M_ZERO);
294 if (sc->sc_tinfo == NULL) {
295 device_printf(sc->sc_dev,
296 "cannot allocate target info buffer\n");
297 error = ENOMEM;
298 goto fail_imess;
299 }
300
301 /*
302 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100
303 * from now on.
304 */
305 if (sc->sc_rev == NCR_VARIANT_NCR53C90_86C01)
306 sc->sc_rev = NCR_VARIANT_ESP100;
307
308 sc->sc_ccf = FREQTOCCF(sc->sc_freq);
309
310 /* The value *must not* be == 1. Make it 2. */
311 if (sc->sc_ccf == 1)
312 sc->sc_ccf = 2;
313
314 /*
315 * The recommended timeout is 250ms. This register is loaded
316 * with a value calculated as follows, from the docs:
317 *
318 * (timout period) x (CLK frequency)
319 * reg = -------------------------------------
320 * 8192 x (Clock Conversion Factor)
321 *
322 * Since CCF has a linear relation to CLK, this generally computes
323 * to the constant of 153.
324 */
325 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf);
326
327 /* The CCF register only has 3 bits; 0 is actually 8. */
328 sc->sc_ccf &= 7;
329
330 /*
331 * Register with CAM.
332 */
333 devq = cam_simq_alloc(sc->sc_ntarg);
334 if (devq == NULL) {
335 device_printf(sc->sc_dev, "cannot allocate device queue\n");
336 error = ENOMEM;
337 goto fail_tinfo;
338 }
339
340 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc,
341 device_get_unit(sc->sc_dev), &sc->sc_lock, 1, NCR_TAG_DEPTH, devq);
342 if (sim == NULL) {
343 device_printf(sc->sc_dev, "cannot allocate SIM entry\n");
344 error = ENOMEM;
345 goto fail_devq;
346 }
347
348 NCR_LOCK(sc);
349
350 if (xpt_bus_register(sim, sc->sc_dev, 0) != CAM_SUCCESS) {
351 device_printf(sc->sc_dev, "cannot register bus\n");
352 error = EIO;
353 goto fail_lock;
354 }
355
356 if (xpt_create_path(&path, NULL, cam_sim_path(sim),
357 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
358 device_printf(sc->sc_dev, "cannot create path\n");
359 error = EIO;
360 goto fail_bus;
361 }
362
363 if (xpt_register_async(AC_LOST_DEVICE, ncr53c9x_async, sim, path) !=
364 CAM_REQ_CMP) {
365 device_printf(sc->sc_dev, "cannot register async handler\n");
366 error = EIO;
367 goto fail_path;
368 }
369
370 sc->sc_sim = sim;
371 sc->sc_path = path;
372
373 /* Reset state and bus. */
374#if 0
375 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags;
376#else
377 sc->sc_cfflags = 0;
378#endif
379 sc->sc_state = 0;
380 ncr53c9x_init(sc, 1);
381
382 TAILQ_INIT(&sc->free_list);
383 if ((sc->ecb_array =
384 malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH, M_DEVBUF,
385 M_NOWAIT | M_ZERO)) == NULL) {
386 device_printf(sc->sc_dev, "cannot allocate ECB array\n");
387 error = ENOMEM;
388 goto fail_async;
389 }
390 for (i = 0; i < NCR_TAG_DEPTH; i++) {
391 ecb = &sc->ecb_array[i];
392 ecb->sc = sc;
393 ecb->tag_id = i;
| 185 NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \
186 if (sc->sc_rev == NCR_VARIANT_FAS366) \
187 NCR_WRITE_REG(sc, NCR_RCH, 0); \
188} while (/* CONSTCOND */0)
189
190#ifndef mstohz
191#define mstohz(ms) \
192 (((ms) < 0x20000) ? \
193 ((ms +0u) / 1000u) * hz : \
194 ((ms +0u) * hz) /1000u)
195#endif
196
197/*
198 * Names for the NCR53c9x variants, corresponding to the variant tags
199 * in ncr53c9xvar.h.
200 */
201static const char *ncr53c9x_variant_names[] = {
202 "ESP100",
203 "ESP100A",
204 "ESP200",
205 "NCR53C94",
206 "NCR53C96",
207 "ESP406",
208 "FAS408",
209 "FAS216",
210 "AM53C974",
211 "FAS366/HME",
212 "NCR53C90 (86C01)",
213 "FAS100A",
214 "FAS236",
215};
216
217/*
218 * Search linked list for LUN info by LUN id.
219 */
220static struct ncr53c9x_linfo *
221ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun)
222{
223 struct ncr53c9x_linfo *li;
224
225 LIST_FOREACH(li, &ti->luns, link)
226 if (li->lun == lun)
227 return (li);
228 return (NULL);
229}
230
231/*
232 * Attach this instance, and then all the sub-devices.
233 */
234int
235ncr53c9x_attach(struct ncr53c9x_softc *sc)
236{
237 struct cam_devq *devq;
238 struct cam_sim *sim;
239 struct cam_path *path;
240 struct ncr53c9x_ecb *ecb;
241 int error, i;
242
243 if (NCR_LOCK_INITIALIZED(sc) == 0) {
244 device_printf(sc->sc_dev, "mutex not initialized\n");
245 return (ENXIO);
246 }
247
248 callout_init_mtx(&sc->sc_watchdog, &sc->sc_lock, 0);
249
250 /*
251 * Note, the front-end has set us up to print the chip variation.
252 */
253 if (sc->sc_rev >= NCR_VARIANT_MAX) {
254 device_printf(sc->sc_dev, "unknown variant %d, devices not "
255 "attached\n", sc->sc_rev);
256 return (EINVAL);
257 }
258
259 device_printf(sc->sc_dev, "%s, %dMHz, SCSI ID %d\n",
260 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id);
261
262 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8;
263
264 /*
265 * Allocate SCSI message buffers.
266 * Front-ends can override allocation to avoid alignment
267 * handling in the DMA engines. Note that ncr53c9x_msgout()
268 * can request a 1 byte DMA transfer.
269 */
270 if (sc->sc_omess == NULL) {
271 sc->sc_omess_self = 1;
272 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT);
273 if (sc->sc_omess == NULL) {
274 device_printf(sc->sc_dev,
275 "cannot allocate MSGOUT buffer\n");
276 return (ENOMEM);
277 }
278 } else
279 sc->sc_omess_self = 0;
280
281 if (sc->sc_imess == NULL) {
282 sc->sc_imess_self = 1;
283 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT);
284 if (sc->sc_imess == NULL) {
285 device_printf(sc->sc_dev,
286 "cannot allocate MSGIN buffer\n");
287 error = ENOMEM;
288 goto fail_omess;
289 }
290 } else
291 sc->sc_imess_self = 0;
292
293 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]),
294 M_DEVBUF, M_NOWAIT | M_ZERO);
295 if (sc->sc_tinfo == NULL) {
296 device_printf(sc->sc_dev,
297 "cannot allocate target info buffer\n");
298 error = ENOMEM;
299 goto fail_imess;
300 }
301
302 /*
303 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100
304 * from now on.
305 */
306 if (sc->sc_rev == NCR_VARIANT_NCR53C90_86C01)
307 sc->sc_rev = NCR_VARIANT_ESP100;
308
309 sc->sc_ccf = FREQTOCCF(sc->sc_freq);
310
311 /* The value *must not* be == 1. Make it 2. */
312 if (sc->sc_ccf == 1)
313 sc->sc_ccf = 2;
314
315 /*
316 * The recommended timeout is 250ms. This register is loaded
317 * with a value calculated as follows, from the docs:
318 *
319 * (timout period) x (CLK frequency)
320 * reg = -------------------------------------
321 * 8192 x (Clock Conversion Factor)
322 *
323 * Since CCF has a linear relation to CLK, this generally computes
324 * to the constant of 153.
325 */
326 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf);
327
328 /* The CCF register only has 3 bits; 0 is actually 8. */
329 sc->sc_ccf &= 7;
330
331 /*
332 * Register with CAM.
333 */
334 devq = cam_simq_alloc(sc->sc_ntarg);
335 if (devq == NULL) {
336 device_printf(sc->sc_dev, "cannot allocate device queue\n");
337 error = ENOMEM;
338 goto fail_tinfo;
339 }
340
341 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc,
342 device_get_unit(sc->sc_dev), &sc->sc_lock, 1, NCR_TAG_DEPTH, devq);
343 if (sim == NULL) {
344 device_printf(sc->sc_dev, "cannot allocate SIM entry\n");
345 error = ENOMEM;
346 goto fail_devq;
347 }
348
349 NCR_LOCK(sc);
350
351 if (xpt_bus_register(sim, sc->sc_dev, 0) != CAM_SUCCESS) {
352 device_printf(sc->sc_dev, "cannot register bus\n");
353 error = EIO;
354 goto fail_lock;
355 }
356
357 if (xpt_create_path(&path, NULL, cam_sim_path(sim),
358 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
359 device_printf(sc->sc_dev, "cannot create path\n");
360 error = EIO;
361 goto fail_bus;
362 }
363
364 if (xpt_register_async(AC_LOST_DEVICE, ncr53c9x_async, sim, path) !=
365 CAM_REQ_CMP) {
366 device_printf(sc->sc_dev, "cannot register async handler\n");
367 error = EIO;
368 goto fail_path;
369 }
370
371 sc->sc_sim = sim;
372 sc->sc_path = path;
373
374 /* Reset state and bus. */
375#if 0
376 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags;
377#else
378 sc->sc_cfflags = 0;
379#endif
380 sc->sc_state = 0;
381 ncr53c9x_init(sc, 1);
382
383 TAILQ_INIT(&sc->free_list);
384 if ((sc->ecb_array =
385 malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH, M_DEVBUF,
386 M_NOWAIT | M_ZERO)) == NULL) {
387 device_printf(sc->sc_dev, "cannot allocate ECB array\n");
388 error = ENOMEM;
389 goto fail_async;
390 }
391 for (i = 0; i < NCR_TAG_DEPTH; i++) {
392 ecb = &sc->ecb_array[i];
393 ecb->sc = sc;
394 ecb->tag_id = i;
|
| 395 callout_init_mtx(&ecb->ch, &sc->sc_lock, 0);
|
394 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links);
395 }
396
397 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
398
399 NCR_UNLOCK(sc);
400
401 return (0);
402
403fail_async:
404 xpt_register_async(0, ncr53c9x_async, sim, path);
405fail_path:
406 xpt_free_path(path);
407fail_bus:
408 xpt_bus_deregister(cam_sim_path(sim));
409fail_lock:
410 NCR_UNLOCK(sc);
411 cam_sim_free(sim, TRUE);
412fail_devq:
413 cam_simq_free(devq);
414fail_tinfo:
415 free(sc->sc_tinfo, M_DEVBUF);
416fail_imess:
417 if (sc->sc_imess_self)
418 free(sc->sc_imess, M_DEVBUF);
419fail_omess:
420 if (sc->sc_omess_self)
421 free(sc->sc_omess, M_DEVBUF);
422 return (error);
423}
424
425int
426ncr53c9x_detach(struct ncr53c9x_softc *sc)
427{
428 struct ncr53c9x_linfo *li, *nextli;
429 int t;
430
431 callout_drain(&sc->sc_watchdog);
432
433 NCR_LOCK(sc);
434
435 if (sc->sc_tinfo) {
436 /* Cancel all commands. */
437 ncr53c9x_clear(sc, CAM_REQ_ABORTED);
438
439 /* Free logical units. */
440 for (t = 0; t < sc->sc_ntarg; t++) {
441 for (li = LIST_FIRST(&sc->sc_tinfo[t].luns); li;
442 li = nextli) {
443 nextli = LIST_NEXT(li, link);
444 free(li, M_DEVBUF);
445 }
446 }
447 }
448
449 xpt_register_async(0, ncr53c9x_async, sc->sc_sim, sc->sc_path);
450 xpt_free_path(sc->sc_path);
451 xpt_bus_deregister(cam_sim_path(sc->sc_sim));
| 396 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links);
397 }
398
399 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
400
401 NCR_UNLOCK(sc);
402
403 return (0);
404
405fail_async:
406 xpt_register_async(0, ncr53c9x_async, sim, path);
407fail_path:
408 xpt_free_path(path);
409fail_bus:
410 xpt_bus_deregister(cam_sim_path(sim));
411fail_lock:
412 NCR_UNLOCK(sc);
413 cam_sim_free(sim, TRUE);
414fail_devq:
415 cam_simq_free(devq);
416fail_tinfo:
417 free(sc->sc_tinfo, M_DEVBUF);
418fail_imess:
419 if (sc->sc_imess_self)
420 free(sc->sc_imess, M_DEVBUF);
421fail_omess:
422 if (sc->sc_omess_self)
423 free(sc->sc_omess, M_DEVBUF);
424 return (error);
425}
426
427int
428ncr53c9x_detach(struct ncr53c9x_softc *sc)
429{
430 struct ncr53c9x_linfo *li, *nextli;
431 int t;
432
433 callout_drain(&sc->sc_watchdog);
434
435 NCR_LOCK(sc);
436
437 if (sc->sc_tinfo) {
438 /* Cancel all commands. */
439 ncr53c9x_clear(sc, CAM_REQ_ABORTED);
440
441 /* Free logical units. */
442 for (t = 0; t < sc->sc_ntarg; t++) {
443 for (li = LIST_FIRST(&sc->sc_tinfo[t].luns); li;
444 li = nextli) {
445 nextli = LIST_NEXT(li, link);
446 free(li, M_DEVBUF);
447 }
448 }
449 }
450
451 xpt_register_async(0, ncr53c9x_async, sc->sc_sim, sc->sc_path);
452 xpt_free_path(sc->sc_path);
453 xpt_bus_deregister(cam_sim_path(sc->sc_sim));
|
| 454 cam_sim_free(sc->sc_sim, TRUE);
|
452
453 NCR_UNLOCK(sc);
454
| 455
456 NCR_UNLOCK(sc);
457
|
455 cam_sim_free(sc->sc_sim, TRUE);
| |
456 free(sc->ecb_array, M_DEVBUF);
457 free(sc->sc_tinfo, M_DEVBUF);
458 if (sc->sc_imess_self)
459 free(sc->sc_imess, M_DEVBUF);
460 if (sc->sc_omess_self)
461 free(sc->sc_omess, M_DEVBUF);
462
463 return (0);
464}
465
466/*
467 * This is the generic ncr53c9x reset function. It does not reset the SCSI
468 * bus, only this controller, but kills any on-going commands, and also stops
469 * and resets the DMA.
470 *
471 * After reset, registers are loaded with the defaults from the attach
472 * routine above.
473 */
474static void
475ncr53c9x_reset(struct ncr53c9x_softc *sc)
476{
477
478 NCR_LOCK_ASSERT(sc, MA_OWNED);
479
480 /* Reset DMA first. */
481 NCRDMA_RESET(sc);
482
483 /* Reset SCSI chip. */
484 NCRCMD(sc, NCRCMD_RSTCHIP);
485 NCRCMD(sc, NCRCMD_NOP);
486 DELAY(500);
487
488 /* Do these backwards, and fall through. */
489 switch (sc->sc_rev) {
490 case NCR_VARIANT_ESP406:
491 case NCR_VARIANT_FAS408:
492 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT);
493 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4);
494 /* FALLTHROUGH */
495 case NCR_VARIANT_AM53C974:
496 case NCR_VARIANT_FAS100A:
497 case NCR_VARIANT_FAS216:
498 case NCR_VARIANT_FAS236:
499 case NCR_VARIANT_NCR53C94:
500 case NCR_VARIANT_NCR53C96:
501 case NCR_VARIANT_ESP200:
502 sc->sc_features |= NCR_F_HASCFG3;
503 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
504 /* FALLTHROUGH */
505 case NCR_VARIANT_ESP100A:
506 sc->sc_features |= NCR_F_SELATN3;
| 458 free(sc->ecb_array, M_DEVBUF);
459 free(sc->sc_tinfo, M_DEVBUF);
460 if (sc->sc_imess_self)
461 free(sc->sc_imess, M_DEVBUF);
462 if (sc->sc_omess_self)
463 free(sc->sc_omess, M_DEVBUF);
464
465 return (0);
466}
467
468/*
469 * This is the generic ncr53c9x reset function. It does not reset the SCSI
470 * bus, only this controller, but kills any on-going commands, and also stops
471 * and resets the DMA.
472 *
473 * After reset, registers are loaded with the defaults from the attach
474 * routine above.
475 */
476static void
477ncr53c9x_reset(struct ncr53c9x_softc *sc)
478{
479
480 NCR_LOCK_ASSERT(sc, MA_OWNED);
481
482 /* Reset DMA first. */
483 NCRDMA_RESET(sc);
484
485 /* Reset SCSI chip. */
486 NCRCMD(sc, NCRCMD_RSTCHIP);
487 NCRCMD(sc, NCRCMD_NOP);
488 DELAY(500);
489
490 /* Do these backwards, and fall through. */
491 switch (sc->sc_rev) {
492 case NCR_VARIANT_ESP406:
493 case NCR_VARIANT_FAS408:
494 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT);
495 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4);
496 /* FALLTHROUGH */
497 case NCR_VARIANT_AM53C974:
498 case NCR_VARIANT_FAS100A:
499 case NCR_VARIANT_FAS216:
500 case NCR_VARIANT_FAS236:
501 case NCR_VARIANT_NCR53C94:
502 case NCR_VARIANT_NCR53C96:
503 case NCR_VARIANT_ESP200:
504 sc->sc_features |= NCR_F_HASCFG3;
505 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
506 /* FALLTHROUGH */
507 case NCR_VARIANT_ESP100A:
508 sc->sc_features |= NCR_F_SELATN3;
|
| 509 if ((sc->sc_cfg2 & NCRCFG2_FE) != 0)
510 sc->sc_features |= NCR_F_LARGEXFER;
|
507 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
508 /* FALLTHROUGH */
509 case NCR_VARIANT_ESP100:
510 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
511 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
512 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
513 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
514 break;
515
516 case NCR_VARIANT_FAS366:
| 511 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
512 /* FALLTHROUGH */
513 case NCR_VARIANT_ESP100:
514 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
515 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
516 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
517 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
518 break;
519
520 case NCR_VARIANT_FAS366:
|
517 sc->sc_features |=
518 NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3;
| 521 sc->sc_features |= NCR_F_HASCFG3 | NCR_F_FASTSCSI |
522 NCR_F_SELATN3 | NCR_F_LARGEXFER;
|
519 sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO;
520 if (sc->sc_id > 7)
521 sc->sc_cfg3 |= NCRFASCFG3_IDBIT3;
522 sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI;
523 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
524 sc->sc_cfg2 = NCRCFG2_HMEFE | NCRCFG2_HME32;
525 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
526 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
527 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
528 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
529 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
530 break;
531
532 default:
533 device_printf(sc->sc_dev,
534 "unknown revision code, assuming ESP100\n");
535 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
536 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
537 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
538 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
539 }
540
541 if (sc->sc_rev == NCR_VARIANT_AM53C974)
542 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4);
543
544#if 0
545 device_printf(sc->sc_dev, "%s: revision %d\n", __func__, sc->sc_rev);
546 device_printf(sc->sc_dev, "%s: cfg1 0x%x, cfg2 0x%x, cfg3 0x%x, ccf "
547 "0x%x, timeout 0x%x\n", __func__, sc->sc_cfg1, sc->sc_cfg2,
548 sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout);
549#endif
550}
551
552/*
553 * Clear all commands.
554 */
555static void
556ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result)
557{
558 struct ncr53c9x_ecb *ecb;
559 int r;
560
561 NCR_LOCK_ASSERT(sc, MA_OWNED);
562
563 /* Cancel any active commands. */
564 sc->sc_state = NCR_CLEANING;
565 sc->sc_msgify = 0;
566 ecb = sc->sc_nexus;
567 if (ecb != NULL) {
568 ecb->ccb->ccb_h.status = result;
569 ncr53c9x_done(sc, ecb);
570 }
571 /* Cancel outstanding disconnected commands. */
572 for (r = 0; r < sc->sc_ntarg; r++)
573 ncr53c9x_clear_target(sc, r, result);
574}
575
576/*
577 * Clear all commands for a specific target.
578 */
579static void
580ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target,
581 cam_status result)
582{
583 struct ncr53c9x_ecb *ecb;
584 struct ncr53c9x_linfo *li;
585 int i;
586
587 NCR_LOCK_ASSERT(sc, MA_OWNED);
588
589 /* Cancel outstanding disconnected commands on each LUN. */
590 LIST_FOREACH(li, &sc->sc_tinfo[target].luns, link) {
591 ecb = li->untagged;
592 if (ecb != NULL) {
593 li->untagged = NULL;
594 /*
595 * XXX should we terminate a command
596 * that never reached the disk?
597 */
598 li->busy = 0;
599 ecb->ccb->ccb_h.status = result;
600 ncr53c9x_done(sc, ecb);
601 }
602 for (i = 0; i < NCR_TAG_DEPTH; i++) {
603 ecb = li->queued[i];
604 if (ecb != NULL) {
605 li->queued[i] = NULL;
606 ecb->ccb->ccb_h.status = result;
607 ncr53c9x_done(sc, ecb);
608 }
609 }
610 li->used = 0;
611 }
612}
613
614/*
615 * Initialize ncr53c9x state machine.
616 */
617static void
618ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset)
619{
620 struct ncr53c9x_tinfo *ti;
621 int r;
622
623 NCR_LOCK_ASSERT(sc, MA_OWNED);
624
625 NCR_MISC(("[NCR_INIT(%d) %d] ", doreset, sc->sc_state));
626
627 if (sc->sc_state == 0) {
628 /* First time through; initialize. */
629
630 TAILQ_INIT(&sc->ready_list);
631 sc->sc_nexus = NULL;
632 memset(sc->sc_tinfo, 0, sizeof(*sc->sc_tinfo));
633 for (r = 0; r < sc->sc_ntarg; r++) {
634 LIST_INIT(&sc->sc_tinfo[r].luns);
635 }
636 } else
637 ncr53c9x_clear(sc, CAM_CMD_TIMEOUT);
638
639 /*
640 * Reset the chip to a known state.
641 */
642 ncr53c9x_reset(sc);
643
644 sc->sc_flags = 0;
645 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
646 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
647
648 /*
649 * If we're the first time through, set the default parameters
650 * for all targets. Otherwise we only clear their current transfer
651 * settings so we'll renegotiate their goal settings with the next
652 * command.
653 */
654 if (sc->sc_state == 0) {
655 for (r = 0; r < sc->sc_ntarg; r++) {
656 ti = &sc->sc_tinfo[r];
657/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
658
659 ti->flags = ((sc->sc_minsync != 0 &&
660 (sc->sc_cfflags & (1 << ((r & 7) + 8))) == 0) ?
661 0 : T_SYNCHOFF) |
662 ((sc->sc_cfflags & (1 << (r & 7))) == 0 ?
663 0 : T_RSELECTOFF);
664 ti->curr.period = ti->goal.period = 0;
665 ti->curr.offset = ti->goal.offset = 0;
666 ti->curr.width = ti->goal.width =
667 MSG_EXT_WDTR_BUS_8_BIT;
668 }
669 } else {
670 for (r = 0; r < sc->sc_ntarg; r++) {
671 ti = &sc->sc_tinfo[r];
672 ti->flags &= ~(T_SDTRSENT | T_WDTRSENT);
673 ti->curr.period = 0;
674 ti->curr.offset = 0;
675 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
676 }
677 }
678
679 if (doreset) {
680 sc->sc_state = NCR_SBR;
681 NCRCMD(sc, NCRCMD_RSTSCSI);
682 /* Give the bus a fighting chance to settle. */
683 DELAY(250000);
684 } else {
685 sc->sc_state = NCR_IDLE;
686 ncr53c9x_sched(sc);
687 }
688}
689
690/*
691 * Read the NCR registers, and save their contents for later use.
692 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading
693 * NCR_INTR - so make sure it is the last read.
694 *
695 * I think that (from reading the docs) most bits in these registers
696 * only make sense when the DMA CSR has an interrupt showing. Call only
697 * if an interrupt is pending.
698 */
699static inline void
700ncr53c9x_readregs(struct ncr53c9x_softc *sc)
701{
702
703 NCR_LOCK_ASSERT(sc, MA_OWNED);
704
705 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT);
706 /* Only the step bits are of interest. */
707 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK;
708
709 if (sc->sc_rev == NCR_VARIANT_FAS366)
710 sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2);
711
712 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR);
713
| 523 sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO;
524 if (sc->sc_id > 7)
525 sc->sc_cfg3 |= NCRFASCFG3_IDBIT3;
526 sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI;
527 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
528 sc->sc_cfg2 = NCRCFG2_HMEFE | NCRCFG2_HME32;
529 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
530 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
531 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
532 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
533 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
534 break;
535
536 default:
537 device_printf(sc->sc_dev,
538 "unknown revision code, assuming ESP100\n");
539 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
540 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
541 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
542 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
543 }
544
545 if (sc->sc_rev == NCR_VARIANT_AM53C974)
546 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4);
547
548#if 0
549 device_printf(sc->sc_dev, "%s: revision %d\n", __func__, sc->sc_rev);
550 device_printf(sc->sc_dev, "%s: cfg1 0x%x, cfg2 0x%x, cfg3 0x%x, ccf "
551 "0x%x, timeout 0x%x\n", __func__, sc->sc_cfg1, sc->sc_cfg2,
552 sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout);
553#endif
554}
555
556/*
557 * Clear all commands.
558 */
559static void
560ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result)
561{
562 struct ncr53c9x_ecb *ecb;
563 int r;
564
565 NCR_LOCK_ASSERT(sc, MA_OWNED);
566
567 /* Cancel any active commands. */
568 sc->sc_state = NCR_CLEANING;
569 sc->sc_msgify = 0;
570 ecb = sc->sc_nexus;
571 if (ecb != NULL) {
572 ecb->ccb->ccb_h.status = result;
573 ncr53c9x_done(sc, ecb);
574 }
575 /* Cancel outstanding disconnected commands. */
576 for (r = 0; r < sc->sc_ntarg; r++)
577 ncr53c9x_clear_target(sc, r, result);
578}
579
580/*
581 * Clear all commands for a specific target.
582 */
583static void
584ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target,
585 cam_status result)
586{
587 struct ncr53c9x_ecb *ecb;
588 struct ncr53c9x_linfo *li;
589 int i;
590
591 NCR_LOCK_ASSERT(sc, MA_OWNED);
592
593 /* Cancel outstanding disconnected commands on each LUN. */
594 LIST_FOREACH(li, &sc->sc_tinfo[target].luns, link) {
595 ecb = li->untagged;
596 if (ecb != NULL) {
597 li->untagged = NULL;
598 /*
599 * XXX should we terminate a command
600 * that never reached the disk?
601 */
602 li->busy = 0;
603 ecb->ccb->ccb_h.status = result;
604 ncr53c9x_done(sc, ecb);
605 }
606 for (i = 0; i < NCR_TAG_DEPTH; i++) {
607 ecb = li->queued[i];
608 if (ecb != NULL) {
609 li->queued[i] = NULL;
610 ecb->ccb->ccb_h.status = result;
611 ncr53c9x_done(sc, ecb);
612 }
613 }
614 li->used = 0;
615 }
616}
617
618/*
619 * Initialize ncr53c9x state machine.
620 */
621static void
622ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset)
623{
624 struct ncr53c9x_tinfo *ti;
625 int r;
626
627 NCR_LOCK_ASSERT(sc, MA_OWNED);
628
629 NCR_MISC(("[NCR_INIT(%d) %d] ", doreset, sc->sc_state));
630
631 if (sc->sc_state == 0) {
632 /* First time through; initialize. */
633
634 TAILQ_INIT(&sc->ready_list);
635 sc->sc_nexus = NULL;
636 memset(sc->sc_tinfo, 0, sizeof(*sc->sc_tinfo));
637 for (r = 0; r < sc->sc_ntarg; r++) {
638 LIST_INIT(&sc->sc_tinfo[r].luns);
639 }
640 } else
641 ncr53c9x_clear(sc, CAM_CMD_TIMEOUT);
642
643 /*
644 * Reset the chip to a known state.
645 */
646 ncr53c9x_reset(sc);
647
648 sc->sc_flags = 0;
649 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
650 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
651
652 /*
653 * If we're the first time through, set the default parameters
654 * for all targets. Otherwise we only clear their current transfer
655 * settings so we'll renegotiate their goal settings with the next
656 * command.
657 */
658 if (sc->sc_state == 0) {
659 for (r = 0; r < sc->sc_ntarg; r++) {
660 ti = &sc->sc_tinfo[r];
661/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
662
663 ti->flags = ((sc->sc_minsync != 0 &&
664 (sc->sc_cfflags & (1 << ((r & 7) + 8))) == 0) ?
665 0 : T_SYNCHOFF) |
666 ((sc->sc_cfflags & (1 << (r & 7))) == 0 ?
667 0 : T_RSELECTOFF);
668 ti->curr.period = ti->goal.period = 0;
669 ti->curr.offset = ti->goal.offset = 0;
670 ti->curr.width = ti->goal.width =
671 MSG_EXT_WDTR_BUS_8_BIT;
672 }
673 } else {
674 for (r = 0; r < sc->sc_ntarg; r++) {
675 ti = &sc->sc_tinfo[r];
676 ti->flags &= ~(T_SDTRSENT | T_WDTRSENT);
677 ti->curr.period = 0;
678 ti->curr.offset = 0;
679 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
680 }
681 }
682
683 if (doreset) {
684 sc->sc_state = NCR_SBR;
685 NCRCMD(sc, NCRCMD_RSTSCSI);
686 /* Give the bus a fighting chance to settle. */
687 DELAY(250000);
688 } else {
689 sc->sc_state = NCR_IDLE;
690 ncr53c9x_sched(sc);
691 }
692}
693
694/*
695 * Read the NCR registers, and save their contents for later use.
696 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading
697 * NCR_INTR - so make sure it is the last read.
698 *
699 * I think that (from reading the docs) most bits in these registers
700 * only make sense when the DMA CSR has an interrupt showing. Call only
701 * if an interrupt is pending.
702 */
703static inline void
704ncr53c9x_readregs(struct ncr53c9x_softc *sc)
705{
706
707 NCR_LOCK_ASSERT(sc, MA_OWNED);
708
709 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT);
710 /* Only the step bits are of interest. */
711 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK;
712
713 if (sc->sc_rev == NCR_VARIANT_FAS366)
714 sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2);
715
716 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR);
717
|
714 if (sc->sc_glue->gl_clear_latched_intr != NULL)
715 (*sc->sc_glue->gl_clear_latched_intr)(sc);
716
| |
717 /*
718 * Determine the SCSI bus phase, return either a real SCSI bus phase
719 * or some pseudo phase we use to detect certain exceptions.
720 */
721 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) ?
722 BUSFREE_PHASE : sc->sc_espstat & NCRSTAT_PHASE;
723
724 NCR_INTS(("regs[intr=%02x,stat=%02x,step=%02x,stat2=%02x] ",
725 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep, sc->sc_espstat2));
726}
727
728/*
729 * Convert Synchronous Transfer Period to chip register Clock Per Byte value.
730 */
731static inline int
732ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period)
733{
734 int v;
735
736 NCR_LOCK_ASSERT(sc, MA_OWNED);
737
738 v = (sc->sc_freq * period) / 250;
739 if (ncr53c9x_cpb2stp(sc, v) < period)
740 /* Correct round-down error. */
741 v++;
742 return (v);
743}
744
745static inline void
746ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti)
747{
748 uint8_t cfg3, syncoff, synctp;
749
750 NCR_LOCK_ASSERT(sc, MA_OWNED);
751
752 cfg3 = sc->sc_cfg3;
753 if (ti->curr.offset != 0) {
754 syncoff = ti->curr.offset;
755 synctp = ncr53c9x_stp2cpb(sc, ti->curr.period);
756 if (sc->sc_features & NCR_F_FASTSCSI) {
757 /*
758 * If the period is 200ns or less (ti->period <= 50),
759 * put the chip in Fast SCSI mode.
760 */
761 if (ti->curr.period <= 50)
762 /*
763 * There are (at least) 4 variations of the
764 * configuration 3 register. The drive attach
765 * routine sets the appropriate bit to put the
766 * chip into Fast SCSI mode so that it doesn't
767 * have to be figured out here each time.
768 */
769 cfg3 |= sc->sc_cfg3_fscsi;
770 }
771
772 /*
773 * Am53c974 requires different SYNCTP values when the
774 * FSCSI bit is off.
775 */
776 if (sc->sc_rev == NCR_VARIANT_AM53C974 &&
777 (cfg3 & NCRAMDCFG3_FSCSI) == 0)
778 synctp--;
779 } else {
780 syncoff = 0;
781 synctp = 0;
782 }
783
784 if (ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT) {
785 if (sc->sc_rev == NCR_VARIANT_FAS366)
786 cfg3 |= NCRFASCFG3_EWIDE;
787 }
788
789 if (sc->sc_features & NCR_F_HASCFG3)
790 NCR_WRITE_REG(sc, NCR_CFG3, cfg3);
791
792 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff);
793 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp);
794}
795
796/*
797 * Send a command to a target, set the driver state to NCR_SELECTING
798 * and let the caller take care of the rest.
799 *
800 * Keeping this as a function allows me to say that this may be done
801 * by DMA instead of programmed I/O soon.
802 */
803static void
804ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
805{
806 struct ncr53c9x_tinfo *ti;
807 uint8_t *cmd;
808 size_t dmasize;
| 718 /*
719 * Determine the SCSI bus phase, return either a real SCSI bus phase
720 * or some pseudo phase we use to detect certain exceptions.
721 */
722 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) ?
723 BUSFREE_PHASE : sc->sc_espstat & NCRSTAT_PHASE;
724
725 NCR_INTS(("regs[intr=%02x,stat=%02x,step=%02x,stat2=%02x] ",
726 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep, sc->sc_espstat2));
727}
728
729/*
730 * Convert Synchronous Transfer Period to chip register Clock Per Byte value.
731 */
732static inline int
733ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period)
734{
735 int v;
736
737 NCR_LOCK_ASSERT(sc, MA_OWNED);
738
739 v = (sc->sc_freq * period) / 250;
740 if (ncr53c9x_cpb2stp(sc, v) < period)
741 /* Correct round-down error. */
742 v++;
743 return (v);
744}
745
746static inline void
747ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti)
748{
749 uint8_t cfg3, syncoff, synctp;
750
751 NCR_LOCK_ASSERT(sc, MA_OWNED);
752
753 cfg3 = sc->sc_cfg3;
754 if (ti->curr.offset != 0) {
755 syncoff = ti->curr.offset;
756 synctp = ncr53c9x_stp2cpb(sc, ti->curr.period);
757 if (sc->sc_features & NCR_F_FASTSCSI) {
758 /*
759 * If the period is 200ns or less (ti->period <= 50),
760 * put the chip in Fast SCSI mode.
761 */
762 if (ti->curr.period <= 50)
763 /*
764 * There are (at least) 4 variations of the
765 * configuration 3 register. The drive attach
766 * routine sets the appropriate bit to put the
767 * chip into Fast SCSI mode so that it doesn't
768 * have to be figured out here each time.
769 */
770 cfg3 |= sc->sc_cfg3_fscsi;
771 }
772
773 /*
774 * Am53c974 requires different SYNCTP values when the
775 * FSCSI bit is off.
776 */
777 if (sc->sc_rev == NCR_VARIANT_AM53C974 &&
778 (cfg3 & NCRAMDCFG3_FSCSI) == 0)
779 synctp--;
780 } else {
781 syncoff = 0;
782 synctp = 0;
783 }
784
785 if (ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT) {
786 if (sc->sc_rev == NCR_VARIANT_FAS366)
787 cfg3 |= NCRFASCFG3_EWIDE;
788 }
789
790 if (sc->sc_features & NCR_F_HASCFG3)
791 NCR_WRITE_REG(sc, NCR_CFG3, cfg3);
792
793 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff);
794 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp);
795}
796
797/*
798 * Send a command to a target, set the driver state to NCR_SELECTING
799 * and let the caller take care of the rest.
800 *
801 * Keeping this as a function allows me to say that this may be done
802 * by DMA instead of programmed I/O soon.
803 */
804static void
805ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
806{
807 struct ncr53c9x_tinfo *ti;
808 uint8_t *cmd;
809 size_t dmasize;
|
809 int clen, selatn3, selatns;
| 810 int clen, error, selatn3, selatns;
|
810 int lun = ecb->ccb->ccb_h.target_lun;
811 int target = ecb->ccb->ccb_h.target_id;
812
813 NCR_LOCK_ASSERT(sc, MA_OWNED);
814
815 NCR_TRACE(("[%s(t%d,l%d,cmd:%x,tag:%x,%x)] ", __func__, target, lun,
816 ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1]));
817
818 ti = &sc->sc_tinfo[target];
819 sc->sc_state = NCR_SELECTING;
820 /*
821 * Schedule the callout now, the first time we will go away
822 * expecting to come back due to an interrupt, because it is
823 * always possible that the interrupt may never happen.
824 */
825 callout_reset(&ecb->ch, mstohz(ecb->timeout), ncr53c9x_callout, ecb);
826
827 /*
828 * The docs say the target register is never reset, and I
829 * can't think of a better place to set it.
830 */
831 if (sc->sc_rev == NCR_VARIANT_FAS366) {
832 NCRCMD(sc, NCRCMD_FLUSH);
833 NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HMEXC32 |
834 NCR_BUSID_HMEENCID);
835 } else
836 NCR_WRITE_REG(sc, NCR_SELID, target);
837
838 /*
839 * If we are requesting sense, force a renegotiation if we are
840 * currently using anything different from asynchronous at 8 bit
841 * as the target might have lost our transfer negotiations.
842 */
843 if ((ecb->flags & ECB_SENSE) != 0 && (ti->curr.offset != 0 ||
844 ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT)) {
845 ti->curr.period = 0;
846 ti->curr.offset = 0;
847 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
848 }
849 ncr53c9x_setsync(sc, ti);
850
851 selatn3 = selatns = 0;
852 if (ecb->tag[0] != 0) {
853 if (sc->sc_features & NCR_F_SELATN3)
854 /* Use SELATN3 to send tag messages. */
855 selatn3 = 1;
856 else
857 /* We don't have SELATN3; use SELATNS to send tags. */
858 selatns = 1;
859 }
860
861 if (ti->curr.period != ti->goal.period ||
862 ti->curr.offset != ti->goal.offset ||
863 ti->curr.width != ti->goal.width) {
864 /* We have to use SELATNS to send sync/wide messages. */
865 selatn3 = 0;
866 selatns = 1;
867 }
868
869 cmd = (uint8_t *)&ecb->cmd.cmd;
870
871 if (selatn3) {
872 /* We'll use tags with SELATN3. */
873 clen = ecb->clen + 3;
874 cmd -= 3;
875 cmd[0] = MSG_IDENTIFY(lun, 1); /* msg[0] */
876 cmd[1] = ecb->tag[0]; /* msg[1] */
877 cmd[2] = ecb->tag[1]; /* msg[2] */
878 } else {
879 /* We don't have tags, or will send messages with SELATNS. */
880 clen = ecb->clen + 1;
881 cmd -= 1;
882 cmd[0] = MSG_IDENTIFY(lun, (ti->flags & T_RSELECTOFF) == 0);
883 }
884
885 if ((sc->sc_features & NCR_F_DMASELECT) && !selatns) {
886 /* Setup DMA transfer for command. */
887 dmasize = clen;
888 sc->sc_cmdlen = clen;
889 sc->sc_cmdp = cmd;
| 811 int lun = ecb->ccb->ccb_h.target_lun;
812 int target = ecb->ccb->ccb_h.target_id;
813
814 NCR_LOCK_ASSERT(sc, MA_OWNED);
815
816 NCR_TRACE(("[%s(t%d,l%d,cmd:%x,tag:%x,%x)] ", __func__, target, lun,
817 ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1]));
818
819 ti = &sc->sc_tinfo[target];
820 sc->sc_state = NCR_SELECTING;
821 /*
822 * Schedule the callout now, the first time we will go away
823 * expecting to come back due to an interrupt, because it is
824 * always possible that the interrupt may never happen.
825 */
826 callout_reset(&ecb->ch, mstohz(ecb->timeout), ncr53c9x_callout, ecb);
827
828 /*
829 * The docs say the target register is never reset, and I
830 * can't think of a better place to set it.
831 */
832 if (sc->sc_rev == NCR_VARIANT_FAS366) {
833 NCRCMD(sc, NCRCMD_FLUSH);
834 NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HMEXC32 |
835 NCR_BUSID_HMEENCID);
836 } else
837 NCR_WRITE_REG(sc, NCR_SELID, target);
838
839 /*
840 * If we are requesting sense, force a renegotiation if we are
841 * currently using anything different from asynchronous at 8 bit
842 * as the target might have lost our transfer negotiations.
843 */
844 if ((ecb->flags & ECB_SENSE) != 0 && (ti->curr.offset != 0 ||
845 ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT)) {
846 ti->curr.period = 0;
847 ti->curr.offset = 0;
848 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
849 }
850 ncr53c9x_setsync(sc, ti);
851
852 selatn3 = selatns = 0;
853 if (ecb->tag[0] != 0) {
854 if (sc->sc_features & NCR_F_SELATN3)
855 /* Use SELATN3 to send tag messages. */
856 selatn3 = 1;
857 else
858 /* We don't have SELATN3; use SELATNS to send tags. */
859 selatns = 1;
860 }
861
862 if (ti->curr.period != ti->goal.period ||
863 ti->curr.offset != ti->goal.offset ||
864 ti->curr.width != ti->goal.width) {
865 /* We have to use SELATNS to send sync/wide messages. */
866 selatn3 = 0;
867 selatns = 1;
868 }
869
870 cmd = (uint8_t *)&ecb->cmd.cmd;
871
872 if (selatn3) {
873 /* We'll use tags with SELATN3. */
874 clen = ecb->clen + 3;
875 cmd -= 3;
876 cmd[0] = MSG_IDENTIFY(lun, 1); /* msg[0] */
877 cmd[1] = ecb->tag[0]; /* msg[1] */
878 cmd[2] = ecb->tag[1]; /* msg[2] */
879 } else {
880 /* We don't have tags, or will send messages with SELATNS. */
881 clen = ecb->clen + 1;
882 cmd -= 1;
883 cmd[0] = MSG_IDENTIFY(lun, (ti->flags & T_RSELECTOFF) == 0);
884 }
885
886 if ((sc->sc_features & NCR_F_DMASELECT) && !selatns) {
887 /* Setup DMA transfer for command. */
888 dmasize = clen;
889 sc->sc_cmdlen = clen;
890 sc->sc_cmdp = cmd;
|
890 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize);
| 891 error = NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0,
892 &dmasize);
893 if (error != 0) {
894 sc->sc_cmdlen = 0;
895 sc->sc_cmdp = NULL;
896 goto cmd;
897 }
898
|
891 /* Program the SCSI counter. */
892 NCR_SET_COUNT(sc, dmasize);
893
894 /* Load the count in. */
| 899 /* Program the SCSI counter. */
900 NCR_SET_COUNT(sc, dmasize);
901
902 /* Load the count in. */
|
895 /* if (sc->sc_rev != NCR_VARIANT_FAS366) */
896 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
| 903 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
|
897
898 /* And get the target's attention. */
899 if (selatn3) {
900 sc->sc_msgout = SEND_TAG;
901 sc->sc_flags |= NCR_ATN;
902 NCRCMD(sc, NCRCMD_SELATN3 | NCRCMD_DMA);
903 } else
904 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA);
905 NCRDMA_GO(sc);
906 return;
907 }
908
| 904
905 /* And get the target's attention. */
906 if (selatn3) {
907 sc->sc_msgout = SEND_TAG;
908 sc->sc_flags |= NCR_ATN;
909 NCRCMD(sc, NCRCMD_SELATN3 | NCRCMD_DMA);
910 } else
911 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA);
912 NCRDMA_GO(sc);
913 return;
914 }
915
|
| 916cmd:
|
909 /*
910 * Who am I? This is where we tell the target that we are
911 * happy for it to disconnect etc.
912 */
913
914 /* Now get the command into the FIFO. */
915 ncr53c9x_wrfifo(sc, cmd, clen);
916
917 /* And get the target's attention. */
918 if (selatns) {
919 NCR_MSGS(("SELATNS \n"));
920 /* Arbitrate, select and stop after IDENTIFY message. */
921 NCRCMD(sc, NCRCMD_SELATNS);
922 } else if (selatn3) {
923 sc->sc_msgout = SEND_TAG;
924 sc->sc_flags |= NCR_ATN;
925 NCRCMD(sc, NCRCMD_SELATN3);
926 } else
927 NCRCMD(sc, NCRCMD_SELATN);
928}
929
930static void
931ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
932{
933
934 NCR_LOCK_ASSERT(sc, MA_OWNED);
935
936 ecb->flags = 0;
937 TAILQ_INSERT_TAIL(&sc->free_list, ecb, free_links);
938}
939
940static struct ncr53c9x_ecb *
941ncr53c9x_get_ecb(struct ncr53c9x_softc *sc)
942{
943 struct ncr53c9x_ecb *ecb;
944
945 NCR_LOCK_ASSERT(sc, MA_OWNED);
946
947 ecb = TAILQ_FIRST(&sc->free_list);
948 if (ecb) {
949 if (ecb->flags != 0)
950 panic("%s: ecb flags not cleared", __func__);
951 TAILQ_REMOVE(&sc->free_list, ecb, free_links);
952 ecb->flags = ECB_ALLOC;
953 bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) -
954 offsetof(struct ncr53c9x_ecb, ccb));
955 }
956 return (ecb);
957}
958
959/*
960 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS:
961 */
962
963/*
964 * Start a SCSI-command.
965 * This function is called by the higher level SCSI-driver to queue/run
966 * SCSI-commands.
967 */
968
969static void
970ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
971{
972 struct ccb_pathinq *cpi;
973 struct ccb_scsiio *csio;
974 struct ccb_trans_settings *cts;
975 struct ccb_trans_settings_scsi *scsi;
976 struct ccb_trans_settings_spi *spi;
977 struct ncr53c9x_ecb *ecb;
978 struct ncr53c9x_softc *sc;
979 struct ncr53c9x_tinfo *ti;
980 int target;
981
982 sc = cam_sim_softc(sim);
983
984 NCR_LOCK_ASSERT(sc, MA_OWNED);
985
986 NCR_TRACE(("[%s %d]", __func__, ccb->ccb_h.func_code));
987
988 switch (ccb->ccb_h.func_code) {
989 case XPT_RESET_BUS:
990 ncr53c9x_init(sc, 1);
991 ccb->ccb_h.status = CAM_REQ_CMP;
| 917 /*
918 * Who am I? This is where we tell the target that we are
919 * happy for it to disconnect etc.
920 */
921
922 /* Now get the command into the FIFO. */
923 ncr53c9x_wrfifo(sc, cmd, clen);
924
925 /* And get the target's attention. */
926 if (selatns) {
927 NCR_MSGS(("SELATNS \n"));
928 /* Arbitrate, select and stop after IDENTIFY message. */
929 NCRCMD(sc, NCRCMD_SELATNS);
930 } else if (selatn3) {
931 sc->sc_msgout = SEND_TAG;
932 sc->sc_flags |= NCR_ATN;
933 NCRCMD(sc, NCRCMD_SELATN3);
934 } else
935 NCRCMD(sc, NCRCMD_SELATN);
936}
937
938static void
939ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
940{
941
942 NCR_LOCK_ASSERT(sc, MA_OWNED);
943
944 ecb->flags = 0;
945 TAILQ_INSERT_TAIL(&sc->free_list, ecb, free_links);
946}
947
948static struct ncr53c9x_ecb *
949ncr53c9x_get_ecb(struct ncr53c9x_softc *sc)
950{
951 struct ncr53c9x_ecb *ecb;
952
953 NCR_LOCK_ASSERT(sc, MA_OWNED);
954
955 ecb = TAILQ_FIRST(&sc->free_list);
956 if (ecb) {
957 if (ecb->flags != 0)
958 panic("%s: ecb flags not cleared", __func__);
959 TAILQ_REMOVE(&sc->free_list, ecb, free_links);
960 ecb->flags = ECB_ALLOC;
961 bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) -
962 offsetof(struct ncr53c9x_ecb, ccb));
963 }
964 return (ecb);
965}
966
967/*
968 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS:
969 */
970
971/*
972 * Start a SCSI-command.
973 * This function is called by the higher level SCSI-driver to queue/run
974 * SCSI-commands.
975 */
976
977static void
978ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
979{
980 struct ccb_pathinq *cpi;
981 struct ccb_scsiio *csio;
982 struct ccb_trans_settings *cts;
983 struct ccb_trans_settings_scsi *scsi;
984 struct ccb_trans_settings_spi *spi;
985 struct ncr53c9x_ecb *ecb;
986 struct ncr53c9x_softc *sc;
987 struct ncr53c9x_tinfo *ti;
988 int target;
989
990 sc = cam_sim_softc(sim);
991
992 NCR_LOCK_ASSERT(sc, MA_OWNED);
993
994 NCR_TRACE(("[%s %d]", __func__, ccb->ccb_h.func_code));
995
996 switch (ccb->ccb_h.func_code) {
997 case XPT_RESET_BUS:
998 ncr53c9x_init(sc, 1);
999 ccb->ccb_h.status = CAM_REQ_CMP;
|
992 xpt_done(ccb);
993 return;
| 1000 break;
|
994
995 case XPT_CALC_GEOMETRY:
996 cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom);
| 1001
1002 case XPT_CALC_GEOMETRY:
1003 cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom);
|
997 xpt_done(ccb);
998 return;
| 1004 break;
|
999
1000 case XPT_PATH_INQ:
1001 cpi = &ccb->cpi;
1002 cpi->version_num = 1;
1003 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
1004 cpi->hba_inquiry |=
1005 (sc->sc_rev == NCR_VARIANT_FAS366) ? PI_WIDE_16 : 0;
1006 cpi->target_sprt = 0;
1007 cpi->hba_misc = 0;
1008 cpi->hba_eng_cnt = 0;
1009 cpi->max_target = sc->sc_ntarg - 1;
1010 cpi->max_lun = 7;
1011 cpi->initiator_id = sc->sc_id;
| 1005
1006 case XPT_PATH_INQ:
1007 cpi = &ccb->cpi;
1008 cpi->version_num = 1;
1009 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
1010 cpi->hba_inquiry |=
1011 (sc->sc_rev == NCR_VARIANT_FAS366) ? PI_WIDE_16 : 0;
1012 cpi->target_sprt = 0;
1013 cpi->hba_misc = 0;
1014 cpi->hba_eng_cnt = 0;
1015 cpi->max_target = sc->sc_ntarg - 1;
1016 cpi->max_lun = 7;
1017 cpi->initiator_id = sc->sc_id;
|
1012 cpi->bus_id = 0;
1013 cpi->base_transfer_speed = 3300;
| |
1014 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
| 1018 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
|
1015 strncpy(cpi->hba_vid, "Sun", HBA_IDLEN);
| 1019 strncpy(cpi->hba_vid, "NCR", HBA_IDLEN);
|
1016 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
1017 cpi->unit_number = cam_sim_unit(sim);
| 1020 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
1021 cpi->unit_number = cam_sim_unit(sim);
|
1018 cpi->transport = XPORT_SPI;
1019 cpi->transport_version = 2;
| 1022 cpi->bus_id = 0;
1023 cpi->base_transfer_speed = 3300;
|
1020 cpi->protocol = PROTO_SCSI;
1021 cpi->protocol_version = SCSI_REV_2;
| 1024 cpi->protocol = PROTO_SCSI;
1025 cpi->protocol_version = SCSI_REV_2;
|
| 1026 cpi->transport = XPORT_SPI;
1027 cpi->transport_version = 2;
1028 cpi->maxio = sc->sc_maxxfer;
|
1022 ccb->ccb_h.status = CAM_REQ_CMP;
| 1029 ccb->ccb_h.status = CAM_REQ_CMP;
|
1023 xpt_done(ccb);
1024 return;
| 1030 break;
|
1025
1026 case XPT_GET_TRAN_SETTINGS:
1027 cts = &ccb->cts;
1028 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
1029 scsi = &cts->proto_specific.scsi;
1030 spi = &cts->xport_specific.spi;
1031
1032 cts->protocol = PROTO_SCSI;
1033 cts->protocol_version = SCSI_REV_2;
1034 cts->transport = XPORT_SPI;
1035 cts->transport_version = 2;
1036
1037 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
1038 spi->sync_period = ti->curr.period;
1039 spi->sync_offset = ti->curr.offset;
1040 spi->bus_width = ti->curr.width;
1041 if ((ti->flags & T_TAG) != 0) {
1042 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
1043 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
1044 } else {
1045 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
1046 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB;
1047 }
1048 } else {
1049 if ((ti->flags & T_SYNCHOFF) != 0) {
1050 spi->sync_period = 0;
1051 spi->sync_offset = 0;
1052 } else {
1053 spi->sync_period = sc->sc_minsync;
1054 spi->sync_offset = sc->sc_maxoffset;
1055 }
1056 spi->bus_width = sc->sc_maxwidth;
1057 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
1058 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
1059 }
1060 spi->valid =
1061 CTS_SPI_VALID_BUS_WIDTH |
1062 CTS_SPI_VALID_SYNC_RATE |
1063 CTS_SPI_VALID_SYNC_OFFSET |
1064 CTS_SPI_VALID_DISC;
1065 scsi->valid = CTS_SCSI_VALID_TQ;
1066 ccb->ccb_h.status = CAM_REQ_CMP;
| 1031
1032 case XPT_GET_TRAN_SETTINGS:
1033 cts = &ccb->cts;
1034 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
1035 scsi = &cts->proto_specific.scsi;
1036 spi = &cts->xport_specific.spi;
1037
1038 cts->protocol = PROTO_SCSI;
1039 cts->protocol_version = SCSI_REV_2;
1040 cts->transport = XPORT_SPI;
1041 cts->transport_version = 2;
1042
1043 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
1044 spi->sync_period = ti->curr.period;
1045 spi->sync_offset = ti->curr.offset;
1046 spi->bus_width = ti->curr.width;
1047 if ((ti->flags & T_TAG) != 0) {
1048 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
1049 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
1050 } else {
1051 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
1052 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB;
1053 }
1054 } else {
1055 if ((ti->flags & T_SYNCHOFF) != 0) {
1056 spi->sync_period = 0;
1057 spi->sync_offset = 0;
1058 } else {
1059 spi->sync_period = sc->sc_minsync;
1060 spi->sync_offset = sc->sc_maxoffset;
1061 }
1062 spi->bus_width = sc->sc_maxwidth;
1063 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
1064 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
1065 }
1066 spi->valid =
1067 CTS_SPI_VALID_BUS_WIDTH |
1068 CTS_SPI_VALID_SYNC_RATE |
1069 CTS_SPI_VALID_SYNC_OFFSET |
1070 CTS_SPI_VALID_DISC;
1071 scsi->valid = CTS_SCSI_VALID_TQ;
1072 ccb->ccb_h.status = CAM_REQ_CMP;
|
1067 xpt_done(ccb);
1068 return;
| 1073 break;
|
1069
1070 case XPT_ABORT:
1071 device_printf(sc->sc_dev, "XPT_ABORT called\n");
1072 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
| 1074
1075 case XPT_ABORT:
1076 device_printf(sc->sc_dev, "XPT_ABORT called\n");
1077 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
|
1073 xpt_done(ccb);
1074 return;
| 1078 break;
|
1075
1076 case XPT_TERM_IO:
1077 device_printf(sc->sc_dev, "XPT_TERM_IO called\n");
1078 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
| 1079
1080 case XPT_TERM_IO:
1081 device_printf(sc->sc_dev, "XPT_TERM_IO called\n");
1082 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
|
1079 xpt_done(ccb);
1080 return;
| 1083 break;
|
1081
1082 case XPT_RESET_DEV:
1083 case XPT_SCSI_IO:
1084 if (ccb->ccb_h.target_id < 0 ||
1085 ccb->ccb_h.target_id >= sc->sc_ntarg) {
1086 ccb->ccb_h.status = CAM_PATH_INVALID;
| 1084
1085 case XPT_RESET_DEV:
1086 case XPT_SCSI_IO:
1087 if (ccb->ccb_h.target_id < 0 ||
1088 ccb->ccb_h.target_id >= sc->sc_ntarg) {
1089 ccb->ccb_h.status = CAM_PATH_INVALID;
|
1087 xpt_done(ccb);
1088 return;
| 1090 goto done;
|
1089 }
1090 /* Get an ECB to use. */
1091 ecb = ncr53c9x_get_ecb(sc);
1092 /*
1093 * This should never happen as we track resources
1094 * in the mid-layer.
1095 */
1096 if (ecb == NULL) {
1097 xpt_freeze_simq(sim, 1);
1098 ccb->ccb_h.status = CAM_REQUEUE_REQ;
1099 device_printf(sc->sc_dev, "unable to allocate ecb\n");
| 1091 }
1092 /* Get an ECB to use. */
1093 ecb = ncr53c9x_get_ecb(sc);
1094 /*
1095 * This should never happen as we track resources
1096 * in the mid-layer.
1097 */
1098 if (ecb == NULL) {
1099 xpt_freeze_simq(sim, 1);
1100 ccb->ccb_h.status = CAM_REQUEUE_REQ;
1101 device_printf(sc->sc_dev, "unable to allocate ecb\n");
|
1100 xpt_done(ccb);
1101 return;
| 1102 goto done;
|
1102 }
1103
1104 /* Initialize ecb. */
1105 ecb->ccb = ccb;
1106 ecb->timeout = ccb->ccb_h.timeout;
1107
1108 if (ccb->ccb_h.func_code == XPT_RESET_DEV) {
1109 ecb->flags |= ECB_RESET;
1110 ecb->clen = 0;
1111 ecb->dleft = 0;
1112 } else {
1113 csio = &ccb->csio;
1114 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
1115 bcopy(csio->cdb_io.cdb_ptr, &ecb->cmd.cmd,
1116 csio->cdb_len);
1117 else
1118 bcopy(csio->cdb_io.cdb_bytes, &ecb->cmd.cmd,
1119 csio->cdb_len);
1120 ecb->clen = csio->cdb_len;
1121 ecb->daddr = csio->data_ptr;
1122 ecb->dleft = csio->dxfer_len;
1123 }
1124 ecb->stat = 0;
1125
1126 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain);
1127 ecb->flags |= ECB_READY;
1128 if (sc->sc_state == NCR_IDLE)
1129 ncr53c9x_sched(sc);
| 1103 }
1104
1105 /* Initialize ecb. */
1106 ecb->ccb = ccb;
1107 ecb->timeout = ccb->ccb_h.timeout;
1108
1109 if (ccb->ccb_h.func_code == XPT_RESET_DEV) {
1110 ecb->flags |= ECB_RESET;
1111 ecb->clen = 0;
1112 ecb->dleft = 0;
1113 } else {
1114 csio = &ccb->csio;
1115 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
1116 bcopy(csio->cdb_io.cdb_ptr, &ecb->cmd.cmd,
1117 csio->cdb_len);
1118 else
1119 bcopy(csio->cdb_io.cdb_bytes, &ecb->cmd.cmd,
1120 csio->cdb_len);
1121 ecb->clen = csio->cdb_len;
1122 ecb->daddr = csio->data_ptr;
1123 ecb->dleft = csio->dxfer_len;
1124 }
1125 ecb->stat = 0;
1126
1127 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain);
1128 ecb->flags |= ECB_READY;
1129 if (sc->sc_state == NCR_IDLE)
1130 ncr53c9x_sched(sc);
|
1130 break;
| 1131 return;
|
1131
1132 case XPT_SET_TRAN_SETTINGS:
1133 cts = &ccb->cts;
1134 target = ccb->ccb_h.target_id;
1135 ti = &sc->sc_tinfo[target];
1136 scsi = &cts->proto_specific.scsi;
1137 spi = &cts->xport_specific.spi;
1138
1139 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
1140 if ((sc->sc_cfflags & (1<<((target & 7) + 16))) == 0 &&
1141 (scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)) {
1142 NCR_MISC(("%s: target %d: tagged queuing\n",
1143 device_get_nameunit(sc->sc_dev), target));
1144 ti->flags |= T_TAG;
1145 } else
1146 ti->flags &= ~T_TAG;
1147 }
1148
1149 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
1150 NCR_MISC(("%s: target %d: wide negotiation\n",
1151 device_get_nameunit(sc->sc_dev), target));
1152 ti->goal.width = spi->bus_width;
1153 }
1154
1155 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) {
1156 NCR_MISC(("%s: target %d: sync period negotiation\n",
1157 device_get_nameunit(sc->sc_dev), target));
1158 ti->goal.period = spi->sync_period;
1159 }
1160
1161 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) {
1162 NCR_MISC(("%s: target %d: sync offset negotiation\n",
1163 device_get_nameunit(sc->sc_dev), target));
1164 ti->goal.offset = spi->sync_offset;
1165 }
1166
1167 ccb->ccb_h.status = CAM_REQ_CMP;
| 1132
1133 case XPT_SET_TRAN_SETTINGS:
1134 cts = &ccb->cts;
1135 target = ccb->ccb_h.target_id;
1136 ti = &sc->sc_tinfo[target];
1137 scsi = &cts->proto_specific.scsi;
1138 spi = &cts->xport_specific.spi;
1139
1140 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
1141 if ((sc->sc_cfflags & (1<<((target & 7) + 16))) == 0 &&
1142 (scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)) {
1143 NCR_MISC(("%s: target %d: tagged queuing\n",
1144 device_get_nameunit(sc->sc_dev), target));
1145 ti->flags |= T_TAG;
1146 } else
1147 ti->flags &= ~T_TAG;
1148 }
1149
1150 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
1151 NCR_MISC(("%s: target %d: wide negotiation\n",
1152 device_get_nameunit(sc->sc_dev), target));
1153 ti->goal.width = spi->bus_width;
1154 }
1155
1156 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) {
1157 NCR_MISC(("%s: target %d: sync period negotiation\n",
1158 device_get_nameunit(sc->sc_dev), target));
1159 ti->goal.period = spi->sync_period;
1160 }
1161
1162 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) {
1163 NCR_MISC(("%s: target %d: sync offset negotiation\n",
1164 device_get_nameunit(sc->sc_dev), target));
1165 ti->goal.offset = spi->sync_offset;
1166 }
1167
1168 ccb->ccb_h.status = CAM_REQ_CMP;
|
1168 xpt_done(ccb);
1169 return;
| 1169 break;
|
1170
1171 default:
1172 device_printf(sc->sc_dev, "Unhandled function code %d\n",
1173 ccb->ccb_h.func_code);
1174 ccb->ccb_h.status = CAM_PROVIDE_FAIL;
| 1170
1171 default:
1172 device_printf(sc->sc_dev, "Unhandled function code %d\n",
1173 ccb->ccb_h.func_code);
1174 ccb->ccb_h.status = CAM_PROVIDE_FAIL;
|
1175 xpt_done(ccb);
1176 return;
| |
1177 }
| 1175 }
|
| 1176
1177done:
1178 xpt_done(ccb);
|
1178}
1179
1180/*
1181 * Used when interrupt driven I/O is not allowed, e.g. during boot.
1182 */
1183static void
1184ncr53c9x_poll(struct cam_sim *sim)
1185{
1186 struct ncr53c9x_softc *sc;
1187
1188 sc = cam_sim_softc(sim);
1189
1190 NCR_LOCK_ASSERT(sc, MA_OWNED);
1191
1192 NCR_TRACE(("[%s] ", __func__));
1193
1194 if (NCRDMA_ISINTR(sc))
1195 ncr53c9x_intr1(sc);
1196}
1197
1198/*
1199 * Asynchronous notification handler
1200 */
1201static void
1202ncr53c9x_async(void *cbarg, uint32_t code, struct cam_path *path, void *arg)
1203{
1204 struct ncr53c9x_softc *sc;
1205 struct ncr53c9x_tinfo *ti;
1206 int target;
1207
1208 sc = cam_sim_softc(cbarg);
1209
1210 NCR_LOCK_ASSERT(sc, MA_OWNED);
1211
1212 switch (code) {
1213 case AC_LOST_DEVICE:
1214 target = xpt_path_target_id(path);
1215 if (target < 0 || target >= sc->sc_ntarg)
1216 break;
1217
1218 /* Cancel outstanding disconnected commands. */
1219 ncr53c9x_clear_target(sc, target, CAM_REQ_ABORTED);
1220
1221 /* Set the default parameters for the target. */
1222 ti = &sc->sc_tinfo[target];
1223/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
1224 ti->flags = ((sc->sc_minsync != 0 &&
1225 (sc->sc_cfflags & (1 << ((target & 7) + 8))) == 0) ?
1226 0 : T_SYNCHOFF) |
1227 ((sc->sc_cfflags & (1 << (target & 7))) == 0 ?
1228 0 : T_RSELECTOFF);
1229 ti->curr.period = ti->goal.period = 0;
1230 ti->curr.offset = ti->goal.offset = 0;
1231 ti->curr.width = ti->goal.width = MSG_EXT_WDTR_BUS_8_BIT;
1232 break;
1233 }
1234}
1235
1236/*
1237 * LOW LEVEL SCSI UTILITIES
1238 */
1239
1240/*
1241 * Schedule a SCSI operation. This has now been pulled out of the interrupt
1242 * handler so that we may call it from ncr53c9x_action and ncr53c9x_done.
1243 * This may save us an unnecessary interrupt just to get things going.
1244 * Should only be called when state == NCR_IDLE and with sc_lock held.
1245 */
1246static void
1247ncr53c9x_sched(struct ncr53c9x_softc *sc)
1248{
1249 struct ncr53c9x_ecb *ecb;
1250 struct ncr53c9x_linfo *li;
1251 struct ncr53c9x_tinfo *ti;
1252 int lun, tag;
1253
1254 NCR_LOCK_ASSERT(sc, MA_OWNED);
1255
1256 NCR_TRACE(("[%s] ", __func__));
1257
1258 if (sc->sc_state != NCR_IDLE)
1259 panic("%s: not IDLE (state=%d)", __func__, sc->sc_state);
1260
1261 /*
1262 * Find first ecb in ready queue that is for a target/lunit
1263 * combinations that is not busy.
1264 */
1265 TAILQ_FOREACH(ecb, &sc->ready_list, chain) {
1266 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
1267 lun = ecb->ccb->ccb_h.target_lun;
1268
1269 /* Select type of tag for this command */
1270 if ((ti->flags & (T_RSELECTOFF | T_TAG)) != T_TAG)
1271 tag = 0;
1272 else if ((ecb->flags & ECB_SENSE) != 0)
1273 tag = 0;
1274 else if ((ecb->ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0)
1275 tag = 0;
1276 else if (ecb->ccb->csio.tag_action == CAM_TAG_ACTION_NONE)
1277 tag = 0;
1278 else
1279 tag = ecb->ccb->csio.tag_action;
1280
1281 li = TINFO_LUN(ti, lun);
1282 if (li == NULL) {
1283 /* Initialize LUN info and add to list. */
1284 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT | M_ZERO);
1285 if (li == NULL)
1286 continue;
1287 li->lun = lun;
1288
1289 LIST_INSERT_HEAD(&ti->luns, li, link);
1290 if (lun < NCR_NLUN)
1291 ti->lun[lun] = li;
1292 }
1293 li->last_used = time_second;
1294 if (tag == 0) {
1295 /* Try to issue this as an untagged command. */
1296 if (li->untagged == NULL)
1297 li->untagged = ecb;
1298 }
1299 if (li->untagged != NULL) {
1300 tag = 0;
1301 if ((li->busy != 1) && li->used == 0) {
1302 /*
1303 * We need to issue this untagged command
1304 * now.
1305 */
1306 ecb = li->untagged;
1307 } else {
1308 /* not ready, yet */
1309 continue;
1310 }
1311 }
1312 ecb->tag[0] = tag;
1313 if (tag != 0) {
1314 li->queued[ecb->tag_id] = ecb;
1315 ecb->tag[1] = ecb->tag_id;
1316 li->used++;
1317 }
1318 if (li->untagged != NULL && (li->busy != 1)) {
1319 li->busy = 1;
1320 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
1321 ecb->flags &= ~ECB_READY;
1322 sc->sc_nexus = ecb;
1323 ncr53c9x_select(sc, ecb);
1324 break;
1325 }
1326 if (li->untagged == NULL && tag != 0) {
1327 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
1328 ecb->flags &= ~ECB_READY;
1329 sc->sc_nexus = ecb;
1330 ncr53c9x_select(sc, ecb);
1331 break;
1332 } else {
1333 NCR_TRACE(("[%s %d:%d busy] \n", __func__,
1334 ecb->ccb->ccb_h.target_id,
1335 ecb->ccb->ccb_h.target_lun));
1336 }
1337 }
1338}
1339
1340static void
1341ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
1342{
1343 union ccb *ccb = ecb->ccb;
1344 struct ncr53c9x_linfo *li;
1345 struct ncr53c9x_tinfo *ti;
1346 struct scsi_request_sense *ss = (void *)&ecb->cmd.cmd;
1347 int lun;
1348
1349 NCR_LOCK_ASSERT(sc, MA_OWNED);
1350
1351 NCR_TRACE(("[%s] ", __func__));
1352
1353 lun = ccb->ccb_h.target_lun;
1354 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
1355
1356 /* Next, setup a REQUEST SENSE command block. */
1357 memset(ss, 0, sizeof(*ss));
1358 ss->opcode = REQUEST_SENSE;
1359 ss->byte2 = ccb->ccb_h.target_lun << SCSI_CMD_LUN_SHIFT;
1360 ss->length = sizeof(struct scsi_sense_data);
1361 ecb->clen = sizeof(*ss);
1362 memset(&ccb->csio.sense_data, 0, sizeof(ccb->csio.sense_data));
1363 ecb->daddr = (uint8_t *)&ccb->csio.sense_data;
1364 ecb->dleft = sizeof(struct scsi_sense_data);
1365 ecb->flags |= ECB_SENSE;
1366 ecb->timeout = NCR_SENSE_TIMEOUT;
1367 ti->senses++;
1368 li = TINFO_LUN(ti, lun);
1369 if (li->busy)
1370 li->busy = 0;
1371 ncr53c9x_dequeue(sc, ecb);
1372 li->untagged = ecb; /* Must be executed first to fix C/A. */
1373 li->busy = 2;
1374 if (ecb == sc->sc_nexus)
1375 ncr53c9x_select(sc, ecb);
1376 else {
1377 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
1378 ecb->flags |= ECB_READY;
1379 if (sc->sc_state == NCR_IDLE)
1380 ncr53c9x_sched(sc);
1381 }
1382}
1383
1384/*
1385 * POST PROCESSING OF SCSI_CMD (usually current)
1386 */
1387static void
1388ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
1389{
1390 union ccb *ccb = ecb->ccb;
1391 struct ncr53c9x_linfo *li;
1392 struct ncr53c9x_tinfo *ti;
1393 int lun, sense_returned;
1394
1395 NCR_LOCK_ASSERT(sc, MA_OWNED);
1396
1397 NCR_TRACE(("[%s(status:%x)] ", __func__, ccb->ccb_h.status));
1398
1399 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
1400 lun = ccb->ccb_h.target_lun;
1401 li = TINFO_LUN(ti, lun);
1402
1403 callout_stop(&ecb->ch);
1404
1405 /*
1406 * Now, if we've come here with no error code, i.e. we've kept the
1407 * initial CAM_REQ_CMP, and the status code signals that we should
1408 * check sense, we'll need to set up a request sense cmd block and
1409 * push the command back into the ready queue *before* any other
1410 * commands for this target/lunit, else we lose the sense info.
1411 * We don't support chk sense conditions for the request sense cmd.
1412 */
1413 if (ccb->ccb_h.status == CAM_REQ_CMP) {
1414 ccb->csio.scsi_status = ecb->stat;
1415 if ((ecb->flags & ECB_ABORT) != 0) {
1416 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1417 } else if ((ecb->flags & ECB_SENSE) != 0 &&
1418 (ecb->stat != SCSI_STATUS_CHECK_COND)) {
1419 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1420 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR |
1421 CAM_AUTOSNS_VALID;
1422 sense_returned = sizeof(ccb->csio.sense_data) -
1423 ecb->dleft;
1424 if (sense_returned < ccb->csio.sense_len)
1425 ccb->csio.sense_resid = ccb->csio.sense_len -
1426 sense_returned;
1427 else
1428 ccb->csio.sense_resid = 0;
1429 } else if (ecb->stat == SCSI_STATUS_CHECK_COND) {
1430 if ((ecb->flags & ECB_SENSE) != 0)
1431 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1432 else {
1433 /* First, save the return values. */
1434 ccb->csio.resid = ecb->dleft;
1435 if ((ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) ==
1436 0) {
1437 ncr53c9x_sense(sc, ecb);
1438 return;
1439 }
1440 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1441 }
1442 } else {
1443 ccb->csio.resid = ecb->dleft;
1444 }
1445 if (ecb->stat == SCSI_STATUS_QUEUE_FULL)
1446 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1447 else if (ecb->stat == SCSI_STATUS_BUSY)
1448 ccb->ccb_h.status = CAM_SCSI_BUSY;
1449 }
1450
1451#ifdef NCR53C9X_DEBUG
1452 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) {
1453 if (ccb->csio.resid != 0)
1454 printf("resid=%d ", ccb->csio.resid);
1455 if ((ccb->ccb_h.status & CAM_AUTOSNS_VALID) != 0)
1456 printf("sense=0x%02x\n",
1457 ccb->csio.sense_data.error_code);
1458 else
1459 printf("status SCSI=0x%x CAM=0x%x\n",
1460 ccb->csio.scsi_status, ccb->ccb_h.status);
1461 }
1462#endif
1463
1464 /*
1465 * Remove the ECB from whatever queue it's on.
1466 */
1467 ncr53c9x_dequeue(sc, ecb);
1468 if (ecb == sc->sc_nexus) {
1469 sc->sc_nexus = NULL;
1470 if (sc->sc_state != NCR_CLEANING) {
1471 sc->sc_state = NCR_IDLE;
1472 ncr53c9x_sched(sc);
1473 }
1474 }
1475
1476 if (ccb->ccb_h.status == CAM_SEL_TIMEOUT) {
1477 /* Selection timeout -- discard this LUN if empty. */
1478 if (li->untagged == NULL && li->used == 0) {
1479 if (lun < NCR_NLUN)
1480 ti->lun[lun] = NULL;
1481 LIST_REMOVE(li, link);
1482 free(li, M_DEVBUF);
1483 }
1484 }
1485
1486 ncr53c9x_free_ecb(sc, ecb);
1487 ti->cmds++;
1488 xpt_done(ccb);
1489}
1490
1491static void
1492ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
1493{
1494 struct ncr53c9x_linfo *li;
1495 struct ncr53c9x_tinfo *ti;
1496 int64_t lun;
1497
1498 NCR_LOCK_ASSERT(sc, MA_OWNED);
1499
1500 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
1501 lun = ecb->ccb->ccb_h.target_lun;
1502 li = TINFO_LUN(ti, lun);
1503#ifdef DIAGNOSTIC
1504 if (li == NULL || li->lun != lun)
1505 panic("%s: lun %qx for ecb %p does not exist", __func__,
1506 (long long)lun, ecb);
1507#endif
1508 if (li->untagged == ecb) {
1509 li->busy = 0;
1510 li->untagged = NULL;
1511 }
1512 if (ecb->tag[0] && li->queued[ecb->tag[1]] != NULL) {
1513#ifdef DIAGNOSTIC
1514 if (li->queued[ecb->tag[1]] != NULL &&
1515 (li->queued[ecb->tag[1]] != ecb))
1516 panic("%s: slot %d for lun %qx has %p instead of ecb "
1517 "%p", __func__, ecb->tag[1], (long long)lun,
1518 li->queued[ecb->tag[1]], ecb);
1519#endif
1520 li->queued[ecb->tag[1]] = NULL;
1521 li->used--;
1522 }
1523 ecb->tag[0] = ecb->tag[1] = 0;
1524
1525 if ((ecb->flags & ECB_READY) != 0) {
1526 ecb->flags &= ~ECB_READY;
1527 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
1528 }
1529}
1530
1531/*
1532 * INTERRUPT/PROTOCOL ENGINE
1533 */
1534
1535/*
1536 * Schedule an outgoing message by prioritizing it, and asserting
1537 * attention on the bus. We can only do this when we are the initiator
1538 * else there will be an illegal command interrupt.
1539 */
1540#define ncr53c9x_sched_msgout(m) do { \
1541 NCR_MSGS(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \
1542 NCRCMD(sc, NCRCMD_SETATN); \
1543 sc->sc_flags |= NCR_ATN; \
1544 sc->sc_msgpriq |= (m); \
1545} while (/* CONSTCOND */0)
1546
1547static void
1548ncr53c9x_flushfifo(struct ncr53c9x_softc *sc)
1549{
1550
1551 NCR_LOCK_ASSERT(sc, MA_OWNED);
1552
1553 NCR_TRACE(("[%s] ", __func__));
1554
1555 NCRCMD(sc, NCRCMD_FLUSH);
1556
1557 if (sc->sc_phase == COMMAND_PHASE ||
1558 sc->sc_phase == MESSAGE_OUT_PHASE)
1559 DELAY(2);
1560}
1561
1562static int
1563ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
1564{
1565 int i, n;
1566 uint8_t *ibuf;
1567
1568 NCR_LOCK_ASSERT(sc, MA_OWNED);
1569
1570 switch (how) {
1571 case NCR_RDFIFO_START:
1572 ibuf = sc->sc_imess;
1573 sc->sc_imlen = 0;
1574 break;
1575
1576 case NCR_RDFIFO_CONTINUE:
1577 ibuf = sc->sc_imess + sc->sc_imlen;
1578 break;
1579
1580 default:
1581 panic("%s: bad flag", __func__);
1582 /* NOTREACHED */
1583 }
1584
1585 /*
1586 * XXX buffer (sc_imess) size for message
1587 */
1588
1589 n = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
1590
1591 if (sc->sc_rev == NCR_VARIANT_FAS366) {
1592 n *= 2;
1593
1594 for (i = 0; i < n; i++)
1595 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO);
1596
1597 if (sc->sc_espstat2 & NCRFAS_STAT2_ISHUTTLE) {
1598
1599 NCR_WRITE_REG(sc, NCR_FIFO, 0);
1600 ibuf[i++] = NCR_READ_REG(sc, NCR_FIFO);
1601
1602 NCR_READ_REG(sc, NCR_FIFO);
1603
1604 ncr53c9x_flushfifo(sc);
1605 }
1606 } else
1607 for (i = 0; i < n; i++)
1608 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO);
1609
1610 sc->sc_imlen += i;
1611
1612#if 0
1613#ifdef NCR53C9X_DEBUG
1614 NCR_TRACE(("\n[rdfifo %s (%d):",
1615 (how == NCR_RDFIFO_START) ? "start" : "cont", (int)sc->sc_imlen));
1616 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) {
1617 for (i = 0; i < sc->sc_imlen; i++)
1618 printf(" %02x", sc->sc_imess[i]);
1619 printf("]\n");
1620 }
1621#endif
1622#endif
1623 return (sc->sc_imlen);
1624}
1625
1626static void
1627ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, uint8_t *p, int len)
1628{
1629 int i;
1630
1631 NCR_LOCK_ASSERT(sc, MA_OWNED);
1632
1633#ifdef NCR53C9X_DEBUG
1634 NCR_MSGS(("[wrfifo(%d):", len));
1635 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) {
1636 for (i = 0; i < len; i++)
1637 printf(" %02x", p[i]);
1638 printf("]\n");
1639 }
1640#endif
1641
1642 for (i = 0; i < len; i++) {
1643 NCR_WRITE_REG(sc, NCR_FIFO, p[i]);
1644
1645 if (sc->sc_rev == NCR_VARIANT_FAS366)
1646 NCR_WRITE_REG(sc, NCR_FIFO, 0);
1647 }
1648}
1649
1650static int
1651ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype,
1652 int tagid)
1653{
1654 struct ncr53c9x_ecb *ecb = NULL;
1655 struct ncr53c9x_linfo *li;
1656 struct ncr53c9x_tinfo *ti;
1657 uint8_t lun, selid, target;
1658
1659 NCR_LOCK_ASSERT(sc, MA_OWNED);
1660
1661 if (sc->sc_rev == NCR_VARIANT_FAS366)
1662 target = sc->sc_selid;
1663 else {
1664 /*
1665 * The SCSI chip made a snapshot of the data bus
1666 * while the reselection was being negotiated.
1667 * This enables us to determine which target did
1668 * the reselect.
1669 */
1670 selid = sc->sc_selid & ~(1 << sc->sc_id);
1671 if (selid & (selid - 1)) {
1672 device_printf(sc->sc_dev, "reselect with invalid "
1673 "selid %02x; sending DEVICE RESET\n", selid);
1674 goto reset;
1675 }
1676
1677 target = ffs(selid) - 1;
1678 }
1679 lun = message & 0x07;
1680
1681 /*
1682 * Search wait queue for disconnected command.
1683 * The list should be short, so I haven't bothered with
1684 * any more sophisticated structures than a simple
1685 * singly linked list.
1686 */
1687 ti = &sc->sc_tinfo[target];
1688 li = TINFO_LUN(ti, lun);
1689
1690 /*
1691 * We can get as far as the LUN with the IDENTIFY
1692 * message. Check to see if we're running an
1693 * untagged command. Otherwise ack the IDENTIFY
1694 * and wait for a tag message.
1695 */
1696 if (li != NULL) {
1697 if (li->untagged != NULL && li->busy)
1698 ecb = li->untagged;
1699 else if (tagtype != MSG_SIMPLE_Q_TAG) {
1700 /* Wait for tag to come by. */
1701 sc->sc_state = NCR_IDENTIFIED;
1702 return (0);
1703 } else if (tagtype)
1704 ecb = li->queued[tagid];
1705 }
1706 if (ecb == NULL) {
1707 device_printf(sc->sc_dev, "reselect from target %d lun %d "
1708 "tag %x:%x with no nexus; sending ABORT\n",
1709 target, lun, tagtype, tagid);
1710 goto abort;
1711 }
1712
1713 /* Make this nexus active again. */
1714 sc->sc_state = NCR_CONNECTED;
1715 sc->sc_nexus = ecb;
1716 ncr53c9x_setsync(sc, ti);
1717
1718 if (ecb->flags & ECB_RESET)
1719 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1720 else if (ecb->flags & ECB_ABORT)
1721 ncr53c9x_sched_msgout(SEND_ABORT);
1722
1723 /* Do an implicit RESTORE POINTERS. */
1724 sc->sc_dp = ecb->daddr;
1725 sc->sc_dleft = ecb->dleft;
1726
1727 return (0);
1728
1729reset:
1730 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1731 return (1);
1732
1733abort:
1734 ncr53c9x_sched_msgout(SEND_ABORT);
1735 return (1);
1736}
1737
1738/* From NetBSD; these should go into CAM at some point. */
1739#define MSG_ISEXTENDED(m) ((m) == MSG_EXTENDED)
1740#define MSG_IS1BYTE(m) \
1741 ((!MSG_ISEXTENDED(m) && (m) < 0x20) || MSG_ISIDENTIFY(m))
1742#define MSG_IS2BYTE(m) (((m) & 0xf0) == 0x20)
1743
1744static inline int
1745__verify_msg_format(uint8_t *p, int len)
1746{
1747
1748 if (len == 1 && MSG_IS1BYTE(p[0]))
1749 return (1);
1750 if (len == 2 && MSG_IS2BYTE(p[0]))
1751 return (1);
1752 if (len >= 3 && MSG_ISEXTENDED(p[0]) &&
1753 len == p[1] + 2)
1754 return (1);
1755
1756 return (0);
1757}
1758
1759/*
1760 * Get an incoming message as initiator.
1761 *
1762 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a
1763 * byte in the FIFO.
1764 */
1765static void
1766ncr53c9x_msgin(struct ncr53c9x_softc *sc)
1767{
1768 struct ncr53c9x_ecb *ecb;
1769 struct ncr53c9x_linfo *li;
1770 struct ncr53c9x_tinfo *ti;
1771 uint8_t *pb;
1772 int lun, plen;
1773
1774 NCR_LOCK_ASSERT(sc, MA_OWNED);
1775
1776 NCR_TRACE(("[%s(curmsglen:%ld)] ", __func__, (long)sc->sc_imlen));
1777
1778 if (sc->sc_imlen == 0) {
1779 device_printf(sc->sc_dev, "msgin: no msg byte available\n");
1780 return;
1781 }
1782
1783 /*
1784 * Prepare for a new message. A message should (according
1785 * to the SCSI standard) be transmitted in one single
1786 * MESSAGE_IN_PHASE. If we have been in some other phase,
1787 * then this is a new message.
1788 */
1789 if (sc->sc_prevphase != MESSAGE_IN_PHASE &&
1790 sc->sc_state != NCR_RESELECTED) {
1791 device_printf(sc->sc_dev, "phase change, dropping message, "
1792 "prev %d, state %d\n", sc->sc_prevphase, sc->sc_state);
1793 sc->sc_flags &= ~NCR_DROP_MSGI;
1794 sc->sc_imlen = 0;
1795 }
1796
1797 /*
1798 * If we're going to reject the message, don't bother storing
1799 * the incoming bytes. But still, we need to ACK them.
1800 */
1801 if ((sc->sc_flags & NCR_DROP_MSGI) != 0) {
1802 NCRCMD(sc, NCRCMD_MSGOK);
1803 device_printf(sc->sc_dev, "<dropping msg byte %x>",
1804 sc->sc_imess[sc->sc_imlen]);
1805 return;
1806 }
1807
1808 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) {
1809 ncr53c9x_sched_msgout(SEND_REJECT);
1810 sc->sc_flags |= NCR_DROP_MSGI;
1811 } else {
1812 switch (sc->sc_state) {
1813 /*
1814 * if received message is the first of reselection
1815 * then first byte is selid, and then message
1816 */
1817 case NCR_RESELECTED:
1818 pb = sc->sc_imess + 1;
1819 plen = sc->sc_imlen - 1;
1820 break;
1821
1822 default:
1823 pb = sc->sc_imess;
1824 plen = sc->sc_imlen;
1825 }
1826
1827 if (__verify_msg_format(pb, plen))
1828 goto gotit;
1829 }
1830
1831 /* Acknowledge what we have so far. */
1832 NCRCMD(sc, NCRCMD_MSGOK);
1833 return;
1834
1835gotit:
1836 NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state));
1837 /*
1838 * We got a complete message, flush the imess.
1839 * XXX nobody uses imlen below.
1840 */
1841 sc->sc_imlen = 0;
1842 /*
1843 * Now we should have a complete message (1 byte, 2 byte
1844 * and moderately long extended messages). We only handle
1845 * extended messages which total length is shorter than
1846 * NCR_MAX_MSG_LEN. Longer messages will be amputated.
1847 */
1848 switch (sc->sc_state) {
1849 case NCR_CONNECTED:
1850 ecb = sc->sc_nexus;
1851 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
1852
1853 switch (sc->sc_imess[0]) {
1854 case MSG_CMDCOMPLETE:
1855 NCR_MSGS(("cmdcomplete "));
1856 if (sc->sc_dleft < 0) {
1857 xpt_print_path(ecb->ccb->ccb_h.path);
1858 printf("got %ld extra bytes\n",
1859 -(long)sc->sc_dleft);
1860 sc->sc_dleft = 0;
1861 }
1862 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) ?
1863 0 : sc->sc_dleft;
1864 if ((ecb->flags & ECB_SENSE) == 0)
1865 ecb->ccb->csio.resid = ecb->dleft;
1866 sc->sc_state = NCR_CMDCOMPLETE;
1867 break;
1868
1869 case MSG_MESSAGE_REJECT:
1870 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout));
1871 switch (sc->sc_msgout) {
1872 case SEND_TAG:
1873 /*
1874 * Target does not like tagged queuing.
1875 * - Flush the command queue
1876 * - Disable tagged queuing for the target
1877 * - Dequeue ecb from the queued array.
1878 */
1879 device_printf(sc->sc_dev, "tagged queuing "
1880 "rejected: target %d\n",
1881 ecb->ccb->ccb_h.target_id);
1882
1883 NCR_MSGS(("(rejected sent tag)"));
1884 NCRCMD(sc, NCRCMD_FLUSH);
1885 DELAY(1);
1886 ti->flags &= ~T_TAG;
1887 lun = ecb->ccb->ccb_h.target_lun;
1888 li = TINFO_LUN(ti, lun);
1889 if (ecb->tag[0] &&
1890 li->queued[ecb->tag[1]] != NULL) {
1891 li->queued[ecb->tag[1]] = NULL;
1892 li->used--;
1893 }
1894 ecb->tag[0] = ecb->tag[1] = 0;
1895 li->untagged = ecb;
1896 li->busy = 1;
1897 break;
1898
1899 case SEND_SDTR:
1900 device_printf(sc->sc_dev, "sync transfer "
1901 "rejected: target %d\n",
1902 ecb->ccb->ccb_h.target_id);
1903
1904 ti->flags &= ~T_SDTRSENT;
1905 ti->curr.period = ti->goal.period = 0;
1906 ti->curr.offset = ti->goal.offset = 0;
1907 ncr53c9x_setsync(sc, ti);
1908 break;
1909
1910 case SEND_WDTR:
1911 device_printf(sc->sc_dev, "wide transfer "
1912 "rejected: target %d\n",
1913 ecb->ccb->ccb_h.target_id);
1914
1915 ti->flags &= ~T_WDTRSENT;
1916 ti->curr.width = ti->goal.width =
1917 MSG_EXT_WDTR_BUS_8_BIT;
1918 ncr53c9x_setsync(sc, ti);
1919 break;
1920
1921 case SEND_INIT_DET_ERR:
1922 goto abort;
1923 }
1924 break;
1925
1926 case MSG_NOOP:
1927 NCR_MSGS(("noop "));
1928 break;
1929
1930 case MSG_HEAD_OF_Q_TAG:
1931 case MSG_SIMPLE_Q_TAG:
1932 case MSG_ORDERED_Q_TAG:
1933 NCR_MSGS(("TAG %x:%x",
1934 sc->sc_imess[0], sc->sc_imess[1]));
1935 break;
1936
1937 case MSG_DISCONNECT:
1938 NCR_MSGS(("disconnect "));
1939 ti->dconns++;
1940 sc->sc_state = NCR_DISCONNECT;
1941
1942 /*
1943 * Mark the fact that all bytes have moved. The
1944 * target may not bother to do a SAVE POINTERS
1945 * at this stage. This flag will set the residual
1946 * count to zero on MSG COMPLETE.
1947 */
1948 if (sc->sc_dleft == 0)
1949 ecb->flags |= ECB_TENTATIVE_DONE;
1950 break;
1951
1952 case MSG_SAVEDATAPOINTER:
1953 NCR_MSGS(("save datapointer "));
1954 ecb->daddr = sc->sc_dp;
1955 ecb->dleft = sc->sc_dleft;
1956 break;
1957
1958 case MSG_RESTOREPOINTERS:
1959 NCR_MSGS(("restore datapointer "));
1960 sc->sc_dp = ecb->daddr;
1961 sc->sc_dleft = ecb->dleft;
1962 break;
1963
1964 case MSG_EXTENDED:
1965 NCR_MSGS(("extended(%x) ", sc->sc_imess[2]));
1966 switch (sc->sc_imess[2]) {
1967 case MSG_EXT_SDTR:
1968 NCR_MSGS(("SDTR period %d, offset %d ",
1969 sc->sc_imess[3], sc->sc_imess[4]));
1970 if (sc->sc_imess[1] != 3)
1971 goto reject;
1972 ti->curr.period = sc->sc_imess[3];
1973 ti->curr.offset = sc->sc_imess[4];
1974 if (sc->sc_minsync == 0 ||
1975 ti->curr.offset == 0 ||
1976 ti->curr.period > 124) {
1977#if 0
1978#ifdef NCR53C9X_DEBUG
1979 xpt_print_path(ecb->ccb->ccb_h.path);
1980 printf("async mode\n");
1981#endif
1982#endif
1983 if ((ti->flags & T_SDTRSENT) == 0) {
1984 /*
1985 * target initiated negotiation
1986 */
1987 ti->curr.offset = 0;
1988 ncr53c9x_sched_msgout(
1989 SEND_SDTR);
1990 }
1991 } else {
1992 ti->curr.period =
1993 ncr53c9x_cpb2stp(sc,
1994 ncr53c9x_stp2cpb(sc,
1995 ti->curr.period));
1996 if ((ti->flags & T_SDTRSENT) == 0) {
1997 /*
1998 * target initiated negotiation
1999 */
2000 if (ti->curr.period <
2001 sc->sc_minsync)
2002 ti->curr.period =
2003 sc->sc_minsync;
2004 if (ti->curr.offset >
2005 sc->sc_maxoffset)
2006 ti->curr.offset =
2007 sc->sc_maxoffset;
2008 ncr53c9x_sched_msgout(
2009 SEND_SDTR);
2010 }
2011 }
2012 ti->flags &= ~T_SDTRSENT;
2013 ti->goal.period = ti->curr.period;
2014 ti->goal.offset = ti->curr.offset;
2015 ncr53c9x_setsync(sc, ti);
2016 break;
2017
2018 case MSG_EXT_WDTR:
2019 NCR_MSGS(("wide mode %d ", sc->sc_imess[3]));
2020 ti->curr.width = sc->sc_imess[3];
2021 if (!(ti->flags & T_WDTRSENT))
2022 /*
2023 * target initiated negotiation
2024 */
2025 ncr53c9x_sched_msgout(SEND_WDTR);
2026 ti->flags &= ~T_WDTRSENT;
2027 ti->goal.width = ti->curr.width;
2028 ncr53c9x_setsync(sc, ti);
2029 break;
2030
2031 default:
2032 xpt_print_path(ecb->ccb->ccb_h.path);
| 1179}
1180
1181/*
1182 * Used when interrupt driven I/O is not allowed, e.g. during boot.
1183 */
1184static void
1185ncr53c9x_poll(struct cam_sim *sim)
1186{
1187 struct ncr53c9x_softc *sc;
1188
1189 sc = cam_sim_softc(sim);
1190
1191 NCR_LOCK_ASSERT(sc, MA_OWNED);
1192
1193 NCR_TRACE(("[%s] ", __func__));
1194
1195 if (NCRDMA_ISINTR(sc))
1196 ncr53c9x_intr1(sc);
1197}
1198
1199/*
1200 * Asynchronous notification handler
1201 */
1202static void
1203ncr53c9x_async(void *cbarg, uint32_t code, struct cam_path *path, void *arg)
1204{
1205 struct ncr53c9x_softc *sc;
1206 struct ncr53c9x_tinfo *ti;
1207 int target;
1208
1209 sc = cam_sim_softc(cbarg);
1210
1211 NCR_LOCK_ASSERT(sc, MA_OWNED);
1212
1213 switch (code) {
1214 case AC_LOST_DEVICE:
1215 target = xpt_path_target_id(path);
1216 if (target < 0 || target >= sc->sc_ntarg)
1217 break;
1218
1219 /* Cancel outstanding disconnected commands. */
1220 ncr53c9x_clear_target(sc, target, CAM_REQ_ABORTED);
1221
1222 /* Set the default parameters for the target. */
1223 ti = &sc->sc_tinfo[target];
1224/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
1225 ti->flags = ((sc->sc_minsync != 0 &&
1226 (sc->sc_cfflags & (1 << ((target & 7) + 8))) == 0) ?
1227 0 : T_SYNCHOFF) |
1228 ((sc->sc_cfflags & (1 << (target & 7))) == 0 ?
1229 0 : T_RSELECTOFF);
1230 ti->curr.period = ti->goal.period = 0;
1231 ti->curr.offset = ti->goal.offset = 0;
1232 ti->curr.width = ti->goal.width = MSG_EXT_WDTR_BUS_8_BIT;
1233 break;
1234 }
1235}
1236
1237/*
1238 * LOW LEVEL SCSI UTILITIES
1239 */
1240
1241/*
1242 * Schedule a SCSI operation. This has now been pulled out of the interrupt
1243 * handler so that we may call it from ncr53c9x_action and ncr53c9x_done.
1244 * This may save us an unnecessary interrupt just to get things going.
1245 * Should only be called when state == NCR_IDLE and with sc_lock held.
1246 */
1247static void
1248ncr53c9x_sched(struct ncr53c9x_softc *sc)
1249{
1250 struct ncr53c9x_ecb *ecb;
1251 struct ncr53c9x_linfo *li;
1252 struct ncr53c9x_tinfo *ti;
1253 int lun, tag;
1254
1255 NCR_LOCK_ASSERT(sc, MA_OWNED);
1256
1257 NCR_TRACE(("[%s] ", __func__));
1258
1259 if (sc->sc_state != NCR_IDLE)
1260 panic("%s: not IDLE (state=%d)", __func__, sc->sc_state);
1261
1262 /*
1263 * Find first ecb in ready queue that is for a target/lunit
1264 * combinations that is not busy.
1265 */
1266 TAILQ_FOREACH(ecb, &sc->ready_list, chain) {
1267 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
1268 lun = ecb->ccb->ccb_h.target_lun;
1269
1270 /* Select type of tag for this command */
1271 if ((ti->flags & (T_RSELECTOFF | T_TAG)) != T_TAG)
1272 tag = 0;
1273 else if ((ecb->flags & ECB_SENSE) != 0)
1274 tag = 0;
1275 else if ((ecb->ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0)
1276 tag = 0;
1277 else if (ecb->ccb->csio.tag_action == CAM_TAG_ACTION_NONE)
1278 tag = 0;
1279 else
1280 tag = ecb->ccb->csio.tag_action;
1281
1282 li = TINFO_LUN(ti, lun);
1283 if (li == NULL) {
1284 /* Initialize LUN info and add to list. */
1285 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT | M_ZERO);
1286 if (li == NULL)
1287 continue;
1288 li->lun = lun;
1289
1290 LIST_INSERT_HEAD(&ti->luns, li, link);
1291 if (lun < NCR_NLUN)
1292 ti->lun[lun] = li;
1293 }
1294 li->last_used = time_second;
1295 if (tag == 0) {
1296 /* Try to issue this as an untagged command. */
1297 if (li->untagged == NULL)
1298 li->untagged = ecb;
1299 }
1300 if (li->untagged != NULL) {
1301 tag = 0;
1302 if ((li->busy != 1) && li->used == 0) {
1303 /*
1304 * We need to issue this untagged command
1305 * now.
1306 */
1307 ecb = li->untagged;
1308 } else {
1309 /* not ready, yet */
1310 continue;
1311 }
1312 }
1313 ecb->tag[0] = tag;
1314 if (tag != 0) {
1315 li->queued[ecb->tag_id] = ecb;
1316 ecb->tag[1] = ecb->tag_id;
1317 li->used++;
1318 }
1319 if (li->untagged != NULL && (li->busy != 1)) {
1320 li->busy = 1;
1321 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
1322 ecb->flags &= ~ECB_READY;
1323 sc->sc_nexus = ecb;
1324 ncr53c9x_select(sc, ecb);
1325 break;
1326 }
1327 if (li->untagged == NULL && tag != 0) {
1328 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
1329 ecb->flags &= ~ECB_READY;
1330 sc->sc_nexus = ecb;
1331 ncr53c9x_select(sc, ecb);
1332 break;
1333 } else {
1334 NCR_TRACE(("[%s %d:%d busy] \n", __func__,
1335 ecb->ccb->ccb_h.target_id,
1336 ecb->ccb->ccb_h.target_lun));
1337 }
1338 }
1339}
1340
1341static void
1342ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
1343{
1344 union ccb *ccb = ecb->ccb;
1345 struct ncr53c9x_linfo *li;
1346 struct ncr53c9x_tinfo *ti;
1347 struct scsi_request_sense *ss = (void *)&ecb->cmd.cmd;
1348 int lun;
1349
1350 NCR_LOCK_ASSERT(sc, MA_OWNED);
1351
1352 NCR_TRACE(("[%s] ", __func__));
1353
1354 lun = ccb->ccb_h.target_lun;
1355 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
1356
1357 /* Next, setup a REQUEST SENSE command block. */
1358 memset(ss, 0, sizeof(*ss));
1359 ss->opcode = REQUEST_SENSE;
1360 ss->byte2 = ccb->ccb_h.target_lun << SCSI_CMD_LUN_SHIFT;
1361 ss->length = sizeof(struct scsi_sense_data);
1362 ecb->clen = sizeof(*ss);
1363 memset(&ccb->csio.sense_data, 0, sizeof(ccb->csio.sense_data));
1364 ecb->daddr = (uint8_t *)&ccb->csio.sense_data;
1365 ecb->dleft = sizeof(struct scsi_sense_data);
1366 ecb->flags |= ECB_SENSE;
1367 ecb->timeout = NCR_SENSE_TIMEOUT;
1368 ti->senses++;
1369 li = TINFO_LUN(ti, lun);
1370 if (li->busy)
1371 li->busy = 0;
1372 ncr53c9x_dequeue(sc, ecb);
1373 li->untagged = ecb; /* Must be executed first to fix C/A. */
1374 li->busy = 2;
1375 if (ecb == sc->sc_nexus)
1376 ncr53c9x_select(sc, ecb);
1377 else {
1378 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
1379 ecb->flags |= ECB_READY;
1380 if (sc->sc_state == NCR_IDLE)
1381 ncr53c9x_sched(sc);
1382 }
1383}
1384
1385/*
1386 * POST PROCESSING OF SCSI_CMD (usually current)
1387 */
1388static void
1389ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
1390{
1391 union ccb *ccb = ecb->ccb;
1392 struct ncr53c9x_linfo *li;
1393 struct ncr53c9x_tinfo *ti;
1394 int lun, sense_returned;
1395
1396 NCR_LOCK_ASSERT(sc, MA_OWNED);
1397
1398 NCR_TRACE(("[%s(status:%x)] ", __func__, ccb->ccb_h.status));
1399
1400 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
1401 lun = ccb->ccb_h.target_lun;
1402 li = TINFO_LUN(ti, lun);
1403
1404 callout_stop(&ecb->ch);
1405
1406 /*
1407 * Now, if we've come here with no error code, i.e. we've kept the
1408 * initial CAM_REQ_CMP, and the status code signals that we should
1409 * check sense, we'll need to set up a request sense cmd block and
1410 * push the command back into the ready queue *before* any other
1411 * commands for this target/lunit, else we lose the sense info.
1412 * We don't support chk sense conditions for the request sense cmd.
1413 */
1414 if (ccb->ccb_h.status == CAM_REQ_CMP) {
1415 ccb->csio.scsi_status = ecb->stat;
1416 if ((ecb->flags & ECB_ABORT) != 0) {
1417 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1418 } else if ((ecb->flags & ECB_SENSE) != 0 &&
1419 (ecb->stat != SCSI_STATUS_CHECK_COND)) {
1420 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1421 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR |
1422 CAM_AUTOSNS_VALID;
1423 sense_returned = sizeof(ccb->csio.sense_data) -
1424 ecb->dleft;
1425 if (sense_returned < ccb->csio.sense_len)
1426 ccb->csio.sense_resid = ccb->csio.sense_len -
1427 sense_returned;
1428 else
1429 ccb->csio.sense_resid = 0;
1430 } else if (ecb->stat == SCSI_STATUS_CHECK_COND) {
1431 if ((ecb->flags & ECB_SENSE) != 0)
1432 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1433 else {
1434 /* First, save the return values. */
1435 ccb->csio.resid = ecb->dleft;
1436 if ((ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) ==
1437 0) {
1438 ncr53c9x_sense(sc, ecb);
1439 return;
1440 }
1441 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1442 }
1443 } else {
1444 ccb->csio.resid = ecb->dleft;
1445 }
1446 if (ecb->stat == SCSI_STATUS_QUEUE_FULL)
1447 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1448 else if (ecb->stat == SCSI_STATUS_BUSY)
1449 ccb->ccb_h.status = CAM_SCSI_BUSY;
1450 }
1451
1452#ifdef NCR53C9X_DEBUG
1453 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) {
1454 if (ccb->csio.resid != 0)
1455 printf("resid=%d ", ccb->csio.resid);
1456 if ((ccb->ccb_h.status & CAM_AUTOSNS_VALID) != 0)
1457 printf("sense=0x%02x\n",
1458 ccb->csio.sense_data.error_code);
1459 else
1460 printf("status SCSI=0x%x CAM=0x%x\n",
1461 ccb->csio.scsi_status, ccb->ccb_h.status);
1462 }
1463#endif
1464
1465 /*
1466 * Remove the ECB from whatever queue it's on.
1467 */
1468 ncr53c9x_dequeue(sc, ecb);
1469 if (ecb == sc->sc_nexus) {
1470 sc->sc_nexus = NULL;
1471 if (sc->sc_state != NCR_CLEANING) {
1472 sc->sc_state = NCR_IDLE;
1473 ncr53c9x_sched(sc);
1474 }
1475 }
1476
1477 if (ccb->ccb_h.status == CAM_SEL_TIMEOUT) {
1478 /* Selection timeout -- discard this LUN if empty. */
1479 if (li->untagged == NULL && li->used == 0) {
1480 if (lun < NCR_NLUN)
1481 ti->lun[lun] = NULL;
1482 LIST_REMOVE(li, link);
1483 free(li, M_DEVBUF);
1484 }
1485 }
1486
1487 ncr53c9x_free_ecb(sc, ecb);
1488 ti->cmds++;
1489 xpt_done(ccb);
1490}
1491
1492static void
1493ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
1494{
1495 struct ncr53c9x_linfo *li;
1496 struct ncr53c9x_tinfo *ti;
1497 int64_t lun;
1498
1499 NCR_LOCK_ASSERT(sc, MA_OWNED);
1500
1501 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
1502 lun = ecb->ccb->ccb_h.target_lun;
1503 li = TINFO_LUN(ti, lun);
1504#ifdef DIAGNOSTIC
1505 if (li == NULL || li->lun != lun)
1506 panic("%s: lun %qx for ecb %p does not exist", __func__,
1507 (long long)lun, ecb);
1508#endif
1509 if (li->untagged == ecb) {
1510 li->busy = 0;
1511 li->untagged = NULL;
1512 }
1513 if (ecb->tag[0] && li->queued[ecb->tag[1]] != NULL) {
1514#ifdef DIAGNOSTIC
1515 if (li->queued[ecb->tag[1]] != NULL &&
1516 (li->queued[ecb->tag[1]] != ecb))
1517 panic("%s: slot %d for lun %qx has %p instead of ecb "
1518 "%p", __func__, ecb->tag[1], (long long)lun,
1519 li->queued[ecb->tag[1]], ecb);
1520#endif
1521 li->queued[ecb->tag[1]] = NULL;
1522 li->used--;
1523 }
1524 ecb->tag[0] = ecb->tag[1] = 0;
1525
1526 if ((ecb->flags & ECB_READY) != 0) {
1527 ecb->flags &= ~ECB_READY;
1528 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
1529 }
1530}
1531
1532/*
1533 * INTERRUPT/PROTOCOL ENGINE
1534 */
1535
1536/*
1537 * Schedule an outgoing message by prioritizing it, and asserting
1538 * attention on the bus. We can only do this when we are the initiator
1539 * else there will be an illegal command interrupt.
1540 */
1541#define ncr53c9x_sched_msgout(m) do { \
1542 NCR_MSGS(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \
1543 NCRCMD(sc, NCRCMD_SETATN); \
1544 sc->sc_flags |= NCR_ATN; \
1545 sc->sc_msgpriq |= (m); \
1546} while (/* CONSTCOND */0)
1547
1548static void
1549ncr53c9x_flushfifo(struct ncr53c9x_softc *sc)
1550{
1551
1552 NCR_LOCK_ASSERT(sc, MA_OWNED);
1553
1554 NCR_TRACE(("[%s] ", __func__));
1555
1556 NCRCMD(sc, NCRCMD_FLUSH);
1557
1558 if (sc->sc_phase == COMMAND_PHASE ||
1559 sc->sc_phase == MESSAGE_OUT_PHASE)
1560 DELAY(2);
1561}
1562
1563static int
1564ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
1565{
1566 int i, n;
1567 uint8_t *ibuf;
1568
1569 NCR_LOCK_ASSERT(sc, MA_OWNED);
1570
1571 switch (how) {
1572 case NCR_RDFIFO_START:
1573 ibuf = sc->sc_imess;
1574 sc->sc_imlen = 0;
1575 break;
1576
1577 case NCR_RDFIFO_CONTINUE:
1578 ibuf = sc->sc_imess + sc->sc_imlen;
1579 break;
1580
1581 default:
1582 panic("%s: bad flag", __func__);
1583 /* NOTREACHED */
1584 }
1585
1586 /*
1587 * XXX buffer (sc_imess) size for message
1588 */
1589
1590 n = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
1591
1592 if (sc->sc_rev == NCR_VARIANT_FAS366) {
1593 n *= 2;
1594
1595 for (i = 0; i < n; i++)
1596 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO);
1597
1598 if (sc->sc_espstat2 & NCRFAS_STAT2_ISHUTTLE) {
1599
1600 NCR_WRITE_REG(sc, NCR_FIFO, 0);
1601 ibuf[i++] = NCR_READ_REG(sc, NCR_FIFO);
1602
1603 NCR_READ_REG(sc, NCR_FIFO);
1604
1605 ncr53c9x_flushfifo(sc);
1606 }
1607 } else
1608 for (i = 0; i < n; i++)
1609 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO);
1610
1611 sc->sc_imlen += i;
1612
1613#if 0
1614#ifdef NCR53C9X_DEBUG
1615 NCR_TRACE(("\n[rdfifo %s (%d):",
1616 (how == NCR_RDFIFO_START) ? "start" : "cont", (int)sc->sc_imlen));
1617 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) {
1618 for (i = 0; i < sc->sc_imlen; i++)
1619 printf(" %02x", sc->sc_imess[i]);
1620 printf("]\n");
1621 }
1622#endif
1623#endif
1624 return (sc->sc_imlen);
1625}
1626
1627static void
1628ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, uint8_t *p, int len)
1629{
1630 int i;
1631
1632 NCR_LOCK_ASSERT(sc, MA_OWNED);
1633
1634#ifdef NCR53C9X_DEBUG
1635 NCR_MSGS(("[wrfifo(%d):", len));
1636 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) {
1637 for (i = 0; i < len; i++)
1638 printf(" %02x", p[i]);
1639 printf("]\n");
1640 }
1641#endif
1642
1643 for (i = 0; i < len; i++) {
1644 NCR_WRITE_REG(sc, NCR_FIFO, p[i]);
1645
1646 if (sc->sc_rev == NCR_VARIANT_FAS366)
1647 NCR_WRITE_REG(sc, NCR_FIFO, 0);
1648 }
1649}
1650
1651static int
1652ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype,
1653 int tagid)
1654{
1655 struct ncr53c9x_ecb *ecb = NULL;
1656 struct ncr53c9x_linfo *li;
1657 struct ncr53c9x_tinfo *ti;
1658 uint8_t lun, selid, target;
1659
1660 NCR_LOCK_ASSERT(sc, MA_OWNED);
1661
1662 if (sc->sc_rev == NCR_VARIANT_FAS366)
1663 target = sc->sc_selid;
1664 else {
1665 /*
1666 * The SCSI chip made a snapshot of the data bus
1667 * while the reselection was being negotiated.
1668 * This enables us to determine which target did
1669 * the reselect.
1670 */
1671 selid = sc->sc_selid & ~(1 << sc->sc_id);
1672 if (selid & (selid - 1)) {
1673 device_printf(sc->sc_dev, "reselect with invalid "
1674 "selid %02x; sending DEVICE RESET\n", selid);
1675 goto reset;
1676 }
1677
1678 target = ffs(selid) - 1;
1679 }
1680 lun = message & 0x07;
1681
1682 /*
1683 * Search wait queue for disconnected command.
1684 * The list should be short, so I haven't bothered with
1685 * any more sophisticated structures than a simple
1686 * singly linked list.
1687 */
1688 ti = &sc->sc_tinfo[target];
1689 li = TINFO_LUN(ti, lun);
1690
1691 /*
1692 * We can get as far as the LUN with the IDENTIFY
1693 * message. Check to see if we're running an
1694 * untagged command. Otherwise ack the IDENTIFY
1695 * and wait for a tag message.
1696 */
1697 if (li != NULL) {
1698 if (li->untagged != NULL && li->busy)
1699 ecb = li->untagged;
1700 else if (tagtype != MSG_SIMPLE_Q_TAG) {
1701 /* Wait for tag to come by. */
1702 sc->sc_state = NCR_IDENTIFIED;
1703 return (0);
1704 } else if (tagtype)
1705 ecb = li->queued[tagid];
1706 }
1707 if (ecb == NULL) {
1708 device_printf(sc->sc_dev, "reselect from target %d lun %d "
1709 "tag %x:%x with no nexus; sending ABORT\n",
1710 target, lun, tagtype, tagid);
1711 goto abort;
1712 }
1713
1714 /* Make this nexus active again. */
1715 sc->sc_state = NCR_CONNECTED;
1716 sc->sc_nexus = ecb;
1717 ncr53c9x_setsync(sc, ti);
1718
1719 if (ecb->flags & ECB_RESET)
1720 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1721 else if (ecb->flags & ECB_ABORT)
1722 ncr53c9x_sched_msgout(SEND_ABORT);
1723
1724 /* Do an implicit RESTORE POINTERS. */
1725 sc->sc_dp = ecb->daddr;
1726 sc->sc_dleft = ecb->dleft;
1727
1728 return (0);
1729
1730reset:
1731 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1732 return (1);
1733
1734abort:
1735 ncr53c9x_sched_msgout(SEND_ABORT);
1736 return (1);
1737}
1738
1739/* From NetBSD; these should go into CAM at some point. */
1740#define MSG_ISEXTENDED(m) ((m) == MSG_EXTENDED)
1741#define MSG_IS1BYTE(m) \
1742 ((!MSG_ISEXTENDED(m) && (m) < 0x20) || MSG_ISIDENTIFY(m))
1743#define MSG_IS2BYTE(m) (((m) & 0xf0) == 0x20)
1744
1745static inline int
1746__verify_msg_format(uint8_t *p, int len)
1747{
1748
1749 if (len == 1 && MSG_IS1BYTE(p[0]))
1750 return (1);
1751 if (len == 2 && MSG_IS2BYTE(p[0]))
1752 return (1);
1753 if (len >= 3 && MSG_ISEXTENDED(p[0]) &&
1754 len == p[1] + 2)
1755 return (1);
1756
1757 return (0);
1758}
1759
1760/*
1761 * Get an incoming message as initiator.
1762 *
1763 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a
1764 * byte in the FIFO.
1765 */
1766static void
1767ncr53c9x_msgin(struct ncr53c9x_softc *sc)
1768{
1769 struct ncr53c9x_ecb *ecb;
1770 struct ncr53c9x_linfo *li;
1771 struct ncr53c9x_tinfo *ti;
1772 uint8_t *pb;
1773 int lun, plen;
1774
1775 NCR_LOCK_ASSERT(sc, MA_OWNED);
1776
1777 NCR_TRACE(("[%s(curmsglen:%ld)] ", __func__, (long)sc->sc_imlen));
1778
1779 if (sc->sc_imlen == 0) {
1780 device_printf(sc->sc_dev, "msgin: no msg byte available\n");
1781 return;
1782 }
1783
1784 /*
1785 * Prepare for a new message. A message should (according
1786 * to the SCSI standard) be transmitted in one single
1787 * MESSAGE_IN_PHASE. If we have been in some other phase,
1788 * then this is a new message.
1789 */
1790 if (sc->sc_prevphase != MESSAGE_IN_PHASE &&
1791 sc->sc_state != NCR_RESELECTED) {
1792 device_printf(sc->sc_dev, "phase change, dropping message, "
1793 "prev %d, state %d\n", sc->sc_prevphase, sc->sc_state);
1794 sc->sc_flags &= ~NCR_DROP_MSGI;
1795 sc->sc_imlen = 0;
1796 }
1797
1798 /*
1799 * If we're going to reject the message, don't bother storing
1800 * the incoming bytes. But still, we need to ACK them.
1801 */
1802 if ((sc->sc_flags & NCR_DROP_MSGI) != 0) {
1803 NCRCMD(sc, NCRCMD_MSGOK);
1804 device_printf(sc->sc_dev, "<dropping msg byte %x>",
1805 sc->sc_imess[sc->sc_imlen]);
1806 return;
1807 }
1808
1809 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) {
1810 ncr53c9x_sched_msgout(SEND_REJECT);
1811 sc->sc_flags |= NCR_DROP_MSGI;
1812 } else {
1813 switch (sc->sc_state) {
1814 /*
1815 * if received message is the first of reselection
1816 * then first byte is selid, and then message
1817 */
1818 case NCR_RESELECTED:
1819 pb = sc->sc_imess + 1;
1820 plen = sc->sc_imlen - 1;
1821 break;
1822
1823 default:
1824 pb = sc->sc_imess;
1825 plen = sc->sc_imlen;
1826 }
1827
1828 if (__verify_msg_format(pb, plen))
1829 goto gotit;
1830 }
1831
1832 /* Acknowledge what we have so far. */
1833 NCRCMD(sc, NCRCMD_MSGOK);
1834 return;
1835
1836gotit:
1837 NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state));
1838 /*
1839 * We got a complete message, flush the imess.
1840 * XXX nobody uses imlen below.
1841 */
1842 sc->sc_imlen = 0;
1843 /*
1844 * Now we should have a complete message (1 byte, 2 byte
1845 * and moderately long extended messages). We only handle
1846 * extended messages which total length is shorter than
1847 * NCR_MAX_MSG_LEN. Longer messages will be amputated.
1848 */
1849 switch (sc->sc_state) {
1850 case NCR_CONNECTED:
1851 ecb = sc->sc_nexus;
1852 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
1853
1854 switch (sc->sc_imess[0]) {
1855 case MSG_CMDCOMPLETE:
1856 NCR_MSGS(("cmdcomplete "));
1857 if (sc->sc_dleft < 0) {
1858 xpt_print_path(ecb->ccb->ccb_h.path);
1859 printf("got %ld extra bytes\n",
1860 -(long)sc->sc_dleft);
1861 sc->sc_dleft = 0;
1862 }
1863 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) ?
1864 0 : sc->sc_dleft;
1865 if ((ecb->flags & ECB_SENSE) == 0)
1866 ecb->ccb->csio.resid = ecb->dleft;
1867 sc->sc_state = NCR_CMDCOMPLETE;
1868 break;
1869
1870 case MSG_MESSAGE_REJECT:
1871 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout));
1872 switch (sc->sc_msgout) {
1873 case SEND_TAG:
1874 /*
1875 * Target does not like tagged queuing.
1876 * - Flush the command queue
1877 * - Disable tagged queuing for the target
1878 * - Dequeue ecb from the queued array.
1879 */
1880 device_printf(sc->sc_dev, "tagged queuing "
1881 "rejected: target %d\n",
1882 ecb->ccb->ccb_h.target_id);
1883
1884 NCR_MSGS(("(rejected sent tag)"));
1885 NCRCMD(sc, NCRCMD_FLUSH);
1886 DELAY(1);
1887 ti->flags &= ~T_TAG;
1888 lun = ecb->ccb->ccb_h.target_lun;
1889 li = TINFO_LUN(ti, lun);
1890 if (ecb->tag[0] &&
1891 li->queued[ecb->tag[1]] != NULL) {
1892 li->queued[ecb->tag[1]] = NULL;
1893 li->used--;
1894 }
1895 ecb->tag[0] = ecb->tag[1] = 0;
1896 li->untagged = ecb;
1897 li->busy = 1;
1898 break;
1899
1900 case SEND_SDTR:
1901 device_printf(sc->sc_dev, "sync transfer "
1902 "rejected: target %d\n",
1903 ecb->ccb->ccb_h.target_id);
1904
1905 ti->flags &= ~T_SDTRSENT;
1906 ti->curr.period = ti->goal.period = 0;
1907 ti->curr.offset = ti->goal.offset = 0;
1908 ncr53c9x_setsync(sc, ti);
1909 break;
1910
1911 case SEND_WDTR:
1912 device_printf(sc->sc_dev, "wide transfer "
1913 "rejected: target %d\n",
1914 ecb->ccb->ccb_h.target_id);
1915
1916 ti->flags &= ~T_WDTRSENT;
1917 ti->curr.width = ti->goal.width =
1918 MSG_EXT_WDTR_BUS_8_BIT;
1919 ncr53c9x_setsync(sc, ti);
1920 break;
1921
1922 case SEND_INIT_DET_ERR:
1923 goto abort;
1924 }
1925 break;
1926
1927 case MSG_NOOP:
1928 NCR_MSGS(("noop "));
1929 break;
1930
1931 case MSG_HEAD_OF_Q_TAG:
1932 case MSG_SIMPLE_Q_TAG:
1933 case MSG_ORDERED_Q_TAG:
1934 NCR_MSGS(("TAG %x:%x",
1935 sc->sc_imess[0], sc->sc_imess[1]));
1936 break;
1937
1938 case MSG_DISCONNECT:
1939 NCR_MSGS(("disconnect "));
1940 ti->dconns++;
1941 sc->sc_state = NCR_DISCONNECT;
1942
1943 /*
1944 * Mark the fact that all bytes have moved. The
1945 * target may not bother to do a SAVE POINTERS
1946 * at this stage. This flag will set the residual
1947 * count to zero on MSG COMPLETE.
1948 */
1949 if (sc->sc_dleft == 0)
1950 ecb->flags |= ECB_TENTATIVE_DONE;
1951 break;
1952
1953 case MSG_SAVEDATAPOINTER:
1954 NCR_MSGS(("save datapointer "));
1955 ecb->daddr = sc->sc_dp;
1956 ecb->dleft = sc->sc_dleft;
1957 break;
1958
1959 case MSG_RESTOREPOINTERS:
1960 NCR_MSGS(("restore datapointer "));
1961 sc->sc_dp = ecb->daddr;
1962 sc->sc_dleft = ecb->dleft;
1963 break;
1964
1965 case MSG_EXTENDED:
1966 NCR_MSGS(("extended(%x) ", sc->sc_imess[2]));
1967 switch (sc->sc_imess[2]) {
1968 case MSG_EXT_SDTR:
1969 NCR_MSGS(("SDTR period %d, offset %d ",
1970 sc->sc_imess[3], sc->sc_imess[4]));
1971 if (sc->sc_imess[1] != 3)
1972 goto reject;
1973 ti->curr.period = sc->sc_imess[3];
1974 ti->curr.offset = sc->sc_imess[4];
1975 if (sc->sc_minsync == 0 ||
1976 ti->curr.offset == 0 ||
1977 ti->curr.period > 124) {
1978#if 0
1979#ifdef NCR53C9X_DEBUG
1980 xpt_print_path(ecb->ccb->ccb_h.path);
1981 printf("async mode\n");
1982#endif
1983#endif
1984 if ((ti->flags & T_SDTRSENT) == 0) {
1985 /*
1986 * target initiated negotiation
1987 */
1988 ti->curr.offset = 0;
1989 ncr53c9x_sched_msgout(
1990 SEND_SDTR);
1991 }
1992 } else {
1993 ti->curr.period =
1994 ncr53c9x_cpb2stp(sc,
1995 ncr53c9x_stp2cpb(sc,
1996 ti->curr.period));
1997 if ((ti->flags & T_SDTRSENT) == 0) {
1998 /*
1999 * target initiated negotiation
2000 */
2001 if (ti->curr.period <
2002 sc->sc_minsync)
2003 ti->curr.period =
2004 sc->sc_minsync;
2005 if (ti->curr.offset >
2006 sc->sc_maxoffset)
2007 ti->curr.offset =
2008 sc->sc_maxoffset;
2009 ncr53c9x_sched_msgout(
2010 SEND_SDTR);
2011 }
2012 }
2013 ti->flags &= ~T_SDTRSENT;
2014 ti->goal.period = ti->curr.period;
2015 ti->goal.offset = ti->curr.offset;
2016 ncr53c9x_setsync(sc, ti);
2017 break;
2018
2019 case MSG_EXT_WDTR:
2020 NCR_MSGS(("wide mode %d ", sc->sc_imess[3]));
2021 ti->curr.width = sc->sc_imess[3];
2022 if (!(ti->flags & T_WDTRSENT))
2023 /*
2024 * target initiated negotiation
2025 */
2026 ncr53c9x_sched_msgout(SEND_WDTR);
2027 ti->flags &= ~T_WDTRSENT;
2028 ti->goal.width = ti->curr.width;
2029 ncr53c9x_setsync(sc, ti);
2030 break;
2031
2032 default:
2033 xpt_print_path(ecb->ccb->ccb_h.path);
|
2033 printf("unrecognized MESSAGE EXTENDED;"
2034 " sending REJECT\n");
| 2034 printf("unrecognized MESSAGE EXTENDED 0x%x;"
2035 " sending REJECT\n", sc->sc_imess[2]);
|
2035 goto reject;
2036 }
2037 break;
2038
2039 default:
2040 NCR_MSGS(("ident "));
2041 xpt_print_path(ecb->ccb->ccb_h.path);
| 2036 goto reject;
2037 }
2038 break;
2039
2040 default:
2041 NCR_MSGS(("ident "));
2042 xpt_print_path(ecb->ccb->ccb_h.path);
|
2042 printf("unrecognized MESSAGE; sending REJECT\n");
| 2043 printf("unrecognized MESSAGE 0x%x; sending REJECT\n",
2044 sc->sc_imess[0]);
|
2043 /* FALLTHROUGH */
2044 reject:
2045 ncr53c9x_sched_msgout(SEND_REJECT);
2046 break;
2047 }
2048 break;
2049
2050 case NCR_IDENTIFIED:
2051 /*
2052 * IDENTIFY message was received and queue tag is expected
2053 * now.
2054 */
2055 if ((sc->sc_imess[0] != MSG_SIMPLE_Q_TAG) ||
2056 (sc->sc_msgify == 0)) {
2057 device_printf(sc->sc_dev, "TAG reselect without "
2058 "IDENTIFY; MSG %x; sending DEVICE RESET\n",
2059 sc->sc_imess[0]);
2060 goto reset;
2061 }
2062 (void)ncr53c9x_reselect(sc, sc->sc_msgify,
2063 sc->sc_imess[0], sc->sc_imess[1]);
2064 break;
2065
2066 case NCR_RESELECTED:
2067 if (MSG_ISIDENTIFY(sc->sc_imess[1]))
2068 sc->sc_msgify = sc->sc_imess[1];
2069 else {
2070 device_printf(sc->sc_dev, "reselect without IDENTIFY;"
2071 " MSG %x; sending DEVICE RESET\n", sc->sc_imess[1]);
2072 goto reset;
2073 }
2074 (void)ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0);
2075 break;
2076
2077 default:
2078 device_printf(sc->sc_dev, "unexpected MESSAGE IN; "
2079 "sending DEVICE RESET\n");
2080 /* FALLTHROUGH */
2081 reset:
2082 ncr53c9x_sched_msgout(SEND_DEV_RESET);
2083 break;
2084
2085 abort:
2086 ncr53c9x_sched_msgout(SEND_ABORT);
2087 }
2088
2089 /* If we have more messages to send set ATN. */
2090 if (sc->sc_msgpriq) {
2091 NCRCMD(sc, NCRCMD_SETATN);
2092 sc->sc_flags |= NCR_ATN;
2093 }
2094
2095 /* Acknowledge last message byte. */
2096 NCRCMD(sc, NCRCMD_MSGOK);
2097
2098 /* Done, reset message pointer. */
2099 sc->sc_flags &= ~NCR_DROP_MSGI;
2100 sc->sc_imlen = 0;
2101}
2102
2103/*
2104 * Send the highest priority, scheduled message.
2105 */
2106static void
2107ncr53c9x_msgout(struct ncr53c9x_softc *sc)
2108{
2109 struct ncr53c9x_tinfo *ti;
2110 struct ncr53c9x_ecb *ecb;
2111 size_t size;
| 2045 /* FALLTHROUGH */
2046 reject:
2047 ncr53c9x_sched_msgout(SEND_REJECT);
2048 break;
2049 }
2050 break;
2051
2052 case NCR_IDENTIFIED:
2053 /*
2054 * IDENTIFY message was received and queue tag is expected
2055 * now.
2056 */
2057 if ((sc->sc_imess[0] != MSG_SIMPLE_Q_TAG) ||
2058 (sc->sc_msgify == 0)) {
2059 device_printf(sc->sc_dev, "TAG reselect without "
2060 "IDENTIFY; MSG %x; sending DEVICE RESET\n",
2061 sc->sc_imess[0]);
2062 goto reset;
2063 }
2064 (void)ncr53c9x_reselect(sc, sc->sc_msgify,
2065 sc->sc_imess[0], sc->sc_imess[1]);
2066 break;
2067
2068 case NCR_RESELECTED:
2069 if (MSG_ISIDENTIFY(sc->sc_imess[1]))
2070 sc->sc_msgify = sc->sc_imess[1];
2071 else {
2072 device_printf(sc->sc_dev, "reselect without IDENTIFY;"
2073 " MSG %x; sending DEVICE RESET\n", sc->sc_imess[1]);
2074 goto reset;
2075 }
2076 (void)ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0);
2077 break;
2078
2079 default:
2080 device_printf(sc->sc_dev, "unexpected MESSAGE IN; "
2081 "sending DEVICE RESET\n");
2082 /* FALLTHROUGH */
2083 reset:
2084 ncr53c9x_sched_msgout(SEND_DEV_RESET);
2085 break;
2086
2087 abort:
2088 ncr53c9x_sched_msgout(SEND_ABORT);
2089 }
2090
2091 /* If we have more messages to send set ATN. */
2092 if (sc->sc_msgpriq) {
2093 NCRCMD(sc, NCRCMD_SETATN);
2094 sc->sc_flags |= NCR_ATN;
2095 }
2096
2097 /* Acknowledge last message byte. */
2098 NCRCMD(sc, NCRCMD_MSGOK);
2099
2100 /* Done, reset message pointer. */
2101 sc->sc_flags &= ~NCR_DROP_MSGI;
2102 sc->sc_imlen = 0;
2103}
2104
2105/*
2106 * Send the highest priority, scheduled message.
2107 */
2108static void
2109ncr53c9x_msgout(struct ncr53c9x_softc *sc)
2110{
2111 struct ncr53c9x_tinfo *ti;
2112 struct ncr53c9x_ecb *ecb;
2113 size_t size;
|
| 2114 int error;
|
2112#ifdef NCR53C9X_DEBUG
2113 int i;
2114#endif
2115
2116 NCR_LOCK_ASSERT(sc, MA_OWNED);
2117
2118 NCR_TRACE(("[%s(priq:%x, prevphase:%x)]", __func__, sc->sc_msgpriq,
2119 sc->sc_prevphase));
2120
2121 /*
2122 * XXX - the NCR_ATN flag is not in sync with the actual ATN
2123 * condition on the SCSI bus. The 53c9x chip
2124 * automatically turns off ATN before sending the
2125 * message byte. (See also the comment below in the
2126 * default case when picking out a message to send.)
2127 */
2128 if (sc->sc_flags & NCR_ATN) {
2129 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
2130 new:
2131 NCRCMD(sc, NCRCMD_FLUSH);
2132#if 0
2133 DELAY(1);
2134#endif
2135 sc->sc_msgoutq = 0;
2136 sc->sc_omlen = 0;
2137 }
2138 } else {
2139 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
2140 ncr53c9x_sched_msgout(sc->sc_msgoutq);
2141 goto new;
2142 } else
2143 device_printf(sc->sc_dev, "at line %d: unexpected "
2144 "MESSAGE OUT phase\n", __LINE__);
2145 }
2146
2147 if (sc->sc_omlen == 0) {
2148 /* Pick up highest priority message. */
2149 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq;
2150 sc->sc_msgoutq |= sc->sc_msgout;
2151 sc->sc_msgpriq &= ~sc->sc_msgout;
2152 sc->sc_omlen = 1; /* "Default" message len */
2153 switch (sc->sc_msgout) {
2154 case SEND_SDTR:
2155 ecb = sc->sc_nexus;
2156 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2157 sc->sc_omess[0] = MSG_EXTENDED;
2158 sc->sc_omess[1] = MSG_EXT_SDTR_LEN;
2159 sc->sc_omess[2] = MSG_EXT_SDTR;
2160 sc->sc_omess[3] = ti->goal.period;
2161 sc->sc_omess[4] = ti->goal.offset;
2162 sc->sc_omlen = 5;
2163 break;
2164
2165 case SEND_WDTR:
2166 ecb = sc->sc_nexus;
2167 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2168 sc->sc_omess[0] = MSG_EXTENDED;
2169 sc->sc_omess[1] = MSG_EXT_WDTR_LEN;
2170 sc->sc_omess[2] = MSG_EXT_WDTR;
2171 sc->sc_omess[3] = ti->goal.width;
2172 sc->sc_omlen = 4;
2173 break;
2174
2175 case SEND_IDENTIFY:
2176 if (sc->sc_state != NCR_CONNECTED)
2177 device_printf(sc->sc_dev, "at line %d: no "
2178 "nexus\n", __LINE__);
2179 ecb = sc->sc_nexus;
2180 sc->sc_omess[0] =
2181 MSG_IDENTIFY(ecb->ccb->ccb_h.target_lun, 0);
2182 break;
2183
2184 case SEND_TAG:
2185 if (sc->sc_state != NCR_CONNECTED)
2186 device_printf(sc->sc_dev, "at line %d: no "
2187 "nexus\n", __LINE__);
2188 ecb = sc->sc_nexus;
2189 sc->sc_omess[0] = ecb->tag[0];
2190 sc->sc_omess[1] = ecb->tag[1];
2191 sc->sc_omlen = 2;
2192 break;
2193
2194 case SEND_DEV_RESET:
2195 sc->sc_flags |= NCR_ABORTING;
2196 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
2197 ecb = sc->sc_nexus;
2198 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2199 ti->curr.period = 0;
2200 ti->curr.offset = 0;
2201 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
2202 break;
2203
2204 case SEND_PARITY_ERROR:
2205 sc->sc_omess[0] = MSG_PARITY_ERROR;
2206 break;
2207
2208 case SEND_ABORT:
2209 sc->sc_flags |= NCR_ABORTING;
2210 sc->sc_omess[0] = MSG_ABORT;
2211 break;
2212
2213 case SEND_INIT_DET_ERR:
2214 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
2215 break;
2216
2217 case SEND_REJECT:
2218 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
2219 break;
2220
2221 default:
2222 /*
2223 * We normally do not get here, since the chip
2224 * automatically turns off ATN before the last
2225 * byte of a message is sent to the target.
2226 * However, if the target rejects our (multi-byte)
2227 * message early by switching to MSG IN phase
2228 * ATN remains on, so the target may return to
2229 * MSG OUT phase. If there are no scheduled messages
2230 * left we send a NO-OP.
2231 *
2232 * XXX - Note that this leaves no useful purpose for
2233 * the NCR_ATN flag.
2234 */
2235 sc->sc_flags &= ~NCR_ATN;
2236 sc->sc_omess[0] = MSG_NOOP;
2237 }
2238 sc->sc_omp = sc->sc_omess;
2239 }
2240
2241#ifdef NCR53C9X_DEBUG
2242 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) {
2243 NCR_MSGS(("<msgout:"));
2244 for (i = 0; i < sc->sc_omlen; i++)
2245 NCR_MSGS((" %02x", sc->sc_omess[i]));
2246 NCR_MSGS(("> "));
2247 }
2248#endif
| 2115#ifdef NCR53C9X_DEBUG
2116 int i;
2117#endif
2118
2119 NCR_LOCK_ASSERT(sc, MA_OWNED);
2120
2121 NCR_TRACE(("[%s(priq:%x, prevphase:%x)]", __func__, sc->sc_msgpriq,
2122 sc->sc_prevphase));
2123
2124 /*
2125 * XXX - the NCR_ATN flag is not in sync with the actual ATN
2126 * condition on the SCSI bus. The 53c9x chip
2127 * automatically turns off ATN before sending the
2128 * message byte. (See also the comment below in the
2129 * default case when picking out a message to send.)
2130 */
2131 if (sc->sc_flags & NCR_ATN) {
2132 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
2133 new:
2134 NCRCMD(sc, NCRCMD_FLUSH);
2135#if 0
2136 DELAY(1);
2137#endif
2138 sc->sc_msgoutq = 0;
2139 sc->sc_omlen = 0;
2140 }
2141 } else {
2142 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
2143 ncr53c9x_sched_msgout(sc->sc_msgoutq);
2144 goto new;
2145 } else
2146 device_printf(sc->sc_dev, "at line %d: unexpected "
2147 "MESSAGE OUT phase\n", __LINE__);
2148 }
2149
2150 if (sc->sc_omlen == 0) {
2151 /* Pick up highest priority message. */
2152 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq;
2153 sc->sc_msgoutq |= sc->sc_msgout;
2154 sc->sc_msgpriq &= ~sc->sc_msgout;
2155 sc->sc_omlen = 1; /* "Default" message len */
2156 switch (sc->sc_msgout) {
2157 case SEND_SDTR:
2158 ecb = sc->sc_nexus;
2159 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2160 sc->sc_omess[0] = MSG_EXTENDED;
2161 sc->sc_omess[1] = MSG_EXT_SDTR_LEN;
2162 sc->sc_omess[2] = MSG_EXT_SDTR;
2163 sc->sc_omess[3] = ti->goal.period;
2164 sc->sc_omess[4] = ti->goal.offset;
2165 sc->sc_omlen = 5;
2166 break;
2167
2168 case SEND_WDTR:
2169 ecb = sc->sc_nexus;
2170 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2171 sc->sc_omess[0] = MSG_EXTENDED;
2172 sc->sc_omess[1] = MSG_EXT_WDTR_LEN;
2173 sc->sc_omess[2] = MSG_EXT_WDTR;
2174 sc->sc_omess[3] = ti->goal.width;
2175 sc->sc_omlen = 4;
2176 break;
2177
2178 case SEND_IDENTIFY:
2179 if (sc->sc_state != NCR_CONNECTED)
2180 device_printf(sc->sc_dev, "at line %d: no "
2181 "nexus\n", __LINE__);
2182 ecb = sc->sc_nexus;
2183 sc->sc_omess[0] =
2184 MSG_IDENTIFY(ecb->ccb->ccb_h.target_lun, 0);
2185 break;
2186
2187 case SEND_TAG:
2188 if (sc->sc_state != NCR_CONNECTED)
2189 device_printf(sc->sc_dev, "at line %d: no "
2190 "nexus\n", __LINE__);
2191 ecb = sc->sc_nexus;
2192 sc->sc_omess[0] = ecb->tag[0];
2193 sc->sc_omess[1] = ecb->tag[1];
2194 sc->sc_omlen = 2;
2195 break;
2196
2197 case SEND_DEV_RESET:
2198 sc->sc_flags |= NCR_ABORTING;
2199 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
2200 ecb = sc->sc_nexus;
2201 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2202 ti->curr.period = 0;
2203 ti->curr.offset = 0;
2204 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
2205 break;
2206
2207 case SEND_PARITY_ERROR:
2208 sc->sc_omess[0] = MSG_PARITY_ERROR;
2209 break;
2210
2211 case SEND_ABORT:
2212 sc->sc_flags |= NCR_ABORTING;
2213 sc->sc_omess[0] = MSG_ABORT;
2214 break;
2215
2216 case SEND_INIT_DET_ERR:
2217 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
2218 break;
2219
2220 case SEND_REJECT:
2221 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
2222 break;
2223
2224 default:
2225 /*
2226 * We normally do not get here, since the chip
2227 * automatically turns off ATN before the last
2228 * byte of a message is sent to the target.
2229 * However, if the target rejects our (multi-byte)
2230 * message early by switching to MSG IN phase
2231 * ATN remains on, so the target may return to
2232 * MSG OUT phase. If there are no scheduled messages
2233 * left we send a NO-OP.
2234 *
2235 * XXX - Note that this leaves no useful purpose for
2236 * the NCR_ATN flag.
2237 */
2238 sc->sc_flags &= ~NCR_ATN;
2239 sc->sc_omess[0] = MSG_NOOP;
2240 }
2241 sc->sc_omp = sc->sc_omess;
2242 }
2243
2244#ifdef NCR53C9X_DEBUG
2245 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) {
2246 NCR_MSGS(("<msgout:"));
2247 for (i = 0; i < sc->sc_omlen; i++)
2248 NCR_MSGS((" %02x", sc->sc_omess[i]));
2249 NCR_MSGS(("> "));
2250 }
2251#endif
|
2249 if (sc->sc_rev == NCR_VARIANT_FAS366) {
2250 /*
2251 * XXX FIFO size
2252 */
2253 ncr53c9x_flushfifo(sc);
2254 ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen);
2255 NCRCMD(sc, NCRCMD_TRANS);
2256 } else {
| 2252
2253 if (sc->sc_rev != NCR_VARIANT_FAS366) {
|
2257 /* (Re)send the message. */
2258 size = ulmin(sc->sc_omlen, sc->sc_maxxfer);
| 2254 /* (Re)send the message. */
2255 size = ulmin(sc->sc_omlen, sc->sc_maxxfer);
|
2259 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size);
| 2256 error = NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size);
2257 if (error != 0)
2258 goto cmd;
2259
|
2260 /* Program the SCSI counter. */
2261 NCR_SET_COUNT(sc, size);
2262
2263 /* Load the count in and start the message-out transfer. */
2264 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
2265 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
2266 NCRDMA_GO(sc);
| 2260 /* Program the SCSI counter. */
2261 NCR_SET_COUNT(sc, size);
2262
2263 /* Load the count in and start the message-out transfer. */
2264 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
2265 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
2266 NCRDMA_GO(sc);
|
| 2267 return;
|
2267 }
| 2268 }
|
| 2269
2270cmd:
2271 /*
2272 * XXX FIFO size
2273 */
2274 ncr53c9x_flushfifo(sc);
2275 ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen);
2276 NCRCMD(sc, NCRCMD_TRANS);
|
2268}
2269
2270void
2271ncr53c9x_intr(void *arg)
2272{
2273 struct ncr53c9x_softc *sc = arg;
2274
2275 if (!NCRDMA_ISINTR(sc))
2276 return;
2277
2278 NCR_LOCK(sc);
2279
2280 ncr53c9x_intr1(sc);
2281
2282 NCR_UNLOCK(sc);
2283}
2284
2285/*
2286 * This is the most critical part of the driver, and has to know
2287 * how to deal with *all* error conditions and phases from the SCSI
2288 * bus. If there are no errors and the DMA was active, then call the
2289 * DMA pseudo-interrupt handler. If this returns 1, then that was it
2290 * and we can return from here without further processing.
2291 *
2292 * Most of this needs verifying.
2293 */
2294static void
2295ncr53c9x_intr1(struct ncr53c9x_softc *sc)
2296{
2297 struct ncr53c9x_ecb *ecb;
2298 struct ncr53c9x_linfo *li;
2299 struct ncr53c9x_tinfo *ti;
2300 struct timeval cur, wait;
2301 size_t size;
| 2277}
2278
2279void
2280ncr53c9x_intr(void *arg)
2281{
2282 struct ncr53c9x_softc *sc = arg;
2283
2284 if (!NCRDMA_ISINTR(sc))
2285 return;
2286
2287 NCR_LOCK(sc);
2288
2289 ncr53c9x_intr1(sc);
2290
2291 NCR_UNLOCK(sc);
2292}
2293
2294/*
2295 * This is the most critical part of the driver, and has to know
2296 * how to deal with *all* error conditions and phases from the SCSI
2297 * bus. If there are no errors and the DMA was active, then call the
2298 * DMA pseudo-interrupt handler. If this returns 1, then that was it
2299 * and we can return from here without further processing.
2300 *
2301 * Most of this needs verifying.
2302 */
2303static void
2304ncr53c9x_intr1(struct ncr53c9x_softc *sc)
2305{
2306 struct ncr53c9x_ecb *ecb;
2307 struct ncr53c9x_linfo *li;
2308 struct ncr53c9x_tinfo *ti;
2309 struct timeval cur, wait;
2310 size_t size;
|
2302 int i, nfifo;
| 2311 int error, i, nfifo;
|
2303 uint8_t msg;
2304
2305 NCR_LOCK_ASSERT(sc, MA_OWNED);
2306
2307 NCR_INTS(("[ncr53c9x_intr: state %d]", sc->sc_state));
2308
2309again:
2310 /* and what do the registers say... */
2311 ncr53c9x_readregs(sc);
2312
2313 /*
2314 * At the moment, only a SCSI Bus Reset or Illegal
2315 * Command are classed as errors. A disconnect is a
2316 * valid condition, and we let the code check is the
2317 * "NCR_BUSFREE_OK" flag was set before declaring it
2318 * and error.
2319 *
2320 * Also, the status register tells us about "Gross
2321 * Errors" and "Parity errors". Only the Gross Error
2322 * is really bad, and the parity errors are dealt
2323 * with later.
2324 *
2325 * TODO
2326 * If there are too many parity error, go to slow
2327 * cable mode?
2328 */
2329
2330 if ((sc->sc_espintr & NCRINTR_SBR) != 0) {
2331 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 0) {
2332 NCRCMD(sc, NCRCMD_FLUSH);
2333 DELAY(1);
2334 }
2335 if (sc->sc_state != NCR_SBR) {
2336 device_printf(sc->sc_dev, "SCSI bus reset\n");
2337 ncr53c9x_init(sc, 0); /* Restart everything. */
2338 return;
2339 }
2340#if 0
2341/*XXX*/ device_printf(sc->sc_dev, "<expected bus reset: "
2342 "[intr %x, stat %x, step %d]>\n",
2343 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2344#endif
2345 if (sc->sc_nexus != NULL)
2346 panic("%s: nexus in reset state",
2347 device_get_nameunit(sc->sc_dev));
2348 goto sched;
2349 }
2350
2351 ecb = sc->sc_nexus;
2352
2353#define NCRINTR_ERR (NCRINTR_SBR | NCRINTR_ILL)
2354 if (sc->sc_espintr & NCRINTR_ERR ||
2355 sc->sc_espstat & NCRSTAT_GE) {
2356 if ((sc->sc_espstat & NCRSTAT_GE) != 0) {
2357 /* Gross Error; no target? */
2358 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2359 NCRCMD(sc, NCRCMD_FLUSH);
2360 DELAY(1);
2361 }
2362 if (sc->sc_state == NCR_CONNECTED ||
2363 sc->sc_state == NCR_SELECTING) {
2364 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2365 ncr53c9x_done(sc, ecb);
2366 }
2367 return;
2368 }
2369
2370 if ((sc->sc_espintr & NCRINTR_ILL) != 0) {
2371 if ((sc->sc_flags & NCR_EXPECT_ILLCMD) != 0) {
2372 /*
2373 * Eat away "Illegal command" interrupt
2374 * on a ESP100 caused by a re-selection
2375 * while we were trying to select
2376 * another target.
2377 */
2378#ifdef NCR53C9X_DEBUG
2379 device_printf(sc->sc_dev, "ESP100 work-around "
2380 "activated\n");
2381#endif
2382 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
2383 return;
2384 }
2385 /* Illegal command, out of sync? */
2386 device_printf(sc->sc_dev, "illegal command: 0x%x "
2387 "(state %d, phase %x, prevphase %x)\n",
2388 sc->sc_lastcmd,
2389 sc->sc_state, sc->sc_phase, sc->sc_prevphase);
2390 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2391 NCRCMD(sc, NCRCMD_FLUSH);
2392 DELAY(1);
2393 }
2394 goto reset;
2395 }
2396 }
2397 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
2398
2399 /*
2400 * Call if DMA is active.
2401 *
2402 * If DMA_INTR returns true, then maybe go 'round the loop
2403 * again in case there is no more DMA queued, but a phase
2404 * change is expected.
2405 */
2406 if (NCRDMA_ISACTIVE(sc)) {
2407 if (NCRDMA_INTR(sc) == -1) {
2408 device_printf(sc->sc_dev, "DMA error; resetting\n");
2409 goto reset;
2410 }
2411 /* If DMA active here, then go back to work... */
2412 if (NCRDMA_ISACTIVE(sc))
2413 return;
2414
2415 if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
2416 /*
2417 * DMA not completed. If we can not find a
2418 * acceptable explanation, print a diagnostic.
2419 */
2420 if (sc->sc_state == NCR_SELECTING)
2421 /*
2422 * This can happen if we are reselected
2423 * while using DMA to select a target.
2424 */
2425 /*void*/;
2426 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
2427 /*
2428 * Our (multi-byte) message (eg SDTR) was
2429 * interrupted by the target to send
2430 * a MSG REJECT.
2431 * Print diagnostic if current phase
2432 * is not MESSAGE IN.
2433 */
2434 if (sc->sc_phase != MESSAGE_IN_PHASE)
2435 device_printf(sc->sc_dev,"!TC on MSGOUT"
2436 " [intr %x, stat %x, step %d]"
2437 " prevphase %x, resid %lx\n",
2438 sc->sc_espintr,
2439 sc->sc_espstat,
2440 sc->sc_espstep,
2441 sc->sc_prevphase,
2442 (u_long)sc->sc_omlen);
2443 } else if (sc->sc_dleft == 0) {
2444 /*
2445 * The DMA operation was started for
2446 * a DATA transfer. Print a diagnostic
2447 * if the DMA counter and TC bit
2448 * appear to be out of sync.
2449 *
2450 * XXX This is fatal and usually means that
2451 * the DMA engine is hopelessly out of
2452 * sync with reality. A disk is likely
2453 * getting spammed at this point.
2454 */
2455 device_printf(sc->sc_dev, "!TC on DATA XFER"
2456 " [intr %x, stat %x, step %d]"
2457 " prevphase %x, resid %x\n",
2458 sc->sc_espintr,
2459 sc->sc_espstat,
2460 sc->sc_espstep,
2461 sc->sc_prevphase,
2462 ecb ? ecb->dleft : -1);
2463 goto reset;
2464 }
2465 }
2466 }
2467
2468 /*
2469 * Check for less serious errors.
2470 */
2471 if ((sc->sc_espstat & NCRSTAT_PE) != 0) {
2472 device_printf(sc->sc_dev, "SCSI bus parity error\n");
2473 if (sc->sc_prevphase == MESSAGE_IN_PHASE)
2474 ncr53c9x_sched_msgout(SEND_PARITY_ERROR);
2475 else
2476 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR);
2477 }
2478
2479 if ((sc->sc_espintr & NCRINTR_DIS) != 0) {
2480 sc->sc_msgify = 0;
2481 NCR_INTS(("<DISC [intr %x, stat %x, step %d]>",
2482 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep));
2483 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2484 NCRCMD(sc, NCRCMD_FLUSH);
2485#if 0
2486 DELAY(1);
2487#endif
2488 }
2489 /*
2490 * This command must (apparently) be issued within
2491 * 250mS of a disconnect. So here you are...
2492 */
2493 NCRCMD(sc, NCRCMD_ENSEL);
2494
2495 switch (sc->sc_state) {
2496 case NCR_RESELECTED:
2497 goto sched;
2498
2499 case NCR_SELECTING:
2500 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2501
2502 /* Selection timeout -- discard all LUNs if empty. */
2503 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2504 li = LIST_FIRST(&ti->luns);
2505 while (li != NULL) {
2506 if (li->untagged == NULL && li->used == 0) {
2507 if (li->lun < NCR_NLUN)
2508 ti->lun[li->lun] = NULL;
2509 LIST_REMOVE(li, link);
2510 free(li, M_DEVBUF);
2511 /*
2512 * Restart the search at the beginning.
2513 */
2514 li = LIST_FIRST(&ti->luns);
2515 continue;
2516 }
2517 li = LIST_NEXT(li, link);
2518 }
2519 goto finish;
2520
2521 case NCR_CONNECTED:
2522 if (ecb != NULL) {
2523 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2524 if ((ti->flags & T_SDTRSENT) != 0) {
2525 xpt_print_path(ecb->ccb->ccb_h.path);
2526 printf("sync nego not completed!\n");
2527 ti->flags &= ~T_SDTRSENT;
2528 ti->curr.period = ti->goal.period = 0;
2529 ti->curr.offset = ti->goal.offset = 0;
2530 ncr53c9x_setsync(sc, ti);
2531 }
2532 if ((ti->flags & T_WDTRSENT) != 0) {
2533 xpt_print_path(ecb->ccb->ccb_h.path);
2534 printf("wide nego not completed!\n");
2535 ti->flags &= ~T_WDTRSENT;
2536 ti->curr.width = ti->goal.width =
2537 MSG_EXT_WDTR_BUS_8_BIT;
2538 ncr53c9x_setsync(sc, ti);
2539 }
2540 }
2541
2542 /* It may be OK to disconnect. */
2543 if ((sc->sc_flags & NCR_ABORTING) == 0) {
2544 /*
2545 * Section 5.1.1 of the SCSI 2 spec
2546 * suggests issuing a REQUEST SENSE
2547 * following an unexpected disconnect.
2548 * Some devices go into a contingent
2549 * allegiance condition when
2550 * disconnecting, and this is necessary
2551 * to clean up their state.
2552 */
2553 device_printf(sc->sc_dev, "unexpected "
2554 "disconnect [state %d, intr %x, stat %x, "
2555 "phase(c %x, p %x)]; ", sc->sc_state,
2556 sc->sc_espintr, sc->sc_espstat,
2557 sc->sc_phase, sc->sc_prevphase);
2558
2559 /*
2560 * XXX This will cause a chip reset and will
2561 * prevent us from finding out the real
2562 * problem with the device. However, it's
2563 * necessary until a way can be found to
2564 * safely cancel the DMA that is in
2565 * progress.
2566 */
2567 if (1 || (ecb->flags & ECB_SENSE) != 0) {
2568 printf("resetting\n");
2569 goto reset;
2570 }
2571 printf("sending REQUEST SENSE\n");
2572 callout_stop(&ecb->ch);
2573 ncr53c9x_sense(sc, ecb);
2574 return;
2575 } else if (ecb != NULL &&
2576 (ecb->flags & ECB_RESET) != 0) {
2577 ecb->ccb->ccb_h.status = CAM_REQ_CMP;
2578 goto finish;
2579 }
2580
2581 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT;
2582 goto finish;
2583
2584 case NCR_DISCONNECT:
2585 sc->sc_nexus = NULL;
2586 goto sched;
2587
2588 case NCR_CMDCOMPLETE:
2589 ecb->ccb->ccb_h.status = CAM_REQ_CMP;
2590 goto finish;
2591 }
2592 }
2593
2594 switch (sc->sc_state) {
2595 case NCR_SBR:
2596 device_printf(sc->sc_dev, "waiting for Bus Reset to happen\n");
2597 return;
2598
2599 case NCR_RESELECTED:
2600 /*
2601 * We must be continuing a message?
2602 */
2603 device_printf(sc->sc_dev, "unhandled reselect continuation, "
2604 "state %d, intr %02x\n", sc->sc_state, sc->sc_espintr);
2605 goto reset;
2606 break;
2607
2608 case NCR_IDENTIFIED:
2609 ecb = sc->sc_nexus;
2610 if (sc->sc_phase != MESSAGE_IN_PHASE) {
2611 i = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
2612 /*
2613 * Things are seriously screwed up.
2614 * Pull the brakes, i.e. reset.
2615 */
2616 device_printf(sc->sc_dev, "target didn't send tag: %d "
2617 "bytes in FIFO\n", i);
2618 /* Drain and display FIFO. */
2619 while (i-- > 0)
2620 printf("[%d] ", NCR_READ_REG(sc, NCR_FIFO));
2621
2622 goto reset;
2623 } else
2624 goto msgin;
2625
2626 case NCR_IDLE:
2627 case NCR_SELECTING:
2628 ecb = sc->sc_nexus;
2629 if (sc->sc_espintr & NCRINTR_RESEL) {
2630 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
2631 sc->sc_flags = 0;
2632 /*
2633 * If we're trying to select a
2634 * target ourselves, push our command
2635 * back into the ready list.
2636 */
2637 if (sc->sc_state == NCR_SELECTING) {
2638 NCR_INTS(("backoff selector "));
2639 callout_stop(&ecb->ch);
2640 ncr53c9x_dequeue(sc, ecb);
2641 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
2642 ecb->flags |= ECB_READY;
2643 ecb = sc->sc_nexus = NULL;
2644 }
2645 sc->sc_state = NCR_RESELECTED;
2646 if (sc->sc_phase != MESSAGE_IN_PHASE) {
2647 /*
2648 * Things are seriously screwed up.
2649 * Pull the brakes, i.e. reset
2650 */
2651 device_printf(sc->sc_dev, "target didn't "
2652 "identify\n");
2653 goto reset;
2654 }
2655 /*
2656 * The C90 only inhibits FIFO writes until reselection
2657 * is complete instead of waiting until the interrupt
2658 * status register has been read. So, if the reselect
2659 * happens while we were entering command bytes (for
2660 * another target) some of those bytes can appear in
2661 * the FIFO here, after the interrupt is taken.
2662 *
2663 * To remedy this situation, pull the Selection ID
2664 * and Identify message from the FIFO directly, and
2665 * ignore any extraneous FIFO contents. Also, set
2666 * a flag that allows one Illegal Command Interrupt
2667 * to occur which the chip also generates as a result
2668 * of writing to the FIFO during a reselect.
2669 */
2670 if (sc->sc_rev == NCR_VARIANT_ESP100) {
2671 nfifo =
2672 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
2673 sc->sc_imess[0] = NCR_READ_REG(sc, NCR_FIFO);
2674 sc->sc_imess[1] = NCR_READ_REG(sc, NCR_FIFO);
2675 sc->sc_imlen = 2;
2676 if (nfifo != 2) {
2677 /* Flush the rest. */
2678 NCRCMD(sc, NCRCMD_FLUSH);
2679 }
2680 sc->sc_flags |= NCR_EXPECT_ILLCMD;
2681 if (nfifo > 2)
2682 nfifo = 2; /* We fixed it... */
2683 } else
2684 nfifo = ncr53c9x_rdfifo(sc, NCR_RDFIFO_START);
2685
2686 if (nfifo != 2) {
2687 device_printf(sc->sc_dev, "RESELECT: %d bytes "
2688 "in FIFO! [intr %x, stat %x, step %d, "
2689 "prevphase %x]\n",
2690 nfifo,
2691 sc->sc_espintr,
2692 sc->sc_espstat,
2693 sc->sc_espstep,
2694 sc->sc_prevphase);
2695 goto reset;
2696 }
2697 sc->sc_selid = sc->sc_imess[0];
2698 NCR_INTS(("selid=%02x ", sc->sc_selid));
2699
2700 /* Handle IDENTIFY message. */
2701 ncr53c9x_msgin(sc);
2702
2703 if (sc->sc_state != NCR_CONNECTED &&
2704 sc->sc_state != NCR_IDENTIFIED) {
2705 /* IDENTIFY fail?! */
2706 device_printf(sc->sc_dev, "identify failed, "
2707 "state %d, intr %02x\n", sc->sc_state,
2708 sc->sc_espintr);
2709 goto reset;
2710 }
2711 goto shortcut; /* i.e. next phase expected soon */
2712 }
2713
2714#define NCRINTR_DONE (NCRINTR_FC | NCRINTR_BS)
2715 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) {
2716 /*
2717 * Arbitration won; examine the `step' register
2718 * to determine how far the selection could progress.
2719 */
2720 if (ecb == NULL) {
2721 /*
2722 * When doing path inquiry during boot
2723 * FAS100A trigger a stray interrupt which
2724 * we just ignore instead of panicing.
2725 */
2726 if (sc->sc_state == NCR_IDLE &&
2727 sc->sc_espstep == 0)
2728 return;
2729 panic("%s: no nexus", __func__);
2730 }
2731
2732 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2733
2734 switch (sc->sc_espstep) {
2735 case 0:
2736 /*
2737 * The target did not respond with a
2738 * message out phase - probably an old
2739 * device that doesn't recognize ATN.
2740 * Clear ATN and just continue, the
2741 * target should be in the command
2742 * phase.
2743 * XXX check for command phase?
2744 */
2745 NCRCMD(sc, NCRCMD_RSTATN);
2746 break;
2747
2748 case 1:
2749 if (ti->curr.period == ti->goal.period &&
2750 ti->curr.offset == ti->goal.offset &&
2751 ti->curr.width == ti->goal.width &&
2752 ecb->tag[0] == 0) {
2753 device_printf(sc->sc_dev, "step 1 "
2754 "and no negotiation to perform "
2755 "or tag to send\n");
2756 goto reset;
2757 }
2758 if (sc->sc_phase != MESSAGE_OUT_PHASE) {
2759 device_printf(sc->sc_dev, "step 1 "
2760 "but not in MESSAGE_OUT_PHASE\n");
2761 goto reset;
2762 }
2763 sc->sc_prevphase = MESSAGE_OUT_PHASE; /* XXX */
2764 if (ecb->flags & ECB_RESET) {
2765 /*
2766 * A DEVICE RESET was scheduled and
2767 * ATNS used. As SEND_DEV_RESET has
2768 * the highest priority, the target
2769 * will reset and disconnect and we
2770 * will end up in ncr53c9x_done w/o
2771 * negotiating or sending a TAG. So
2772 * we just break here in order to
2773 * avoid warnings about negotiation
2774 * not having completed.
2775 */
2776 ncr53c9x_sched_msgout(SEND_DEV_RESET);
2777 break;
2778 }
2779 if (ti->curr.width != ti->goal.width) {
2780 ti->flags |= T_WDTRSENT | T_SDTRSENT;
2781 ncr53c9x_sched_msgout(SEND_WDTR |
2782 SEND_SDTR);
2783 }
2784 if (ti->curr.period != ti->goal.period ||
2785 ti->curr.offset != ti->goal.offset) {
2786 ti->flags |= T_SDTRSENT;
2787 ncr53c9x_sched_msgout(SEND_SDTR);
2788 }
2789 if (ecb->tag[0] != 0)
2790 /* Could not do ATN3 so send TAG. */
2791 ncr53c9x_sched_msgout(SEND_TAG);
2792 break;
2793
2794 case 3:
2795 /*
2796 * Grr, this is supposed to mean
2797 * "target left command phase prematurely".
2798 * It seems to happen regularly when
2799 * sync mode is on.
2800 * Look at FIFO to see if command went out.
2801 * (Timing problems?)
2802 */
2803 if (sc->sc_features & NCR_F_DMASELECT) {
2804 if (sc->sc_cmdlen == 0)
2805 /* Hope for the best... */
2806 break;
2807 } else if ((NCR_READ_REG(sc, NCR_FFLAG) &
2808 NCRFIFO_FF) == 0) {
2809 /* Hope for the best... */
2810 break;
2811 }
2812 xpt_print_path(ecb->ccb->ccb_h.path);
2813 printf("selection failed; %d left in FIFO "
2814 "[intr %x, stat %x, step %d]\n",
2815 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF,
2816 sc->sc_espintr, sc->sc_espstat,
2817 sc->sc_espstep);
2818 NCRCMD(sc, NCRCMD_FLUSH);
2819 ncr53c9x_sched_msgout(SEND_ABORT);
2820 return;
2821
2822 case 2:
2823 /* Select stuck at Command Phase. */
2824 NCRCMD(sc, NCRCMD_FLUSH);
2825 break;
2826
2827 case 4:
2828 if (sc->sc_features & NCR_F_DMASELECT &&
2829 sc->sc_cmdlen != 0) {
2830 xpt_print_path(ecb->ccb->ccb_h.path);
2831 printf("select; %lu left in DMA buffer "
2832 "[intr %x, stat %x, step %d]\n",
2833 (u_long)sc->sc_cmdlen,
2834 sc->sc_espintr,
2835 sc->sc_espstat,
2836 sc->sc_espstep);
2837 }
2838 /* So far, everything went fine. */
2839 break;
2840 }
2841
2842 sc->sc_prevphase = INVALID_PHASE; /* ??? */
2843 /* Do an implicit RESTORE POINTERS. */
2844 sc->sc_dp = ecb->daddr;
2845 sc->sc_dleft = ecb->dleft;
2846 sc->sc_state = NCR_CONNECTED;
2847 break;
2848 } else {
2849 device_printf(sc->sc_dev, "unexpected status after "
2850 "select: [intr %x, stat %x, step %x]\n",
2851 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2852 NCRCMD(sc, NCRCMD_FLUSH);
2853 DELAY(1);
2854 goto reset;
2855 }
2856 if (sc->sc_state == NCR_IDLE) {
2857 device_printf(sc->sc_dev, "stray interrupt\n");
2858 return;
2859 }
2860 break;
2861
2862 case NCR_CONNECTED:
2863 if ((sc->sc_flags & NCR_ICCS) != 0) {
2864 /* "Initiate Command Complete Steps" in progress */
2865 sc->sc_flags &= ~NCR_ICCS;
2866
2867 if ((sc->sc_espintr & NCRINTR_DONE) == 0) {
2868 device_printf(sc->sc_dev, "ICCS: "
2869 ": [intr %x, stat %x, step %x]\n",
2870 sc->sc_espintr, sc->sc_espstat,
2871 sc->sc_espstep);
2872 }
2873 ncr53c9x_rdfifo(sc, NCR_RDFIFO_START);
2874 if (sc->sc_imlen < 2)
2875 device_printf(sc->sc_dev, "can't get status, "
2876 "only %d bytes\n", (int)sc->sc_imlen);
2877 ecb->stat = sc->sc_imess[sc->sc_imlen - 2];
2878 msg = sc->sc_imess[sc->sc_imlen - 1];
2879 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg));
2880 if (msg == MSG_CMDCOMPLETE) {
2881 ecb->dleft =
2882 (ecb->flags & ECB_TENTATIVE_DONE) ?
2883 0 : sc->sc_dleft;
2884 if ((ecb->flags & ECB_SENSE) == 0)
2885 ecb->ccb->csio.resid = ecb->dleft;
2886 sc->sc_state = NCR_CMDCOMPLETE;
2887 } else
2888 device_printf(sc->sc_dev, "STATUS_PHASE: "
2889 "msg %d\n", msg);
2890 sc->sc_imlen = 0;
2891 NCRCMD(sc, NCRCMD_MSGOK);
2892 goto shortcut; /* i.e. wait for disconnect */
2893 }
2894 break;
2895
2896 default:
2897 device_printf(sc->sc_dev, "invalid state: %d [intr %x, "
2898 "phase(c %x, p %x)]\n", sc->sc_state,
2899 sc->sc_espintr, sc->sc_phase, sc->sc_prevphase);
2900 goto reset;
2901 }
2902
2903 /*
2904 * Driver is now in state NCR_CONNECTED, i.e. we
2905 * have a current command working the SCSI bus.
2906 */
2907 if (sc->sc_state != NCR_CONNECTED || ecb == NULL)
2908 panic("%s: no nexus", __func__);
2909
2910 switch (sc->sc_phase) {
2911 case MESSAGE_OUT_PHASE:
2912 NCR_PHASE(("MESSAGE_OUT_PHASE "));
2913 ncr53c9x_msgout(sc);
2914 sc->sc_prevphase = MESSAGE_OUT_PHASE;
2915 break;
2916
2917 case MESSAGE_IN_PHASE:
2918msgin:
2919 NCR_PHASE(("MESSAGE_IN_PHASE "));
2920 if ((sc->sc_espintr & NCRINTR_BS) != 0) {
2921 if ((sc->sc_rev != NCR_VARIANT_FAS366) ||
2922 (sc->sc_espstat2 & NCRFAS_STAT2_EMPTY) == 0) {
2923 NCRCMD(sc, NCRCMD_FLUSH);
2924 }
2925 sc->sc_flags |= NCR_WAITI;
2926 NCRCMD(sc, NCRCMD_TRANS);
2927 } else if ((sc->sc_espintr & NCRINTR_FC) != 0) {
2928 if ((sc->sc_flags & NCR_WAITI) == 0) {
2929 device_printf(sc->sc_dev, "MSGIN: unexpected "
2930 "FC bit: [intr %x, stat %x, step %x]\n",
2931 sc->sc_espintr, sc->sc_espstat,
2932 sc->sc_espstep);
2933 }
2934 sc->sc_flags &= ~NCR_WAITI;
2935 ncr53c9x_rdfifo(sc,
2936 (sc->sc_prevphase == sc->sc_phase) ?
2937 NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START);
2938 ncr53c9x_msgin(sc);
2939 } else
2940 device_printf(sc->sc_dev, "MSGIN: weird bits: "
2941 "[intr %x, stat %x, step %x]\n",
2942 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2943 sc->sc_prevphase = MESSAGE_IN_PHASE;
2944 goto shortcut; /* i.e. expect data to be ready */
2945
2946 case COMMAND_PHASE:
2947 /*
2948 * Send the command block. Normally we don't see this
2949 * phase because the SEL_ATN command takes care of
2950 * all this. However, we end up here if either the
2951 * target or we wanted to exchange some more messages
2952 * first (e.g. to start negotiations).
2953 */
2954
2955 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ",
2956 ecb->cmd.cmd.opcode, ecb->clen));
2957 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2958 NCRCMD(sc, NCRCMD_FLUSH);
2959#if 0
2960 DELAY(1);
2961#endif
2962 }
2963 /*
2964 * If we have more messages to send, e.g. WDTR or SDTR
2965 * after we've sent a TAG, set ATN so we'll go back to
2966 * MESSAGE_OUT_PHASE.
2967 */
2968 if (sc->sc_msgpriq) {
2969 NCRCMD(sc, NCRCMD_SETATN);
2970 sc->sc_flags |= NCR_ATN;
2971 }
2972 if (sc->sc_features & NCR_F_DMASELECT) {
2973 /* Setup DMA transfer for command. */
2974 size = ecb->clen;
2975 sc->sc_cmdlen = size;
2976 sc->sc_cmdp = (void *)&ecb->cmd.cmd;
| 2312 uint8_t msg;
2313
2314 NCR_LOCK_ASSERT(sc, MA_OWNED);
2315
2316 NCR_INTS(("[ncr53c9x_intr: state %d]", sc->sc_state));
2317
2318again:
2319 /* and what do the registers say... */
2320 ncr53c9x_readregs(sc);
2321
2322 /*
2323 * At the moment, only a SCSI Bus Reset or Illegal
2324 * Command are classed as errors. A disconnect is a
2325 * valid condition, and we let the code check is the
2326 * "NCR_BUSFREE_OK" flag was set before declaring it
2327 * and error.
2328 *
2329 * Also, the status register tells us about "Gross
2330 * Errors" and "Parity errors". Only the Gross Error
2331 * is really bad, and the parity errors are dealt
2332 * with later.
2333 *
2334 * TODO
2335 * If there are too many parity error, go to slow
2336 * cable mode?
2337 */
2338
2339 if ((sc->sc_espintr & NCRINTR_SBR) != 0) {
2340 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 0) {
2341 NCRCMD(sc, NCRCMD_FLUSH);
2342 DELAY(1);
2343 }
2344 if (sc->sc_state != NCR_SBR) {
2345 device_printf(sc->sc_dev, "SCSI bus reset\n");
2346 ncr53c9x_init(sc, 0); /* Restart everything. */
2347 return;
2348 }
2349#if 0
2350/*XXX*/ device_printf(sc->sc_dev, "<expected bus reset: "
2351 "[intr %x, stat %x, step %d]>\n",
2352 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2353#endif
2354 if (sc->sc_nexus != NULL)
2355 panic("%s: nexus in reset state",
2356 device_get_nameunit(sc->sc_dev));
2357 goto sched;
2358 }
2359
2360 ecb = sc->sc_nexus;
2361
2362#define NCRINTR_ERR (NCRINTR_SBR | NCRINTR_ILL)
2363 if (sc->sc_espintr & NCRINTR_ERR ||
2364 sc->sc_espstat & NCRSTAT_GE) {
2365 if ((sc->sc_espstat & NCRSTAT_GE) != 0) {
2366 /* Gross Error; no target? */
2367 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2368 NCRCMD(sc, NCRCMD_FLUSH);
2369 DELAY(1);
2370 }
2371 if (sc->sc_state == NCR_CONNECTED ||
2372 sc->sc_state == NCR_SELECTING) {
2373 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2374 ncr53c9x_done(sc, ecb);
2375 }
2376 return;
2377 }
2378
2379 if ((sc->sc_espintr & NCRINTR_ILL) != 0) {
2380 if ((sc->sc_flags & NCR_EXPECT_ILLCMD) != 0) {
2381 /*
2382 * Eat away "Illegal command" interrupt
2383 * on a ESP100 caused by a re-selection
2384 * while we were trying to select
2385 * another target.
2386 */
2387#ifdef NCR53C9X_DEBUG
2388 device_printf(sc->sc_dev, "ESP100 work-around "
2389 "activated\n");
2390#endif
2391 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
2392 return;
2393 }
2394 /* Illegal command, out of sync? */
2395 device_printf(sc->sc_dev, "illegal command: 0x%x "
2396 "(state %d, phase %x, prevphase %x)\n",
2397 sc->sc_lastcmd,
2398 sc->sc_state, sc->sc_phase, sc->sc_prevphase);
2399 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2400 NCRCMD(sc, NCRCMD_FLUSH);
2401 DELAY(1);
2402 }
2403 goto reset;
2404 }
2405 }
2406 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
2407
2408 /*
2409 * Call if DMA is active.
2410 *
2411 * If DMA_INTR returns true, then maybe go 'round the loop
2412 * again in case there is no more DMA queued, but a phase
2413 * change is expected.
2414 */
2415 if (NCRDMA_ISACTIVE(sc)) {
2416 if (NCRDMA_INTR(sc) == -1) {
2417 device_printf(sc->sc_dev, "DMA error; resetting\n");
2418 goto reset;
2419 }
2420 /* If DMA active here, then go back to work... */
2421 if (NCRDMA_ISACTIVE(sc))
2422 return;
2423
2424 if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
2425 /*
2426 * DMA not completed. If we can not find a
2427 * acceptable explanation, print a diagnostic.
2428 */
2429 if (sc->sc_state == NCR_SELECTING)
2430 /*
2431 * This can happen if we are reselected
2432 * while using DMA to select a target.
2433 */
2434 /*void*/;
2435 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
2436 /*
2437 * Our (multi-byte) message (eg SDTR) was
2438 * interrupted by the target to send
2439 * a MSG REJECT.
2440 * Print diagnostic if current phase
2441 * is not MESSAGE IN.
2442 */
2443 if (sc->sc_phase != MESSAGE_IN_PHASE)
2444 device_printf(sc->sc_dev,"!TC on MSGOUT"
2445 " [intr %x, stat %x, step %d]"
2446 " prevphase %x, resid %lx\n",
2447 sc->sc_espintr,
2448 sc->sc_espstat,
2449 sc->sc_espstep,
2450 sc->sc_prevphase,
2451 (u_long)sc->sc_omlen);
2452 } else if (sc->sc_dleft == 0) {
2453 /*
2454 * The DMA operation was started for
2455 * a DATA transfer. Print a diagnostic
2456 * if the DMA counter and TC bit
2457 * appear to be out of sync.
2458 *
2459 * XXX This is fatal and usually means that
2460 * the DMA engine is hopelessly out of
2461 * sync with reality. A disk is likely
2462 * getting spammed at this point.
2463 */
2464 device_printf(sc->sc_dev, "!TC on DATA XFER"
2465 " [intr %x, stat %x, step %d]"
2466 " prevphase %x, resid %x\n",
2467 sc->sc_espintr,
2468 sc->sc_espstat,
2469 sc->sc_espstep,
2470 sc->sc_prevphase,
2471 ecb ? ecb->dleft : -1);
2472 goto reset;
2473 }
2474 }
2475 }
2476
2477 /*
2478 * Check for less serious errors.
2479 */
2480 if ((sc->sc_espstat & NCRSTAT_PE) != 0) {
2481 device_printf(sc->sc_dev, "SCSI bus parity error\n");
2482 if (sc->sc_prevphase == MESSAGE_IN_PHASE)
2483 ncr53c9x_sched_msgout(SEND_PARITY_ERROR);
2484 else
2485 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR);
2486 }
2487
2488 if ((sc->sc_espintr & NCRINTR_DIS) != 0) {
2489 sc->sc_msgify = 0;
2490 NCR_INTS(("<DISC [intr %x, stat %x, step %d]>",
2491 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep));
2492 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2493 NCRCMD(sc, NCRCMD_FLUSH);
2494#if 0
2495 DELAY(1);
2496#endif
2497 }
2498 /*
2499 * This command must (apparently) be issued within
2500 * 250mS of a disconnect. So here you are...
2501 */
2502 NCRCMD(sc, NCRCMD_ENSEL);
2503
2504 switch (sc->sc_state) {
2505 case NCR_RESELECTED:
2506 goto sched;
2507
2508 case NCR_SELECTING:
2509 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2510
2511 /* Selection timeout -- discard all LUNs if empty. */
2512 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2513 li = LIST_FIRST(&ti->luns);
2514 while (li != NULL) {
2515 if (li->untagged == NULL && li->used == 0) {
2516 if (li->lun < NCR_NLUN)
2517 ti->lun[li->lun] = NULL;
2518 LIST_REMOVE(li, link);
2519 free(li, M_DEVBUF);
2520 /*
2521 * Restart the search at the beginning.
2522 */
2523 li = LIST_FIRST(&ti->luns);
2524 continue;
2525 }
2526 li = LIST_NEXT(li, link);
2527 }
2528 goto finish;
2529
2530 case NCR_CONNECTED:
2531 if (ecb != NULL) {
2532 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2533 if ((ti->flags & T_SDTRSENT) != 0) {
2534 xpt_print_path(ecb->ccb->ccb_h.path);
2535 printf("sync nego not completed!\n");
2536 ti->flags &= ~T_SDTRSENT;
2537 ti->curr.period = ti->goal.period = 0;
2538 ti->curr.offset = ti->goal.offset = 0;
2539 ncr53c9x_setsync(sc, ti);
2540 }
2541 if ((ti->flags & T_WDTRSENT) != 0) {
2542 xpt_print_path(ecb->ccb->ccb_h.path);
2543 printf("wide nego not completed!\n");
2544 ti->flags &= ~T_WDTRSENT;
2545 ti->curr.width = ti->goal.width =
2546 MSG_EXT_WDTR_BUS_8_BIT;
2547 ncr53c9x_setsync(sc, ti);
2548 }
2549 }
2550
2551 /* It may be OK to disconnect. */
2552 if ((sc->sc_flags & NCR_ABORTING) == 0) {
2553 /*
2554 * Section 5.1.1 of the SCSI 2 spec
2555 * suggests issuing a REQUEST SENSE
2556 * following an unexpected disconnect.
2557 * Some devices go into a contingent
2558 * allegiance condition when
2559 * disconnecting, and this is necessary
2560 * to clean up their state.
2561 */
2562 device_printf(sc->sc_dev, "unexpected "
2563 "disconnect [state %d, intr %x, stat %x, "
2564 "phase(c %x, p %x)]; ", sc->sc_state,
2565 sc->sc_espintr, sc->sc_espstat,
2566 sc->sc_phase, sc->sc_prevphase);
2567
2568 /*
2569 * XXX This will cause a chip reset and will
2570 * prevent us from finding out the real
2571 * problem with the device. However, it's
2572 * necessary until a way can be found to
2573 * safely cancel the DMA that is in
2574 * progress.
2575 */
2576 if (1 || (ecb->flags & ECB_SENSE) != 0) {
2577 printf("resetting\n");
2578 goto reset;
2579 }
2580 printf("sending REQUEST SENSE\n");
2581 callout_stop(&ecb->ch);
2582 ncr53c9x_sense(sc, ecb);
2583 return;
2584 } else if (ecb != NULL &&
2585 (ecb->flags & ECB_RESET) != 0) {
2586 ecb->ccb->ccb_h.status = CAM_REQ_CMP;
2587 goto finish;
2588 }
2589
2590 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT;
2591 goto finish;
2592
2593 case NCR_DISCONNECT:
2594 sc->sc_nexus = NULL;
2595 goto sched;
2596
2597 case NCR_CMDCOMPLETE:
2598 ecb->ccb->ccb_h.status = CAM_REQ_CMP;
2599 goto finish;
2600 }
2601 }
2602
2603 switch (sc->sc_state) {
2604 case NCR_SBR:
2605 device_printf(sc->sc_dev, "waiting for Bus Reset to happen\n");
2606 return;
2607
2608 case NCR_RESELECTED:
2609 /*
2610 * We must be continuing a message?
2611 */
2612 device_printf(sc->sc_dev, "unhandled reselect continuation, "
2613 "state %d, intr %02x\n", sc->sc_state, sc->sc_espintr);
2614 goto reset;
2615 break;
2616
2617 case NCR_IDENTIFIED:
2618 ecb = sc->sc_nexus;
2619 if (sc->sc_phase != MESSAGE_IN_PHASE) {
2620 i = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
2621 /*
2622 * Things are seriously screwed up.
2623 * Pull the brakes, i.e. reset.
2624 */
2625 device_printf(sc->sc_dev, "target didn't send tag: %d "
2626 "bytes in FIFO\n", i);
2627 /* Drain and display FIFO. */
2628 while (i-- > 0)
2629 printf("[%d] ", NCR_READ_REG(sc, NCR_FIFO));
2630
2631 goto reset;
2632 } else
2633 goto msgin;
2634
2635 case NCR_IDLE:
2636 case NCR_SELECTING:
2637 ecb = sc->sc_nexus;
2638 if (sc->sc_espintr & NCRINTR_RESEL) {
2639 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
2640 sc->sc_flags = 0;
2641 /*
2642 * If we're trying to select a
2643 * target ourselves, push our command
2644 * back into the ready list.
2645 */
2646 if (sc->sc_state == NCR_SELECTING) {
2647 NCR_INTS(("backoff selector "));
2648 callout_stop(&ecb->ch);
2649 ncr53c9x_dequeue(sc, ecb);
2650 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
2651 ecb->flags |= ECB_READY;
2652 ecb = sc->sc_nexus = NULL;
2653 }
2654 sc->sc_state = NCR_RESELECTED;
2655 if (sc->sc_phase != MESSAGE_IN_PHASE) {
2656 /*
2657 * Things are seriously screwed up.
2658 * Pull the brakes, i.e. reset
2659 */
2660 device_printf(sc->sc_dev, "target didn't "
2661 "identify\n");
2662 goto reset;
2663 }
2664 /*
2665 * The C90 only inhibits FIFO writes until reselection
2666 * is complete instead of waiting until the interrupt
2667 * status register has been read. So, if the reselect
2668 * happens while we were entering command bytes (for
2669 * another target) some of those bytes can appear in
2670 * the FIFO here, after the interrupt is taken.
2671 *
2672 * To remedy this situation, pull the Selection ID
2673 * and Identify message from the FIFO directly, and
2674 * ignore any extraneous FIFO contents. Also, set
2675 * a flag that allows one Illegal Command Interrupt
2676 * to occur which the chip also generates as a result
2677 * of writing to the FIFO during a reselect.
2678 */
2679 if (sc->sc_rev == NCR_VARIANT_ESP100) {
2680 nfifo =
2681 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
2682 sc->sc_imess[0] = NCR_READ_REG(sc, NCR_FIFO);
2683 sc->sc_imess[1] = NCR_READ_REG(sc, NCR_FIFO);
2684 sc->sc_imlen = 2;
2685 if (nfifo != 2) {
2686 /* Flush the rest. */
2687 NCRCMD(sc, NCRCMD_FLUSH);
2688 }
2689 sc->sc_flags |= NCR_EXPECT_ILLCMD;
2690 if (nfifo > 2)
2691 nfifo = 2; /* We fixed it... */
2692 } else
2693 nfifo = ncr53c9x_rdfifo(sc, NCR_RDFIFO_START);
2694
2695 if (nfifo != 2) {
2696 device_printf(sc->sc_dev, "RESELECT: %d bytes "
2697 "in FIFO! [intr %x, stat %x, step %d, "
2698 "prevphase %x]\n",
2699 nfifo,
2700 sc->sc_espintr,
2701 sc->sc_espstat,
2702 sc->sc_espstep,
2703 sc->sc_prevphase);
2704 goto reset;
2705 }
2706 sc->sc_selid = sc->sc_imess[0];
2707 NCR_INTS(("selid=%02x ", sc->sc_selid));
2708
2709 /* Handle IDENTIFY message. */
2710 ncr53c9x_msgin(sc);
2711
2712 if (sc->sc_state != NCR_CONNECTED &&
2713 sc->sc_state != NCR_IDENTIFIED) {
2714 /* IDENTIFY fail?! */
2715 device_printf(sc->sc_dev, "identify failed, "
2716 "state %d, intr %02x\n", sc->sc_state,
2717 sc->sc_espintr);
2718 goto reset;
2719 }
2720 goto shortcut; /* i.e. next phase expected soon */
2721 }
2722
2723#define NCRINTR_DONE (NCRINTR_FC | NCRINTR_BS)
2724 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) {
2725 /*
2726 * Arbitration won; examine the `step' register
2727 * to determine how far the selection could progress.
2728 */
2729 if (ecb == NULL) {
2730 /*
2731 * When doing path inquiry during boot
2732 * FAS100A trigger a stray interrupt which
2733 * we just ignore instead of panicing.
2734 */
2735 if (sc->sc_state == NCR_IDLE &&
2736 sc->sc_espstep == 0)
2737 return;
2738 panic("%s: no nexus", __func__);
2739 }
2740
2741 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2742
2743 switch (sc->sc_espstep) {
2744 case 0:
2745 /*
2746 * The target did not respond with a
2747 * message out phase - probably an old
2748 * device that doesn't recognize ATN.
2749 * Clear ATN and just continue, the
2750 * target should be in the command
2751 * phase.
2752 * XXX check for command phase?
2753 */
2754 NCRCMD(sc, NCRCMD_RSTATN);
2755 break;
2756
2757 case 1:
2758 if (ti->curr.period == ti->goal.period &&
2759 ti->curr.offset == ti->goal.offset &&
2760 ti->curr.width == ti->goal.width &&
2761 ecb->tag[0] == 0) {
2762 device_printf(sc->sc_dev, "step 1 "
2763 "and no negotiation to perform "
2764 "or tag to send\n");
2765 goto reset;
2766 }
2767 if (sc->sc_phase != MESSAGE_OUT_PHASE) {
2768 device_printf(sc->sc_dev, "step 1 "
2769 "but not in MESSAGE_OUT_PHASE\n");
2770 goto reset;
2771 }
2772 sc->sc_prevphase = MESSAGE_OUT_PHASE; /* XXX */
2773 if (ecb->flags & ECB_RESET) {
2774 /*
2775 * A DEVICE RESET was scheduled and
2776 * ATNS used. As SEND_DEV_RESET has
2777 * the highest priority, the target
2778 * will reset and disconnect and we
2779 * will end up in ncr53c9x_done w/o
2780 * negotiating or sending a TAG. So
2781 * we just break here in order to
2782 * avoid warnings about negotiation
2783 * not having completed.
2784 */
2785 ncr53c9x_sched_msgout(SEND_DEV_RESET);
2786 break;
2787 }
2788 if (ti->curr.width != ti->goal.width) {
2789 ti->flags |= T_WDTRSENT | T_SDTRSENT;
2790 ncr53c9x_sched_msgout(SEND_WDTR |
2791 SEND_SDTR);
2792 }
2793 if (ti->curr.period != ti->goal.period ||
2794 ti->curr.offset != ti->goal.offset) {
2795 ti->flags |= T_SDTRSENT;
2796 ncr53c9x_sched_msgout(SEND_SDTR);
2797 }
2798 if (ecb->tag[0] != 0)
2799 /* Could not do ATN3 so send TAG. */
2800 ncr53c9x_sched_msgout(SEND_TAG);
2801 break;
2802
2803 case 3:
2804 /*
2805 * Grr, this is supposed to mean
2806 * "target left command phase prematurely".
2807 * It seems to happen regularly when
2808 * sync mode is on.
2809 * Look at FIFO to see if command went out.
2810 * (Timing problems?)
2811 */
2812 if (sc->sc_features & NCR_F_DMASELECT) {
2813 if (sc->sc_cmdlen == 0)
2814 /* Hope for the best... */
2815 break;
2816 } else if ((NCR_READ_REG(sc, NCR_FFLAG) &
2817 NCRFIFO_FF) == 0) {
2818 /* Hope for the best... */
2819 break;
2820 }
2821 xpt_print_path(ecb->ccb->ccb_h.path);
2822 printf("selection failed; %d left in FIFO "
2823 "[intr %x, stat %x, step %d]\n",
2824 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF,
2825 sc->sc_espintr, sc->sc_espstat,
2826 sc->sc_espstep);
2827 NCRCMD(sc, NCRCMD_FLUSH);
2828 ncr53c9x_sched_msgout(SEND_ABORT);
2829 return;
2830
2831 case 2:
2832 /* Select stuck at Command Phase. */
2833 NCRCMD(sc, NCRCMD_FLUSH);
2834 break;
2835
2836 case 4:
2837 if (sc->sc_features & NCR_F_DMASELECT &&
2838 sc->sc_cmdlen != 0) {
2839 xpt_print_path(ecb->ccb->ccb_h.path);
2840 printf("select; %lu left in DMA buffer "
2841 "[intr %x, stat %x, step %d]\n",
2842 (u_long)sc->sc_cmdlen,
2843 sc->sc_espintr,
2844 sc->sc_espstat,
2845 sc->sc_espstep);
2846 }
2847 /* So far, everything went fine. */
2848 break;
2849 }
2850
2851 sc->sc_prevphase = INVALID_PHASE; /* ??? */
2852 /* Do an implicit RESTORE POINTERS. */
2853 sc->sc_dp = ecb->daddr;
2854 sc->sc_dleft = ecb->dleft;
2855 sc->sc_state = NCR_CONNECTED;
2856 break;
2857 } else {
2858 device_printf(sc->sc_dev, "unexpected status after "
2859 "select: [intr %x, stat %x, step %x]\n",
2860 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2861 NCRCMD(sc, NCRCMD_FLUSH);
2862 DELAY(1);
2863 goto reset;
2864 }
2865 if (sc->sc_state == NCR_IDLE) {
2866 device_printf(sc->sc_dev, "stray interrupt\n");
2867 return;
2868 }
2869 break;
2870
2871 case NCR_CONNECTED:
2872 if ((sc->sc_flags & NCR_ICCS) != 0) {
2873 /* "Initiate Command Complete Steps" in progress */
2874 sc->sc_flags &= ~NCR_ICCS;
2875
2876 if ((sc->sc_espintr & NCRINTR_DONE) == 0) {
2877 device_printf(sc->sc_dev, "ICCS: "
2878 ": [intr %x, stat %x, step %x]\n",
2879 sc->sc_espintr, sc->sc_espstat,
2880 sc->sc_espstep);
2881 }
2882 ncr53c9x_rdfifo(sc, NCR_RDFIFO_START);
2883 if (sc->sc_imlen < 2)
2884 device_printf(sc->sc_dev, "can't get status, "
2885 "only %d bytes\n", (int)sc->sc_imlen);
2886 ecb->stat = sc->sc_imess[sc->sc_imlen - 2];
2887 msg = sc->sc_imess[sc->sc_imlen - 1];
2888 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg));
2889 if (msg == MSG_CMDCOMPLETE) {
2890 ecb->dleft =
2891 (ecb->flags & ECB_TENTATIVE_DONE) ?
2892 0 : sc->sc_dleft;
2893 if ((ecb->flags & ECB_SENSE) == 0)
2894 ecb->ccb->csio.resid = ecb->dleft;
2895 sc->sc_state = NCR_CMDCOMPLETE;
2896 } else
2897 device_printf(sc->sc_dev, "STATUS_PHASE: "
2898 "msg %d\n", msg);
2899 sc->sc_imlen = 0;
2900 NCRCMD(sc, NCRCMD_MSGOK);
2901 goto shortcut; /* i.e. wait for disconnect */
2902 }
2903 break;
2904
2905 default:
2906 device_printf(sc->sc_dev, "invalid state: %d [intr %x, "
2907 "phase(c %x, p %x)]\n", sc->sc_state,
2908 sc->sc_espintr, sc->sc_phase, sc->sc_prevphase);
2909 goto reset;
2910 }
2911
2912 /*
2913 * Driver is now in state NCR_CONNECTED, i.e. we
2914 * have a current command working the SCSI bus.
2915 */
2916 if (sc->sc_state != NCR_CONNECTED || ecb == NULL)
2917 panic("%s: no nexus", __func__);
2918
2919 switch (sc->sc_phase) {
2920 case MESSAGE_OUT_PHASE:
2921 NCR_PHASE(("MESSAGE_OUT_PHASE "));
2922 ncr53c9x_msgout(sc);
2923 sc->sc_prevphase = MESSAGE_OUT_PHASE;
2924 break;
2925
2926 case MESSAGE_IN_PHASE:
2927msgin:
2928 NCR_PHASE(("MESSAGE_IN_PHASE "));
2929 if ((sc->sc_espintr & NCRINTR_BS) != 0) {
2930 if ((sc->sc_rev != NCR_VARIANT_FAS366) ||
2931 (sc->sc_espstat2 & NCRFAS_STAT2_EMPTY) == 0) {
2932 NCRCMD(sc, NCRCMD_FLUSH);
2933 }
2934 sc->sc_flags |= NCR_WAITI;
2935 NCRCMD(sc, NCRCMD_TRANS);
2936 } else if ((sc->sc_espintr & NCRINTR_FC) != 0) {
2937 if ((sc->sc_flags & NCR_WAITI) == 0) {
2938 device_printf(sc->sc_dev, "MSGIN: unexpected "
2939 "FC bit: [intr %x, stat %x, step %x]\n",
2940 sc->sc_espintr, sc->sc_espstat,
2941 sc->sc_espstep);
2942 }
2943 sc->sc_flags &= ~NCR_WAITI;
2944 ncr53c9x_rdfifo(sc,
2945 (sc->sc_prevphase == sc->sc_phase) ?
2946 NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START);
2947 ncr53c9x_msgin(sc);
2948 } else
2949 device_printf(sc->sc_dev, "MSGIN: weird bits: "
2950 "[intr %x, stat %x, step %x]\n",
2951 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2952 sc->sc_prevphase = MESSAGE_IN_PHASE;
2953 goto shortcut; /* i.e. expect data to be ready */
2954
2955 case COMMAND_PHASE:
2956 /*
2957 * Send the command block. Normally we don't see this
2958 * phase because the SEL_ATN command takes care of
2959 * all this. However, we end up here if either the
2960 * target or we wanted to exchange some more messages
2961 * first (e.g. to start negotiations).
2962 */
2963
2964 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ",
2965 ecb->cmd.cmd.opcode, ecb->clen));
2966 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2967 NCRCMD(sc, NCRCMD_FLUSH);
2968#if 0
2969 DELAY(1);
2970#endif
2971 }
2972 /*
2973 * If we have more messages to send, e.g. WDTR or SDTR
2974 * after we've sent a TAG, set ATN so we'll go back to
2975 * MESSAGE_OUT_PHASE.
2976 */
2977 if (sc->sc_msgpriq) {
2978 NCRCMD(sc, NCRCMD_SETATN);
2979 sc->sc_flags |= NCR_ATN;
2980 }
2981 if (sc->sc_features & NCR_F_DMASELECT) {
2982 /* Setup DMA transfer for command. */
2983 size = ecb->clen;
2984 sc->sc_cmdlen = size;
2985 sc->sc_cmdp = (void *)&ecb->cmd.cmd;
|
2977 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen,
| 2986 error = NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen,
|
2978 0, &size);
| 2987 0, &size);
|
| 2988 if (error != 0) {
2989 sc->sc_cmdlen = 0;
2990 sc->sc_cmdp = NULL;
2991 goto cmd;
2992 }
2993
|
2979 /* Program the SCSI counter. */
2980 NCR_SET_COUNT(sc, size);
2981
2982 /* Load the count in. */
2983 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
2984
2985 /* Start the command transfer. */
2986 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
2987 NCRDMA_GO(sc);
| 2994 /* Program the SCSI counter. */
2995 NCR_SET_COUNT(sc, size);
2996
2997 /* Load the count in. */
2998 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
2999
3000 /* Start the command transfer. */
3001 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
3002 NCRDMA_GO(sc);
|
2988 } else {
2989 ncr53c9x_wrfifo(sc, (uint8_t *)&ecb->cmd.cmd,
2990 ecb->clen);
2991 NCRCMD(sc, NCRCMD_TRANS);
| 3003 sc->sc_prevphase = COMMAND_PHASE;
3004 break;
|
2992 }
| 3005 }
|
| 3006cmd:
3007 ncr53c9x_wrfifo(sc, (uint8_t *)&ecb->cmd.cmd, ecb->clen);
3008 NCRCMD(sc, NCRCMD_TRANS);
|
2993 sc->sc_prevphase = COMMAND_PHASE;
2994 break;
2995
2996 case DATA_OUT_PHASE:
2997 NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft));
| 3009 sc->sc_prevphase = COMMAND_PHASE;
3010 break;
3011
3012 case DATA_OUT_PHASE:
3013 NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft));
|
| 3014 sc->sc_prevphase = DATA_OUT_PHASE;
|
2998 NCRCMD(sc, NCRCMD_FLUSH);
2999 size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
| 3015 NCRCMD(sc, NCRCMD_FLUSH);
3016 size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
|
3000 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size);
3001 sc->sc_prevphase = DATA_OUT_PHASE;
| 3017 error = NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size);
|
3002 goto setup_xfer;
3003
3004 case DATA_IN_PHASE:
3005 NCR_PHASE(("DATA_IN_PHASE "));
| 3018 goto setup_xfer;
3019
3020 case DATA_IN_PHASE:
3021 NCR_PHASE(("DATA_IN_PHASE "));
|
| 3022 sc->sc_prevphase = DATA_IN_PHASE;
|
3006 if (sc->sc_rev == NCR_VARIANT_ESP100)
3007 NCRCMD(sc, NCRCMD_FLUSH);
3008 size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
| 3023 if (sc->sc_rev == NCR_VARIANT_ESP100)
3024 NCRCMD(sc, NCRCMD_FLUSH);
3025 size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
|
3009 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size);
3010 sc->sc_prevphase = DATA_IN_PHASE;
3011 setup_xfer:
| 3026 error = NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size);
3027setup_xfer:
3028 if (error != 0) {
3029 switch (error) {
3030 case EFBIG:
3031 ecb->ccb->ccb_h.status |= CAM_REQ_TOO_BIG;
3032 break;
3033 case EINPROGRESS:
3034 panic("%s: cannot deal with deferred DMA",
3035 __func__);
3036 case EINVAL:
3037 ecb->ccb->ccb_h.status |= CAM_REQ_INVALID;
3038 break;
3039 case ENOMEM:
3040 ecb->ccb->ccb_h.status |= CAM_REQUEUE_REQ;
3041 break;
3042 default:
3043 ecb->ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
3044 }
3045 goto finish;
3046 }
3047
|
3012 /* Target returned to data phase: wipe "done" memory */
3013 ecb->flags &= ~ECB_TENTATIVE_DONE;
3014
3015 /* Program the SCSI counter. */
3016 NCR_SET_COUNT(sc, size);
3017
3018 /* Load the count in. */
3019 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
3020
3021 /*
3022 * Note that if `size' is 0, we've already transceived
3023 * all the bytes we want but we're still in DATA PHASE.
3024 * Apparently, the device needs padding. Also, a
3025 * transfer size of 0 means "maximum" to the chip
3026 * DMA logic.
3027 */
3028 NCRCMD(sc,
3029 (size == 0 ? NCRCMD_TRPAD : NCRCMD_TRANS) | NCRCMD_DMA);
3030 NCRDMA_GO(sc);
3031 return;
3032
3033 case STATUS_PHASE:
3034 NCR_PHASE(("STATUS_PHASE "));
3035 sc->sc_flags |= NCR_ICCS;
3036 NCRCMD(sc, NCRCMD_ICCS);
3037 sc->sc_prevphase = STATUS_PHASE;
3038 goto shortcut; /* i.e. expect status results soon */
3039
3040 case INVALID_PHASE:
3041 break;
3042
3043 default:
3044 device_printf(sc->sc_dev,
3045 "unexpected bus phase; resetting\n");
3046 goto reset;
3047 }
3048
3049 return;
3050
3051reset:
3052 ncr53c9x_init(sc, 1);
3053 return;
3054
3055finish:
3056 ncr53c9x_done(sc, ecb);
3057 return;
3058
3059sched:
3060 sc->sc_state = NCR_IDLE;
3061 ncr53c9x_sched(sc);
3062 return;
3063
3064shortcut:
3065 /*
3066 * The idea is that many of the SCSI operations take very little
3067 * time, and going away and getting interrupted is too high an
3068 * overhead to pay. For example, selecting, sending a message
3069 * and command and then doing some work can be done in one "pass".
3070 *
3071 * The delay is a heuristic. It is 2 when at 20MHz, 2 at 25MHz and 1
3072 * at 40MHz. This needs testing.
3073 */
3074 microtime(&wait);
3075 wait.tv_usec += 50 / sc->sc_freq;
3076 if (wait.tv_usec > 1000000) {
3077 wait.tv_sec++;
3078 wait.tv_usec -= 1000000;
3079 }
3080 do {
3081 if (NCRDMA_ISINTR(sc))
3082 goto again;
3083 microtime(&cur);
3084 } while (cur.tv_sec <= wait.tv_sec && cur.tv_usec <= wait.tv_usec);
3085}
3086
3087static void
3088ncr53c9x_abort(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
3089{
3090
3091 NCR_LOCK_ASSERT(sc, MA_OWNED);
3092
3093 /* 2 secs for the abort */
3094 ecb->timeout = NCR_ABORT_TIMEOUT;
3095 ecb->flags |= ECB_ABORT;
3096
3097 if (ecb == sc->sc_nexus) {
3098 /*
3099 * If we're still selecting, the message will be scheduled
3100 * after selection is complete.
3101 */
3102 if (sc->sc_state == NCR_CONNECTED)
3103 ncr53c9x_sched_msgout(SEND_ABORT);
3104
3105 /*
3106 * Reschedule callout.
3107 */
3108 callout_reset(&ecb->ch, mstohz(ecb->timeout),
3109 ncr53c9x_callout, ecb);
3110 } else {
3111 /*
3112 * Just leave the command where it is.
3113 * XXX - what choice do we have but to reset the SCSI
3114 * eventually?
3115 */
3116 if (sc->sc_state == NCR_IDLE)
3117 ncr53c9x_sched(sc);
3118 }
3119}
3120
3121static void
3122ncr53c9x_callout(void *arg)
3123{
3124 struct ncr53c9x_ecb *ecb = arg;
3125 union ccb *ccb = ecb->ccb;
3126 struct ncr53c9x_softc *sc = ecb->sc;
3127 struct ncr53c9x_tinfo *ti;
3128
3129 NCR_LOCK_ASSERT(sc, MA_OWNED);
3130
3131 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
3132 xpt_print_path(ccb->ccb_h.path);
3133 device_printf(sc->sc_dev, "timed out [ecb %p (flags 0x%x, dleft %x, "
3134 "stat %x)], <state %d, nexus %p, phase(l %x, c %x, p %x), "
3135 "resid %lx, msg(q %x,o %x) %s>",
3136 ecb, ecb->flags, ecb->dleft, ecb->stat,
3137 sc->sc_state, sc->sc_nexus,
3138 NCR_READ_REG(sc, NCR_STAT),
3139 sc->sc_phase, sc->sc_prevphase,
3140 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout,
3141 NCRDMA_ISACTIVE(sc) ? "DMA active" : "");
3142#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
3143 printf("TRACE: %s.", ecb->trace);
3144#endif
3145
3146 if (ecb->flags & ECB_ABORT) {
3147 /* Abort timed out. */
3148 printf(" AGAIN\n");
3149 ncr53c9x_init(sc, 1);
3150 } else {
3151 /* Abort the operation that has timed out. */
3152 printf("\n");
3153 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
3154 ncr53c9x_abort(sc, ecb);
3155
3156 /* Disable sync mode if stuck in a data phase. */
3157 if (ecb == sc->sc_nexus &&
3158 ti->curr.offset != 0 &&
3159 (sc->sc_phase & (MSGI | CDI)) == 0) {
3160 /* XXX ASYNC CALLBACK! */
3161 ti->goal.offset = 0;
3162 xpt_print_path(ccb->ccb_h.path);
3163 printf("sync negotiation disabled\n");
3164 }
3165 }
3166}
3167
3168static void
3169ncr53c9x_watch(void *arg)
3170{
3171 struct ncr53c9x_softc *sc = arg;
3172 struct ncr53c9x_linfo *li;
3173 struct ncr53c9x_tinfo *ti;
3174 time_t old;
3175 int t;
3176
3177 NCR_LOCK_ASSERT(sc, MA_OWNED);
3178
3179 /* Delete any structures that have not been used in 10min. */
3180 old = time_second - (10 * 60);
3181
3182 for (t = 0; t < sc->sc_ntarg; t++) {
3183 ti = &sc->sc_tinfo[t];
3184 li = LIST_FIRST(&ti->luns);
3185 while (li) {
3186 if (li->last_used < old &&
3187 li->untagged == NULL &&
3188 li->used == 0) {
3189 if (li->lun < NCR_NLUN)
3190 ti->lun[li->lun] = NULL;
3191 LIST_REMOVE(li, link);
3192 free(li, M_DEVBUF);
3193 /* Restart the search at the beginning. */
3194 li = LIST_FIRST(&ti->luns);
3195 continue;
3196 }
3197 li = LIST_NEXT(li, link);
3198 }
3199 }
3200 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
3201}
| 3048 /* Target returned to data phase: wipe "done" memory */
3049 ecb->flags &= ~ECB_TENTATIVE_DONE;
3050
3051 /* Program the SCSI counter. */
3052 NCR_SET_COUNT(sc, size);
3053
3054 /* Load the count in. */
3055 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
3056
3057 /*
3058 * Note that if `size' is 0, we've already transceived
3059 * all the bytes we want but we're still in DATA PHASE.
3060 * Apparently, the device needs padding. Also, a
3061 * transfer size of 0 means "maximum" to the chip
3062 * DMA logic.
3063 */
3064 NCRCMD(sc,
3065 (size == 0 ? NCRCMD_TRPAD : NCRCMD_TRANS) | NCRCMD_DMA);
3066 NCRDMA_GO(sc);
3067 return;
3068
3069 case STATUS_PHASE:
3070 NCR_PHASE(("STATUS_PHASE "));
3071 sc->sc_flags |= NCR_ICCS;
3072 NCRCMD(sc, NCRCMD_ICCS);
3073 sc->sc_prevphase = STATUS_PHASE;
3074 goto shortcut; /* i.e. expect status results soon */
3075
3076 case INVALID_PHASE:
3077 break;
3078
3079 default:
3080 device_printf(sc->sc_dev,
3081 "unexpected bus phase; resetting\n");
3082 goto reset;
3083 }
3084
3085 return;
3086
3087reset:
3088 ncr53c9x_init(sc, 1);
3089 return;
3090
3091finish:
3092 ncr53c9x_done(sc, ecb);
3093 return;
3094
3095sched:
3096 sc->sc_state = NCR_IDLE;
3097 ncr53c9x_sched(sc);
3098 return;
3099
3100shortcut:
3101 /*
3102 * The idea is that many of the SCSI operations take very little
3103 * time, and going away and getting interrupted is too high an
3104 * overhead to pay. For example, selecting, sending a message
3105 * and command and then doing some work can be done in one "pass".
3106 *
3107 * The delay is a heuristic. It is 2 when at 20MHz, 2 at 25MHz and 1
3108 * at 40MHz. This needs testing.
3109 */
3110 microtime(&wait);
3111 wait.tv_usec += 50 / sc->sc_freq;
3112 if (wait.tv_usec > 1000000) {
3113 wait.tv_sec++;
3114 wait.tv_usec -= 1000000;
3115 }
3116 do {
3117 if (NCRDMA_ISINTR(sc))
3118 goto again;
3119 microtime(&cur);
3120 } while (cur.tv_sec <= wait.tv_sec && cur.tv_usec <= wait.tv_usec);
3121}
3122
3123static void
3124ncr53c9x_abort(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
3125{
3126
3127 NCR_LOCK_ASSERT(sc, MA_OWNED);
3128
3129 /* 2 secs for the abort */
3130 ecb->timeout = NCR_ABORT_TIMEOUT;
3131 ecb->flags |= ECB_ABORT;
3132
3133 if (ecb == sc->sc_nexus) {
3134 /*
3135 * If we're still selecting, the message will be scheduled
3136 * after selection is complete.
3137 */
3138 if (sc->sc_state == NCR_CONNECTED)
3139 ncr53c9x_sched_msgout(SEND_ABORT);
3140
3141 /*
3142 * Reschedule callout.
3143 */
3144 callout_reset(&ecb->ch, mstohz(ecb->timeout),
3145 ncr53c9x_callout, ecb);
3146 } else {
3147 /*
3148 * Just leave the command where it is.
3149 * XXX - what choice do we have but to reset the SCSI
3150 * eventually?
3151 */
3152 if (sc->sc_state == NCR_IDLE)
3153 ncr53c9x_sched(sc);
3154 }
3155}
3156
3157static void
3158ncr53c9x_callout(void *arg)
3159{
3160 struct ncr53c9x_ecb *ecb = arg;
3161 union ccb *ccb = ecb->ccb;
3162 struct ncr53c9x_softc *sc = ecb->sc;
3163 struct ncr53c9x_tinfo *ti;
3164
3165 NCR_LOCK_ASSERT(sc, MA_OWNED);
3166
3167 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
3168 xpt_print_path(ccb->ccb_h.path);
3169 device_printf(sc->sc_dev, "timed out [ecb %p (flags 0x%x, dleft %x, "
3170 "stat %x)], <state %d, nexus %p, phase(l %x, c %x, p %x), "
3171 "resid %lx, msg(q %x,o %x) %s>",
3172 ecb, ecb->flags, ecb->dleft, ecb->stat,
3173 sc->sc_state, sc->sc_nexus,
3174 NCR_READ_REG(sc, NCR_STAT),
3175 sc->sc_phase, sc->sc_prevphase,
3176 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout,
3177 NCRDMA_ISACTIVE(sc) ? "DMA active" : "");
3178#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
3179 printf("TRACE: %s.", ecb->trace);
3180#endif
3181
3182 if (ecb->flags & ECB_ABORT) {
3183 /* Abort timed out. */
3184 printf(" AGAIN\n");
3185 ncr53c9x_init(sc, 1);
3186 } else {
3187 /* Abort the operation that has timed out. */
3188 printf("\n");
3189 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
3190 ncr53c9x_abort(sc, ecb);
3191
3192 /* Disable sync mode if stuck in a data phase. */
3193 if (ecb == sc->sc_nexus &&
3194 ti->curr.offset != 0 &&
3195 (sc->sc_phase & (MSGI | CDI)) == 0) {
3196 /* XXX ASYNC CALLBACK! */
3197 ti->goal.offset = 0;
3198 xpt_print_path(ccb->ccb_h.path);
3199 printf("sync negotiation disabled\n");
3200 }
3201 }
3202}
3203
3204static void
3205ncr53c9x_watch(void *arg)
3206{
3207 struct ncr53c9x_softc *sc = arg;
3208 struct ncr53c9x_linfo *li;
3209 struct ncr53c9x_tinfo *ti;
3210 time_t old;
3211 int t;
3212
3213 NCR_LOCK_ASSERT(sc, MA_OWNED);
3214
3215 /* Delete any structures that have not been used in 10min. */
3216 old = time_second - (10 * 60);
3217
3218 for (t = 0; t < sc->sc_ntarg; t++) {
3219 ti = &sc->sc_tinfo[t];
3220 li = LIST_FIRST(&ti->luns);
3221 while (li) {
3222 if (li->last_used < old &&
3223 li->untagged == NULL &&
3224 li->used == 0) {
3225 if (li->lun < NCR_NLUN)
3226 ti->lun[li->lun] = NULL;
3227 LIST_REMOVE(li, link);
3228 free(li, M_DEVBUF);
3229 /* Restart the search at the beginning. */
3230 li = LIST_FIRST(&ti->luns);
3231 continue;
3232 }
3233 li = LIST_NEXT(li, link);
3234 }
3235 }
3236 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
3237}
|