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esp_sbus.c (226381) esp_sbus.c (226947)
1/*-
2 * Copyright (c) 2004 Scott Long
3 * Copyright (c) 2005 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 45 unchanged lines hidden (view full) ---

54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
59 */
60
61#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2004 Scott Long
3 * Copyright (c) 2005 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 45 unchanged lines hidden (view full) ---

54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
59 */
60
61#include <sys/cdefs.h>
62__FBSDID("$FreeBSD: head/sys/dev/esp/esp_sbus.c 226381 2011-10-15 09:29:43Z marius $");
62__FBSDID("$FreeBSD: head/sys/dev/esp/esp_sbus.c 226947 2011-10-30 21:17:42Z marius $");
63
64#include <sys/param.h>
65#include <sys/systm.h>
66#include <sys/bus.h>
67#include <sys/kernel.h>
68#include <sys/lock.h>
69#include <sys/module.h>
70#include <sys/mutex.h>
63
64#include <sys/param.h>
65#include <sys/systm.h>
66#include <sys/bus.h>
67#include <sys/kernel.h>
68#include <sys/lock.h>
69#include <sys/module.h>
70#include <sys/mutex.h>
71#include <sys/rman.h>
71
72#include <dev/ofw/ofw_bus.h>
73#include <dev/ofw/openfirm.h>
74#include <machine/bus.h>
75#include <machine/ofw_machdep.h>
76#include <machine/resource.h>
72
73#include <dev/ofw/ofw_bus.h>
74#include <dev/ofw/openfirm.h>
75#include <machine/bus.h>
76#include <machine/ofw_machdep.h>
77#include <machine/resource.h>
77#include <sys/rman.h>
78
79#include <cam/cam.h>
80#include <cam/cam_ccb.h>
81#include <cam/scsi/scsi_all.h>
82#include <cam/scsi/scsi_message.h>
83
84#include <sparc64/sbus/lsi64854reg.h>
85#include <sparc64/sbus/lsi64854var.h>
86#include <sparc64/sbus/sbusvar.h>
87
88#include <dev/esp/ncr53c9xreg.h>
89#include <dev/esp/ncr53c9xvar.h>
90
91/* #define ESP_SBUS_DEBUG */
92
93struct esp_softc {
94 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
78
79#include <cam/cam.h>
80#include <cam/cam_ccb.h>
81#include <cam/scsi/scsi_all.h>
82#include <cam/scsi/scsi_message.h>
83
84#include <sparc64/sbus/lsi64854reg.h>
85#include <sparc64/sbus/lsi64854var.h>
86#include <sparc64/sbus/sbusvar.h>
87
88#include <dev/esp/ncr53c9xreg.h>
89#include <dev/esp/ncr53c9xvar.h>
90
91/* #define ESP_SBUS_DEBUG */
92
93struct esp_softc {
94 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
95 struct device *sc_dev;
95 device_t sc_dev;
96
97 struct resource *sc_res;
98
99 struct resource *sc_irqres;
100 void *sc_irq;
101
102 struct lsi64854_softc *sc_dma; /* pointer to my DMA */
103};
104
96
97 struct resource *sc_res;
98
99 struct resource *sc_irqres;
100 void *sc_irq;
101
102 struct lsi64854_softc *sc_dma; /* pointer to my DMA */
103};
104
105static devclass_t esp_devclass;
106
107static int esp_probe(device_t);
108static int esp_dma_attach(device_t);
109static int esp_dma_detach(device_t);
110static int esp_sbus_attach(device_t);
111static int esp_sbus_detach(device_t);
112static int esp_suspend(device_t);
113static int esp_resume(device_t);
114
115static device_method_t esp_dma_methods[] = {
116 DEVMETHOD(device_probe, esp_probe),
117 DEVMETHOD(device_attach, esp_dma_attach),
118 DEVMETHOD(device_detach, esp_dma_detach),
119 DEVMETHOD(device_suspend, esp_suspend),
120 DEVMETHOD(device_resume, esp_resume),
105static int esp_probe(device_t);
106static int esp_dma_attach(device_t);
107static int esp_dma_detach(device_t);
108static int esp_sbus_attach(device_t);
109static int esp_sbus_detach(device_t);
110static int esp_suspend(device_t);
111static int esp_resume(device_t);
112
113static device_method_t esp_dma_methods[] = {
114 DEVMETHOD(device_probe, esp_probe),
115 DEVMETHOD(device_attach, esp_dma_attach),
116 DEVMETHOD(device_detach, esp_dma_detach),
117 DEVMETHOD(device_suspend, esp_suspend),
118 DEVMETHOD(device_resume, esp_resume),
121 {0, 0}
119
120 KOBJMETHOD_END
122};
123
124static driver_t esp_dma_driver = {
125 "esp",
126 esp_dma_methods,
127 sizeof(struct esp_softc)
128};
129
130DRIVER_MODULE(esp, dma, esp_dma_driver, esp_devclass, 0, 0);
131MODULE_DEPEND(esp, dma, 1, 1, 1);
132
133static device_method_t esp_sbus_methods[] = {
134 DEVMETHOD(device_probe, esp_probe),
135 DEVMETHOD(device_attach, esp_sbus_attach),
136 DEVMETHOD(device_detach, esp_sbus_detach),
137 DEVMETHOD(device_suspend, esp_suspend),
138 DEVMETHOD(device_resume, esp_resume),
121};
122
123static driver_t esp_dma_driver = {
124 "esp",
125 esp_dma_methods,
126 sizeof(struct esp_softc)
127};
128
129DRIVER_MODULE(esp, dma, esp_dma_driver, esp_devclass, 0, 0);
130MODULE_DEPEND(esp, dma, 1, 1, 1);
131
132static device_method_t esp_sbus_methods[] = {
133 DEVMETHOD(device_probe, esp_probe),
134 DEVMETHOD(device_attach, esp_sbus_attach),
135 DEVMETHOD(device_detach, esp_sbus_detach),
136 DEVMETHOD(device_suspend, esp_suspend),
137 DEVMETHOD(device_resume, esp_resume),
139 {0, 0}
138
139 KOBJMETHOD_END
140};
141
142static driver_t esp_sbus_driver = {
143 "esp",
144 esp_sbus_methods,
145 sizeof(struct esp_softc)
146};
147

--- 22 unchanged lines hidden (view full) ---

170 esp_write_reg,
171 esp_dma_isintr,
172 esp_dma_reset,
173 esp_dma_intr,
174 esp_dma_setup,
175 esp_dma_go,
176 esp_dma_stop,
177 esp_dma_isactive,
140};
141
142static driver_t esp_sbus_driver = {
143 "esp",
144 esp_sbus_methods,
145 sizeof(struct esp_softc)
146};
147

--- 22 unchanged lines hidden (view full) ---

170 esp_write_reg,
171 esp_dma_isintr,
172 esp_dma_reset,
173 esp_dma_intr,
174 esp_dma_setup,
175 esp_dma_go,
176 esp_dma_stop,
177 esp_dma_isactive,
178 NULL, /* gl_clear_latched_intr */
179};
180
181static int
182esp_probe(device_t dev)
183{
184 const char *name;
185
186 name = ofw_bus_get_name(dev);

--- 53 unchanged lines hidden (view full) ---

240
241 /* Create a parent DMA tag based on this bus. */
242 error = bus_dma_tag_create(
243 bus_get_dma_tag(dev), /* parent */
244 1, 0, /* alignment, boundary */
245 BUS_SPACE_MAXADDR, /* lowaddr */
246 BUS_SPACE_MAXADDR, /* highaddr */
247 NULL, NULL, /* filter, filterarg */
178};
179
180static int
181esp_probe(device_t dev)
182{
183 const char *name;
184
185 name = ofw_bus_get_name(dev);

--- 53 unchanged lines hidden (view full) ---

239
240 /* Create a parent DMA tag based on this bus. */
241 error = bus_dma_tag_create(
242 bus_get_dma_tag(dev), /* parent */
243 1, 0, /* alignment, boundary */
244 BUS_SPACE_MAXADDR, /* lowaddr */
245 BUS_SPACE_MAXADDR, /* highaddr */
246 NULL, NULL, /* filter, filterarg */
248 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
249 0, /* nsegments */
250 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
247 BUS_SPACE_MAXSIZE, /* maxsize */
248 BUS_SPACE_UNRESTRICTED, /* nsegments */
249 BUS_SPACE_MAXSIZE, /* maxsegsize */
251 0, /* flags */
252 NULL, NULL, /* no locking */
253 &lsc->sc_parent_dmat);
254 if (error != 0) {
255 device_printf(dev, "cannot allocate parent DMA tag\n");
256 goto fail_sbus_lres;
257 }
258

--- 28 unchanged lines hidden (view full) ---

287 */
288 if (device_get_children(device_get_parent(dev), &children,
289 &nchildren) != 0) {
290 device_printf(dev, "cannot determine siblings\n");
291 return (ENXIO);
292 }
293 for (i = 0; i < nchildren; i++) {
294 if (device_is_attached(children[i]) &&
250 0, /* flags */
251 NULL, NULL, /* no locking */
252 &lsc->sc_parent_dmat);
253 if (error != 0) {
254 device_printf(dev, "cannot allocate parent DMA tag\n");
255 goto fail_sbus_lres;
256 }
257

--- 28 unchanged lines hidden (view full) ---

286 */
287 if (device_get_children(device_get_parent(dev), &children,
288 &nchildren) != 0) {
289 device_printf(dev, "cannot determine siblings\n");
290 return (ENXIO);
291 }
292 for (i = 0; i < nchildren; i++) {
293 if (device_is_attached(children[i]) &&
295 sbus_get_slot(children[i]) == sbus_get_slot(dev) &&
296 strcmp(ofw_bus_get_name(children[i]), "dma") == 0) {
294 sbus_get_slot(children[i]) ==
295 sbus_get_slot(dev) &&
296 strcmp(ofw_bus_get_name(children[i]),
297 "dma") == 0) {
297 /* XXX hackery */
298 esc->sc_dma = (struct lsi64854_softc *)
299 device_get_softc(children[i]);
300 break;
301 }
302 }
303 free(children, M_TEMP);
304 if (esc->sc_dma == NULL) {

--- 143 unchanged lines hidden (view full) ---

448espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
449{
450 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
451 unsigned int uid = 0;
452 int error, i;
453
454 NCR_LOCK_INIT(sc);
455
298 /* XXX hackery */
299 esc->sc_dma = (struct lsi64854_softc *)
300 device_get_softc(children[i]);
301 break;
302 }
303 }
304 free(children, M_TEMP);
305 if (esc->sc_dma == NULL) {

--- 143 unchanged lines hidden (view full) ---

449espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
450{
451 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
452 unsigned int uid = 0;
453 int error, i;
454
455 NCR_LOCK_INIT(sc);
456
456 /* Attach the DMA engine. */
457 error = lsi64854_attach(esc->sc_dma);
458 if (error != 0) {
459 device_printf(esc->sc_dev, "lsi64854_attach failed\n");
460 goto fail_lock;
461 }
462
463 sc->sc_id = OF_getscsinitid(esc->sc_dev);
464
465#ifdef ESP_SBUS_DEBUG
466 device_printf(esc->sc_dev, "%s: sc_id %d, freq %d\n",
467 __func__, sc->sc_id, sc->sc_freq);
468#endif
469
470 /*

--- 40 unchanged lines hidden (view full) ---

511 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
512 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
513 sc->sc_cfg2 = 0;
514 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
515 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
516 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
517
518 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
457 sc->sc_id = OF_getscsinitid(esc->sc_dev);
458
459#ifdef ESP_SBUS_DEBUG
460 device_printf(esc->sc_dev, "%s: sc_id %d, freq %d\n",
461 __func__, sc->sc_id, sc->sc_freq);
462#endif
463
464 /*

--- 40 unchanged lines hidden (view full) ---

505 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
506 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
507 sc->sc_cfg2 = 0;
508 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
509 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
510 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
511
512 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
519 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
513 (NCRCFG2_SCSI2 | NCRCFG2_RPE))
520 sc->sc_rev = NCR_VARIANT_ESP100;
514 sc->sc_rev = NCR_VARIANT_ESP100;
521 } else {
515 else {
522 sc->sc_cfg2 = NCRCFG2_SCSI2;
523 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
524 sc->sc_cfg3 = 0;
525 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
526 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
527 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
528 if (NCR_READ_REG(sc, NCR_CFG3) !=
516 sc->sc_cfg2 = NCRCFG2_SCSI2;
517 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
518 sc->sc_cfg3 = 0;
519 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
520 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
521 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
522 if (NCR_READ_REG(sc, NCR_CFG3) !=
529 (NCRCFG3_CDB | NCRCFG3_FCLK)) {
523 (NCRCFG3_CDB | NCRCFG3_FCLK))
530 sc->sc_rev = NCR_VARIANT_ESP100A;
524 sc->sc_rev = NCR_VARIANT_ESP100A;
531 } else {
525 else {
532 /* NCRCFG2_FE enables > 64K transfers. */
533 sc->sc_cfg2 |= NCRCFG2_FE;
534 sc->sc_cfg3 = 0;
535 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
536 if (sc->sc_freq <= 25)
537 sc->sc_rev = NCR_VARIANT_ESP200;
538 else {
539 switch ((uid & 0xf8) >> 3) {
540 case 0x00:
541 sc->sc_rev = NCR_VARIANT_FAS100A;
542 break;
543
544 case 0x02:
545 if ((uid & 0x07) == 0x02)
526 /* NCRCFG2_FE enables > 64K transfers. */
527 sc->sc_cfg2 |= NCRCFG2_FE;
528 sc->sc_cfg3 = 0;
529 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
530 if (sc->sc_freq <= 25)
531 sc->sc_rev = NCR_VARIANT_ESP200;
532 else {
533 switch ((uid & 0xf8) >> 3) {
534 case 0x00:
535 sc->sc_rev = NCR_VARIANT_FAS100A;
536 break;
537
538 case 0x02:
539 if ((uid & 0x07) == 0x02)
546 sc->sc_rev = NCR_VARIANT_FAS216;
540 sc->sc_rev =
541 NCR_VARIANT_FAS216;
547 else
542 else
548 sc->sc_rev = NCR_VARIANT_FAS236;
543 sc->sc_rev =
544 NCR_VARIANT_FAS236;
549 break;
550
551 case 0x0a:
552 sc->sc_rev = NCR_VARIANT_FAS366;
553 break;
554
555 default:
556 /*
557 * We could just treat unknown chips
558 * as ESP200 but then we would most
559 * likely drive them out of specs.
560 */
561 device_printf(esc->sc_dev,
562 "Unknown chip\n");
545 break;
546
547 case 0x0a:
548 sc->sc_rev = NCR_VARIANT_FAS366;
549 break;
550
551 default:
552 /*
553 * We could just treat unknown chips
554 * as ESP200 but then we would most
555 * likely drive them out of specs.
556 */
557 device_printf(esc->sc_dev,
558 "Unknown chip\n");
563 goto fail_lsi;
559 error = ENXIO;
560 goto fail_lock;
564 }
565 }
566 }
567 }
568
569#ifdef ESP_SBUS_DEBUG
570 printf("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid);
571#endif
572
573 /*
561 }
562 }
563 }
564 }
565
566#ifdef ESP_SBUS_DEBUG
567 printf("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid);
568#endif
569
570 /*
574 * XXX minsync and maxxfer _should_ be set up in MI code,
575 * XXX but it appears to have some dependency on what sort
576 * XXX of DMA we're hooked up to, etc.
577 */
578
579 /*
580 * This is the value used to start sync negotiations
581 * Note that the NCR register "SYNCTP" is programmed
582 * in "clocks per byte", and has a minimum value of 4.
583 * The SCSI period used in negotiation is one-fourth
584 * of the time (in nanoseconds) needed to transfer one byte.
585 * Since the chip's clock is given in MHz, we have the following
586 * formula: 4 * period = (1000 / freq) * 4
587 */
588 sc->sc_minsync = 1000 / sc->sc_freq;
589
571 * This is the value used to start sync negotiations
572 * Note that the NCR register "SYNCTP" is programmed
573 * in "clocks per byte", and has a minimum value of 4.
574 * The SCSI period used in negotiation is one-fourth
575 * of the time (in nanoseconds) needed to transfer one byte.
576 * Since the chip's clock is given in MHz, we have the following
577 * formula: 4 * period = (1000 / freq) * 4
578 */
579 sc->sc_minsync = 1000 / sc->sc_freq;
580
581 /*
582 * Except for some variants the maximum transfer size is 64k.
583 */
584 sc->sc_maxxfer = 64 * 1024;
590 sc->sc_maxoffset = 15;
591 sc->sc_extended_geom = 1;
592
593 /*
594 * Alas, we must now modify the value a bit, because it's
585 sc->sc_maxoffset = 15;
586 sc->sc_extended_geom = 1;
587
588 /*
589 * Alas, we must now modify the value a bit, because it's
595 * only valid when can switch on FASTCLK and FASTSCSI bits
596 * in config register 3...
590 * only valid when we can switch on FASTCLK and FASTSCSI bits
591 * in the config register 3...
597 */
598 switch (sc->sc_rev) {
599 case NCR_VARIANT_ESP100:
600 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
592 */
593 switch (sc->sc_rev) {
594 case NCR_VARIANT_ESP100:
595 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
601 sc->sc_maxxfer = 64 * 1024;
602 sc->sc_minsync = 0; /* No synch on old chip? */
603 break;
604
605 case NCR_VARIANT_ESP100A:
596 sc->sc_minsync = 0; /* No synch on old chip? */
597 break;
598
599 case NCR_VARIANT_ESP100A:
606 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
607 sc->sc_maxxfer = 64 * 1024;
608 /* Min clocks/byte is 5 */
609 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
610 break;
611
612 case NCR_VARIANT_ESP200:
613 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
600 case NCR_VARIANT_ESP200:
601 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
614 sc->sc_maxxfer = 16 * 1024 * 1024;
615 /* Min clocks/byte is 5 */
616 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
617 break;
618
619 case NCR_VARIANT_FAS100A:
620 case NCR_VARIANT_FAS216:
621 case NCR_VARIANT_FAS236:
622 /*

--- 14 unchanged lines hidden (view full) ---

637 break;
638
639 case NCR_VARIANT_FAS366:
640 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_16_BIT;
641 sc->sc_maxxfer = 16 * 1024 * 1024;
642 break;
643 }
644
602 /* Min clocks/byte is 5 */
603 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
604 break;
605
606 case NCR_VARIANT_FAS100A:
607 case NCR_VARIANT_FAS216:
608 case NCR_VARIANT_FAS236:
609 /*

--- 14 unchanged lines hidden (view full) ---

624 break;
625
626 case NCR_VARIANT_FAS366:
627 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_16_BIT;
628 sc->sc_maxxfer = 16 * 1024 * 1024;
629 break;
630 }
631
632 /*
633 * Given that we allocate resources based on sc->sc_maxxfer it doesn't
634 * make sense to supply a value higher than the maximum actually used.
635 */
636 sc->sc_maxxfer = min(sc->sc_maxxfer, MAXPHYS);
637
638 /* Attach the DMA engine. */
639 error = lsi64854_attach(esc->sc_dma);
640 if (error != 0) {
641 device_printf(esc->sc_dev, "lsi64854_attach failed\n");
642 goto fail_lock;
643 }
644
645 /* Establish interrupt channel. */
646 i = 0;
647 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,
648 &i, RF_SHAREABLE|RF_ACTIVE)) == NULL) {
649 device_printf(esc->sc_dev, "cannot allocate interrupt\n");
650 goto fail_lsi;
651 }
652 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres,

--- 192 unchanged lines hidden --- 		645 /* Establish interrupt channel. */
646 i = 0;
647 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,
648 &i, RF_SHAREABLE|RF_ACTIVE)) == NULL) {
649 device_printf(esc->sc_dev, "cannot allocate interrupt\n");
650 goto fail_lsi;
651 }
652 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres,

--- 192 unchanged lines hidden ---