61#endif
62
63#ifdef NS
64#include <netns/ns.h>
65#include <netns/ns_if.h>
66#endif
67
68#if NBPFILTER > 0
69#include <net/bpf.h>
70#endif
71
72#include <machine/clock.h>
73#include <machine/md_var.h>
74
75#include <i386/isa/isa_device.h>
76#include <i386/isa/icu.h>
77#include <i386/isa/if_edreg.h>
78
79/*
80 * ed_softc: per line info and status
81 */
82struct ed_softc {
83 struct arpcom arpcom; /* ethernet common */
84
85 char *type_str; /* pointer to type string */
86 u_char vendor; /* interface vendor */
87 u_char type; /* interface type code */
88 u_char gone; /* HW missing, presumed having a good time */
89
90 u_short asic_addr; /* ASIC I/O bus address */
91 u_short nic_addr; /* NIC (DS8390) I/O bus address */
92
93/*
94 * The following 'proto' variable is part of a work-around for 8013EBT asics
95 * being write-only. It's sort of a prototype/shadow of the real thing.
96 */
97 u_char wd_laar_proto;
98 u_char cr_proto;
99 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
100 int is790; /* set by the probe code if the card is 790
101 * based */
102
103/*
104 * HP PC LAN PLUS card support.
105 */
106
107 u_short hpp_options; /* flags controlling behaviour of the HP card */
108 u_short hpp_id; /* software revision and other fields */
109 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
110
111 caddr_t mem_start; /* NIC memory start address */
112 caddr_t mem_end; /* NIC memory end address */
113 u_long mem_size; /* total NIC memory size */
114 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
115
116 u_char mem_shared; /* NIC memory is shared with host */
117 u_char xmit_busy; /* transmitter is busy */
118 u_char txb_cnt; /* number of transmit buffers */
119 u_char txb_inuse; /* number of TX buffers currently in-use */
120
121 u_char txb_new; /* pointer to where new buffer will be added */
122 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
123 u_short txb_len[8]; /* buffered xmit buffer lengths */
124 u_char tx_page_start; /* first page of TX buffer area */
125 u_char rec_page_start; /* first page of RX ring-buffer */
126 u_char rec_page_stop; /* last page of RX ring-buffer */
127 u_char next_packet; /* pointer to next unread RX packet */
128 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
129};
130
131static struct ed_softc ed_softc[NED];
132
133static int ed_attach __P((struct ed_softc *, int, int));
134static int ed_attach_isa __P((struct isa_device *));
135
136static void ed_init __P((void *));
137static int ed_ioctl __P((struct ifnet *, int, caddr_t));
138static int ed_probe __P((struct isa_device *));
139static void ed_start __P((struct ifnet *));
140static void ed_reset __P((struct ifnet *));
141static void ed_watchdog __P((struct ifnet *));
142
143static void ed_stop __P((struct ed_softc *));
144static int ed_probe_generic8390 __P((struct ed_softc *));
145static int ed_probe_WD80x3 __P((struct isa_device *));
146static int ed_probe_3Com __P((struct isa_device *));
147static int ed_probe_Novell __P((struct isa_device *));
148static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int));
149static int ed_probe_HP_pclanp __P((struct isa_device *));
150
151#include "pci.h"
152#if NPCI > 0
153void *ed_attach_NE2000_pci __P((int, int));
154#endif
155
156#include "card.h"
157#if NCARD > 0
158static int ed_probe_pccard __P((struct isa_device *, u_char *));
159#endif
160
161static void ds_getmcaf __P((struct ed_softc *, u_long *));
162
163static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int);
164
165static void ed_rint __P((struct ed_softc *));
166static void ed_xmit __P((struct ed_softc *));
167static char * ed_ring_copy __P((struct ed_softc *, char *, char *,
168 /* u_short */ int));
169static void ed_hpp_set_physical_link __P((struct ed_softc *));
170static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
171 /* u_short */ int));
172static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
173 int));
174
175static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
176 /* u_short */ int));
177static void ed_pio_writemem __P((struct ed_softc *, char *,
178 /* u_short */ int, /* u_short */ int));
179static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
180 int));
181void edintr_sc __P((struct ed_softc *));
182
183static void ed_setrcr(struct ed_softc *);
184
185static u_long ds_crc(u_char *ep);
186
187#if NCARD > 0
188#include <sys/kernel.h>
189#include <sys/select.h>
190#include <pccard/cardinfo.h>
191#include <pccard/driver.h>
192#include <pccard/slot.h>
193
194/*
195 * PC-Card (PCMCIA) specific code.
196 */
197static int edinit(struct pccard_devinfo *); /* init device */
198static void edunload(struct pccard_devinfo *); /* Disable driver */
199static int card_intr(struct pccard_devinfo *); /* Interrupt handler */
200
201static struct pccard_device ed_info = {
202 "ed",
203 edinit,
204 edunload,
205 card_intr,
206 0, /* Attributes - presently unused */
207 &net_imask /* Interrupt mask for device */
208 /* XXX - Should this also include net_imask? */
209};
210
211DATA_SET(pccarddrv_set, ed_info);
212
213/*
214 * Initialize the device - called from Slot manager.
215 */
216static int
217edinit(struct pccard_devinfo *devi)
218{
219 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
220
221 /* validate unit number. */
222 if (devi->isahd.id_unit >= NED)
223 return(ENODEV);
224 /*
225 * Probe the device. If a value is returned, the
226 * device was found at the location.
227 */
228 sc->gone = 0;
229 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0)
230 return(ENXIO);
231 if (ed_attach_isa(&devi->isahd) == 0)
232 return(ENXIO);
233
234 return(0);
235}
236
237/*
238 * edunload - unload the driver and clear the table.
239 * XXX TODO:
240 * This is usually called when the card is ejected, but
241 * can be caused by a modunload of a controller driver.
242 * The idea is to reset the driver's view of the device
243 * and ensure that any driver entry points such as
244 * read and write do not hang.
245 */
246static void
247edunload(struct pccard_devinfo *devi)
248{
249 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
250 struct ifnet *ifp = &sc->arpcom.ac_if;
251
252 if (sc->gone) {
253 printf("ed%d: already unloaded\n", devi->isahd.id_unit);
254 return;
255 }
256 ifp->if_flags &= ~IFF_RUNNING;
257 if_down(ifp);
258 sc->gone = 1;
259 printf("ed%d: unload\n", devi->isahd.id_unit);
260}
261
262/*
263 * card_intr - Shared interrupt called from
264 * front end of PC-Card handler.
265 */
266static int
267card_intr(struct pccard_devinfo *devi)
268{
269 edintr_sc(&ed_softc[devi->isahd.id_unit]);
270 return(1);
271}
272#endif /* NCARD > 0 */
273
274struct isa_driver eddriver = {
275 ed_probe,
276 ed_attach_isa,
277 "ed",
278 1 /* We are ultra sensitive */
279};
280
281/*
282 * Interrupt conversion table for WD/SMC ASIC/83C584
283 * (IRQ* are defined in icu.h)
284 */
285static unsigned short ed_intr_mask[] = {
286 IRQ9,
287 IRQ3,
288 IRQ5,
289 IRQ7,
290 IRQ10,
291 IRQ11,
292 IRQ15,
293 IRQ4
294};
295
296/*
297 * Interrupt conversion table for 83C790
298 */
299static unsigned short ed_790_intr_mask[] = {
300 0,
301 IRQ9,
302 IRQ3,
303 IRQ5,
304 IRQ7,
305 IRQ10,
306 IRQ11,
307 IRQ15
308};
309
310/*
311 * Interrupt conversion table for the HP PC LAN+
312 */
313
314static unsigned short ed_hpp_intr_mask[] = {
315 0, /* 0 */
316 0, /* 1 */
317 0, /* 2 */
318 IRQ3, /* 3 */
319 IRQ4, /* 4 */
320 IRQ5, /* 5 */
321 IRQ6, /* 6 */
322 IRQ7, /* 7 */
323 0, /* 8 */
324 IRQ9, /* 9 */
325 IRQ10, /* 10 */
326 IRQ11, /* 11 */
327 IRQ12, /* 12 */
328 0, /* 13 */
329 0, /* 14 */
330 IRQ15 /* 15 */
331};
332
333/*
334 * Determine if the device is present
335 *
336 * on entry:
337 * a pointer to an isa_device struct
338 * on exit:
339 * NULL if device not found
340 * or # of i/o addresses used (if found)
341 */
342static int
343ed_probe(isa_dev)
344 struct isa_device *isa_dev;
345{
346 int nports;
347
348 nports = ed_probe_WD80x3(isa_dev);
349 if (nports)
350 return (nports);
351
352 nports = ed_probe_3Com(isa_dev);
353 if (nports)
354 return (nports);
355
356 nports = ed_probe_Novell(isa_dev);
357 if (nports)
358 return (nports);
359
360 nports = ed_probe_HP_pclanp(isa_dev);
361 if (nports)
362 return (nports);
363
364 return (0);
365}
366
367/*
368 * Generic probe routine for testing for the existance of a DS8390.
369 * Must be called after the NIC has just been reset. This routine
370 * works by looking at certain register values that are guaranteed
371 * to be initialized a certain way after power-up or reset. Seems
372 * not to currently work on the 83C690.
373 *
374 * Specifically:
375 *
376 * Register reset bits set bits
377 * Command Register (CR) TXP, STA RD2, STP
378 * Interrupt Status (ISR) RST
379 * Interrupt Mask (IMR) All bits
380 * Data Control (DCR) LAS
381 * Transmit Config. (TCR) LB1, LB0
382 *
383 * We only look at the CR and ISR registers, however, because looking at
384 * the others would require changing register pages (which would be
385 * intrusive if this isn't an 8390).
386 *
387 * Return 1 if 8390 was found, 0 if not.
388 */
389
390static int
391ed_probe_generic8390(sc)
392 struct ed_softc *sc;
393{
394 if ((inb(sc->nic_addr + ED_P0_CR) &
395 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
396 (ED_CR_RD2 | ED_CR_STP))
397 return (0);
398 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
399 return (0);
400
401 return (1);
402}
403
404/*
405 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
406 */
407static int
408ed_probe_WD80x3(isa_dev)
409 struct isa_device *isa_dev;
410{
411 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
412 int i;
413 u_int memsize, maddr;
414 u_char iptr, isa16bit, sum;
415
416 sc->asic_addr = isa_dev->id_iobase;
417 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
418 sc->is790 = 0;
419
420#ifdef TOSH_ETHER
421 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
422 DELAY(10000);
423#endif
424
425 /*
426 * Attempt to do a checksum over the station address PROM. If it
427 * fails, it's probably not a SMC/WD board. There is a problem with
428 * this, though: some clone WD boards don't pass the checksum test.
429 * Danpex boards for one.
430 */
431 for (sum = 0, i = 0; i < 8; ++i)
432 sum += inb(sc->asic_addr + ED_WD_PROM + i);
433
434 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
435
436 /*
437 * Checksum is invalid. This often happens with cheap WD8003E
438 * clones. In this case, the checksum byte (the eighth byte)
439 * seems to always be zero.
440 */
441 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
442 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
443 return (0);
444 }
445 /* reset card to force it into a known state. */
446#ifdef TOSH_ETHER
447 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
448#else
449 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
450#endif
451 DELAY(100);
452 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
453 /* wait in the case this card is reading it's EEROM */
454 DELAY(5000);
455
456 sc->vendor = ED_VENDOR_WD_SMC;
457 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
458
459 /*
460 * Set initial values for width/size.
461 */
462 memsize = 8192;
463 isa16bit = 0;
464 switch (sc->type) {
465 case ED_TYPE_WD8003S:
466 sc->type_str = "WD8003S";
467 break;
468 case ED_TYPE_WD8003E:
469 sc->type_str = "WD8003E";
470 break;
471 case ED_TYPE_WD8003EB:
472 sc->type_str = "WD8003EB";
473 break;
474 case ED_TYPE_WD8003W:
475 sc->type_str = "WD8003W";
476 break;
477 case ED_TYPE_WD8013EBT:
478 sc->type_str = "WD8013EBT";
479 memsize = 16384;
480 isa16bit = 1;
481 break;
482 case ED_TYPE_WD8013W:
483 sc->type_str = "WD8013W";
484 memsize = 16384;
485 isa16bit = 1;
486 break;
487 case ED_TYPE_WD8013EP: /* also WD8003EP */
488 if (inb(sc->asic_addr + ED_WD_ICR)
489 & ED_WD_ICR_16BIT) {
490 isa16bit = 1;
491 memsize = 16384;
492 sc->type_str = "WD8013EP";
493 } else {
494 sc->type_str = "WD8003EP";
495 }
496 break;
497 case ED_TYPE_WD8013WC:
498 sc->type_str = "WD8013WC";
499 memsize = 16384;
500 isa16bit = 1;
501 break;
502 case ED_TYPE_WD8013EBP:
503 sc->type_str = "WD8013EBP";
504 memsize = 16384;
505 isa16bit = 1;
506 break;
507 case ED_TYPE_WD8013EPC:
508 sc->type_str = "WD8013EPC";
509 memsize = 16384;
510 isa16bit = 1;
511 break;
512 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
513 case ED_TYPE_SMC8216T:
514 if (sc->type == ED_TYPE_SMC8216C) {
515 sc->type_str = "SMC8216/SMC8216C";
516 } else {
517 sc->type_str = "SMC8216T";
518 }
519
520 outb(sc->asic_addr + ED_WD790_HWR,
521 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
522 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
523 case ED_WD790_RAR_SZ64:
524 memsize = 65536;
525 break;
526 case ED_WD790_RAR_SZ32:
527 memsize = 32768;
528 break;
529 case ED_WD790_RAR_SZ16:
530 memsize = 16384;
531 break;
532 case ED_WD790_RAR_SZ8:
533 /* 8216 has 16K shared mem -- 8416 has 8K */
534 if (sc->type == ED_TYPE_SMC8216C) {
535 sc->type_str = "SMC8416C/SMC8416BT";
536 } else {
537 sc->type_str = "SMC8416T";
538 }
539 memsize = 8192;
540 break;
541 }
542 outb(sc->asic_addr + ED_WD790_HWR,
543 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
544
545 isa16bit = 1;
546 sc->is790 = 1;
547 break;
548#ifdef TOSH_ETHER
549 case ED_TYPE_TOSHIBA1:
550 sc->type_str = "Toshiba1";
551 memsize = 32768;
552 isa16bit = 1;
553 break;
554 case ED_TYPE_TOSHIBA4:
555 sc->type_str = "Toshiba4";
556 memsize = 32768;
557 isa16bit = 1;
558 break;
559#endif
560 default:
561 sc->type_str = "";
562 break;
563 }
564
565 /*
566 * Make some adjustments to initial values depending on what is found
567 * in the ICR.
568 */
569 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
570#ifdef TOSH_ETHER
571 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
572#endif
573 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
574 isa16bit = 0;
575 memsize = 8192;
576 }
577
578#if ED_DEBUG
579 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
580 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
581 for (i = 0; i < 8; i++)
582 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
583#endif
584
585 /*
586 * Allow the user to override the autoconfiguration
587 */
588 if (isa_dev->id_msize)
589 memsize = isa_dev->id_msize;
590
591 maddr = (u_int) isa_dev->id_maddr & 0xffffff;
592 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
593 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n",
594 isa_dev->id_unit, maddr, maddr + memsize);
595 return 0;
596 }
597
598 /*
599 * (note that if the user specifies both of the following flags that
600 * '8bit' mode intentionally has precedence)
601 */
602 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
603 isa16bit = 1;
604 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
605 isa16bit = 0;
606
607 /*
608 * If possible, get the assigned interrupt number from the card and
609 * use it.
610 */
611 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
612
613 /*
614 * Assemble together the encoded interrupt number.
615 */
616 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
617 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
618 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
619
620 /*
621 * If no interrupt specified (or "?"), use what the board tells us.
622 */
623 if (isa_dev->id_irq <= 0)
624 isa_dev->id_irq = ed_intr_mask[iptr];
625
626 /*
627 * Enable the interrupt.
628 */
629 outb(isa_dev->id_iobase + ED_WD_IRR,
630 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
631 }
632 if (sc->is790) {
633 outb(isa_dev->id_iobase + ED_WD790_HWR,
634 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
635 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
636 (inb(isa_dev->id_iobase + ED_WD790_GCR) &
637 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
638 outb(isa_dev->id_iobase + ED_WD790_HWR,
639 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
640
641 /*
642 * If no interrupt specified (or "?"), use what the board tells us.
643 */
644 if (isa_dev->id_irq <= 0)
645 isa_dev->id_irq = ed_790_intr_mask[iptr];
646
647 /*
648 * Enable interrupts.
649 */
650 outb(isa_dev->id_iobase + ED_WD790_ICR,
651 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
652 }
653 if (isa_dev->id_irq <= 0) {
654 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n",
655 isa_dev->id_unit, sc->type_str);
656 return (0);
657 }
658 sc->isa16bit = isa16bit;
659 sc->mem_shared = 1;
660 isa_dev->id_msize = memsize;
661 sc->mem_start = (caddr_t) isa_dev->id_maddr;
662
663 /*
664 * allocate one xmit buffer if < 16k, two buffers otherwise
665 */
666 if ((memsize < 16384) ||
667 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
668 sc->txb_cnt = 1;
669 } else {
670 sc->txb_cnt = 2;
671 }
672 sc->tx_page_start = ED_WD_PAGE_OFFSET;
673 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
674 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
675 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
676 sc->mem_size = memsize;
677 sc->mem_end = sc->mem_start + memsize;
678
679 /*
680 * Get station address from on-board ROM
681 */
682 for (i = 0; i < ETHER_ADDR_LEN; ++i)
683 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
684
685 /*
686 * Set upper address bits and 8/16 bit access to shared memory.
687 */
688 if (isa16bit) {
689 if (sc->is790) {
690 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
691 } else {
692 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
693 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
694 }
695 /*
696 * Enable 16bit access
697 */
698 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
699 ED_WD_LAAR_M16EN);
700 } else {
701 if (((sc->type & ED_WD_SOFTCONFIG) ||
702#ifdef TOSH_ETHER
703 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
704#endif
705 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
706 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
707 ED_WD_LAAR_ADDRHI;
708 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
709 }
710 }
711
712 /*
713 * Set address and enable interface shared memory.
714 */
715 if (!sc->is790) {
716#ifdef TOSH_ETHER
717 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
718 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
719 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
720
721#else
722 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
723 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
724#endif
725 sc->cr_proto = ED_CR_RD2;
726 } else {
727 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
728 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
729 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
730 ((kvtop(sc->mem_start) >> 11) & 0x40) |
731 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
732 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
733 sc->cr_proto = 0;
734 }
735
736#if 0
737 printf("starting memory performance test at 0x%x, size %d...\n",
738 sc->mem_start, memsize*16384);
739 for (i = 0; i < 16384; i++)
740 bzero(sc->mem_start, memsize);
741 printf("***DONE***\n");
742#endif
743
744 /*
745 * Now zero memory and verify that it is clear
746 */
747 bzero(sc->mem_start, memsize);
748
749 for (i = 0; i < memsize; ++i) {
750 if (sc->mem_start[i]) {
751 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
752 isa_dev->id_unit, kvtop(sc->mem_start + i));
753
754 /*
755 * Disable 16 bit access to shared memory
756 */
757 if (isa16bit) {
758 if (sc->is790) {
759 outb(sc->asic_addr + ED_WD_MSR, 0x00);
760 }
761 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
762 ~ED_WD_LAAR_M16EN);
763 }
764 return (0);
765 }
766 }
767
768 /*
769 * Disable 16bit access to shared memory - we leave it
770 * disabled so that 1) machines reboot properly when the board
771 * is set 16 bit mode and there are conflicting 8bit
772 * devices/ROMS in the same 128k address space as this boards
773 * shared memory. and 2) so that other 8 bit devices with
774 * shared memory can be used in this 128k region, too.
775 */
776 if (isa16bit) {
777 if (sc->is790) {
778 outb(sc->asic_addr + ED_WD_MSR, 0x00);
779 }
780 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
781 ~ED_WD_LAAR_M16EN);
782 }
783 return (ED_WD_IO_PORTS);
784}
785
786/*
787 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
788 */
789static int
790ed_probe_3Com(isa_dev)
791 struct isa_device *isa_dev;
792{
793 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
794 int i;
795 u_int memsize;
796 u_char isa16bit;
797
798 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
799 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
800
801 /*
802 * Verify that the kernel configured I/O address matches the board
803 * configured address
804 */
805 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
806 case ED_3COM_BCFR_300:
807 if (isa_dev->id_iobase != 0x300)
808 return (0);
809 break;
810 case ED_3COM_BCFR_310:
811 if (isa_dev->id_iobase != 0x310)
812 return (0);
813 break;
814 case ED_3COM_BCFR_330:
815 if (isa_dev->id_iobase != 0x330)
816 return (0);
817 break;
818 case ED_3COM_BCFR_350:
819 if (isa_dev->id_iobase != 0x350)
820 return (0);
821 break;
822 case ED_3COM_BCFR_250:
823 if (isa_dev->id_iobase != 0x250)
824 return (0);
825 break;
826 case ED_3COM_BCFR_280:
827 if (isa_dev->id_iobase != 0x280)
828 return (0);
829 break;
830 case ED_3COM_BCFR_2A0:
831 if (isa_dev->id_iobase != 0x2a0)
832 return (0);
833 break;
834 case ED_3COM_BCFR_2E0:
835 if (isa_dev->id_iobase != 0x2e0)
836 return (0);
837 break;
838 default:
839 return (0);
840 }
841
842 /*
843 * Verify that the kernel shared memory address matches the board
844 * configured address.
845 */
846 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
847 case ED_3COM_PCFR_DC000:
848 if (kvtop(isa_dev->id_maddr) != 0xdc000)
849 return (0);
850 break;
851 case ED_3COM_PCFR_D8000:
852 if (kvtop(isa_dev->id_maddr) != 0xd8000)
853 return (0);
854 break;
855 case ED_3COM_PCFR_CC000:
856 if (kvtop(isa_dev->id_maddr) != 0xcc000)
857 return (0);
858 break;
859 case ED_3COM_PCFR_C8000:
860 if (kvtop(isa_dev->id_maddr) != 0xc8000)
861 return (0);
862 break;
863 default:
864 return (0);
865 }
866
867
868 /*
869 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
870 * sequence because it'll lock up if the cable isn't connected if we
871 * don't.
872 */
873 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
874
875 /*
876 * Wait for a while, then un-reset it
877 */
878 DELAY(50);
879
880 /*
881 * The 3Com ASIC defaults to rather strange settings for the CR after
882 * a reset - it's important to set it again after the following outb
883 * (this is done when we map the PROM below).
884 */
885 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
886
887 /*
888 * Wait a bit for the NIC to recover from the reset
889 */
890 DELAY(5000);
891
892 sc->vendor = ED_VENDOR_3COM;
893 sc->type_str = "3c503";
894 sc->mem_shared = 1;
895 sc->cr_proto = ED_CR_RD2;
896
897 /*
898 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
899 * to it.
900 */
901 memsize = 8192;
902
903 /*
904 * Get station address from on-board ROM
905 */
906
907 /*
908 * First, map ethernet address PROM over the top of where the NIC
909 * registers normally appear.
910 */
911 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
912
913 for (i = 0; i < ETHER_ADDR_LEN; ++i)
914 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
915
916 /*
917 * Unmap PROM - select NIC registers. The proper setting of the
918 * tranceiver is set in ed_init so that the attach code is given a
919 * chance to set the default based on a compile-time config option
920 */
921 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
922
923 /*
924 * Determine if this is an 8bit or 16bit board
925 */
926
927 /*
928 * select page 0 registers
929 */
930 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
931
932 /*
933 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
934 * board.
935 */
936 outb(sc->nic_addr + ED_P0_DCR, 0);
937
938 /*
939 * select page 2 registers
940 */
941 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
942
943 /*
944 * The 3c503 forces the WTS bit to a one if this is a 16bit board
945 */
946 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
947 isa16bit = 1;
948 else
949 isa16bit = 0;
950
951 /*
952 * select page 0 registers
953 */
954 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
955
956 sc->mem_start = (caddr_t) isa_dev->id_maddr;
957 sc->mem_size = memsize;
958 sc->mem_end = sc->mem_start + memsize;
959
960 /*
961 * We have an entire 8k window to put the transmit buffers on the
962 * 16bit boards. But since the 16bit 3c503's shared memory is only
963 * fast enough to overlap the loading of one full-size packet, trying
964 * to load more than 2 buffers can actually leave the transmitter idle
965 * during the load. So 2 seems the best value. (Although a mix of
966 * variable-sized packets might change this assumption. Nonetheless,
967 * we optimize for linear transfers of same-size packets.)
968 */
969 if (isa16bit) {
970 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
971 sc->txb_cnt = 1;
972 else
973 sc->txb_cnt = 2;
974
975 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
976 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
977 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
978 ED_3COM_RX_PAGE_OFFSET_16BIT;
979 sc->mem_ring = sc->mem_start;
980 } else {
981 sc->txb_cnt = 1;
982 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
983 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
984 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
985 ED_3COM_TX_PAGE_OFFSET_8BIT;
986 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
987 }
988
989 sc->isa16bit = isa16bit;
990
991 /*
992 * Initialize GA page start/stop registers. Probably only needed if
993 * doing DMA, but what the hell.
994 */
995 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
996 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
997
998 /*
999 * Set IRQ. 3c503 only allows a choice of irq 2-5.
1000 */
1001 switch (isa_dev->id_irq) {
1002 case IRQ2:
1003 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
1004 break;
1005 case IRQ3:
1006 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
1007 break;
1008 case IRQ4:
1009 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
1010 break;
1011 case IRQ5:
1012 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
1013 break;
1014 default:
1015 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n",
1016 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
1017 return (0);
1018 }
1019
1020 /*
1021 * Initialize GA configuration register. Set bank and enable shared
1022 * mem.
1023 */
1024 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
1025 ED_3COM_GACFR_MBS0);
1026
1027 /*
1028 * Initialize "Vector Pointer" registers. These gawd-awful things are
1029 * compared to 20 bits of the address on ISA, and if they match, the
1030 * shared memory is disabled. We set them to 0xffff0...allegedly the
1031 * reset vector.
1032 */
1033 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
1034 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
1035 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
1036
1037 /*
1038 * Zero memory and verify that it is clear
1039 */
1040 bzero(sc->mem_start, memsize);
1041
1042 for (i = 0; i < memsize; ++i)
1043 if (sc->mem_start[i]) {
1044 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
1045 isa_dev->id_unit, kvtop(sc->mem_start + i));
1046 return (0);
1047 }
1048 isa_dev->id_msize = memsize;
1049 return (ED_3COM_IO_PORTS);
1050}
1051
1052/*
1053 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1054 */
1055static int
1056ed_probe_Novell_generic(sc, port, unit, flags)
1057 struct ed_softc *sc;
1058 int port;
1059 int unit;
1060 int flags;
1061{
1062 u_int memsize, n;
1063 u_char romdata[16], tmp;
1064 static char test_pattern[32] = "THIS is A memory TEST pattern";
1065 char test_buffer[32];
1066
1067 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET;
1068 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
1069
1070 /* XXX - do Novell-specific probe here */
1071
1072 /* Reset the board */
1073#ifdef GWETHER
1074 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
1075 DELAY(200);
1076#endif /* GWETHER */
1077 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
1078
1079 /*
1080 * I don't know if this is necessary; probably cruft leftover from
1081 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1082 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
1083 * non-invasive...but some boards don't seem to reset and I don't have
1084 * complete documentation on what the 'right' thing to do is...so we
1085 * do the invasive thing for now. Yuck.]
1086 */
1087 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
1088 DELAY(5000);
1089
1090 /*
1091 * This is needed because some NE clones apparently don't reset the
1092 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1093 * - this makes the probe invasive! ...Done against my better
1094 * judgement. -DLG
1095 */
1096 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1097
1098 DELAY(5000);
1099
1100 /* Make sure that we really have an 8390 based board */
1101 if (!ed_probe_generic8390(sc))
1102 return (0);
1103
1104 sc->vendor = ED_VENDOR_NOVELL;
1105 sc->mem_shared = 0;
1106 sc->cr_proto = ED_CR_RD2;
1107
1108 /*
1109 * Test the ability to read and write to the NIC memory. This has the
1110 * side affect of determining if this is an NE1000 or an NE2000.
1111 */
1112
1113 /*
1114 * This prevents packets from being stored in the NIC memory when the
1115 * readmem routine turns on the start bit in the CR.
1116 */
1117 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1118
1119 /* Temporarily initialize DCR for byte operations */
1120 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1121
1122 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1123 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1124
1125 sc->isa16bit = 0;
1126
1127 /*
1128 * Write a test pattern in byte mode. If this fails, then there
1129 * probably isn't any memory at 8k - which likely means that the board
1130 * is an NE2000.
1131 */
1132 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1133 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1134
1135 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
1136 /* not an NE1000 - try NE2000 */
1137
1138 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1139 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1140 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1141
1142 sc->isa16bit = 1;
1143
1144 /*
1145 * Write a test pattern in word mode. If this also fails, then
1146 * we don't know what this board is.
1147 */
1148 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1149 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1150
1151 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
1152 return (0); /* not an NE2000 either */
1153
1154 sc->type = ED_TYPE_NE2000;
1155 sc->type_str = "NE2000";
1156 } else {
1157 sc->type = ED_TYPE_NE1000;
1158 sc->type_str = "NE1000";
1159 }
1160
1161 /* 8k of memory plus an additional 8k if 16bit */
1162 memsize = 8192 + sc->isa16bit * 8192;
1163
1164#if 0 /* probably not useful - NE boards only come two ways */
1165 /* allow kernel config file overrides */
1166 if (isa_dev->id_msize)
1167 memsize = isa_dev->id_msize;
1168#endif
1169
1170 sc->mem_size = memsize;
1171
1172 /* NIC memory doesn't start at zero on an NE board */
1173 /* The start address is tied to the bus width */
1174 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1175 sc->mem_end = sc->mem_start + memsize;
1176 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1177
1178#ifdef GWETHER
1179 {
1180 int x, i, mstart = 0, msize = 0;
1181 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1182
1183 for (i = 0; i < ED_PAGE_SIZE; i++)
1184 pbuf0[i] = 0;
1185
1186 /* Clear all the memory. */
1187 for (x = 1; x < 256; x++)
1188 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1189
1190 /* Search for the start of RAM. */
1191 for (x = 1; x < 256; x++) {
1192 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1193 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1194 for (i = 0; i < ED_PAGE_SIZE; i++)
1195 pbuf[i] = 255 - x;
1196 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1197 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1198 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1199 mstart = x * ED_PAGE_SIZE;
1200 msize = ED_PAGE_SIZE;
1201 break;
1202 }
1203 }
1204 }
1205
1206 if (mstart == 0) {
1207 printf("ed%d: Cannot find start of RAM.\n", unit);
1208 return 0;
1209 }
1210 /* Search for the start of RAM. */
1211 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1212 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1213 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1214 for (i = 0; i < ED_PAGE_SIZE; i++)
1215 pbuf[i] = 255 - x;
1216 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1217 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1218 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1219 msize += ED_PAGE_SIZE;
1220 else {
1221 break;
1222 }
1223 } else {
1224 break;
1225 }
1226 }
1227
1228 if (msize == 0) {
1229 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x);
1230 return 0;
1231 }
1232 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
1233
1234 sc->mem_size = msize;
1235 sc->mem_start = (char *) mstart;
1236 sc->mem_end = (char *) (msize + mstart);
1237 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1238 }
1239#endif /* GWETHER */
1240
1241 /*
1242 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1243 * otherwise).
1244 */
1245 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1246 sc->txb_cnt = 1;
1247 else
1248 sc->txb_cnt = 2;
1249
1250 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1251 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1252
1253 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1254
1255 ed_pio_readmem(sc, 0, romdata, 16);
1256 for (n = 0; n < ETHER_ADDR_LEN; n++)
1257 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1258
1259#ifdef GWETHER
1260 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1261 sc->type_str = "Gateway AT";
1262 }
1263#endif /* GWETHER */
1264
1265 /* clear any pending interrupts that might have occurred above */
1266 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1267
1268 return (ED_NOVELL_IO_PORTS);
1269}
1270
1271static int
1272ed_probe_Novell(isa_dev)
1273 struct isa_device *isa_dev;
1274{
1275 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1276
1277 isa_dev->id_maddr = 0;
1278 return ed_probe_Novell_generic(sc, isa_dev->id_iobase,
1279 isa_dev->id_unit, isa_dev->id_flags);
1280}
1281
1282#if NCARD > 0
1283/*
1284 * Probe framework for pccards. Replicates the standard framework,
1285 * minus the pccard driver registration and ignores the ether address
1286 * supplied (from the CIS), relying on the probe to find it instead.
1287 */
1288static int
1289ed_probe_pccard(isa_dev, ether)
1290 struct isa_device *isa_dev;
1291 u_char *ether;
1292{
1293 int nports;
1294
1295 nports = ed_probe_WD80x3(isa_dev);
1296 if (nports)
1297 return (nports);
1298
1299 nports = ed_probe_Novell(isa_dev);
1300 if (nports)
1301 return (nports);
1302
1303 return (0);
1304}
1305
1306#endif /* NCARD > 0 */
1307
1308#define ED_HPP_TEST_SIZE 16
1309
1310/*
1311 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1312 * (HP Part nos: 27247B and 27252A).
1313 *
1314 * The card has an asic wrapper around a DS8390 core. The asic handles
1315 * host accesses and offers both standard register IO and memory mapped
1316 * IO. Memory mapped I/O allows better performance at the expense of greater
1317 * chance of an incompatibility with existing ISA cards.
1318 *
1319 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1320 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1321 * don't allow 32 bit accesses; these are indicated by a bit in the software
1322 * ID register (see if_edreg.h).
1323 *
1324 * Other caveats are: we should read the MAC address only when the card
1325 * is inactive.
1326 *
1327 * For more information; please consult the CRYNWR packet driver.
1328 *
1329 * The AUI port is turned on using the "link2" option on the ifconfig
1330 * command line.
1331 */
1332static int
1333ed_probe_HP_pclanp(isa_dev)
1334 struct isa_device *isa_dev;
1335{
1336 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1337 int n; /* temp var */
1338 int memsize; /* mem on board */
1339 u_char checksum; /* checksum of board address */
1340 u_char irq; /* board configured IRQ */
1341 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1342 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1343
1344
1345 /* Fill in basic information */
1346 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET;
1347 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
1348 sc->is790 = 0;
1349 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1350
1351 /*
1352 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1353 */
1354
1355 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1356 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1357 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1358 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1359 return 0;
1360
1361 /*
1362 * Read the MAC address and verify checksum on the address.
1363 */
1364
1365 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1366 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1367 checksum += (sc->arpcom.ac_enaddr[n] =
1368 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1369
1370 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1371
1372 if (checksum != 0xFF)
1373 return 0;
1374
1375 /*
1376 * Verify that the software model number is 0.
1377 */
1378
1379 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1380 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1381 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1382 return 0;
1383
1384 /*
1385 * Read in and save the current options configured on card.
1386 */
1387
1388 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1389
1390 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1391 ED_HPP_OPTION_CHIP_RESET |
1392 ED_HPP_OPTION_ENABLE_IRQ);
1393
1394 /*
1395 * Reset the chip. This requires writing to the option register
1396 * so take care to preserve the other bits.
1397 */
1398
1399 outw(sc->asic_addr + ED_HPP_OPTION,
1400 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1401 ED_HPP_OPTION_CHIP_RESET)));
1402
1403 DELAY(5000); /* wait for chip reset to complete */
1404
1405 outw(sc->asic_addr + ED_HPP_OPTION,
1406 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1407 ED_HPP_OPTION_CHIP_RESET |
1408 ED_HPP_OPTION_ENABLE_IRQ)));
1409
1410 DELAY(5000);
1411
1412 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1413 return 0; /* reset did not complete */
1414
1415 /*
1416 * Read out configuration information.
1417 */
1418
1419 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1420
1421 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1422
1423 /*
1424 * Check for impossible IRQ.
1425 */
1426
1427 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
1428 return 0;
1429
1430 /*
1431 * If the kernel IRQ was specified with a '?' use the cards idea
1432 * of the IRQ. If the kernel IRQ was explicitly specified, it
1433 * should match that of the hardware.
1434 */
1435
1436 if (isa_dev->id_irq <= 0)
1437 isa_dev->id_irq = ed_hpp_intr_mask[irq];
1438 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq])
1439 return 0;
1440
1441 /*
1442 * Fill in softconfig info.
1443 */
1444
1445 sc->vendor = ED_VENDOR_HP;
1446 sc->type = ED_TYPE_HP_PCLANPLUS;
1447 sc->type_str = "HP-PCLAN+";
1448
1449 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1450 sc->mem_start = 0; /* we use offsets inside the card RAM */
1451
1452 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1453
1454 /*
1455 * Check if memory mapping of the I/O registers possible.
1456 */
1457
1458 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1459 {
1460 u_long mem_addr;
1461
1462 /*
1463 * determine the memory address from the board.
1464 */
1465
1466 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1467 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1468
1469 /*
1470 * Check that the kernel specified start of memory and
1471 * hardware's idea of it match.
1472 */
1473
1474 if (mem_addr != kvtop(isa_dev->id_maddr))
1475 return 0;
1476
1477 sc->hpp_mem_start = isa_dev->id_maddr;
1478 }
1479
1480 /*
1481 * The board has 32KB of memory. Is there a way to determine
1482 * this programmatically?
1483 */
1484
1485 memsize = 32768;
1486
1487 /*
1488 * Fill in the rest of the soft config structure.
1489 */
1490
1491 /*
1492 * The transmit page index.
1493 */
1494
1495 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1496
1497 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1498 sc->txb_cnt = 1;
1499 else
1500 sc->txb_cnt = 2;
1501
1502 /*
1503 * Memory description
1504 */
1505
1506 sc->mem_size = memsize;
1507 sc->mem_ring = sc->mem_start +
1508 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1509 sc->mem_end = sc->mem_start + sc->mem_size;
1510
1511 /*
1512 * Receive area starts after the transmit area and
1513 * continues till the end of memory.
1514 */
1515
1516 sc->rec_page_start = sc->tx_page_start +
1517 (sc->txb_cnt * ED_TXBUF_SIZE);
1518 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1519
1520
1521 sc->cr_proto = 0; /* value works */
1522
1523 /*
1524 * Set the wrap registers for string I/O reads.
1525 */
1526
1527 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1528 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1529 ((sc->rec_page_start / ED_PAGE_SIZE) |
1530 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1531
1532 /*
1533 * Reset the register page to normal operation.
1534 */
1535
1536 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1537
1538 /*
1539 * Verify that we can read/write from adapter memory.
1540 * Create test pattern.
1541 */
1542
1543 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1544 {
1545 test_pattern[n] = (n*n) ^ ~n;
1546 }
1547
1548#undef ED_HPP_TEST_SIZE
1549
1550 /*
1551 * Check that the memory is accessible thru the I/O ports.
1552 * Write out the contents of "test_pattern", read back
1553 * into "test_buffer" and compare the two for any
1554 * mismatch.
1555 */
1556
1557 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1558
1559 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1560 sizeof(test_pattern));
1561 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1562 test_buffer, sizeof(test_pattern));
1563
1564 if (bcmp(test_pattern, test_buffer,
1565 sizeof(test_pattern)))
1566 return 0;
1567 }
1568
1569 return (ED_HPP_IO_PORTS);
1570
1571}
1572
1573/*
1574 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1575 */
1576
1577void
1578ed_hpp_set_physical_link(struct ed_softc *sc)
1579{
1580 struct ifnet *ifp = &sc->arpcom.ac_if;
1581 int lan_page;
1582
1583 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1584 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1585
1586 if (ifp->if_flags & IFF_ALTPHYS) {
1587
1588 /*
1589 * Use the AUI port.
1590 */
1591
1592 lan_page |= ED_HPP_LAN_AUI;
1593
1594 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1595 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1596
1597
1598 } else {
1599
1600 /*
1601 * Use the ThinLan interface
1602 */
1603
1604 lan_page &= ~ED_HPP_LAN_AUI;
1605
1606 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1607 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1608
1609 }
1610
1611 /*
1612 * Wait for the lan card to re-initialize itself
1613 */
1614
1615 DELAY(150000); /* wait 150 ms */
1616
1617 /*
1618 * Restore normal pages.
1619 */
1620
1621 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1622
1623}
1624
1625
1626/*
1627 * Install interface into kernel networking data structures
1628 */
1629static int
1630ed_attach(sc, unit, flags)
1631 struct ed_softc *sc;
1632 int unit;
1633 int flags;
1634{
1635 struct ifnet *ifp = &sc->arpcom.ac_if;
1636
1637 /*
1638 * Set interface to stopped condition (reset)
1639 */
1640 ed_stop(sc);
1641
1642 if (!ifp->if_name) {
1643 /*
1644 * Initialize ifnet structure
1645 */
1646 ifp->if_softc = sc;
1647 ifp->if_unit = unit;
1648 ifp->if_name = "ed";
1649 ifp->if_output = ether_output;
1650 ifp->if_start = ed_start;
1651 ifp->if_ioctl = ed_ioctl;
1652 ifp->if_watchdog = ed_watchdog;
1653 ifp->if_init = ed_init;
1654 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1655 ifp->if_linkmib = &sc->mibdata;
1656 ifp->if_linkmiblen = sizeof sc->mibdata;
1657 /*
1658 * XXX - should do a better job.
1659 */
1660 if (sc->is790)
1661 sc->mibdata.dot3StatsEtherChipSet =
1662 DOT3CHIPSET(dot3VendorWesternDigital,
1663 dot3ChipSetWesternDigital83C790);
1664 else
1665 sc->mibdata.dot3StatsEtherChipSet =
1666 DOT3CHIPSET(dot3VendorNational,
1667 dot3ChipSetNational8390);
1668 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1669
1670 /*
1671 * Set default state for ALTPHYS flag (used to disable the
1672 * tranceiver for AUI operation), based on compile-time
1673 * config option.
1674 */
1675 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1676 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1677 IFF_MULTICAST | IFF_ALTPHYS);
1678 else
1679 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1680 IFF_MULTICAST);
1681
1682 /*
1683 * Attach the interface
1684 */
1685 if_attach(ifp);
1686 ether_ifattach(ifp);
1687 }
1688 /* device attach does transition from UNCONFIGURED to IDLE state */
1689
1690 /*
1691 * Print additional info when attached
1692 */
1693 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1694 sc->arpcom.ac_enaddr, ":");
1695
1696 if (sc->type_str && (*sc->type_str != 0))
1697 printf("type %s ", sc->type_str);
1698 else
1699 printf("type unknown (0x%x) ", sc->type);
1700
1701 if (sc->vendor == ED_VENDOR_HP)
1702 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1703 "16-bit" : "32-bit",
1704 sc->hpp_mem_start ? "memory mapped" : "regular");
1705 else
1706 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1707
1708 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1709 (sc->vendor == ED_VENDOR_HP)) &&
1710 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1711
1712 /*
1713 * If BPF is in the kernel, call the attach for it
1714 */
1715#if NBPFILTER > 0
1716 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1717#endif
1718 return 1;
1719}
1720
1721static int
1722ed_attach_isa(isa_dev)
1723 struct isa_device *isa_dev;
1724{
1725 int unit = isa_dev->id_unit;
1726 struct ed_softc *sc = &ed_softc[unit];
1727 int flags = isa_dev->id_flags;
1728
1729 return ed_attach(sc, unit, flags);
1730}
1731
1732#if NPCI > 0
1733void *
1734ed_attach_NE2000_pci(unit, port)
1735 int unit;
1736 int port;
1737{
1738 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT);
1739 int isa_flags = 0;
1740
1741 if (!sc)
1742 return sc;
1743
1744 bzero(sc, sizeof *sc);
1745 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0
1746 || ed_attach(sc, unit, isa_flags) == 0) {
1747 free(sc, M_DEVBUF);
1748 return NULL;
1749 }
1750 return sc;
1751}
1752#endif
1753
1754/*
1755 * Reset interface.
1756 */
1757static void
1758ed_reset(ifp)
1759 struct ifnet *ifp;
1760{
1761 struct ed_softc *sc = ifp->if_softc;
1762 int s;
1763
1764 if (sc->gone)
1765 return;
1766 s = splimp();
1767
1768 /*
1769 * Stop interface and re-initialize.
1770 */
1771 ed_stop(sc);
1772 ed_init(sc);
1773
1774 (void) splx(s);
1775}
1776
1777/*
1778 * Take interface offline.
1779 */
1780static void
1781ed_stop(sc)
1782 struct ed_softc *sc;
1783{
1784 int n = 5000;
1785
1786 if (sc->gone)
1787 return;
1788 /*
1789 * Stop everything on the interface, and select page 0 registers.
1790 */
1791 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1792
1793 /*
1794 * Wait for interface to enter stopped state, but limit # of checks to
1795 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1796 * just in case it's an old one.
1797 */
1798 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1799}
1800
1801/*
1802 * Device timeout/watchdog routine. Entered if the device neglects to
1803 * generate an interrupt after a transmit has been started on it.
1804 */
1805static void
1806ed_watchdog(ifp)
1807 struct ifnet *ifp;
1808{
1809 struct ed_softc *sc = ifp->if_softc;
1810
1811 if (sc->gone)
1812 return;
1813 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1814 ifp->if_oerrors++;
1815
1816 ed_reset(ifp);
1817}
1818
1819/*
1820 * Initialize device.
1821 */
1822static void
1823ed_init(xsc)
1824 void *xsc;
1825{
1826 struct ed_softc *sc = xsc;
1827 struct ifnet *ifp = &sc->arpcom.ac_if;
1828 int i, s;
1829
1830 if (sc->gone)
1831 return;
1832
1833 /* address not known */
1834 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1835 return;
1836
1837 /*
1838 * Initialize the NIC in the exact order outlined in the NS manual.
1839 * This init procedure is "mandatory"...don't change what or when
1840 * things happen.
1841 */
1842 s = splimp();
1843
1844 /* reset transmitter flags */
1845 sc->xmit_busy = 0;
1846 ifp->if_timer = 0;
1847
1848 sc->txb_inuse = 0;
1849 sc->txb_new = 0;
1850 sc->txb_next_tx = 0;
1851
1852 /* This variable is used below - don't move this assignment */
1853 sc->next_packet = sc->rec_page_start + 1;
1854
1855 /*
1856 * Set interface for page 0, Remote DMA complete, Stopped
1857 */
1858 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1859
1860 if (sc->isa16bit) {
1861
1862 /*
1863 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1864 * order=80x86, word-wide DMA xfers,
1865 */
1866 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1867 } else {
1868
1869 /*
1870 * Same as above, but byte-wide DMA xfers
1871 */
1872 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1873 }
1874
1875 /*
1876 * Clear Remote Byte Count Registers
1877 */
1878 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1879 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1880
1881 /*
1882 * For the moment, don't store incoming packets in memory.
1883 */
1884 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1885
1886 /*
1887 * Place NIC in internal loopback mode
1888 */
1889 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1890
1891 /*
1892 * Initialize transmit/receive (ring-buffer) Page Start
1893 */
1894 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1895 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1896 /* Set lower bits of byte addressable framing to 0 */
1897 if (sc->is790)
1898 outb(sc->nic_addr + 0x09, 0);
1899
1900 /*
1901 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1902 */
1903 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1904 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1905
1906 /*
1907 * Clear all interrupts. A '1' in each bit position clears the
1908 * corresponding flag.
1909 */
1910 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1911
1912 /*
1913 * Enable the following interrupts: receive/transmit complete,
1914 * receive/transmit error, and Receiver OverWrite.
1915 *
1916 * Counter overflow and Remote DMA complete are *not* enabled.
1917 */
1918 outb(sc->nic_addr + ED_P0_IMR,
1919 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1920
1921 /*
1922 * Program Command Register for page 1
1923 */
1924 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1925
1926 /*
1927 * Copy out our station address
1928 */
1929 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1930 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1931
1932 /*
1933 * Set Current Page pointer to next_packet (initialized above)
1934 */
1935 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1936
1937 /*
1938 * Program Receiver Configuration Register and multicast filter. CR is
1939 * set to page 0 on return.
1940 */
1941 ed_setrcr(sc);
1942
1943 /*
1944 * Take interface out of loopback
1945 */
1946 outb(sc->nic_addr + ED_P0_TCR, 0);
1947
1948 /*
1949 * If this is a 3Com board, the tranceiver must be software enabled
1950 * (there is no settable hardware default).
1951 */
1952 if (sc->vendor == ED_VENDOR_3COM) {
1953 if (ifp->if_flags & IFF_ALTPHYS) {
1954 outb(sc->asic_addr + ED_3COM_CR, 0);
1955 } else {
1956 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1957 }
1958 }
1959
1960 /*
1961 * Set 'running' flag, and clear output active flag.
1962 */
1963 ifp->if_flags |= IFF_RUNNING;
1964 ifp->if_flags &= ~IFF_OACTIVE;
1965
1966 /*
1967 * ...and attempt to start output
1968 */
1969 ed_start(ifp);
1970
1971 (void) splx(s);
1972}
1973
1974/*
1975 * This routine actually starts the transmission on the interface
1976 */
1977static inline void
1978ed_xmit(sc)
1979 struct ed_softc *sc;
1980{
1981 struct ifnet *ifp = (struct ifnet *)sc;
1982 unsigned short len;
1983
1984 if (sc->gone)
1985 return;
1986 len = sc->txb_len[sc->txb_next_tx];
1987
1988 /*
1989 * Set NIC for page 0 register access
1990 */
1991 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
1992
1993 /*
1994 * Set TX buffer start page
1995 */
1996 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1997 sc->txb_next_tx * ED_TXBUF_SIZE);
1998
1999 /*
2000 * Set TX length
2001 */
2002 outb(sc->nic_addr + ED_P0_TBCR0, len);
2003 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
2004
2005 /*
2006 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2007 */
2008 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2009 sc->xmit_busy = 1;
2010
2011 /*
2012 * Point to next transmit buffer slot and wrap if necessary.
2013 */
2014 sc->txb_next_tx++;
2015 if (sc->txb_next_tx == sc->txb_cnt)
2016 sc->txb_next_tx = 0;
2017
2018 /*
2019 * Set a timer just in case we never hear from the board again
2020 */
2021 ifp->if_timer = 2;
2022}
2023
2024/*
2025 * Start output on interface.
2026 * We make two assumptions here:
2027 * 1) that the current priority is set to splimp _before_ this code
2028 * is called *and* is returned to the appropriate priority after
2029 * return
2030 * 2) that the IFF_OACTIVE flag is checked before this code is called
2031 * (i.e. that the output part of the interface is idle)
2032 */
2033static void
2034ed_start(ifp)
2035 struct ifnet *ifp;
2036{
2037 struct ed_softc *sc = ifp->if_softc;
2038 struct mbuf *m0, *m;
2039 caddr_t buffer;
2040 int len;
2041
2042 if (sc->gone) {
2043 printf("ed_start(%p) GONE\n",ifp);
2044 return;
2045 }
2046outloop:
2047
2048 /*
2049 * First, see if there are buffered packets and an idle transmitter -
2050 * should never happen at this point.
2051 */
2052 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2053 printf("ed: packets buffered, but transmitter idle\n");
2054 ed_xmit(sc);
2055 }
2056
2057 /*
2058 * See if there is room to put another packet in the buffer.
2059 */
2060 if (sc->txb_inuse == sc->txb_cnt) {
2061
2062 /*
2063 * No room. Indicate this to the outside world and exit.
2064 */
2065 ifp->if_flags |= IFF_OACTIVE;
2066 return;
2067 }
2068 IF_DEQUEUE(&ifp->if_snd, m);
2069 if (m == 0) {
2070
2071 /*
2072 * We are using the !OACTIVE flag to indicate to the outside
2073 * world that we can accept an additional packet rather than
2074 * that the transmitter is _actually_ active. Indeed, the
2075 * transmitter may be active, but if we haven't filled all the
2076 * buffers with data then we still want to accept more.
2077 */
2078 ifp->if_flags &= ~IFF_OACTIVE;
2079 return;
2080 }
2081
2082 /*
2083 * Copy the mbuf chain into the transmit buffer
2084 */
2085
2086 m0 = m;
2087
2088 /* txb_new points to next open buffer slot */
2089 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2090
2091 if (sc->mem_shared) {
2092
2093 /*
2094 * Special case setup for 16 bit boards...
2095 */
2096 if (sc->isa16bit) {
2097 switch (sc->vendor) {
2098
2099 /*
2100 * For 16bit 3Com boards (which have 16k of
2101 * memory), we have the xmit buffers in a
2102 * different page of memory ('page 0') - so
2103 * change pages.
2104 */
2105 case ED_VENDOR_3COM:
2106 outb(sc->asic_addr + ED_3COM_GACFR,
2107 ED_3COM_GACFR_RSEL);
2108 break;
2109
2110 /*
2111 * Enable 16bit access to shared memory on
2112 * WD/SMC boards.
2113 */
2114 case ED_VENDOR_WD_SMC:{
2115 outb(sc->asic_addr + ED_WD_LAAR,
2116 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2117 if (sc->is790) {
2118 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2119 }
2120 break;
2121 }
2122 }
2123 }
2124 for (len = 0; m != 0; m = m->m_next) {
2125 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2126 buffer += m->m_len;
2127 len += m->m_len;
2128 }
2129
2130 /*
2131 * Restore previous shared memory access
2132 */
2133 if (sc->isa16bit) {
2134 switch (sc->vendor) {
2135 case ED_VENDOR_3COM:
2136 outb(sc->asic_addr + ED_3COM_GACFR,
2137 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2138 break;
2139 case ED_VENDOR_WD_SMC:{
2140 if (sc->is790) {
2141 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2142 }
2143 outb(sc->asic_addr + ED_WD_LAAR,
2144 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2145 break;
2146 }
2147 }
2148 }
2149 } else {
2150 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2151 if (len == 0)
2152 goto outloop;
2153 }
2154
2155 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2156
2157 sc->txb_inuse++;
2158
2159 /*
2160 * Point to next buffer slot and wrap if necessary.
2161 */
2162 sc->txb_new++;
2163 if (sc->txb_new == sc->txb_cnt)
2164 sc->txb_new = 0;
2165
2166 if (sc->xmit_busy == 0)
2167 ed_xmit(sc);
2168
2169 /*
2170 * Tap off here if there is a bpf listener.
2171 */
2172#if NBPFILTER > 0
2173 if (ifp->if_bpf) {
2174 bpf_mtap(ifp, m0);
2175 }
2176#endif
2177
2178 m_freem(m0);
2179
2180 /*
2181 * Loop back to the top to possibly buffer more packets
2182 */
2183 goto outloop;
2184}
2185
2186/*
2187 * Ethernet interface receiver interrupt.
2188 */
2189static inline void
2190ed_rint(sc)
2191 struct ed_softc *sc;
2192{
2193 struct ifnet *ifp = &sc->arpcom.ac_if;
2194 u_char boundry;
2195 u_short len;
2196 struct ed_ring packet_hdr;
2197 char *packet_ptr;
2198
2199 if (sc->gone)
2200 return;
2201
2202 /*
2203 * Set NIC to page 1 registers to get 'current' pointer
2204 */
2205 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2206
2207 /*
2208 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2209 * i.e. it points to where new data has been buffered. The 'CURR'
2210 * (current) register points to the logical end of the ring-buffer -
2211 * i.e. it points to where additional new data will be added. We loop
2212 * here until the logical beginning equals the logical end (or in
2213 * other words, until the ring-buffer is empty).
2214 */
2215 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2216
2217 /* get pointer to this buffer's header structure */
2218 packet_ptr = sc->mem_ring +
2219 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2220
2221 /*
2222 * The byte count includes a 4 byte header that was added by
2223 * the NIC.
2224 */
2225 if (sc->mem_shared)
2226 packet_hdr = *(struct ed_ring *) packet_ptr;
2227 else
2228 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2229 sizeof(packet_hdr));
2230 len = packet_hdr.count;
2231 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2232 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2233 /*
2234 * Length is a wild value. There's a good chance that
2235 * this was caused by the NIC being old and buggy.
2236 * The bug is that the length low byte is duplicated in
2237 * the high byte. Try to recalculate the length based on
2238 * the pointer to the next packet.
2239 */
2240 /*
2241 * NOTE: sc->next_packet is pointing at the current packet.
2242 */
2243 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2244 if (packet_hdr.next_packet >= sc->next_packet) {
2245 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2246 } else {
2247 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2248 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2249 }
2250 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2251 + sizeof(struct ed_ring)))
2252 sc->mibdata.dot3StatsFrameTooLongs++;
2253 }
2254 /*
2255 * Be fairly liberal about what we allow as a "reasonable" length
2256 * so that a [crufty] packet will make it to BPF (and can thus
2257 * be analyzed). Note that all that is really important is that
2258 * we have a length that will fit into one mbuf cluster or less;
2259 * the upper layer protocols can then figure out the length from
2260 * their own length field(s).
2261 */
2262 if ((len > sizeof(struct ed_ring)) &&
2263 (len <= MCLBYTES) &&
2264 (packet_hdr.next_packet >= sc->rec_page_start) &&
2265 (packet_hdr.next_packet < sc->rec_page_stop)) {
2266 /*
2267 * Go get packet.
2268 */
2269 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2270 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY);
2271 ifp->if_ipackets++;
2272 } else {
2273 /*
2274 * Really BAD. The ring pointers are corrupted.
2275 */
2276 log(LOG_ERR,
2277 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2278 ifp->if_unit, len);
2279 ifp->if_ierrors++;
2280 ed_reset(ifp);
2281 return;
2282 }
2283
2284 /*
2285 * Update next packet pointer
2286 */
2287 sc->next_packet = packet_hdr.next_packet;
2288
2289 /*
2290 * Update NIC boundry pointer - being careful to keep it one
2291 * buffer behind. (as recommended by NS databook)
2292 */
2293 boundry = sc->next_packet - 1;
2294 if (boundry < sc->rec_page_start)
2295 boundry = sc->rec_page_stop - 1;
2296
2297 /*
2298 * Set NIC to page 0 registers to update boundry register
2299 */
2300 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2301
2302 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2303
2304 /*
2305 * Set NIC to page 1 registers before looping to top (prepare
2306 * to get 'CURR' current pointer)
2307 */
2308 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2309 }
2310}
2311
2312/*
2313 * Ethernet interface interrupt processor
2314 */
2315void
2316edintr_sc(sc)
2317 struct ed_softc *sc;
2318{
2319 struct ifnet *ifp = (struct ifnet *)sc;
2320 u_char isr;
2321
2322 if (sc->gone)
2323 return;
2324 /*
2325 * Set NIC to page 0 registers
2326 */
2327 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2328
2329 /*
2330 * loop until there are no more new interrupts
2331 */
2332 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2333
2334 /*
2335 * reset all the bits that we are 'acknowledging' by writing a
2336 * '1' to each bit position that was set (writing a '1'
2337 * *clears* the bit)
2338 */
2339 outb(sc->nic_addr + ED_P0_ISR, isr);
2340
2341 /*
2342 * Handle transmitter interrupts. Handle these first because
2343 * the receiver will reset the board under some conditions.
2344 */
2345 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2346 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2347
2348 /*
2349 * Check for transmit error. If a TX completed with an
2350 * error, we end up throwing the packet away. Really
2351 * the only error that is possible is excessive
2352 * collisions, and in this case it is best to allow
2353 * the automatic mechanisms of TCP to backoff the
2354 * flow. Of course, with UDP we're screwed, but this
2355 * is expected when a network is heavily loaded.
2356 */
2357 (void) inb(sc->nic_addr + ED_P0_TSR);
2358 if (isr & ED_ISR_TXE) {
2359 u_char tsr;
2360
2361 /*
2362 * Excessive collisions (16)
2363 */
2364 tsr = inb(sc->nic_addr + ED_P0_TSR);
2365 if ((tsr & ED_TSR_ABT)
2366 && (collisions == 0)) {
2367
2368 /*
2369 * When collisions total 16, the
2370 * P0_NCR will indicate 0, and the
2371 * TSR_ABT is set.
2372 */
2373 collisions = 16;
2374 sc->mibdata.dot3StatsExcessiveCollisions++;
2375 sc->mibdata.dot3StatsCollFrequencies[15]++;
2376 }
2377 if (tsr & ED_TSR_OWC)
2378 sc->mibdata.dot3StatsLateCollisions++;
2379 if (tsr & ED_TSR_CDH)
2380 sc->mibdata.dot3StatsSQETestErrors++;
2381 if (tsr & ED_TSR_CRS)
2382 sc->mibdata.dot3StatsCarrierSenseErrors++;
2383 if (tsr & ED_TSR_FU)
2384 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2385
2386 /*
2387 * update output errors counter
2388 */
2389 ifp->if_oerrors++;
2390 } else {
2391
2392 /*
2393 * Update total number of successfully
2394 * transmitted packets.
2395 */
2396 ifp->if_opackets++;
2397 }
2398
2399 /*
2400 * reset tx busy and output active flags
2401 */
2402 sc->xmit_busy = 0;
2403 ifp->if_flags &= ~IFF_OACTIVE;
2404
2405 /*
2406 * clear watchdog timer
2407 */
2408 ifp->if_timer = 0;
2409
2410 /*
2411 * Add in total number of collisions on last
2412 * transmission.
2413 */
2414 ifp->if_collisions += collisions;
2415 switch(collisions) {
2416 case 0:
2417 case 16:
2418 break;
2419 case 1:
2420 sc->mibdata.dot3StatsSingleCollisionFrames++;
2421 sc->mibdata.dot3StatsCollFrequencies[0]++;
2422 break;
2423 default:
2424 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2425 sc->mibdata.
2426 dot3StatsCollFrequencies[collisions-1]
2427 ++;
2428 break;
2429 }
2430
2431 /*
2432 * Decrement buffer in-use count if not zero (can only
2433 * be zero if a transmitter interrupt occured while
2434 * not actually transmitting). If data is ready to
2435 * transmit, start it transmitting, otherwise defer
2436 * until after handling receiver
2437 */
2438 if (sc->txb_inuse && --sc->txb_inuse)
2439 ed_xmit(sc);
2440 }
2441
2442 /*
2443 * Handle receiver interrupts
2444 */
2445 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2446
2447 /*
2448 * Overwrite warning. In order to make sure that a
2449 * lockup of the local DMA hasn't occurred, we reset
2450 * and re-init the NIC. The NSC manual suggests only a
2451 * partial reset/re-init is necessary - but some chips
2452 * seem to want more. The DMA lockup has been seen
2453 * only with early rev chips - Methinks this bug was
2454 * fixed in later revs. -DG
2455 */
2456 if (isr & ED_ISR_OVW) {
2457 ifp->if_ierrors++;
2458#ifdef DIAGNOSTIC
2459 log(LOG_WARNING,
2460 "ed%d: warning - receiver ring buffer overrun\n",
2461 ifp->if_unit);
2462#endif
2463
2464 /*
2465 * Stop/reset/re-init NIC
2466 */
2467 ed_reset(ifp);
2468 } else {
2469
2470 /*
2471 * Receiver Error. One or more of: CRC error,
2472 * frame alignment error FIFO overrun, or
2473 * missed packet.
2474 */
2475 if (isr & ED_ISR_RXE) {
2476 u_char rsr;
2477 rsr = inb(sc->nic_addr + ED_P0_RSR);
2478 if (rsr & ED_RSR_CRC)
2479 sc->mibdata.dot3StatsFCSErrors++;
2480 if (rsr & ED_RSR_FAE)
2481 sc->mibdata.dot3StatsAlignmentErrors++;
2482 if (rsr & ED_RSR_FO)
2483 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2484 ifp->if_ierrors++;
2485#ifdef ED_DEBUG
2486 printf("ed%d: receive error %x\n", ifp->if_unit,
2487 inb(sc->nic_addr + ED_P0_RSR));
2488#endif
2489 }
2490
2491 /*
2492 * Go get the packet(s) XXX - Doing this on an
2493 * error is dubious because there shouldn't be
2494 * any data to get (we've configured the
2495 * interface to not accept packets with
2496 * errors).
2497 */
2498
2499 /*
2500 * Enable 16bit access to shared memory first
2501 * on WD/SMC boards.
2502 */
2503 if (sc->isa16bit &&
2504 (sc->vendor == ED_VENDOR_WD_SMC)) {
2505
2506 outb(sc->asic_addr + ED_WD_LAAR,
2507 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2508 if (sc->is790) {
2509 outb(sc->asic_addr + ED_WD_MSR,
2510 ED_WD_MSR_MENB);
2511 }
2512 }
2513 ed_rint(sc);
2514
2515 /* disable 16bit access */
2516 if (sc->isa16bit &&
2517 (sc->vendor == ED_VENDOR_WD_SMC)) {
2518
2519 if (sc->is790) {
2520 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2521 }
2522 outb(sc->asic_addr + ED_WD_LAAR,
2523 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2524 }
2525 }
2526 }
2527
2528 /*
2529 * If it looks like the transmitter can take more data,
2530 * attempt to start output on the interface. This is done
2531 * after handling the receiver to give the receiver priority.
2532 */
2533 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2534 ed_start(ifp);
2535
2536 /*
2537 * return NIC CR to standard state: page 0, remote DMA
2538 * complete, start (toggling the TXP bit off, even if was just
2539 * set in the transmit routine, is *okay* - it is 'edge'
2540 * triggered from low to high)
2541 */
2542 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2543
2544 /*
2545 * If the Network Talley Counters overflow, read them to reset
2546 * them. It appears that old 8390's won't clear the ISR flag
2547 * otherwise - resulting in an infinite loop.
2548 */
2549 if (isr & ED_ISR_CNT) {
2550 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2551 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2552 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2553 }
2554 }
2555}
2556
2557void
2558edintr(unit)
2559 int unit;
2560{
2561 edintr_sc (&ed_softc[unit]);
2562}
2563
2564/*
2565 * Process an ioctl request. This code needs some work - it looks
2566 * pretty ugly.
2567 */
2568static int
2569ed_ioctl(ifp, command, data)
2570 register struct ifnet *ifp;
2571 int command;
2572 caddr_t data;
2573{
2574 struct ed_softc *sc = ifp->if_softc;
2575 int s, error = 0;
2576
2577 if (sc->gone) {
2578 ifp->if_flags &= ~IFF_RUNNING;
2579 return ENXIO;
2580 }
2581 s = splimp();
2582
2583 switch (command) {
2584
2585 case SIOCSIFADDR:
2586 case SIOCGIFADDR:
2587 case SIOCSIFMTU:
2588 error = ether_ioctl(ifp, command, data);
2589 break;
2590
2591 case SIOCSIFFLAGS:
2592
2593 /*
2594 * If the interface is marked up and stopped, then start it.
2595 * If it is marked down and running, then stop it.
2596 */
2597 if (ifp->if_flags & IFF_UP) {
2598 if ((ifp->if_flags & IFF_RUNNING) == 0)
2599 ed_init(sc);
2600 } else {
2601 if (ifp->if_flags & IFF_RUNNING) {
2602 ed_stop(sc);
2603 ifp->if_flags &= ~IFF_RUNNING;
2604 }
2605 }
2606
2607#if NBPFILTER > 0
2608
2609 /*
2610 * Promiscuous flag may have changed, so reprogram the RCR.
2611 */
2612 ed_setrcr(sc);
2613#endif
2614
2615 /*
2616 * An unfortunate hack to provide the (required) software
2617 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2618 * disables the tranceiver if set.
2619 */
2620 if (sc->vendor == ED_VENDOR_3COM) {
2621 if (ifp->if_flags & IFF_ALTPHYS) {
2622 outb(sc->asic_addr + ED_3COM_CR, 0);
2623 } else {
2624 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2625 }
2626 } else if (sc->vendor == ED_VENDOR_HP)
2627 ed_hpp_set_physical_link(sc);
2628 break;
2629
2630 case SIOCADDMULTI:
2631 case SIOCDELMULTI:
2632 /*
2633 * Multicast list has changed; set the hardware filter
2634 * accordingly.
2635 */
2636 ed_setrcr(sc);
2637 error = 0;
2638 break;
2639
2640 default:
2641 error = EINVAL;
2642 }
2643 (void) splx(s);
2644 return (error);
2645}
2646
2647/*
2648 * Given a source and destination address, copy 'amount' of a packet from
2649 * the ring buffer into a linear destination buffer. Takes into account
2650 * ring-wrap.
2651 */
2652static inline char *
2653ed_ring_copy(sc, src, dst, amount)
2654 struct ed_softc *sc;
2655 char *src;
2656 char *dst;
2657 u_short amount;
2658{
2659 u_short tmp_amount;
2660
2661 /* does copy wrap to lower addr in ring buffer? */
2662 if (src + amount > sc->mem_end) {
2663 tmp_amount = sc->mem_end - src;
2664
2665 /* copy amount up to end of NIC memory */
2666 if (sc->mem_shared)
2667 bcopy(src, dst, tmp_amount);
2668 else
2669 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2670
2671 amount -= tmp_amount;
2672 src = sc->mem_ring;
2673 dst += tmp_amount;
2674 }
2675 if (sc->mem_shared)
2676 bcopy(src, dst, amount);
2677 else
2678 ed_pio_readmem(sc, (int)src, dst, amount);
2679
2680 return (src + amount);
2681}
2682
2683/*
2684 * Retreive packet from shared memory and send to the next level up via
2685 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2686 */
2687static void
2688ed_get_packet(sc, buf, len, multicast)
2689 struct ed_softc *sc;
2690 char *buf;
2691 u_short len;
2692 int multicast;
2693{
2694 struct ether_header *eh;
2695 struct mbuf *m;
2696
2697 /* Allocate a header mbuf */
2698 MGETHDR(m, M_DONTWAIT, MT_DATA);
2699 if (m == NULL)
2700 return;
2701 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2702 m->m_pkthdr.len = m->m_len = len;
2703
2704 /*
2705 * We always put the received packet in a single buffer -
2706 * either with just an mbuf header or in a cluster attached
2707 * to the header. The +2 is to compensate for the alignment
2708 * fixup below.
2709 */
2710 if ((len + 2) > MHLEN) {
2711 /* Attach an mbuf cluster */
2712 MCLGET(m, M_DONTWAIT);
2713
2714 /* Insist on getting a cluster */
2715 if ((m->m_flags & M_EXT) == 0) {
2716 m_freem(m);
2717 return;
2718 }
2719 }
2720
2721 /*
2722 * The +2 is to longword align the start of the real packet.
2723 * This is important for NFS.
2724 */
2725 m->m_data += 2;
2726 eh = mtod(m, struct ether_header *);
2727
2728 /*
2729 * Get packet, including link layer address, from interface.
2730 */
2731 ed_ring_copy(sc, buf, (char *)eh, len);
2732
2733#if NBPFILTER > 0
2734
2735 /*
2736 * Check if there's a BPF listener on this interface. If so, hand off
2737 * the raw packet to bpf.
2738 */
2739 if (sc->arpcom.ac_if.if_bpf) {
2740 bpf_mtap(&sc->arpcom.ac_if, m);
2741
2742 /*
2743 * Note that the interface cannot be in promiscuous mode if
2744 * there are no BPF listeners. And if we are in promiscuous
2745 * mode, we have to check if this packet is really ours.
2746 */
2747 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2748 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2749 sizeof(eh->ether_dhost)) != 0 && multicast == 0) {
2750 m_freem(m);
2751 return;
2752 }
2753 }
2754#endif
2755
2756 /*
2757 * Remove link layer address.
2758 */
2759 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2760 m->m_data += sizeof(struct ether_header);
2761
2762 ether_input(&sc->arpcom.ac_if, eh, m);
2763 return;
2764}
2765
2766/*
2767 * Supporting routines
2768 */
2769
2770/*
2771 * Given a NIC memory source address and a host memory destination
2772 * address, copy 'amount' from NIC to host using Programmed I/O.
2773 * The 'amount' is rounded up to a word - okay as long as mbufs
2774 * are word sized.
2775 * This routine is currently Novell-specific.
2776 */
2777static void
2778ed_pio_readmem(sc, src, dst, amount)
2779 struct ed_softc *sc;
2780 int src;
2781 unsigned char *dst;
2782 unsigned short amount;
2783{
2784 /* HP cards need special handling */
2785 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2786 ed_hpp_readmem(sc, src, dst, amount);
2787 return;
2788 }
2789
2790 /* Regular Novell cards */
2791 /* select page 0 registers */
2792 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2793
2794 /* round up to a word */
2795 if (amount & 1)
2796 ++amount;
2797
2798 /* set up DMA byte count */
2799 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2800 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2801
2802 /* set up source address in NIC mem */
2803 outb(sc->nic_addr + ED_P0_RSAR0, src);
2804 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2805
2806 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2807
2808 if (sc->isa16bit) {
2809 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2810 } else
2811 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2812
2813}
2814
2815/*
2816 * Stripped down routine for writing a linear buffer to NIC memory.
2817 * Only used in the probe routine to test the memory. 'len' must
2818 * be even.
2819 */
2820static void
2821ed_pio_writemem(sc, src, dst, len)
2822 struct ed_softc *sc;
2823 char *src;
2824 unsigned short dst;
2825 unsigned short len;
2826{
2827 int maxwait = 200; /* about 240us */
2828
2829 if (sc->vendor == ED_VENDOR_NOVELL) {
2830
2831 /* select page 0 registers */
2832 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2833
2834 /* reset remote DMA complete flag */
2835 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2836
2837 /* set up DMA byte count */
2838 outb(sc->nic_addr + ED_P0_RBCR0, len);
2839 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2840
2841 /* set up destination address in NIC mem */
2842 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2843 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2844
2845 /* set remote DMA write */
2846 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2847
2848 if (sc->isa16bit)
2849 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2850 else
2851 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2852
2853 /*
2854 * Wait for remote DMA complete. This is necessary because on the
2855 * transmit side, data is handled internally by the NIC in bursts and
2856 * we can't start another remote DMA until this one completes. Not
2857 * waiting causes really bad things to happen - like the NIC
2858 * irrecoverably jamming the ISA bus.
2859 */
2860 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2861
2862 } else if ((sc->vendor == ED_VENDOR_HP) &&
2863 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2864
2865 /* HP PCLAN+ */
2866
2867 /* reset remote DMA complete flag */
2868 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2869
2870 /* program the write address in RAM */
2871 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2872
2873 if (sc->hpp_mem_start) {
2874 u_short *s = (u_short *) src;
2875 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2876 u_short *const fence = s + (len >> 1);
2877
2878 /*
2879 * Enable memory mapped access.
2880 */
2881
2882 outw(sc->asic_addr + ED_HPP_OPTION,
2883 sc->hpp_options &
2884 ~(ED_HPP_OPTION_MEM_DISABLE |
2885 ED_HPP_OPTION_BOOT_ROM_ENB));
2886
2887 /*
2888 * Copy to NIC memory.
2889 */
2890
2891 while (s < fence)
2892 *d = *s++;
2893
2894 /*
2895 * Restore Boot ROM access.
2896 */
2897
2898 outw(sc->asic_addr + ED_HPP_OPTION,
2899 sc->hpp_options);
2900
2901 } else {
2902 /* write data using I/O writes */
2903 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2904 }
2905
2906 }
2907}
2908
2909/*
2910 * Write an mbuf chain to the destination NIC memory address using
2911 * programmed I/O.
2912 */
2913static u_short
2914ed_pio_write_mbufs(sc, m, dst)
2915 struct ed_softc *sc;
2916 struct mbuf *m;
2917 int dst;
2918{
2919 struct ifnet *ifp = (struct ifnet *)sc;
2920 unsigned short total_len, dma_len;
2921 struct mbuf *mp;
2922 int maxwait = 200; /* about 240us */
2923
2924 /* HP PC Lan+ cards need special handling */
2925 if ((sc->vendor == ED_VENDOR_HP) &&
2926 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2927 return ed_hpp_write_mbufs(sc, m, dst);
2928 }
2929
2930 /* First, count up the total number of bytes to copy */
2931 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2932 total_len += mp->m_len;
2933
2934 dma_len = total_len;
2935 if (sc->isa16bit && (dma_len & 1))
2936 dma_len++;
2937
2938 /* select page 0 registers */
2939 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2940
2941 /* reset remote DMA complete flag */
2942 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2943
2944 /* set up DMA byte count */
2945 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2946 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
2947
2948 /* set up destination address in NIC mem */
2949 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2950 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2951
2952 /* set remote DMA write */
2953 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2954
2955 /*
2956 * Transfer the mbuf chain to the NIC memory.
2957 * 16-bit cards require that data be transferred as words, and only words.
2958 * So that case requires some extra code to patch over odd-length mbufs.
2959 */
2960
2961 if (!sc->isa16bit) {
2962 /* NE1000s are easy */
2963 while (m) {
2964 if (m->m_len) {
2965 outsb(sc->asic_addr + ED_NOVELL_DATA,
2966 m->m_data, m->m_len);
2967 }
2968 m = m->m_next;
2969 }
2970 } else {
2971 /* NE2000s are a pain */
2972 unsigned char *data;
2973 int len, wantbyte;
2974 unsigned char savebyte[2];
2975
2976 wantbyte = 0;
2977
2978 while (m) {
2979 len = m->m_len;
2980 if (len) {
2981 data = mtod(m, caddr_t);
2982 /* finish the last word */
2983 if (wantbyte) {
2984 savebyte[1] = *data;
2985 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
2986 data++;
2987 len--;
2988 wantbyte = 0;
2989 }
2990 /* output contiguous words */
2991 if (len > 1) {
2992 outsw(sc->asic_addr + ED_NOVELL_DATA,
2993 data, len >> 1);
2994 data += len & ~1;
2995 len &= 1;
2996 }
2997 /* save last byte, if necessary */
2998 if (len == 1) {
2999 savebyte[0] = *data;
3000 wantbyte = 1;
3001 }
3002 }
3003 m = m->m_next;
3004 }
3005 /* spit last byte */
3006 if (wantbyte) {
3007 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3008 }
3009 }
3010
3011 /*
3012 * Wait for remote DMA complete. This is necessary because on the
3013 * transmit side, data is handled internally by the NIC in bursts and
3014 * we can't start another remote DMA until this one completes. Not
3015 * waiting causes really bad things to happen - like the NIC
3016 * irrecoverably jamming the ISA bus.
3017 */
3018 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3019
3020 if (!maxwait) {
3021 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
3022 ifp->if_unit);
3023 ed_reset(ifp);
3024 return(0);
3025 }
3026 return (total_len);
3027}
3028
3029/*
3030 * Support routines to handle the HP PC Lan+ card.
3031 */
3032
3033/*
3034 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3035 * IO.
3036 */
3037
3038static void
3039ed_hpp_readmem(sc, src, dst, amount)
3040 struct ed_softc *sc;
3041 unsigned short src;
3042 unsigned char *dst;
3043 unsigned short amount;
3044{
3045
3046 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3047
3048
3049 /* Program the source address in RAM */
3050 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
3051
3052 /*
3053 * The HP PC Lan+ card supports word reads as well as
3054 * a memory mapped i/o port that is aliased to every
3055 * even address on the board.
3056 */
3057
3058 if (sc->hpp_mem_start) {
3059
3060 /* Enable memory mapped access. */
3061 outw(sc->asic_addr + ED_HPP_OPTION,
3062 sc->hpp_options &
3063 ~(ED_HPP_OPTION_MEM_DISABLE |
3064 ED_HPP_OPTION_BOOT_ROM_ENB));
3065
3066 if (use_32bit_access && (amount > 3)) {
3067 u_long *dl = (u_long *) dst;
3068 volatile u_long *const sl =
3069 (u_long *) sc->hpp_mem_start;
3070 u_long *const fence = dl + (amount >> 2);
3071
3072 /* Copy out NIC data. We could probably write this
3073 as a `movsl'. The currently generated code is lousy.
3074 */
3075
3076 while (dl < fence)
3077 *dl++ = *sl;
3078
3079 dst += (amount & ~3);
3080 amount &= 3;
3081
3082 }
3083
3084 /* Finish off any words left, as a series of short reads */
3085 if (amount > 1) {
3086 u_short *d = (u_short *) dst;
3087 volatile u_short *const s =
3088 (u_short *) sc->hpp_mem_start;
3089 u_short *const fence = d + (amount >> 1);
3090
3091 /* Copy out NIC data. */
3092
3093 while (d < fence)
3094 *d++ = *s;
3095
3096 dst += (amount & ~1);
3097 amount &= 1;
3098 }
3099
3100 /*
3101 * read in a byte; however we need to always read 16 bits
3102 * at a time or the hardware gets into a funny state
3103 */
3104
3105 if (amount == 1) {
3106 /* need to read in a short and copy LSB */
3107 volatile u_short *const s =
3108 (volatile u_short *) sc->hpp_mem_start;
3109
3110 *dst = (*s) & 0xFF;
3111 }
3112
3113 /* Restore Boot ROM access. */
3114
3115 outw(sc->asic_addr + ED_HPP_OPTION,
3116 sc->hpp_options);
3117
3118
3119 } else {
3120 /* Read in data using the I/O port */
3121 if (use_32bit_access && (amount > 3)) {
3122 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3123 dst += (amount & ~3);
3124 amount &= 3;
3125 }
3126 if (amount > 1) {
3127 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3128 dst += (amount & ~1);
3129 amount &= 1;
3130 }
3131 if (amount == 1) { /* read in a short and keep the LSB */
3132 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3133 }
3134 }
3135}
3136
3137/*
3138 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3139 * outsw() or via the memory mapped interface to the same register.
3140 * Writes have to be in word units; byte accesses won't work and may cause
3141 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3142 * allows it.
3143 */
3144
3145static u_short
3146ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3147{
3148 int len, wantbyte;
3149 unsigned short total_len;
3150 unsigned char savebyte[2];
3151 volatile u_short * const d =
3152 (volatile u_short *) sc->hpp_mem_start;
3153 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3154
3155 /* select page 0 registers */
3156 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3157
3158 /* reset remote DMA complete flag */
3159 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3160
3161 /* program the write address in RAM */
3162 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3163
3164 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3165 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3166 ~(ED_HPP_OPTION_MEM_DISABLE |
3167 ED_HPP_OPTION_BOOT_ROM_ENB));
3168
3169 wantbyte = 0;
3170 total_len = 0;
3171
3172 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3173 while (m) {
3174 total_len += (len = m->m_len);
3175 if (len) {
3176 caddr_t data = mtod(m, caddr_t);
3177 /* finish the last word of the previous mbuf */
3178 if (wantbyte) {
3179 savebyte[1] = *data;
3180 *d = *((ushort *) savebyte);
3181 data++; len--; wantbyte = 0;
3182 }
3183 /* output contiguous words */
3184 if ((len > 3) && (use_32bit_accesses)) {
3185 volatile u_long *const dl =
3186 (volatile u_long *) d;
3187 u_long *sl = (u_long *) data;
3188 u_long *fence = sl + (len >> 2);
3189
3190 while (sl < fence)
3191 *dl = *sl++;
3192
3193 data += (len & ~3);
3194 len &= 3;
3195 }
3196 /* finish off remain 16 bit writes */
3197 if (len > 1) {
3198 u_short *s = (u_short *) data;
3199 u_short *fence = s + (len >> 1);
3200
3201 while (s < fence)
3202 *d = *s++;
3203
3204 data += (len & ~1);
3205 len &= 1;
3206 }
3207 /* save last byte if needed */
3208 if (wantbyte = (len == 1))
3209 savebyte[0] = *data;
3210 }
3211 m = m->m_next; /* to next mbuf */
3212 }
3213 if (wantbyte) /* write last byte */
3214 *d = *((u_short *) savebyte);
3215 } else {
3216 /* use programmed I/O */
3217 while (m) {
3218 total_len += (len = m->m_len);
3219 if (len) {
3220 caddr_t data = mtod(m, caddr_t);
3221 /* finish the last word of the previous mbuf */
3222 if (wantbyte) {
3223 savebyte[1] = *data;
3224 outw(sc->asic_addr + ED_HPP_PAGE_4,
3225 *((u_short *)savebyte));
3226 data++;
3227 len--;
3228 wantbyte = 0;
3229 }
3230 /* output contiguous words */
3231 if ((len > 3) && use_32bit_accesses) {
3232 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3233 data, len >> 2);
3234 data += (len & ~3);
3235 len &= 3;
3236 }
3237 /* finish off remaining 16 bit accesses */
3238 if (len > 1) {
3239 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3240 data, len >> 1);
3241 data += (len & ~1);
3242 len &= 1;
3243 }
3244 if (wantbyte = (len == 1))
3245 savebyte[0] = *data;
3246
3247 } /* if len != 0 */
3248 m = m->m_next;
3249 }
3250 if (wantbyte) /* spit last byte */
3251 outw(sc->asic_addr + ED_HPP_PAGE_4,
3252 *(u_short *)savebyte);
3253
3254 }
3255
3256 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3257 outw(sc->asic_addr + ED_HPP_OPTION,
3258 sc->hpp_options);
3259
3260 return (total_len);
3261}
3262
3263static void
3264ed_setrcr(sc)
3265 struct ed_softc *sc;
3266{
3267 struct ifnet *ifp = (struct ifnet *)sc;
3268 int i;
3269
3270 /* set page 1 registers */
3271 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3272
3273 if (ifp->if_flags & IFF_PROMISC) {
3274
3275 /*
3276 * Reconfigure the multicast filter.
3277 */
3278 for (i = 0; i < 8; i++)
3279 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
3280
3281 /*
3282 * And turn on promiscuous mode. Also enable reception of
3283 * runts and packets with CRC & alignment errors.
3284 */
3285 /* Set page 0 registers */
3286 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3287
3288 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3289 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3290 } else {
3291 /* set up multicast addresses and filter modes */
3292 if (ifp->if_flags & IFF_MULTICAST) {
3293 u_long mcaf[2];
3294
3295 if (ifp->if_flags & IFF_ALLMULTI) {
3296 mcaf[0] = 0xffffffff;
3297 mcaf[1] = 0xffffffff;
3298 } else
3299 ds_getmcaf(sc, mcaf);
3300
3301 /*
3302 * Set multicast filter on chip.
3303 */
3304 for (i = 0; i < 8; i++)
3305 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]);
3306
3307 /* Set page 0 registers */
3308 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3309
3310 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3311 } else {
3312
3313 /*
3314 * Initialize multicast address hashing registers to
3315 * not accept multicasts.
3316 */
3317 for (i = 0; i < 8; ++i)
3318 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00);
3319
3320 /* Set page 0 registers */
3321 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3322
3323 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3324 }
3325 }
3326
3327 /*
3328 * Start interface.
3329 */
3330 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3331}
3332
3333/*
3334 * Compute crc for ethernet address
3335 */
3336static u_long
3337ds_crc(ep)
3338 u_char *ep;
3339{
3340#define POLYNOMIAL 0x04c11db6
3341 register u_long crc = 0xffffffffL;
3342 register int carry, i, j;
3343 register u_char b;
3344
3345 for (i = 6; --i >= 0;) {
3346 b = *ep++;
3347 for (j = 8; --j >= 0;) {
3348 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3349 crc <<= 1;
3350 b >>= 1;
3351 if (carry)
3352 crc = ((crc ^ POLYNOMIAL) | carry);
3353 }
3354 }
3355 return crc;
3356#undef POLYNOMIAL
3357}
3358
3359/*
3360 * Compute the multicast address filter from the
3361 * list of multicast addresses we need to listen to.
3362 */
3363static void
3364ds_getmcaf(sc, mcaf)
3365 struct ed_softc *sc;
3366 u_long *mcaf;
3367{
3368 register u_int index;
3369 register u_char *af = (u_char *) mcaf;
3370 struct ifmultiaddr *ifma;
3371
3372 mcaf[0] = 0;
3373 mcaf[1] = 0;
3374
3375 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3376 ifma = ifma->ifma_link.le_next) {
3377 if (ifma->ifma_addr->sa_family != AF_LINK)
3378 continue;
3379 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3380 >> 26;
3381 af[index >> 3] |= 1 << (index & 7);
3382 }
3383}
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