1/*
2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
3 * adapters. By David Greenman, 29-April-1993
4 *
5 * Copyright (C) 1993, David Greenman. This software may be used, modified,
6 * copied, distributed, and sold, in both source and binary form provided
7 * that the above copyright and these terms are retained. Under no
8 * circumstances is the author responsible for the proper functioning
9 * of this software, nor does the author assume any responsibility
10 * for damages incurred with its use.
11 *
12 * Currently supports the Western Digital/SMC 8003 and 8013 series,
13 * the 3Com 3c503, the NE1000 and NE2000, and a variety of similar
14 * clones.
15 *
16 * Thanks to Charles Hannum for proving to me with example code that the
17 * NE1000/2000 support could be added with minimal impact. Without
18 * this, I wouldn't have proceeded in this direction.
19 *
20 */
21
22/*
| 1/*
2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
3 * adapters. By David Greenman, 29-April-1993
4 *
5 * Copyright (C) 1993, David Greenman. This software may be used, modified,
6 * copied, distributed, and sold, in both source and binary form provided
7 * that the above copyright and these terms are retained. Under no
8 * circumstances is the author responsible for the proper functioning
9 * of this software, nor does the author assume any responsibility
10 * for damages incurred with its use.
11 *
12 * Currently supports the Western Digital/SMC 8003 and 8013 series,
13 * the 3Com 3c503, the NE1000 and NE2000, and a variety of similar
14 * clones.
15 *
16 * Thanks to Charles Hannum for proving to me with example code that the
17 * NE1000/2000 support could be added with minimal impact. Without
18 * this, I wouldn't have proceeded in this direction.
19 *
20 */
21
22/*
|
23 * $Id: if_ed.c,v 2.14 1993/11/22 10:55:30 davidg Exp davidg $
| 23 * $Id: if_ed.c,v 1.23 1993/11/22 11:08:14 davidg Exp $
|
24 */
25
26/*
27 * Modification history
28 *
29 * Revision 2.14 1993/11/22 10:55:30 davidg
30 * change all splnet's to splimp's
31 *
32 * Revision 2.13 1993/11/22 10:53:52 davidg
33 * patch to add support for SMC8216 (Elite-Ultra) boards
34 * from Glen H. Lowe
35 *
36 * Revision 2.12 1993/11/07 18:04:13 davidg
37 * fix from Garrett Wollman:
38 * add a return(0) at the end of ed_probe so that if the various device
39 * specific probes fail that we just don't fall of the end of the function.
40 *
41 * Revision 2.11 1993/10/23 04:21:03 davidg
42 * Novell probe changed to be invasive because of too many complaints
43 * about some clone boards not being reset properly and thus not
44 * found on a warmboot. Yuck.
45 *
46 * Revision 2.10 1993/10/23 04:07:12 davidg
47 * increment output errors if the device times out (done via watchdog)
48 *
49 * Revision 2.9 1993/10/23 04:01:45 davidg
50 * increment input error counter if a packet with a bad length is
51 * detected.
52 *
53 * Revision 2.8 1993/10/15 10:59:56 davidg
54 * increase maximum time to wait for transmit DMA to complete to 120us.
55 * call ed_reset() if the time limit is reached instead of trying
56 * to abort the remote DMA.
57 *
58 * Revision 2.7 1993/10/15 10:49:10 davidg
59 * minor change to way the mbuf pointer temp variable is assigned in
60 * ed_start (slightly improves code readability)
61 *
62 * Revision 2.6 93/10/02 01:12:20 davidg
63 * use ETHER_ADDR_LEN in NE probe rather than '6'.
64 *
65 * Revision 2.5 93/09/30 17:44:14 davidg
66 * patch from vak@zebub.msk.su (Serge V.Vakulenko) to work around
67 * a hardware bug in cheap WD clone boards where the PROM checksum
68 * byte is always zero
69 *
70 * Revision 2.4 93/09/29 21:24:30 davidg
71 * Added software NIC reset in NE probe to work around a problem
72 * with some NE boards where the 8390 doesn't reset properly on
73 * power-up. Remove initialization of IMR/ISR in the NE probe
74 * because this is inherent in the reset.
75 *
76 * Revision 2.3 93/09/29 15:10:16 davidg
77 * credit Charles Hannum
78 *
79 * Revision 2.2 93/09/29 13:23:25 davidg
80 * added no multi-buffer override for 3c503
81 *
82 * Revision 2.1 93/09/29 12:32:12 davidg
83 * changed multi-buffer count for 16bit 3c503's from 5 to 2 after
84 * noticing that the transmitter becomes idle because of so many
85 * packets to load.
86 *
87 * Revision 2.0 93/09/29 00:00:19 davidg
88 * many changes, rewrites, additions, etc. Now supports the
89 * NE1000, NE2000, WD8003, WD8013, 3C503, 16bit 3C503, and
90 * a variety of similar clones. 16bit 3c503 now does multi
91 * transmit buffers. Nearly every part of the driver has
92 * changed in some way since rev 1.30.
93 *
94 * Revision 1.1 93/06/14 22:21:24 davidg
95 * Beta release of device driver for SMC/WD80x3 and 3C503 ethernet boards.
96 *
97 */
98
99#include "ed.h"
100#if NED > 0
101/* bpfilter included here in case it is needed in future net includes */
102#include "bpfilter.h"
103
104#include "param.h"
105#include "systm.h"
106#include "errno.h"
107#include "ioctl.h"
108#include "mbuf.h"
109#include "socket.h"
110#include "syslog.h"
111
112#include "net/if.h"
113#include "net/if_dl.h"
114#include "net/if_types.h"
115#include "net/netisr.h"
116
117#ifdef INET
118#include "netinet/in.h"
119#include "netinet/in_systm.h"
120#include "netinet/in_var.h"
121#include "netinet/ip.h"
122#include "netinet/if_ether.h"
123#endif
124
125#ifdef NS
126#include "netns/ns.h"
127#include "netns/ns_if.h"
128#endif
129
130#if NBPFILTER > 0
131#include "net/bpf.h"
132#include "net/bpfdesc.h"
133#endif
134
135#include "i386/isa/isa.h"
136#include "i386/isa/isa_device.h"
137#include "i386/isa/icu.h"
138#include "i386/isa/if_edreg.h"
139
140#include "i386/include/pio.h"
141
142/* For backwards compatibility */
143#ifndef IFF_ALTPHYS
144#define IFF_ALTPHYS IFF_LLC0
145#endif
146
147/*
148 * ed_softc: per line info and status
149 */
150struct ed_softc {
151 struct arpcom arpcom; /* ethernet common */
152
153 char *type_str; /* pointer to type string */
154 u_char vendor; /* interface vendor */
155 u_char type; /* interface type code */
156
157 u_short asic_addr; /* ASIC I/O bus address */
158 u_short nic_addr; /* NIC (DS8390) I/O bus address */
159
160/*
161 * The following 'proto' variable is part of a work-around for 8013EBT asics
162 * being write-only. It's sort of a prototype/shadow of the real thing.
163 */
164 u_char wd_laar_proto;
165 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
166 int is790; /* set by the probe code if the card is 790 based */
167
168 caddr_t bpf; /* BPF "magic cookie" */
169 caddr_t mem_start; /* NIC memory start address */
170 caddr_t mem_end; /* NIC memory end address */
171 u_long mem_size; /* total NIC memory size */
172 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
173
174 u_char mem_shared; /* NIC memory is shared with host */
175 u_char xmit_busy; /* transmitter is busy */
176 u_char txb_cnt; /* number of transmit buffers */
177 u_char txb_inuse; /* number of TX buffers currently in-use*/
178
179 u_char txb_new; /* pointer to where new buffer will be added */
180 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
181 u_short txb_len[8]; /* buffered xmit buffer lengths */
182 u_char tx_page_start; /* first page of TX buffer area */
183 u_char rec_page_start; /* first page of RX ring-buffer */
184 u_char rec_page_stop; /* last page of RX ring-buffer */
185 u_char next_packet; /* pointer to next unread RX packet */
186} ed_softc[NED];
187
| 24 */
25
26/*
27 * Modification history
28 *
29 * Revision 2.14 1993/11/22 10:55:30 davidg
30 * change all splnet's to splimp's
31 *
32 * Revision 2.13 1993/11/22 10:53:52 davidg
33 * patch to add support for SMC8216 (Elite-Ultra) boards
34 * from Glen H. Lowe
35 *
36 * Revision 2.12 1993/11/07 18:04:13 davidg
37 * fix from Garrett Wollman:
38 * add a return(0) at the end of ed_probe so that if the various device
39 * specific probes fail that we just don't fall of the end of the function.
40 *
41 * Revision 2.11 1993/10/23 04:21:03 davidg
42 * Novell probe changed to be invasive because of too many complaints
43 * about some clone boards not being reset properly and thus not
44 * found on a warmboot. Yuck.
45 *
46 * Revision 2.10 1993/10/23 04:07:12 davidg
47 * increment output errors if the device times out (done via watchdog)
48 *
49 * Revision 2.9 1993/10/23 04:01:45 davidg
50 * increment input error counter if a packet with a bad length is
51 * detected.
52 *
53 * Revision 2.8 1993/10/15 10:59:56 davidg
54 * increase maximum time to wait for transmit DMA to complete to 120us.
55 * call ed_reset() if the time limit is reached instead of trying
56 * to abort the remote DMA.
57 *
58 * Revision 2.7 1993/10/15 10:49:10 davidg
59 * minor change to way the mbuf pointer temp variable is assigned in
60 * ed_start (slightly improves code readability)
61 *
62 * Revision 2.6 93/10/02 01:12:20 davidg
63 * use ETHER_ADDR_LEN in NE probe rather than '6'.
64 *
65 * Revision 2.5 93/09/30 17:44:14 davidg
66 * patch from vak@zebub.msk.su (Serge V.Vakulenko) to work around
67 * a hardware bug in cheap WD clone boards where the PROM checksum
68 * byte is always zero
69 *
70 * Revision 2.4 93/09/29 21:24:30 davidg
71 * Added software NIC reset in NE probe to work around a problem
72 * with some NE boards where the 8390 doesn't reset properly on
73 * power-up. Remove initialization of IMR/ISR in the NE probe
74 * because this is inherent in the reset.
75 *
76 * Revision 2.3 93/09/29 15:10:16 davidg
77 * credit Charles Hannum
78 *
79 * Revision 2.2 93/09/29 13:23:25 davidg
80 * added no multi-buffer override for 3c503
81 *
82 * Revision 2.1 93/09/29 12:32:12 davidg
83 * changed multi-buffer count for 16bit 3c503's from 5 to 2 after
84 * noticing that the transmitter becomes idle because of so many
85 * packets to load.
86 *
87 * Revision 2.0 93/09/29 00:00:19 davidg
88 * many changes, rewrites, additions, etc. Now supports the
89 * NE1000, NE2000, WD8003, WD8013, 3C503, 16bit 3C503, and
90 * a variety of similar clones. 16bit 3c503 now does multi
91 * transmit buffers. Nearly every part of the driver has
92 * changed in some way since rev 1.30.
93 *
94 * Revision 1.1 93/06/14 22:21:24 davidg
95 * Beta release of device driver for SMC/WD80x3 and 3C503 ethernet boards.
96 *
97 */
98
99#include "ed.h"
100#if NED > 0
101/* bpfilter included here in case it is needed in future net includes */
102#include "bpfilter.h"
103
104#include "param.h"
105#include "systm.h"
106#include "errno.h"
107#include "ioctl.h"
108#include "mbuf.h"
109#include "socket.h"
110#include "syslog.h"
111
112#include "net/if.h"
113#include "net/if_dl.h"
114#include "net/if_types.h"
115#include "net/netisr.h"
116
117#ifdef INET
118#include "netinet/in.h"
119#include "netinet/in_systm.h"
120#include "netinet/in_var.h"
121#include "netinet/ip.h"
122#include "netinet/if_ether.h"
123#endif
124
125#ifdef NS
126#include "netns/ns.h"
127#include "netns/ns_if.h"
128#endif
129
130#if NBPFILTER > 0
131#include "net/bpf.h"
132#include "net/bpfdesc.h"
133#endif
134
135#include "i386/isa/isa.h"
136#include "i386/isa/isa_device.h"
137#include "i386/isa/icu.h"
138#include "i386/isa/if_edreg.h"
139
140#include "i386/include/pio.h"
141
142/* For backwards compatibility */
143#ifndef IFF_ALTPHYS
144#define IFF_ALTPHYS IFF_LLC0
145#endif
146
147/*
148 * ed_softc: per line info and status
149 */
150struct ed_softc {
151 struct arpcom arpcom; /* ethernet common */
152
153 char *type_str; /* pointer to type string */
154 u_char vendor; /* interface vendor */
155 u_char type; /* interface type code */
156
157 u_short asic_addr; /* ASIC I/O bus address */
158 u_short nic_addr; /* NIC (DS8390) I/O bus address */
159
160/*
161 * The following 'proto' variable is part of a work-around for 8013EBT asics
162 * being write-only. It's sort of a prototype/shadow of the real thing.
163 */
164 u_char wd_laar_proto;
165 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
166 int is790; /* set by the probe code if the card is 790 based */
167
168 caddr_t bpf; /* BPF "magic cookie" */
169 caddr_t mem_start; /* NIC memory start address */
170 caddr_t mem_end; /* NIC memory end address */
171 u_long mem_size; /* total NIC memory size */
172 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
173
174 u_char mem_shared; /* NIC memory is shared with host */
175 u_char xmit_busy; /* transmitter is busy */
176 u_char txb_cnt; /* number of transmit buffers */
177 u_char txb_inuse; /* number of TX buffers currently in-use*/
178
179 u_char txb_new; /* pointer to where new buffer will be added */
180 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
181 u_short txb_len[8]; /* buffered xmit buffer lengths */
182 u_char tx_page_start; /* first page of TX buffer area */
183 u_char rec_page_start; /* first page of RX ring-buffer */
184 u_char rec_page_stop; /* last page of RX ring-buffer */
185 u_char next_packet; /* pointer to next unread RX packet */
186} ed_softc[NED];
187
|
188int ed_attach(), ed_init(), edintr(), ed_ioctl(), ed_probe(),
189 ed_start(), ed_reset(), ed_watchdog();
| 188int ed_attach(struct isa_device *);
189void ed_init(int);
190void edintr(int);
191int ed_ioctl(struct ifnet *, int, caddr_t);
192int ed_probe(struct isa_device *);
193void ed_start(struct ifnet *);
194void ed_reset(int, int);
195void ed_watchdog(int);
196static void ed_get_packet(struct ed_softc *, char *, int /*u_short*/);
197static void ed_stop(int);
|
190
| 198
|
191static void ed_stop();
192
| |
193static inline void ed_rint();
194static inline void ed_xmit();
195static inline char *ed_ring_copy();
196
197void ed_pio_readmem(), ed_pio_writemem();
198u_short ed_pio_write_mbufs();
199
200extern int ether_output();
201
202struct trailer_header {
203 u_short ether_type;
204 u_short ether_residual;
205};
206
207struct isa_driver eddriver = {
208 ed_probe,
209 ed_attach,
210 "ed"
211};
212/*
213 * Interrupt conversion table for WD/SMC ASIC
214 * (IRQ* are defined in icu.h)
215 */
216static unsigned short ed_intr_mask[] = {
217 IRQ9,
218 IRQ3,
219 IRQ5,
220 IRQ7,
221 IRQ10,
222 IRQ11,
223 IRQ15,
224 IRQ4
225};
226
227/*
228 * Interrupt conversion table for 585/790 Combo
229 */
230static unsigned short ed_790_intr_mask[] = {
231 0,
232 IRQ9,
233 IRQ3,
234 IRQ4,
235 IRQ5,
236 IRQ10,
237 IRQ11,
238 IRQ15
239};
240#define ETHER_MIN_LEN 64
241#define ETHER_MAX_LEN 1518
242#define ETHER_ADDR_LEN 6
243#define ETHER_HDR_SIZE 14
244
245/*
246 * Determine if the device is present
247 *
248 * on entry:
249 * a pointer to an isa_device struct
250 * on exit:
251 * NULL if device not found
252 * or # of i/o addresses used (if found)
253 */
254int
255ed_probe(isa_dev)
256 struct isa_device *isa_dev;
257{
258 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
259 int nports;
260
261 if (nports = ed_probe_WD80x3(isa_dev))
262 return (nports);
263
264 if (nports = ed_probe_3Com(isa_dev))
265 return (nports);
266
267 if (nports = ed_probe_Novell(isa_dev))
268 return (nports);
269
270 return(0);
271}
272
273/*
274 * Generic probe routine for testing for the existance of a DS8390.
275 * Must be called after the NIC has just been reset. This routine
276 * works by looking at certain register values that are gauranteed
277 * to be initialized a certain way after power-up or reset. Seems
278 * not to currently work on the 83C690.
279 *
280 * Specifically:
281 *
282 * Register reset bits set bits
283 * Command Register (CR) TXP, STA RD2, STP
284 * Interrupt Status (ISR) RST
285 * Interrupt Mask (IMR) All bits
286 * Data Control (DCR) LAS
287 * Transmit Config. (TCR) LB1, LB0
288 *
289 * We only look at the CR and ISR registers, however, because looking at
290 * the others would require changing register pages (which would be
291 * intrusive if this isn't an 8390).
292 *
293 * Return 1 if 8390 was found, 0 if not.
294 */
295
296int
297ed_probe_generic8390(sc)
298 struct ed_softc *sc;
299{
300 if ((inb(sc->nic_addr + ED_P0_CR) &
301 (ED_CR_RD2|ED_CR_TXP|ED_CR_STA|ED_CR_STP)) !=
302 (ED_CR_RD2|ED_CR_STP))
303 return (0);
304 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
305 return (0);
306
307 return(1);
308}
309
310/*
311 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
312 */
313int
314ed_probe_WD80x3(isa_dev)
315 struct isa_device *isa_dev;
316{
317 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
318 int i;
319 u_int memsize;
320 u_char iptr, isa16bit, sum;
321
322 sc->asic_addr = isa_dev->id_iobase;
323 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
324 sc->is790 = 0;
325
326 /*
327 * Attempt to do a checksum over the station address PROM.
328 * If it fails, it's probably not a SMC/WD board. There
329 * is a problem with this, though: some clone WD boards
330 * don't pass the checksum test. Danpex boards for one.
331 */
332 for (sum = 0, i = 0; i < 8; ++i)
333 sum += inb(sc->asic_addr + ED_WD_PROM + i);
334
335 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
336 /*
337 * Checksum is invalid. This often happens with cheap
338 * WD8003E clones. In this case, the checksum byte
339 * (the eighth byte) seems to always be zero.
340 */
341 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
342 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
343 return(0);
344 }
345
346 /* reset card to force it into a known state. */
347 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
348 DELAY(100);
349 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
350 /* wait in the case this card is reading it's EEROM */
351 DELAY(5000);
352
353 sc->vendor = ED_VENDOR_WD_SMC;
354 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
355
356 /*
357 * Set initial values for width/size.
358 */
359 switch (sc->type) {
360 case ED_TYPE_WD8003S:
361 sc->type_str = "WD8003S";
362 memsize = 8192;
363 isa16bit = 0;
364 break;
365 case ED_TYPE_WD8003E:
366 sc->type_str = "WD8003E";
367 memsize = 8192;
368 isa16bit = 0;
369 break;
370 case ED_TYPE_WD8013EBT:
371 sc->type_str = "WD8013EBT";
372 memsize = 16384;
373 isa16bit = 1;
374 break;
375 case ED_TYPE_WD8013EP: /* also WD8003EP */
376 if (inb(sc->asic_addr + ED_WD_ICR)
377 & ED_WD_ICR_16BIT) {
378 isa16bit = 1;
379 memsize = 16384;
380 sc->type_str = "WD8013EP";
381 } else {
382 isa16bit = 0;
383 memsize = 8192;
384 sc->type_str = "WD8003EP";
385 }
386 break;
387 case ED_TYPE_WD8013WC:
388 sc->type_str = "WD8013WC";
389 memsize = 16384;
390 isa16bit = 1;
391 break;
392 case ED_TYPE_WD8013EBP:
393 sc->type_str = "WD8013EBP";
394 memsize = 16384;
395 isa16bit = 1;
396 break;
397 case ED_TYPE_WD8013EPC:
398 sc->type_str = "WD8013EPC";
399 memsize = 16384;
400 isa16bit = 1;
401 break;
402 case ED_TYPE_SMC8216C:
403 sc->type_str = "SMC8216/SMC8216C";
404 memsize = 16384;
405 isa16bit = 1;
406 sc->is790 = 1;
407 break;
408 case ED_TYPE_SMC8216T:
409 sc->type_str = "SMC8216T";
410 memsize = 16384;
411 isa16bit = 1;
412 sc->is790 = 1;
413 break;
414 default:
415 sc->type_str = "";
416 memsize = 8192;
417 isa16bit = 0;
418 break;
419 }
420 /*
421 * Make some adjustments to initial values depending on what is
422 * found in the ICR.
423 */
424 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
425 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
426 isa16bit = 0;
427 memsize = 8192;
428 }
429
430#if ED_DEBUG
431 printf("type=%s isa16bit=%d memsize=%d id_msize=%d\n",
432 sc->type_str,isa16bit,memsize,isa_dev->id_msize);
433 for (i=0; i<8; i++)
434 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
435#endif
436 /*
437 * Allow the user to override the autoconfiguration
438 */
439 if (isa_dev->id_msize)
440 memsize = isa_dev->id_msize;
441 /*
442 * (note that if the user specifies both of the following flags
443 * that '8bit' mode intentionally has precedence)
444 */
445 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
446 isa16bit = 1;
447 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
448 isa16bit = 0;
449
450 /*
451 * Check 83C584 interrupt configuration register if this board has one
452 * XXX - we could also check the IO address register. But why
453 * bother...if we get past this, it *has* to be correct.
454 */
455 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
456 /*
457 * Assemble together the encoded interrupt number.
458 */
459 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
460 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
461 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
462 /*
463 * Translate it using translation table, and check for correctness.
464 */
465 if (ed_intr_mask[iptr] != isa_dev->id_irq) {
466 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
467 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
468 return(0);
469 }
470 /*
471 * Enable the interrupt.
472 */
473 outb(isa_dev->id_iobase + ED_WD_IRR,
474 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
475 }
476 if (sc->is790) {
477 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
478 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
479 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
480 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
481
482 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
483 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
484 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
485 return 0;
486 }
487 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
488 }
489
490 sc->isa16bit = isa16bit;
491
492#ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */
493 /*
494 * The following allows the WD/SMC boards to be used in Programmed I/O
495 * mode - without mapping the NIC memory shared. ...Not the prefered
496 * way, but it might be the only way.
497 */
498 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) {
499 sc->mem_shared = 0;
500 isa_dev->id_maddr = 0;
501 } else {
502 sc->mem_shared = 1;
503 }
504#else
505 sc->mem_shared = 1;
506#endif
507 isa_dev->id_msize = memsize;
508
509 sc->mem_start = (caddr_t)isa_dev->id_maddr;
510
511 /*
512 * allocate one xmit buffer if < 16k, two buffers otherwise
513 */
514 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
515 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
516 sc->txb_cnt = 1;
517 sc->rec_page_start = ED_TXBUF_SIZE;
518 } else {
519 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2);
520 sc->txb_cnt = 2;
521 sc->rec_page_start = ED_TXBUF_SIZE * 2;
522 }
523 sc->mem_size = memsize;
524 sc->mem_end = sc->mem_start + memsize;
525 sc->rec_page_stop = memsize / ED_PAGE_SIZE;
526 sc->tx_page_start = ED_WD_PAGE_OFFSET;
527
528 /*
529 * Get station address from on-board ROM
530 */
531 for (i = 0; i < ETHER_ADDR_LEN; ++i)
532 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
533
534 if (sc->mem_shared) {
535 /*
536 * Set address and enable interface shared memory.
537 */
538 if(!sc->is790) {
539 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
540 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
541 } else {
542 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
543 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
544 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
545 ((kvtop(sc->mem_start) >> 11) & 0x40) |
546 (inb(sc->asic_addr + 0x0b) & 0xb0));
547 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
548 }
549
550 /*
551 * Set upper address bits and 8/16 bit access to shared memory
552 */
553 if (isa16bit) {
554 if (sc->is790) {
555 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
556 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
557 } else {
558 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
559 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
560 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
561 }
562 } else {
563 if ((sc->type & ED_WD_SOFTCONFIG) || (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) {
564 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
565 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
566 }
567 }
568
569 /*
570 * Now zero memory and verify that it is clear
571 */
572 bzero(sc->mem_start, memsize);
573
574 for (i = 0; i < memsize; ++i)
575 if (sc->mem_start[i]) {
576 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
577 isa_dev->id_unit, kvtop(sc->mem_start + i));
578
579 /*
580 * Disable 16 bit access to shared memory
581 */
582 if (isa16bit)
583 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
584 ~ED_WD_LAAR_M16EN));
585
586 return(0);
587 }
588
589 /*
590 * Disable 16bit access to shared memory - we leave it disabled so
591 * that 1) machines reboot properly when the board is set
592 * 16 bit mode and there are conflicting 8bit devices/ROMS
593 * in the same 128k address space as this boards shared
594 * memory. and 2) so that other 8 bit devices with shared
595 * memory can be used in this 128k region, too.
596 */
597 if (isa16bit)
598 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
599 ~ED_WD_LAAR_M16EN));
600
601 }
602
603 return (ED_WD_IO_PORTS);
604}
605
606/*
607 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
608 */
609int
610ed_probe_3Com(isa_dev)
611 struct isa_device *isa_dev;
612{
613 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
614 int i;
615 u_int memsize;
616 u_char isa16bit, sum;
617
618 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
619 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
620
621 /*
622 * Verify that the kernel configured I/O address matches the board
623 * configured address
624 */
625 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
626 case ED_3COM_BCFR_300:
627 if (isa_dev->id_iobase != 0x300)
628 return(0);
629 break;
630 case ED_3COM_BCFR_310:
631 if (isa_dev->id_iobase != 0x310)
632 return(0);
633 break;
634 case ED_3COM_BCFR_330:
635 if (isa_dev->id_iobase != 0x330)
636 return(0);
637 break;
638 case ED_3COM_BCFR_350:
639 if (isa_dev->id_iobase != 0x350)
640 return(0);
641 break;
642 case ED_3COM_BCFR_250:
643 if (isa_dev->id_iobase != 0x250)
644 return(0);
645 break;
646 case ED_3COM_BCFR_280:
647 if (isa_dev->id_iobase != 0x280)
648 return(0);
649 break;
650 case ED_3COM_BCFR_2A0:
651 if (isa_dev->id_iobase != 0x2a0)
652 return(0);
653 break;
654 case ED_3COM_BCFR_2E0:
655 if (isa_dev->id_iobase != 0x2e0)
656 return(0);
657 break;
658 default:
659 return(0);
660 }
661
662 /*
663 * Verify that the kernel shared memory address matches the
664 * board configured address.
665 */
666 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
667 case ED_3COM_PCFR_DC000:
668 if (kvtop(isa_dev->id_maddr) != 0xdc000)
669 return(0);
670 break;
671 case ED_3COM_PCFR_D8000:
672 if (kvtop(isa_dev->id_maddr) != 0xd8000)
673 return(0);
674 break;
675 case ED_3COM_PCFR_CC000:
676 if (kvtop(isa_dev->id_maddr) != 0xcc000)
677 return(0);
678 break;
679 case ED_3COM_PCFR_C8000:
680 if (kvtop(isa_dev->id_maddr) != 0xc8000)
681 return(0);
682 break;
683 default:
684 return(0);
685 }
686
687
688 /*
689 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
690 * sequence because it'll lock up if the cable isn't connected
691 * if we don't.
692 */
693 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
694
695 /*
696 * Wait for a while, then un-reset it
697 */
698 DELAY(50);
699 /*
700 * The 3Com ASIC defaults to rather strange settings for the CR after
701 * a reset - it's important to set it again after the following
702 * outb (this is done when we map the PROM below).
703 */
704 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
705
706 /*
707 * Wait a bit for the NIC to recover from the reset
708 */
709 DELAY(5000);
710
711 sc->vendor = ED_VENDOR_3COM;
712 sc->type_str = "3c503";
713
714 sc->mem_shared = 1;
715
716 /*
717 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k
718 * window to it.
719 */
720 memsize = 8192;
721
722 /*
723 * Get station address from on-board ROM
724 */
725 /*
726 * First, map ethernet address PROM over the top of where the NIC
727 * registers normally appear.
728 */
729 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
730
731 for (i = 0; i < ETHER_ADDR_LEN; ++i)
732 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
733
734 /*
735 * Unmap PROM - select NIC registers. The proper setting of the
736 * tranceiver is set in ed_init so that the attach code
737 * is given a chance to set the default based on a compile-time
738 * config option
739 */
740 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
741
742 /*
743 * Determine if this is an 8bit or 16bit board
744 */
745
746 /*
747 * select page 0 registers
748 */
749 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
750
751 /*
752 * Attempt to clear WTS bit. If it doesn't clear, then this is a
753 * 16bit board.
754 */
755 outb(sc->nic_addr + ED_P0_DCR, 0);
756
757 /*
758 * select page 2 registers
759 */
760 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP);
761
762 /*
763 * The 3c503 forces the WTS bit to a one if this is a 16bit board
764 */
765 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
766 isa16bit = 1;
767 else
768 isa16bit = 0;
769
770 /*
771 * select page 0 registers
772 */
773 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP);
774
775 sc->mem_start = (caddr_t)isa_dev->id_maddr;
776 sc->mem_size = memsize;
777 sc->mem_end = sc->mem_start + memsize;
778
779 /*
780 * We have an entire 8k window to put the transmit buffers on the
781 * 16bit boards. But since the 16bit 3c503's shared memory
782 * is only fast enough to overlap the loading of one full-size
783 * packet, trying to load more than 2 buffers can actually
784 * leave the transmitter idle during the load. So 2 seems
785 * the best value. (Although a mix of variable-sized packets
786 * might change this assumption. Nonetheless, we optimize for
787 * linear transfers of same-size packets.)
788 */
789 if (isa16bit) {
790 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
791 sc->txb_cnt = 1;
792 else
793 sc->txb_cnt = 2;
794
795 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
796 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
797 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
798 ED_3COM_RX_PAGE_OFFSET_16BIT;
799 sc->mem_ring = sc->mem_start;
800 } else {
801 sc->txb_cnt = 1;
802 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
803 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
804 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
805 ED_3COM_TX_PAGE_OFFSET_8BIT;
806 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
807 }
808
809 sc->isa16bit = isa16bit;
810
811 /*
812 * Initialize GA page start/stop registers. Probably only needed
813 * if doing DMA, but what the hell.
814 */
815 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
816 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
817
818 /*
819 * Set IRQ. 3c503 only allows a choice of irq 2-5.
820 */
821 switch (isa_dev->id_irq) {
822 case IRQ2:
823 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
824 break;
825 case IRQ3:
826 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
827 break;
828 case IRQ4:
829 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
830 break;
831 case IRQ5:
832 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
833 break;
834 default:
835 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n",
836 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
837 return(0);
838 }
839
840 /*
841 * Initialize GA configuration register. Set bank and enable shared mem.
842 */
843 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
844 ED_3COM_GACFR_MBS0);
845
846 /*
847 * Initialize "Vector Pointer" registers. These gawd-awful things
848 * are compared to 20 bits of the address on ISA, and if they
849 * match, the shared memory is disabled. We set them to
850 * 0xffff0...allegedly the reset vector.
851 */
852 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
853 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
854 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
855
856 /*
857 * Zero memory and verify that it is clear
858 */
859 bzero(sc->mem_start, memsize);
860
861 for (i = 0; i < memsize; ++i)
862 if (sc->mem_start[i]) {
863 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
864 isa_dev->id_unit, kvtop(sc->mem_start + i));
865 return(0);
866 }
867
868 isa_dev->id_msize = memsize;
869 return(ED_3COM_IO_PORTS);
870}
871
872/*
873 * Probe and vendor-specific initialization routine for NE1000/2000 boards
874 */
875int
876ed_probe_Novell(isa_dev)
877 struct isa_device *isa_dev;
878{
879 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
880 u_int memsize, n;
881 u_char romdata[16], isa16bit = 0, tmp;
882 static char test_pattern[32] = "THIS is A memory TEST pattern";
883 char test_buffer[32];
884
885 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET;
886 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET;
887
888 /* XXX - do Novell-specific probe here */
889
890 /* Reset the board */
891 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
892
893#if 0
894 /*
895 * This total and completely screwy thing is to work around braindamage
896 * in some NE compatible boards. Why it works, I have *no* idea.
897 * It appears that the boards watch the ISA bus for an outb, and
898 * will lock up the ISA bus if they see an inb first. Weird.
899 */
900 outb(0x84, 0);
901#endif
902
903 /*
904 * I don't know if this is necessary; probably cruft leftover from
905 * Clarkson packet driver code. Doesn't do a thing on the boards
906 * I've tested. -DG [note that a outb(0x84, 0) seems to work
907 * here, and is non-invasive...but some boards don't seem to reset
908 * and I don't have complete documentation on what the 'right'
909 * thing to do is...so we do the invasive thing for now. Yuck.]
910 */
911 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
912 DELAY(5000);
913
914 /*
915 * This is needed because some NE clones apparently don't reset the
916 * NIC properly (or the NIC chip doesn't reset fully on power-up)
917 * XXX - this makes the probe invasive! ...Done against my better
918 * judgement. -DLG
919 */
920 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
921
922 DELAY(5000);
923
924 /* Make sure that we really have an 8390 based board */
925 if (!ed_probe_generic8390(sc))
926 return(0);
927
928 sc->vendor = ED_VENDOR_NOVELL;
929 sc->mem_shared = 0;
930 isa_dev->id_maddr = 0;
931
932 /*
933 * Test the ability to read and write to the NIC memory. This has
934 * the side affect of determining if this is an NE1000 or an NE2000.
935 */
936
937 /*
938 * This prevents packets from being stored in the NIC memory when
939 * the readmem routine turns on the start bit in the CR.
940 */
941 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
942
943 /* Temporarily initialize DCR for byte operations */
944 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
945
946 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
947 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
948
949 sc->isa16bit = 0;
950
951 /*
952 * Write a test pattern in byte mode. If this fails, then there
953 * probably isn't any memory at 8k - which likely means
954 * that the board is an NE2000.
955 */
956 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
957 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
958
959 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
960 /* not an NE1000 - try NE2000 */
961
962 outb(sc->nic_addr + ED_P0_DCR,
963 ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS);
964 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
965 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
966
967 sc->isa16bit = 1;
968 /*
969 * Write a test pattern in word mode. If this also fails, then
970 * we don't know what this board is.
971 */
972 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
973 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
974
975 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
976 return(0); /* not an NE2000 either */
977
978 sc->type = ED_TYPE_NE2000;
979 sc->type_str = "NE2000";
980 } else {
981 sc->type = ED_TYPE_NE1000;
982 sc->type_str = "NE1000";
983 }
984
985 /* 8k of memory plus an additional 8k if 16bit */
986 memsize = 8192 + sc->isa16bit * 8192;
987
988#if 0 /* probably not useful - NE boards only come two ways */
989 /* allow kernel config file overrides */
990 if (isa_dev->id_msize)
991 memsize = isa_dev->id_msize;
992#endif
993
994 sc->mem_size = memsize;
995
996 /* NIC memory doesn't start at zero on an NE board */
997 /* The start address is tied to the bus width */
998 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
999 sc->mem_end = sc->mem_start + memsize;
1000 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1001
1002 /*
1003 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1004 * otherwise).
1005 */
1006 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING))
1007 sc->txb_cnt = 1;
1008 else
1009 sc->txb_cnt = 2;
1010
1011 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1012 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1013
1014 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1015
1016 ed_pio_readmem(sc, 0, romdata, 16);
1017 for (n = 0; n < ETHER_ADDR_LEN; n++)
1018 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
1019
1020 /* clear any pending interrupts that might have occurred above */
1021 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1022
1023 return(ED_NOVELL_IO_PORTS);
1024}
1025
1026/*
1027 * Install interface into kernel networking data structures
1028 */
1029int
1030ed_attach(isa_dev)
1031 struct isa_device *isa_dev;
1032{
1033 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1034 struct ifnet *ifp = &sc->arpcom.ac_if;
1035 struct ifaddr *ifa;
1036 struct sockaddr_dl *sdl;
1037
1038 /*
1039 * Set interface to stopped condition (reset)
1040 */
1041 ed_stop(isa_dev->id_unit);
1042
1043 /*
1044 * Initialize ifnet structure
1045 */
1046 ifp->if_unit = isa_dev->id_unit;
1047 ifp->if_name = "ed" ;
1048 ifp->if_mtu = ETHERMTU;
1049 ifp->if_init = ed_init;
1050 ifp->if_output = ether_output;
1051 ifp->if_start = ed_start;
1052 ifp->if_ioctl = ed_ioctl;
1053 ifp->if_reset = ed_reset;
1054 ifp->if_watchdog = ed_watchdog;
1055
1056 /*
1057 * Set default state for ALTPHYS flag (used to disable the tranceiver
1058 * for AUI operation), based on compile-time config option.
1059 */
1060 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER)
1061 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS
1062 | IFF_ALTPHYS);
1063 else
1064 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
1065
1066 /*
1067 * Attach the interface
1068 */
1069 if_attach(ifp);
1070
1071 /*
1072 * Search down the ifa address list looking for the AF_LINK type entry
1073 */
1074 ifa = ifp->if_addrlist;
1075 while ((ifa != 0) && (ifa->ifa_addr != 0) &&
1076 (ifa->ifa_addr->sa_family != AF_LINK))
1077 ifa = ifa->ifa_next;
1078 /*
1079 * If we find an AF_LINK type entry we fill in the hardware address.
1080 * This is useful for netstat(1) to keep track of which interface
1081 * is which.
1082 */
1083 if ((ifa != 0) && (ifa->ifa_addr != 0)) {
1084 /*
1085 * Fill in the link-level address for this interface
1086 */
1087 sdl = (struct sockaddr_dl *)ifa->ifa_addr;
1088 sdl->sdl_type = IFT_ETHER;
1089 sdl->sdl_alen = ETHER_ADDR_LEN;
1090 sdl->sdl_slen = 0;
1091 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
1092 }
1093
1094 /*
1095 * Print additional info when attached
1096 */
1097 printf("ed%d: address %s, ", isa_dev->id_unit,
1098 ether_sprintf(sc->arpcom.ac_enaddr));
1099
1100 if (sc->type_str && (*sc->type_str != 0))
1101 printf("type %s ", sc->type_str);
1102 else
1103 printf("type unknown (0x%x) ", sc->type);
1104
1105 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)");
1106
1107 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) &&
1108 (ifp->if_flags & IFF_ALTPHYS)) ? "tranceiver disabled" : "");
1109
1110 /*
1111 * If BPF is in the kernel, call the attach for it
1112 */
1113#if NBPFILTER > 0
1114 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
1115#endif
| 199static inline void ed_rint();
200static inline void ed_xmit();
201static inline char *ed_ring_copy();
202
203void ed_pio_readmem(), ed_pio_writemem();
204u_short ed_pio_write_mbufs();
205
206extern int ether_output();
207
208struct trailer_header {
209 u_short ether_type;
210 u_short ether_residual;
211};
212
213struct isa_driver eddriver = {
214 ed_probe,
215 ed_attach,
216 "ed"
217};
218/*
219 * Interrupt conversion table for WD/SMC ASIC
220 * (IRQ* are defined in icu.h)
221 */
222static unsigned short ed_intr_mask[] = {
223 IRQ9,
224 IRQ3,
225 IRQ5,
226 IRQ7,
227 IRQ10,
228 IRQ11,
229 IRQ15,
230 IRQ4
231};
232
233/*
234 * Interrupt conversion table for 585/790 Combo
235 */
236static unsigned short ed_790_intr_mask[] = {
237 0,
238 IRQ9,
239 IRQ3,
240 IRQ4,
241 IRQ5,
242 IRQ10,
243 IRQ11,
244 IRQ15
245};
246#define ETHER_MIN_LEN 64
247#define ETHER_MAX_LEN 1518
248#define ETHER_ADDR_LEN 6
249#define ETHER_HDR_SIZE 14
250
251/*
252 * Determine if the device is present
253 *
254 * on entry:
255 * a pointer to an isa_device struct
256 * on exit:
257 * NULL if device not found
258 * or # of i/o addresses used (if found)
259 */
260int
261ed_probe(isa_dev)
262 struct isa_device *isa_dev;
263{
264 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
265 int nports;
266
267 if (nports = ed_probe_WD80x3(isa_dev))
268 return (nports);
269
270 if (nports = ed_probe_3Com(isa_dev))
271 return (nports);
272
273 if (nports = ed_probe_Novell(isa_dev))
274 return (nports);
275
276 return(0);
277}
278
279/*
280 * Generic probe routine for testing for the existance of a DS8390.
281 * Must be called after the NIC has just been reset. This routine
282 * works by looking at certain register values that are gauranteed
283 * to be initialized a certain way after power-up or reset. Seems
284 * not to currently work on the 83C690.
285 *
286 * Specifically:
287 *
288 * Register reset bits set bits
289 * Command Register (CR) TXP, STA RD2, STP
290 * Interrupt Status (ISR) RST
291 * Interrupt Mask (IMR) All bits
292 * Data Control (DCR) LAS
293 * Transmit Config. (TCR) LB1, LB0
294 *
295 * We only look at the CR and ISR registers, however, because looking at
296 * the others would require changing register pages (which would be
297 * intrusive if this isn't an 8390).
298 *
299 * Return 1 if 8390 was found, 0 if not.
300 */
301
302int
303ed_probe_generic8390(sc)
304 struct ed_softc *sc;
305{
306 if ((inb(sc->nic_addr + ED_P0_CR) &
307 (ED_CR_RD2|ED_CR_TXP|ED_CR_STA|ED_CR_STP)) !=
308 (ED_CR_RD2|ED_CR_STP))
309 return (0);
310 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
311 return (0);
312
313 return(1);
314}
315
316/*
317 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
318 */
319int
320ed_probe_WD80x3(isa_dev)
321 struct isa_device *isa_dev;
322{
323 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
324 int i;
325 u_int memsize;
326 u_char iptr, isa16bit, sum;
327
328 sc->asic_addr = isa_dev->id_iobase;
329 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
330 sc->is790 = 0;
331
332 /*
333 * Attempt to do a checksum over the station address PROM.
334 * If it fails, it's probably not a SMC/WD board. There
335 * is a problem with this, though: some clone WD boards
336 * don't pass the checksum test. Danpex boards for one.
337 */
338 for (sum = 0, i = 0; i < 8; ++i)
339 sum += inb(sc->asic_addr + ED_WD_PROM + i);
340
341 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
342 /*
343 * Checksum is invalid. This often happens with cheap
344 * WD8003E clones. In this case, the checksum byte
345 * (the eighth byte) seems to always be zero.
346 */
347 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
348 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
349 return(0);
350 }
351
352 /* reset card to force it into a known state. */
353 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
354 DELAY(100);
355 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
356 /* wait in the case this card is reading it's EEROM */
357 DELAY(5000);
358
359 sc->vendor = ED_VENDOR_WD_SMC;
360 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
361
362 /*
363 * Set initial values for width/size.
364 */
365 switch (sc->type) {
366 case ED_TYPE_WD8003S:
367 sc->type_str = "WD8003S";
368 memsize = 8192;
369 isa16bit = 0;
370 break;
371 case ED_TYPE_WD8003E:
372 sc->type_str = "WD8003E";
373 memsize = 8192;
374 isa16bit = 0;
375 break;
376 case ED_TYPE_WD8013EBT:
377 sc->type_str = "WD8013EBT";
378 memsize = 16384;
379 isa16bit = 1;
380 break;
381 case ED_TYPE_WD8013EP: /* also WD8003EP */
382 if (inb(sc->asic_addr + ED_WD_ICR)
383 & ED_WD_ICR_16BIT) {
384 isa16bit = 1;
385 memsize = 16384;
386 sc->type_str = "WD8013EP";
387 } else {
388 isa16bit = 0;
389 memsize = 8192;
390 sc->type_str = "WD8003EP";
391 }
392 break;
393 case ED_TYPE_WD8013WC:
394 sc->type_str = "WD8013WC";
395 memsize = 16384;
396 isa16bit = 1;
397 break;
398 case ED_TYPE_WD8013EBP:
399 sc->type_str = "WD8013EBP";
400 memsize = 16384;
401 isa16bit = 1;
402 break;
403 case ED_TYPE_WD8013EPC:
404 sc->type_str = "WD8013EPC";
405 memsize = 16384;
406 isa16bit = 1;
407 break;
408 case ED_TYPE_SMC8216C:
409 sc->type_str = "SMC8216/SMC8216C";
410 memsize = 16384;
411 isa16bit = 1;
412 sc->is790 = 1;
413 break;
414 case ED_TYPE_SMC8216T:
415 sc->type_str = "SMC8216T";
416 memsize = 16384;
417 isa16bit = 1;
418 sc->is790 = 1;
419 break;
420 default:
421 sc->type_str = "";
422 memsize = 8192;
423 isa16bit = 0;
424 break;
425 }
426 /*
427 * Make some adjustments to initial values depending on what is
428 * found in the ICR.
429 */
430 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
431 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
432 isa16bit = 0;
433 memsize = 8192;
434 }
435
436#if ED_DEBUG
437 printf("type=%s isa16bit=%d memsize=%d id_msize=%d\n",
438 sc->type_str,isa16bit,memsize,isa_dev->id_msize);
439 for (i=0; i<8; i++)
440 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
441#endif
442 /*
443 * Allow the user to override the autoconfiguration
444 */
445 if (isa_dev->id_msize)
446 memsize = isa_dev->id_msize;
447 /*
448 * (note that if the user specifies both of the following flags
449 * that '8bit' mode intentionally has precedence)
450 */
451 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
452 isa16bit = 1;
453 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
454 isa16bit = 0;
455
456 /*
457 * Check 83C584 interrupt configuration register if this board has one
458 * XXX - we could also check the IO address register. But why
459 * bother...if we get past this, it *has* to be correct.
460 */
461 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
462 /*
463 * Assemble together the encoded interrupt number.
464 */
465 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
466 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
467 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
468 /*
469 * Translate it using translation table, and check for correctness.
470 */
471 if (ed_intr_mask[iptr] != isa_dev->id_irq) {
472 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
473 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
474 return(0);
475 }
476 /*
477 * Enable the interrupt.
478 */
479 outb(isa_dev->id_iobase + ED_WD_IRR,
480 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
481 }
482 if (sc->is790) {
483 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
484 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
485 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
486 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
487
488 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
489 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
490 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
491 return 0;
492 }
493 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
494 }
495
496 sc->isa16bit = isa16bit;
497
498#ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */
499 /*
500 * The following allows the WD/SMC boards to be used in Programmed I/O
501 * mode - without mapping the NIC memory shared. ...Not the prefered
502 * way, but it might be the only way.
503 */
504 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) {
505 sc->mem_shared = 0;
506 isa_dev->id_maddr = 0;
507 } else {
508 sc->mem_shared = 1;
509 }
510#else
511 sc->mem_shared = 1;
512#endif
513 isa_dev->id_msize = memsize;
514
515 sc->mem_start = (caddr_t)isa_dev->id_maddr;
516
517 /*
518 * allocate one xmit buffer if < 16k, two buffers otherwise
519 */
520 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
521 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
522 sc->txb_cnt = 1;
523 sc->rec_page_start = ED_TXBUF_SIZE;
524 } else {
525 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2);
526 sc->txb_cnt = 2;
527 sc->rec_page_start = ED_TXBUF_SIZE * 2;
528 }
529 sc->mem_size = memsize;
530 sc->mem_end = sc->mem_start + memsize;
531 sc->rec_page_stop = memsize / ED_PAGE_SIZE;
532 sc->tx_page_start = ED_WD_PAGE_OFFSET;
533
534 /*
535 * Get station address from on-board ROM
536 */
537 for (i = 0; i < ETHER_ADDR_LEN; ++i)
538 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
539
540 if (sc->mem_shared) {
541 /*
542 * Set address and enable interface shared memory.
543 */
544 if(!sc->is790) {
545 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
546 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
547 } else {
548 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
549 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
550 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
551 ((kvtop(sc->mem_start) >> 11) & 0x40) |
552 (inb(sc->asic_addr + 0x0b) & 0xb0));
553 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
554 }
555
556 /*
557 * Set upper address bits and 8/16 bit access to shared memory
558 */
559 if (isa16bit) {
560 if (sc->is790) {
561 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
562 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
563 } else {
564 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
565 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
566 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
567 }
568 } else {
569 if ((sc->type & ED_WD_SOFTCONFIG) || (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) {
570 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
571 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
572 }
573 }
574
575 /*
576 * Now zero memory and verify that it is clear
577 */
578 bzero(sc->mem_start, memsize);
579
580 for (i = 0; i < memsize; ++i)
581 if (sc->mem_start[i]) {
582 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
583 isa_dev->id_unit, kvtop(sc->mem_start + i));
584
585 /*
586 * Disable 16 bit access to shared memory
587 */
588 if (isa16bit)
589 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
590 ~ED_WD_LAAR_M16EN));
591
592 return(0);
593 }
594
595 /*
596 * Disable 16bit access to shared memory - we leave it disabled so
597 * that 1) machines reboot properly when the board is set
598 * 16 bit mode and there are conflicting 8bit devices/ROMS
599 * in the same 128k address space as this boards shared
600 * memory. and 2) so that other 8 bit devices with shared
601 * memory can be used in this 128k region, too.
602 */
603 if (isa16bit)
604 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
605 ~ED_WD_LAAR_M16EN));
606
607 }
608
609 return (ED_WD_IO_PORTS);
610}
611
612/*
613 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
614 */
615int
616ed_probe_3Com(isa_dev)
617 struct isa_device *isa_dev;
618{
619 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
620 int i;
621 u_int memsize;
622 u_char isa16bit, sum;
623
624 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
625 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
626
627 /*
628 * Verify that the kernel configured I/O address matches the board
629 * configured address
630 */
631 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
632 case ED_3COM_BCFR_300:
633 if (isa_dev->id_iobase != 0x300)
634 return(0);
635 break;
636 case ED_3COM_BCFR_310:
637 if (isa_dev->id_iobase != 0x310)
638 return(0);
639 break;
640 case ED_3COM_BCFR_330:
641 if (isa_dev->id_iobase != 0x330)
642 return(0);
643 break;
644 case ED_3COM_BCFR_350:
645 if (isa_dev->id_iobase != 0x350)
646 return(0);
647 break;
648 case ED_3COM_BCFR_250:
649 if (isa_dev->id_iobase != 0x250)
650 return(0);
651 break;
652 case ED_3COM_BCFR_280:
653 if (isa_dev->id_iobase != 0x280)
654 return(0);
655 break;
656 case ED_3COM_BCFR_2A0:
657 if (isa_dev->id_iobase != 0x2a0)
658 return(0);
659 break;
660 case ED_3COM_BCFR_2E0:
661 if (isa_dev->id_iobase != 0x2e0)
662 return(0);
663 break;
664 default:
665 return(0);
666 }
667
668 /*
669 * Verify that the kernel shared memory address matches the
670 * board configured address.
671 */
672 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
673 case ED_3COM_PCFR_DC000:
674 if (kvtop(isa_dev->id_maddr) != 0xdc000)
675 return(0);
676 break;
677 case ED_3COM_PCFR_D8000:
678 if (kvtop(isa_dev->id_maddr) != 0xd8000)
679 return(0);
680 break;
681 case ED_3COM_PCFR_CC000:
682 if (kvtop(isa_dev->id_maddr) != 0xcc000)
683 return(0);
684 break;
685 case ED_3COM_PCFR_C8000:
686 if (kvtop(isa_dev->id_maddr) != 0xc8000)
687 return(0);
688 break;
689 default:
690 return(0);
691 }
692
693
694 /*
695 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
696 * sequence because it'll lock up if the cable isn't connected
697 * if we don't.
698 */
699 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
700
701 /*
702 * Wait for a while, then un-reset it
703 */
704 DELAY(50);
705 /*
706 * The 3Com ASIC defaults to rather strange settings for the CR after
707 * a reset - it's important to set it again after the following
708 * outb (this is done when we map the PROM below).
709 */
710 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
711
712 /*
713 * Wait a bit for the NIC to recover from the reset
714 */
715 DELAY(5000);
716
717 sc->vendor = ED_VENDOR_3COM;
718 sc->type_str = "3c503";
719
720 sc->mem_shared = 1;
721
722 /*
723 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k
724 * window to it.
725 */
726 memsize = 8192;
727
728 /*
729 * Get station address from on-board ROM
730 */
731 /*
732 * First, map ethernet address PROM over the top of where the NIC
733 * registers normally appear.
734 */
735 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
736
737 for (i = 0; i < ETHER_ADDR_LEN; ++i)
738 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
739
740 /*
741 * Unmap PROM - select NIC registers. The proper setting of the
742 * tranceiver is set in ed_init so that the attach code
743 * is given a chance to set the default based on a compile-time
744 * config option
745 */
746 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
747
748 /*
749 * Determine if this is an 8bit or 16bit board
750 */
751
752 /*
753 * select page 0 registers
754 */
755 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
756
757 /*
758 * Attempt to clear WTS bit. If it doesn't clear, then this is a
759 * 16bit board.
760 */
761 outb(sc->nic_addr + ED_P0_DCR, 0);
762
763 /*
764 * select page 2 registers
765 */
766 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP);
767
768 /*
769 * The 3c503 forces the WTS bit to a one if this is a 16bit board
770 */
771 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
772 isa16bit = 1;
773 else
774 isa16bit = 0;
775
776 /*
777 * select page 0 registers
778 */
779 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP);
780
781 sc->mem_start = (caddr_t)isa_dev->id_maddr;
782 sc->mem_size = memsize;
783 sc->mem_end = sc->mem_start + memsize;
784
785 /*
786 * We have an entire 8k window to put the transmit buffers on the
787 * 16bit boards. But since the 16bit 3c503's shared memory
788 * is only fast enough to overlap the loading of one full-size
789 * packet, trying to load more than 2 buffers can actually
790 * leave the transmitter idle during the load. So 2 seems
791 * the best value. (Although a mix of variable-sized packets
792 * might change this assumption. Nonetheless, we optimize for
793 * linear transfers of same-size packets.)
794 */
795 if (isa16bit) {
796 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
797 sc->txb_cnt = 1;
798 else
799 sc->txb_cnt = 2;
800
801 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
802 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
803 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
804 ED_3COM_RX_PAGE_OFFSET_16BIT;
805 sc->mem_ring = sc->mem_start;
806 } else {
807 sc->txb_cnt = 1;
808 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
809 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
810 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
811 ED_3COM_TX_PAGE_OFFSET_8BIT;
812 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
813 }
814
815 sc->isa16bit = isa16bit;
816
817 /*
818 * Initialize GA page start/stop registers. Probably only needed
819 * if doing DMA, but what the hell.
820 */
821 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
822 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
823
824 /*
825 * Set IRQ. 3c503 only allows a choice of irq 2-5.
826 */
827 switch (isa_dev->id_irq) {
828 case IRQ2:
829 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
830 break;
831 case IRQ3:
832 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
833 break;
834 case IRQ4:
835 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
836 break;
837 case IRQ5:
838 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
839 break;
840 default:
841 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n",
842 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
843 return(0);
844 }
845
846 /*
847 * Initialize GA configuration register. Set bank and enable shared mem.
848 */
849 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
850 ED_3COM_GACFR_MBS0);
851
852 /*
853 * Initialize "Vector Pointer" registers. These gawd-awful things
854 * are compared to 20 bits of the address on ISA, and if they
855 * match, the shared memory is disabled. We set them to
856 * 0xffff0...allegedly the reset vector.
857 */
858 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
859 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
860 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
861
862 /*
863 * Zero memory and verify that it is clear
864 */
865 bzero(sc->mem_start, memsize);
866
867 for (i = 0; i < memsize; ++i)
868 if (sc->mem_start[i]) {
869 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
870 isa_dev->id_unit, kvtop(sc->mem_start + i));
871 return(0);
872 }
873
874 isa_dev->id_msize = memsize;
875 return(ED_3COM_IO_PORTS);
876}
877
878/*
879 * Probe and vendor-specific initialization routine for NE1000/2000 boards
880 */
881int
882ed_probe_Novell(isa_dev)
883 struct isa_device *isa_dev;
884{
885 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
886 u_int memsize, n;
887 u_char romdata[16], isa16bit = 0, tmp;
888 static char test_pattern[32] = "THIS is A memory TEST pattern";
889 char test_buffer[32];
890
891 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET;
892 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET;
893
894 /* XXX - do Novell-specific probe here */
895
896 /* Reset the board */
897 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
898
899#if 0
900 /*
901 * This total and completely screwy thing is to work around braindamage
902 * in some NE compatible boards. Why it works, I have *no* idea.
903 * It appears that the boards watch the ISA bus for an outb, and
904 * will lock up the ISA bus if they see an inb first. Weird.
905 */
906 outb(0x84, 0);
907#endif
908
909 /*
910 * I don't know if this is necessary; probably cruft leftover from
911 * Clarkson packet driver code. Doesn't do a thing on the boards
912 * I've tested. -DG [note that a outb(0x84, 0) seems to work
913 * here, and is non-invasive...but some boards don't seem to reset
914 * and I don't have complete documentation on what the 'right'
915 * thing to do is...so we do the invasive thing for now. Yuck.]
916 */
917 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
918 DELAY(5000);
919
920 /*
921 * This is needed because some NE clones apparently don't reset the
922 * NIC properly (or the NIC chip doesn't reset fully on power-up)
923 * XXX - this makes the probe invasive! ...Done against my better
924 * judgement. -DLG
925 */
926 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
927
928 DELAY(5000);
929
930 /* Make sure that we really have an 8390 based board */
931 if (!ed_probe_generic8390(sc))
932 return(0);
933
934 sc->vendor = ED_VENDOR_NOVELL;
935 sc->mem_shared = 0;
936 isa_dev->id_maddr = 0;
937
938 /*
939 * Test the ability to read and write to the NIC memory. This has
940 * the side affect of determining if this is an NE1000 or an NE2000.
941 */
942
943 /*
944 * This prevents packets from being stored in the NIC memory when
945 * the readmem routine turns on the start bit in the CR.
946 */
947 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
948
949 /* Temporarily initialize DCR for byte operations */
950 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
951
952 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
953 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
954
955 sc->isa16bit = 0;
956
957 /*
958 * Write a test pattern in byte mode. If this fails, then there
959 * probably isn't any memory at 8k - which likely means
960 * that the board is an NE2000.
961 */
962 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
963 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
964
965 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
966 /* not an NE1000 - try NE2000 */
967
968 outb(sc->nic_addr + ED_P0_DCR,
969 ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS);
970 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
971 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
972
973 sc->isa16bit = 1;
974 /*
975 * Write a test pattern in word mode. If this also fails, then
976 * we don't know what this board is.
977 */
978 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
979 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
980
981 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
982 return(0); /* not an NE2000 either */
983
984 sc->type = ED_TYPE_NE2000;
985 sc->type_str = "NE2000";
986 } else {
987 sc->type = ED_TYPE_NE1000;
988 sc->type_str = "NE1000";
989 }
990
991 /* 8k of memory plus an additional 8k if 16bit */
992 memsize = 8192 + sc->isa16bit * 8192;
993
994#if 0 /* probably not useful - NE boards only come two ways */
995 /* allow kernel config file overrides */
996 if (isa_dev->id_msize)
997 memsize = isa_dev->id_msize;
998#endif
999
1000 sc->mem_size = memsize;
1001
1002 /* NIC memory doesn't start at zero on an NE board */
1003 /* The start address is tied to the bus width */
1004 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1005 sc->mem_end = sc->mem_start + memsize;
1006 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1007
1008 /*
1009 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1010 * otherwise).
1011 */
1012 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING))
1013 sc->txb_cnt = 1;
1014 else
1015 sc->txb_cnt = 2;
1016
1017 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1018 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1019
1020 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1021
1022 ed_pio_readmem(sc, 0, romdata, 16);
1023 for (n = 0; n < ETHER_ADDR_LEN; n++)
1024 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
1025
1026 /* clear any pending interrupts that might have occurred above */
1027 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1028
1029 return(ED_NOVELL_IO_PORTS);
1030}
1031
1032/*
1033 * Install interface into kernel networking data structures
1034 */
1035int
1036ed_attach(isa_dev)
1037 struct isa_device *isa_dev;
1038{
1039 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1040 struct ifnet *ifp = &sc->arpcom.ac_if;
1041 struct ifaddr *ifa;
1042 struct sockaddr_dl *sdl;
1043
1044 /*
1045 * Set interface to stopped condition (reset)
1046 */
1047 ed_stop(isa_dev->id_unit);
1048
1049 /*
1050 * Initialize ifnet structure
1051 */
1052 ifp->if_unit = isa_dev->id_unit;
1053 ifp->if_name = "ed" ;
1054 ifp->if_mtu = ETHERMTU;
1055 ifp->if_init = ed_init;
1056 ifp->if_output = ether_output;
1057 ifp->if_start = ed_start;
1058 ifp->if_ioctl = ed_ioctl;
1059 ifp->if_reset = ed_reset;
1060 ifp->if_watchdog = ed_watchdog;
1061
1062 /*
1063 * Set default state for ALTPHYS flag (used to disable the tranceiver
1064 * for AUI operation), based on compile-time config option.
1065 */
1066 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER)
1067 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS
1068 | IFF_ALTPHYS);
1069 else
1070 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
1071
1072 /*
1073 * Attach the interface
1074 */
1075 if_attach(ifp);
1076
1077 /*
1078 * Search down the ifa address list looking for the AF_LINK type entry
1079 */
1080 ifa = ifp->if_addrlist;
1081 while ((ifa != 0) && (ifa->ifa_addr != 0) &&
1082 (ifa->ifa_addr->sa_family != AF_LINK))
1083 ifa = ifa->ifa_next;
1084 /*
1085 * If we find an AF_LINK type entry we fill in the hardware address.
1086 * This is useful for netstat(1) to keep track of which interface
1087 * is which.
1088 */
1089 if ((ifa != 0) && (ifa->ifa_addr != 0)) {
1090 /*
1091 * Fill in the link-level address for this interface
1092 */
1093 sdl = (struct sockaddr_dl *)ifa->ifa_addr;
1094 sdl->sdl_type = IFT_ETHER;
1095 sdl->sdl_alen = ETHER_ADDR_LEN;
1096 sdl->sdl_slen = 0;
1097 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
1098 }
1099
1100 /*
1101 * Print additional info when attached
1102 */
1103 printf("ed%d: address %s, ", isa_dev->id_unit,
1104 ether_sprintf(sc->arpcom.ac_enaddr));
1105
1106 if (sc->type_str && (*sc->type_str != 0))
1107 printf("type %s ", sc->type_str);
1108 else
1109 printf("type unknown (0x%x) ", sc->type);
1110
1111 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)");
1112
1113 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) &&
1114 (ifp->if_flags & IFF_ALTPHYS)) ? "tranceiver disabled" : "");
1115
1116 /*
1117 * If BPF is in the kernel, call the attach for it
1118 */
1119#if NBPFILTER > 0
1120 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
1121#endif
|
1116
| 1122 return 1;
|
1117}
1118
1119/*
1120 * Reset interface.
1121 */
| 1123}
1124
1125/*
1126 * Reset interface.
1127 */
|
1122int
1123ed_reset(unit)
| 1128void
1129ed_reset(unit, uban)
|
1124 int unit;
| 1130 int unit;
|
| 1131 int uban; /* XXX */
|
1125{
1126 int s;
1127
1128 s = splimp();
1129
1130 /*
1131 * Stop interface and re-initialize.
1132 */
1133 ed_stop(unit);
1134 ed_init(unit);
1135
1136 (void) splx(s);
1137}
1138
1139/*
1140 * Take interface offline.
1141 */
1142void
1143ed_stop(unit)
1144 int unit;
1145{
1146 struct ed_softc *sc = &ed_softc[unit];
1147 int n = 5000;
1148
1149 /*
1150 * Stop everything on the interface, and select page 0 registers.
1151 */
1152 if (sc->is790) {
1153 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1154 } else {
1155 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1156 }
1157 /*
1158 * Wait for interface to enter stopped state, but limit # of checks
1159 * to 'n' (about 5ms). It shouldn't even take 5us on modern
1160 * DS8390's, but just in case it's an old one.
1161 */
1162 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1163
1164}
1165
1166/*
1167 * Device timeout/watchdog routine. Entered if the device neglects to
1168 * generate an interrupt after a transmit has been started on it.
1169 */
| 1132{
1133 int s;
1134
1135 s = splimp();
1136
1137 /*
1138 * Stop interface and re-initialize.
1139 */
1140 ed_stop(unit);
1141 ed_init(unit);
1142
1143 (void) splx(s);
1144}
1145
1146/*
1147 * Take interface offline.
1148 */
1149void
1150ed_stop(unit)
1151 int unit;
1152{
1153 struct ed_softc *sc = &ed_softc[unit];
1154 int n = 5000;
1155
1156 /*
1157 * Stop everything on the interface, and select page 0 registers.
1158 */
1159 if (sc->is790) {
1160 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1161 } else {
1162 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1163 }
1164 /*
1165 * Wait for interface to enter stopped state, but limit # of checks
1166 * to 'n' (about 5ms). It shouldn't even take 5us on modern
1167 * DS8390's, but just in case it's an old one.
1168 */
1169 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1170
1171}
1172
1173/*
1174 * Device timeout/watchdog routine. Entered if the device neglects to
1175 * generate an interrupt after a transmit has been started on it.
1176 */
|
1170int
| 1177void
|
1171ed_watchdog(unit)
1172 int unit;
1173{
1174 struct ed_softc *sc = &ed_softc[unit];
1175
1176 log(LOG_ERR, "ed%d: device timeout\n", unit);
1177 ++sc->arpcom.ac_if.if_oerrors;
1178
| 1178ed_watchdog(unit)
1179 int unit;
1180{
1181 struct ed_softc *sc = &ed_softc[unit];
1182
1183 log(LOG_ERR, "ed%d: device timeout\n", unit);
1184 ++sc->arpcom.ac_if.if_oerrors;
1185
|
1179 ed_reset(unit);
| 1186 ed_reset(unit, 0);
|
1180}
1181
1182/*
1183 * Initialize device.
1184 */
| 1187}
1188
1189/*
1190 * Initialize device.
1191 */
|
| 1192void
|
1185ed_init(unit)
1186 int unit;
1187{
1188 struct ed_softc *sc = &ed_softc[unit];
1189 struct ifnet *ifp = &sc->arpcom.ac_if;
1190 int i, s;
1191 u_char command;
1192
1193
1194 /* address not known */
1195 if (ifp->if_addrlist == (struct ifaddr *)0) return;
1196
1197 /*
1198 * Initialize the NIC in the exact order outlined in the NS manual.
1199 * This init procedure is "mandatory"...don't change what or when
1200 * things happen.
1201 */
1202 s = splimp();
1203
1204 /* reset transmitter flags */
1205 sc->xmit_busy = 0;
1206 sc->arpcom.ac_if.if_timer = 0;
1207
1208 sc->txb_inuse = 0;
1209 sc->txb_new = 0;
1210 sc->txb_next_tx = 0;
1211
1212 /* This variable is used below - don't move this assignment */
1213 sc->next_packet = sc->rec_page_start + 1;
1214
1215 /*
1216 * Set interface for page 0, Remote DMA complete, Stopped
1217 */
1218 if (sc->is790) {
1219 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1220 } else {
1221 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1222 }
1223 if (sc->isa16bit) {
1224 /*
1225 * Set FIFO threshold to 8, No auto-init Remote DMA,
1226 * byte order=80x86, word-wide DMA xfers,
1227 */
1228 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
1229 } else {
1230 /*
1231 * Same as above, but byte-wide DMA xfers
1232 */
1233 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
1234 }
1235
1236 /*
1237 * Clear Remote Byte Count Registers
1238 */
1239 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1240 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1241
1242 /*
1243 * Enable reception of broadcast packets
1244 */
1245 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1246
1247 /*
1248 * Place NIC in internal loopback mode
1249 */
1250 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1251
1252 /*
1253 * Initialize transmit/receive (ring-buffer) Page Start
1254 */
1255 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1256 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1257 /* Set lower bits of byte addressable framing to 0 */
1258 if (sc->is790)
1259 outb(sc->nic_addr + 0x09, 0);
1260
1261 /*
1262 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1263 */
1264 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1265 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1266
1267 /*
1268 * Clear all interrupts. A '1' in each bit position clears the
1269 * corresponding flag.
1270 */
1271 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1272
1273 /*
1274 * Enable the following interrupts: receive/transmit complete,
1275 * receive/transmit error, and Receiver OverWrite.
1276 *
1277 * Counter overflow and Remote DMA complete are *not* enabled.
1278 */
1279 outb(sc->nic_addr + ED_P0_IMR,
1280 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE);
1281
1282 /*
1283 * Program Command Register for page 1
1284 */
1285 if (sc->is790) {
1286 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP);
1287 } else {
1288 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP);
1289 }
1290 /*
1291 * Copy out our station address
1292 */
1293 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1294 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1295
1296#if NBPFILTER > 0
1297 /*
1298 * Initialize multicast address hashing registers to accept
1299 * all multicasts (only used when in promiscuous mode)
1300 */
1301 for (i = 0; i < 8; ++i)
1302 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
1303#endif
1304
1305 /*
1306 * Set Current Page pointer to next_packet (initialized above)
1307 */
1308 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1309
1310 /*
1311 * Set Command Register for page 0, Remote DMA complete,
1312 * and interface Start.
1313 */
1314 if (sc->is790) {
1315 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA);
1316 } else {
1317 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA);
1318 }
1319 /*
1320 * Take interface out of loopback
1321 */
1322 outb(sc->nic_addr + ED_P0_TCR, 0);
1323
1324 /*
1325 * If this is a 3Com board, the tranceiver must be software enabled
1326 * (there is no settable hardware default).
1327 */
1328 if (sc->vendor == ED_VENDOR_3COM) {
1329 if (ifp->if_flags & IFF_ALTPHYS) {
1330 outb(sc->asic_addr + ED_3COM_CR, 0);
1331 } else {
1332 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1333 }
1334 }
1335
1336 /*
1337 * Set 'running' flag, and clear output active flag.
1338 */
1339 ifp->if_flags |= IFF_RUNNING;
1340 ifp->if_flags &= ~IFF_OACTIVE;
1341
1342 /*
1343 * ...and attempt to start output
1344 */
1345 ed_start(ifp);
1346
1347 (void) splx(s);
1348}
1349
1350/*
1351 * This routine actually starts the transmission on the interface
1352 */
1353static inline void ed_xmit(ifp)
1354 struct ifnet *ifp;
1355{
1356 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1357 unsigned short len;
1358
1359 len = sc->txb_len[sc->txb_next_tx];
1360
1361 /*
1362 * Set NIC for page 0 register access
1363 */
1364 if (sc->is790) {
1365 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1366 } else {
1367 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1368 }
1369 /*
1370 * Set TX buffer start page
1371 */
1372 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1373 sc->txb_next_tx * ED_TXBUF_SIZE);
1374
1375 /*
1376 * Set TX length
1377 */
1378 outb(sc->nic_addr + ED_P0_TBCR0, len);
1379 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1380
1381 /*
1382 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1383 */
1384 if (sc->is790) {
1385 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA);
1386 } else {
1387 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
1388 }
1389 sc->xmit_busy = 1;
1390
1391 /*
1392 * Point to next transmit buffer slot and wrap if necessary.
1393 */
1394 sc->txb_next_tx++;
1395 if (sc->txb_next_tx == sc->txb_cnt)
1396 sc->txb_next_tx = 0;
1397
1398 /*
1399 * Set a timer just in case we never hear from the board again
1400 */
1401 ifp->if_timer = 2;
1402}
1403
1404/*
1405 * Start output on interface.
1406 * We make two assumptions here:
1407 * 1) that the current priority is set to splimp _before_ this code
1408 * is called *and* is returned to the appropriate priority after
1409 * return
1410 * 2) that the IFF_OACTIVE flag is checked before this code is called
1411 * (i.e. that the output part of the interface is idle)
1412 */
| 1193ed_init(unit)
1194 int unit;
1195{
1196 struct ed_softc *sc = &ed_softc[unit];
1197 struct ifnet *ifp = &sc->arpcom.ac_if;
1198 int i, s;
1199 u_char command;
1200
1201
1202 /* address not known */
1203 if (ifp->if_addrlist == (struct ifaddr *)0) return;
1204
1205 /*
1206 * Initialize the NIC in the exact order outlined in the NS manual.
1207 * This init procedure is "mandatory"...don't change what or when
1208 * things happen.
1209 */
1210 s = splimp();
1211
1212 /* reset transmitter flags */
1213 sc->xmit_busy = 0;
1214 sc->arpcom.ac_if.if_timer = 0;
1215
1216 sc->txb_inuse = 0;
1217 sc->txb_new = 0;
1218 sc->txb_next_tx = 0;
1219
1220 /* This variable is used below - don't move this assignment */
1221 sc->next_packet = sc->rec_page_start + 1;
1222
1223 /*
1224 * Set interface for page 0, Remote DMA complete, Stopped
1225 */
1226 if (sc->is790) {
1227 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1228 } else {
1229 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1230 }
1231 if (sc->isa16bit) {
1232 /*
1233 * Set FIFO threshold to 8, No auto-init Remote DMA,
1234 * byte order=80x86, word-wide DMA xfers,
1235 */
1236 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
1237 } else {
1238 /*
1239 * Same as above, but byte-wide DMA xfers
1240 */
1241 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
1242 }
1243
1244 /*
1245 * Clear Remote Byte Count Registers
1246 */
1247 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1248 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1249
1250 /*
1251 * Enable reception of broadcast packets
1252 */
1253 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1254
1255 /*
1256 * Place NIC in internal loopback mode
1257 */
1258 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1259
1260 /*
1261 * Initialize transmit/receive (ring-buffer) Page Start
1262 */
1263 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1264 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1265 /* Set lower bits of byte addressable framing to 0 */
1266 if (sc->is790)
1267 outb(sc->nic_addr + 0x09, 0);
1268
1269 /*
1270 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1271 */
1272 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1273 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1274
1275 /*
1276 * Clear all interrupts. A '1' in each bit position clears the
1277 * corresponding flag.
1278 */
1279 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1280
1281 /*
1282 * Enable the following interrupts: receive/transmit complete,
1283 * receive/transmit error, and Receiver OverWrite.
1284 *
1285 * Counter overflow and Remote DMA complete are *not* enabled.
1286 */
1287 outb(sc->nic_addr + ED_P0_IMR,
1288 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE);
1289
1290 /*
1291 * Program Command Register for page 1
1292 */
1293 if (sc->is790) {
1294 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP);
1295 } else {
1296 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP);
1297 }
1298 /*
1299 * Copy out our station address
1300 */
1301 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1302 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1303
1304#if NBPFILTER > 0
1305 /*
1306 * Initialize multicast address hashing registers to accept
1307 * all multicasts (only used when in promiscuous mode)
1308 */
1309 for (i = 0; i < 8; ++i)
1310 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
1311#endif
1312
1313 /*
1314 * Set Current Page pointer to next_packet (initialized above)
1315 */
1316 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1317
1318 /*
1319 * Set Command Register for page 0, Remote DMA complete,
1320 * and interface Start.
1321 */
1322 if (sc->is790) {
1323 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA);
1324 } else {
1325 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA);
1326 }
1327 /*
1328 * Take interface out of loopback
1329 */
1330 outb(sc->nic_addr + ED_P0_TCR, 0);
1331
1332 /*
1333 * If this is a 3Com board, the tranceiver must be software enabled
1334 * (there is no settable hardware default).
1335 */
1336 if (sc->vendor == ED_VENDOR_3COM) {
1337 if (ifp->if_flags & IFF_ALTPHYS) {
1338 outb(sc->asic_addr + ED_3COM_CR, 0);
1339 } else {
1340 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1341 }
1342 }
1343
1344 /*
1345 * Set 'running' flag, and clear output active flag.
1346 */
1347 ifp->if_flags |= IFF_RUNNING;
1348 ifp->if_flags &= ~IFF_OACTIVE;
1349
1350 /*
1351 * ...and attempt to start output
1352 */
1353 ed_start(ifp);
1354
1355 (void) splx(s);
1356}
1357
1358/*
1359 * This routine actually starts the transmission on the interface
1360 */
1361static inline void ed_xmit(ifp)
1362 struct ifnet *ifp;
1363{
1364 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1365 unsigned short len;
1366
1367 len = sc->txb_len[sc->txb_next_tx];
1368
1369 /*
1370 * Set NIC for page 0 register access
1371 */
1372 if (sc->is790) {
1373 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1374 } else {
1375 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1376 }
1377 /*
1378 * Set TX buffer start page
1379 */
1380 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1381 sc->txb_next_tx * ED_TXBUF_SIZE);
1382
1383 /*
1384 * Set TX length
1385 */
1386 outb(sc->nic_addr + ED_P0_TBCR0, len);
1387 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1388
1389 /*
1390 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1391 */
1392 if (sc->is790) {
1393 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA);
1394 } else {
1395 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
1396 }
1397 sc->xmit_busy = 1;
1398
1399 /*
1400 * Point to next transmit buffer slot and wrap if necessary.
1401 */
1402 sc->txb_next_tx++;
1403 if (sc->txb_next_tx == sc->txb_cnt)
1404 sc->txb_next_tx = 0;
1405
1406 /*
1407 * Set a timer just in case we never hear from the board again
1408 */
1409 ifp->if_timer = 2;
1410}
1411
1412/*
1413 * Start output on interface.
1414 * We make two assumptions here:
1415 * 1) that the current priority is set to splimp _before_ this code
1416 * is called *and* is returned to the appropriate priority after
1417 * return
1418 * 2) that the IFF_OACTIVE flag is checked before this code is called
1419 * (i.e. that the output part of the interface is idle)
1420 */
|
1413int
| 1421void
|
1414ed_start(ifp)
1415 struct ifnet *ifp;
1416{
1417 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1418 struct mbuf *m0, *m;
1419 caddr_t buffer;
1420 int len;
1421
1422outloop:
1423 /*
1424 * First, see if there are buffered packets and an idle
1425 * transmitter - should never happen at this point.
1426 */
1427 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1428 printf("ed: packets buffers, but transmitter idle\n");
1429 ed_xmit(ifp);
1430 }
1431
1432 /*
1433 * See if there is room to put another packet in the buffer.
1434 */
1435 if (sc->txb_inuse == sc->txb_cnt) {
1436 /*
1437 * No room. Indicate this to the outside world
1438 * and exit.
1439 */
1440 ifp->if_flags |= IFF_OACTIVE;
1441 return;
1442 }
1443
1444 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
1445 if (m == 0) {
1446 /*
1447 * We are using the !OACTIVE flag to indicate to the outside
1448 * world that we can accept an additional packet rather than
1449 * that the transmitter is _actually_ active. Indeed, the
1450 * transmitter may be active, but if we haven't filled all
1451 * the buffers with data then we still want to accept more.
1452 */
1453 ifp->if_flags &= ~IFF_OACTIVE;
1454 return;
1455 }
1456
1457 /*
1458 * Copy the mbuf chain into the transmit buffer
1459 */
1460
1461 m0 = m;
1462
1463 /* txb_new points to next open buffer slot */
1464 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
1465
1466 if (sc->mem_shared) {
1467 /*
1468 * Special case setup for 16 bit boards...
1469 */
1470 if (sc->isa16bit) {
1471 switch (sc->vendor) {
1472 /*
1473 * For 16bit 3Com boards (which have 16k of memory),
1474 * we have the xmit buffers in a different page
1475 * of memory ('page 0') - so change pages.
1476 */
1477 case ED_VENDOR_3COM:
1478 outb(sc->asic_addr + ED_3COM_GACFR,
1479 ED_3COM_GACFR_RSEL);
1480 break;
1481 /*
1482 * Enable 16bit access to shared memory on WD/SMC boards
1483 * Don't update wd_laar_proto because we want to restore the
1484 * previous state (because an arp reply in the input code
1485 * may cause a call-back to ed_start)
1486 * XXX - the call-back to 'start' is a bug, IMHO.
1487 */
1488 case ED_VENDOR_WD_SMC:
1489 outb(sc->asic_addr + ED_WD_LAAR,
1490 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
1491 }
1492 }
1493
1494 for (len = 0; m != 0; m = m->m_next) {
1495 bcopy(mtod(m, caddr_t), buffer, m->m_len);
1496 buffer += m->m_len;
1497 len += m->m_len;
1498 }
1499
1500 /*
1501 * Restore previous shared memory access
1502 */
1503 if (sc->isa16bit) {
1504 switch (sc->vendor) {
1505 case ED_VENDOR_3COM:
1506 outb(sc->asic_addr + ED_3COM_GACFR,
1507 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1508 break;
1509 case ED_VENDOR_WD_SMC:
1510 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
1511 break;
1512 }
1513 }
1514 } else {
1515 len = ed_pio_write_mbufs(sc, m, buffer);
1516 }
1517
1518 sc->txb_len[sc->txb_new] = MAX(len, ETHER_MIN_LEN);
1519
1520 sc->txb_inuse++;
1521
1522 /*
1523 * Point to next buffer slot and wrap if necessary.
1524 */
1525 sc->txb_new++;
1526 if (sc->txb_new == sc->txb_cnt)
1527 sc->txb_new = 0;
1528
1529 if (sc->xmit_busy == 0)
1530 ed_xmit(ifp);
1531 /*
1532 * If there is BPF support in the configuration, tap off here.
1533 * The following has support for converting trailer packets
1534 * back to normal.
1535 * XXX - support for trailer packets in BPF should be moved into
1536 * the bpf code proper to avoid code duplication in all of
1537 * the drivers.
1538 */
1539#if NBPFILTER > 0
1540 if (sc->bpf) {
1541 u_short etype;
1542 int off, datasize, resid;
1543 struct ether_header *eh;
1544 struct trailer_header trailer_header;
1545 char ether_packet[ETHER_MAX_LEN];
1546 char *ep;
1547
1548 ep = ether_packet;
1549
1550 /*
1551 * We handle trailers below:
1552 * Copy ether header first, then residual data,
1553 * then data. Put all this in a temporary buffer
1554 * 'ether_packet' and send off to bpf. Since the
1555 * system has generated this packet, we assume
1556 * that all of the offsets in the packet are
1557 * correct; if they're not, the system will almost
1558 * certainly crash in m_copydata.
1559 * We make no assumptions about how the data is
1560 * arranged in the mbuf chain (i.e. how much
1561 * data is in each mbuf, if mbuf clusters are
1562 * used, etc.), which is why we use m_copydata
1563 * to get the ether header rather than assume
1564 * that this is located in the first mbuf.
1565 */
1566 /* copy ether header */
1567 m_copydata(m0, 0, sizeof(struct ether_header), ep);
1568 eh = (struct ether_header *) ep;
1569 ep += sizeof(struct ether_header);
1570 etype = ntohs(eh->ether_type);
1571 if (etype >= ETHERTYPE_TRAIL &&
1572 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
1573 datasize = ((etype - ETHERTYPE_TRAIL) << 9);
1574 off = datasize + sizeof(struct ether_header);
1575
1576 /* copy trailer_header into a data structure */
1577 m_copydata(m0, off, sizeof(struct trailer_header),
1578 &trailer_header.ether_type);
1579
1580 /* copy residual data */
1581 m_copydata(m0, off+sizeof(struct trailer_header),
1582 resid = ntohs(trailer_header.ether_residual) -
1583 sizeof(struct trailer_header), ep);
1584 ep += resid;
1585
1586 /* copy data */
1587 m_copydata(m0, sizeof(struct ether_header),
1588 datasize, ep);
1589 ep += datasize;
1590
1591 /* restore original ether packet type */
1592 eh->ether_type = trailer_header.ether_type;
1593
1594 bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
1595 } else
1596 bpf_mtap(sc->bpf, m0);
1597 }
1598#endif
1599
1600 m_freem(m0);
1601
1602 /*
1603 * Loop back to the top to possibly buffer more packets
1604 */
1605 goto outloop;
1606}
1607
1608/*
1609 * Ethernet interface receiver interrupt.
1610 */
1611static inline void
1612ed_rint(unit)
1613 int unit;
1614{
1615 register struct ed_softc *sc = &ed_softc[unit];
1616 u_char boundry, current;
1617 u_short len;
1618 struct ed_ring packet_hdr;
1619 char *packet_ptr;
1620
1621 /*
1622 * Set NIC to page 1 registers to get 'current' pointer
1623 */
1624 if (sc->is790) {
1625 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1626 } else {
1627 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1628 }
1629 /*
1630 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
1631 * it points to where new data has been buffered. The 'CURR'
1632 * (current) register points to the logical end of the ring-buffer
1633 * - i.e. it points to where additional new data will be added.
1634 * We loop here until the logical beginning equals the logical
1635 * end (or in other words, until the ring-buffer is empty).
1636 */
1637 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
1638
1639 /* get pointer to this buffer's header structure */
1640 packet_ptr = sc->mem_ring +
1641 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
1642
1643 /*
1644 * The byte count includes the FCS - Frame Check Sequence (a
1645 * 32 bit CRC).
1646 */
1647 if (sc->mem_shared)
1648 packet_hdr = *(struct ed_ring *)packet_ptr;
1649 else
1650 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr,
1651 sizeof(packet_hdr));
1652 len = packet_hdr.count;
1653 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
1654 /*
1655 * Go get packet. len - 4 removes CRC from length.
1656 */
1657 ed_get_packet(sc, packet_ptr + 4, len - 4);
1658 ++sc->arpcom.ac_if.if_ipackets;
1659 } else {
1660 /*
1661 * Really BAD...probably indicates that the ring pointers
1662 * are corrupted. Also seen on early rev chips under
1663 * high load - the byte order of the length gets switched.
1664 */
1665 log(LOG_ERR,
1666 "ed%d: NIC memory corrupt - invalid packet length %d\n",
1667 unit, len);
1668 ++sc->arpcom.ac_if.if_ierrors;
| 1422ed_start(ifp)
1423 struct ifnet *ifp;
1424{
1425 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1426 struct mbuf *m0, *m;
1427 caddr_t buffer;
1428 int len;
1429
1430outloop:
1431 /*
1432 * First, see if there are buffered packets and an idle
1433 * transmitter - should never happen at this point.
1434 */
1435 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1436 printf("ed: packets buffers, but transmitter idle\n");
1437 ed_xmit(ifp);
1438 }
1439
1440 /*
1441 * See if there is room to put another packet in the buffer.
1442 */
1443 if (sc->txb_inuse == sc->txb_cnt) {
1444 /*
1445 * No room. Indicate this to the outside world
1446 * and exit.
1447 */
1448 ifp->if_flags |= IFF_OACTIVE;
1449 return;
1450 }
1451
1452 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
1453 if (m == 0) {
1454 /*
1455 * We are using the !OACTIVE flag to indicate to the outside
1456 * world that we can accept an additional packet rather than
1457 * that the transmitter is _actually_ active. Indeed, the
1458 * transmitter may be active, but if we haven't filled all
1459 * the buffers with data then we still want to accept more.
1460 */
1461 ifp->if_flags &= ~IFF_OACTIVE;
1462 return;
1463 }
1464
1465 /*
1466 * Copy the mbuf chain into the transmit buffer
1467 */
1468
1469 m0 = m;
1470
1471 /* txb_new points to next open buffer slot */
1472 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
1473
1474 if (sc->mem_shared) {
1475 /*
1476 * Special case setup for 16 bit boards...
1477 */
1478 if (sc->isa16bit) {
1479 switch (sc->vendor) {
1480 /*
1481 * For 16bit 3Com boards (which have 16k of memory),
1482 * we have the xmit buffers in a different page
1483 * of memory ('page 0') - so change pages.
1484 */
1485 case ED_VENDOR_3COM:
1486 outb(sc->asic_addr + ED_3COM_GACFR,
1487 ED_3COM_GACFR_RSEL);
1488 break;
1489 /*
1490 * Enable 16bit access to shared memory on WD/SMC boards
1491 * Don't update wd_laar_proto because we want to restore the
1492 * previous state (because an arp reply in the input code
1493 * may cause a call-back to ed_start)
1494 * XXX - the call-back to 'start' is a bug, IMHO.
1495 */
1496 case ED_VENDOR_WD_SMC:
1497 outb(sc->asic_addr + ED_WD_LAAR,
1498 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
1499 }
1500 }
1501
1502 for (len = 0; m != 0; m = m->m_next) {
1503 bcopy(mtod(m, caddr_t), buffer, m->m_len);
1504 buffer += m->m_len;
1505 len += m->m_len;
1506 }
1507
1508 /*
1509 * Restore previous shared memory access
1510 */
1511 if (sc->isa16bit) {
1512 switch (sc->vendor) {
1513 case ED_VENDOR_3COM:
1514 outb(sc->asic_addr + ED_3COM_GACFR,
1515 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1516 break;
1517 case ED_VENDOR_WD_SMC:
1518 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
1519 break;
1520 }
1521 }
1522 } else {
1523 len = ed_pio_write_mbufs(sc, m, buffer);
1524 }
1525
1526 sc->txb_len[sc->txb_new] = MAX(len, ETHER_MIN_LEN);
1527
1528 sc->txb_inuse++;
1529
1530 /*
1531 * Point to next buffer slot and wrap if necessary.
1532 */
1533 sc->txb_new++;
1534 if (sc->txb_new == sc->txb_cnt)
1535 sc->txb_new = 0;
1536
1537 if (sc->xmit_busy == 0)
1538 ed_xmit(ifp);
1539 /*
1540 * If there is BPF support in the configuration, tap off here.
1541 * The following has support for converting trailer packets
1542 * back to normal.
1543 * XXX - support for trailer packets in BPF should be moved into
1544 * the bpf code proper to avoid code duplication in all of
1545 * the drivers.
1546 */
1547#if NBPFILTER > 0
1548 if (sc->bpf) {
1549 u_short etype;
1550 int off, datasize, resid;
1551 struct ether_header *eh;
1552 struct trailer_header trailer_header;
1553 char ether_packet[ETHER_MAX_LEN];
1554 char *ep;
1555
1556 ep = ether_packet;
1557
1558 /*
1559 * We handle trailers below:
1560 * Copy ether header first, then residual data,
1561 * then data. Put all this in a temporary buffer
1562 * 'ether_packet' and send off to bpf. Since the
1563 * system has generated this packet, we assume
1564 * that all of the offsets in the packet are
1565 * correct; if they're not, the system will almost
1566 * certainly crash in m_copydata.
1567 * We make no assumptions about how the data is
1568 * arranged in the mbuf chain (i.e. how much
1569 * data is in each mbuf, if mbuf clusters are
1570 * used, etc.), which is why we use m_copydata
1571 * to get the ether header rather than assume
1572 * that this is located in the first mbuf.
1573 */
1574 /* copy ether header */
1575 m_copydata(m0, 0, sizeof(struct ether_header), ep);
1576 eh = (struct ether_header *) ep;
1577 ep += sizeof(struct ether_header);
1578 etype = ntohs(eh->ether_type);
1579 if (etype >= ETHERTYPE_TRAIL &&
1580 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
1581 datasize = ((etype - ETHERTYPE_TRAIL) << 9);
1582 off = datasize + sizeof(struct ether_header);
1583
1584 /* copy trailer_header into a data structure */
1585 m_copydata(m0, off, sizeof(struct trailer_header),
1586 &trailer_header.ether_type);
1587
1588 /* copy residual data */
1589 m_copydata(m0, off+sizeof(struct trailer_header),
1590 resid = ntohs(trailer_header.ether_residual) -
1591 sizeof(struct trailer_header), ep);
1592 ep += resid;
1593
1594 /* copy data */
1595 m_copydata(m0, sizeof(struct ether_header),
1596 datasize, ep);
1597 ep += datasize;
1598
1599 /* restore original ether packet type */
1600 eh->ether_type = trailer_header.ether_type;
1601
1602 bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
1603 } else
1604 bpf_mtap(sc->bpf, m0);
1605 }
1606#endif
1607
1608 m_freem(m0);
1609
1610 /*
1611 * Loop back to the top to possibly buffer more packets
1612 */
1613 goto outloop;
1614}
1615
1616/*
1617 * Ethernet interface receiver interrupt.
1618 */
1619static inline void
1620ed_rint(unit)
1621 int unit;
1622{
1623 register struct ed_softc *sc = &ed_softc[unit];
1624 u_char boundry, current;
1625 u_short len;
1626 struct ed_ring packet_hdr;
1627 char *packet_ptr;
1628
1629 /*
1630 * Set NIC to page 1 registers to get 'current' pointer
1631 */
1632 if (sc->is790) {
1633 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1634 } else {
1635 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1636 }
1637 /*
1638 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
1639 * it points to where new data has been buffered. The 'CURR'
1640 * (current) register points to the logical end of the ring-buffer
1641 * - i.e. it points to where additional new data will be added.
1642 * We loop here until the logical beginning equals the logical
1643 * end (or in other words, until the ring-buffer is empty).
1644 */
1645 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
1646
1647 /* get pointer to this buffer's header structure */
1648 packet_ptr = sc->mem_ring +
1649 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
1650
1651 /*
1652 * The byte count includes the FCS - Frame Check Sequence (a
1653 * 32 bit CRC).
1654 */
1655 if (sc->mem_shared)
1656 packet_hdr = *(struct ed_ring *)packet_ptr;
1657 else
1658 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr,
1659 sizeof(packet_hdr));
1660 len = packet_hdr.count;
1661 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
1662 /*
1663 * Go get packet. len - 4 removes CRC from length.
1664 */
1665 ed_get_packet(sc, packet_ptr + 4, len - 4);
1666 ++sc->arpcom.ac_if.if_ipackets;
1667 } else {
1668 /*
1669 * Really BAD...probably indicates that the ring pointers
1670 * are corrupted. Also seen on early rev chips under
1671 * high load - the byte order of the length gets switched.
1672 */
1673 log(LOG_ERR,
1674 "ed%d: NIC memory corrupt - invalid packet length %d\n",
1675 unit, len);
1676 ++sc->arpcom.ac_if.if_ierrors;
|
1669 ed_reset(unit);
| 1677 ed_reset(unit, 0);
|
1670 return;
1671 }
1672
1673 /*
1674 * Update next packet pointer
1675 */
1676 sc->next_packet = packet_hdr.next_packet;
1677
1678 /*
1679 * Update NIC boundry pointer - being careful to keep it
1680 * one buffer behind. (as recommended by NS databook)
1681 */
1682 boundry = sc->next_packet - 1;
1683 if (boundry < sc->rec_page_start)
1684 boundry = sc->rec_page_stop - 1;
1685
1686 /*
1687 * Set NIC to page 0 registers to update boundry register
1688 */
1689 if (sc->is790) {
1690 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1691 } else {
1692 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1693 }
1694 outb(sc->nic_addr + ED_P0_BNRY, boundry);
1695
1696 /*
1697 * Set NIC to page 1 registers before looping to top (prepare to
1698 * get 'CURR' current pointer)
1699 */
1700 if (sc->is790) {
1701 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1702 } else {
1703 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1704 }
1705 }
1706}
1707
1708/*
1709 * Ethernet interface interrupt processor
1710 */
| 1678 return;
1679 }
1680
1681 /*
1682 * Update next packet pointer
1683 */
1684 sc->next_packet = packet_hdr.next_packet;
1685
1686 /*
1687 * Update NIC boundry pointer - being careful to keep it
1688 * one buffer behind. (as recommended by NS databook)
1689 */
1690 boundry = sc->next_packet - 1;
1691 if (boundry < sc->rec_page_start)
1692 boundry = sc->rec_page_stop - 1;
1693
1694 /*
1695 * Set NIC to page 0 registers to update boundry register
1696 */
1697 if (sc->is790) {
1698 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1699 } else {
1700 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1701 }
1702 outb(sc->nic_addr + ED_P0_BNRY, boundry);
1703
1704 /*
1705 * Set NIC to page 1 registers before looping to top (prepare to
1706 * get 'CURR' current pointer)
1707 */
1708 if (sc->is790) {
1709 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1710 } else {
1711 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1712 }
1713 }
1714}
1715
1716/*
1717 * Ethernet interface interrupt processor
1718 */
|
1711int
| 1719void
|
1712edintr(unit)
1713 int unit;
1714{
1715 struct ed_softc *sc = &ed_softc[unit];
1716 u_char isr;
1717
1718 /*
1719 * Set NIC to page 0 registers
1720 */
1721 if (sc->is790) {
1722 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1723 } else {
1724 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1725 }
1726 /*
1727 * loop until there are no more new interrupts
1728 */
1729 while (isr = inb(sc->nic_addr + ED_P0_ISR)) {
1730
1731 /*
1732 * reset all the bits that we are 'acknowledging'
1733 * by writing a '1' to each bit position that was set
1734 * (writing a '1' *clears* the bit)
1735 */
1736 outb(sc->nic_addr + ED_P0_ISR, isr);
1737
1738 /*
1739 * Handle transmitter interrupts. Handle these first
1740 * because the receiver will reset the board under
1741 * some conditions.
1742 */
1743 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) {
1744 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
1745
1746 /*
1747 * Check for transmit error. If a TX completed with an
1748 * error, we end up throwing the packet away. Really
1749 * the only error that is possible is excessive
1750 * collisions, and in this case it is best to allow the
1751 * automatic mechanisms of TCP to backoff the flow. Of
1752 * course, with UDP we're screwed, but this is expected
1753 * when a network is heavily loaded.
1754 */
1755 (void) inb(sc->nic_addr + ED_P0_TSR);
1756 if (isr & ED_ISR_TXE) {
1757
1758 /*
1759 * Excessive collisions (16)
1760 */
1761 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT)
1762 && (collisions == 0)) {
1763 /*
1764 * When collisions total 16, the
1765 * P0_NCR will indicate 0, and the
1766 * TSR_ABT is set.
1767 */
1768 collisions = 16;
1769 }
1770
1771 /*
1772 * update output errors counter
1773 */
1774 ++sc->arpcom.ac_if.if_oerrors;
1775 } else {
1776 /*
1777 * Update total number of successfully
1778 * transmitted packets.
1779 */
1780 ++sc->arpcom.ac_if.if_opackets;
1781 }
1782
1783 /*
1784 * reset tx busy and output active flags
1785 */
1786 sc->xmit_busy = 0;
1787 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1788
1789 /*
1790 * clear watchdog timer
1791 */
1792 sc->arpcom.ac_if.if_timer = 0;
1793
1794 /*
1795 * Add in total number of collisions on last
1796 * transmission.
1797 */
1798 sc->arpcom.ac_if.if_collisions += collisions;
1799
1800 /*
1801 * Decrement buffer in-use count if not zero (can only
1802 * be zero if a transmitter interrupt occured while
1803 * not actually transmitting).
1804 * If data is ready to transmit, start it transmitting,
1805 * otherwise defer until after handling receiver
1806 */
1807 if (sc->txb_inuse && --sc->txb_inuse)
1808 ed_xmit(&sc->arpcom.ac_if);
1809 }
1810
1811 /*
1812 * Handle receiver interrupts
1813 */
1814 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) {
1815 /*
1816 * Overwrite warning. In order to make sure that a lockup
1817 * of the local DMA hasn't occurred, we reset and
1818 * re-init the NIC. The NSC manual suggests only a
1819 * partial reset/re-init is necessary - but some
1820 * chips seem to want more. The DMA lockup has been
1821 * seen only with early rev chips - Methinks this
1822 * bug was fixed in later revs. -DG
1823 */
1824 if (isr & ED_ISR_OVW) {
1825 ++sc->arpcom.ac_if.if_ierrors;
1826#ifdef DIAGNOSTIC
1827 log(LOG_WARNING,
1828 "ed%d: warning - receiver ring buffer overrun\n",
1829 unit);
1830#endif
1831 /*
1832 * Stop/reset/re-init NIC
1833 */
| 1720edintr(unit)
1721 int unit;
1722{
1723 struct ed_softc *sc = &ed_softc[unit];
1724 u_char isr;
1725
1726 /*
1727 * Set NIC to page 0 registers
1728 */
1729 if (sc->is790) {
1730 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1731 } else {
1732 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1733 }
1734 /*
1735 * loop until there are no more new interrupts
1736 */
1737 while (isr = inb(sc->nic_addr + ED_P0_ISR)) {
1738
1739 /*
1740 * reset all the bits that we are 'acknowledging'
1741 * by writing a '1' to each bit position that was set
1742 * (writing a '1' *clears* the bit)
1743 */
1744 outb(sc->nic_addr + ED_P0_ISR, isr);
1745
1746 /*
1747 * Handle transmitter interrupts. Handle these first
1748 * because the receiver will reset the board under
1749 * some conditions.
1750 */
1751 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) {
1752 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
1753
1754 /*
1755 * Check for transmit error. If a TX completed with an
1756 * error, we end up throwing the packet away. Really
1757 * the only error that is possible is excessive
1758 * collisions, and in this case it is best to allow the
1759 * automatic mechanisms of TCP to backoff the flow. Of
1760 * course, with UDP we're screwed, but this is expected
1761 * when a network is heavily loaded.
1762 */
1763 (void) inb(sc->nic_addr + ED_P0_TSR);
1764 if (isr & ED_ISR_TXE) {
1765
1766 /*
1767 * Excessive collisions (16)
1768 */
1769 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT)
1770 && (collisions == 0)) {
1771 /*
1772 * When collisions total 16, the
1773 * P0_NCR will indicate 0, and the
1774 * TSR_ABT is set.
1775 */
1776 collisions = 16;
1777 }
1778
1779 /*
1780 * update output errors counter
1781 */
1782 ++sc->arpcom.ac_if.if_oerrors;
1783 } else {
1784 /*
1785 * Update total number of successfully
1786 * transmitted packets.
1787 */
1788 ++sc->arpcom.ac_if.if_opackets;
1789 }
1790
1791 /*
1792 * reset tx busy and output active flags
1793 */
1794 sc->xmit_busy = 0;
1795 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1796
1797 /*
1798 * clear watchdog timer
1799 */
1800 sc->arpcom.ac_if.if_timer = 0;
1801
1802 /*
1803 * Add in total number of collisions on last
1804 * transmission.
1805 */
1806 sc->arpcom.ac_if.if_collisions += collisions;
1807
1808 /*
1809 * Decrement buffer in-use count if not zero (can only
1810 * be zero if a transmitter interrupt occured while
1811 * not actually transmitting).
1812 * If data is ready to transmit, start it transmitting,
1813 * otherwise defer until after handling receiver
1814 */
1815 if (sc->txb_inuse && --sc->txb_inuse)
1816 ed_xmit(&sc->arpcom.ac_if);
1817 }
1818
1819 /*
1820 * Handle receiver interrupts
1821 */
1822 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) {
1823 /*
1824 * Overwrite warning. In order to make sure that a lockup
1825 * of the local DMA hasn't occurred, we reset and
1826 * re-init the NIC. The NSC manual suggests only a
1827 * partial reset/re-init is necessary - but some
1828 * chips seem to want more. The DMA lockup has been
1829 * seen only with early rev chips - Methinks this
1830 * bug was fixed in later revs. -DG
1831 */
1832 if (isr & ED_ISR_OVW) {
1833 ++sc->arpcom.ac_if.if_ierrors;
1834#ifdef DIAGNOSTIC
1835 log(LOG_WARNING,
1836 "ed%d: warning - receiver ring buffer overrun\n",
1837 unit);
1838#endif
1839 /*
1840 * Stop/reset/re-init NIC
1841 */
|
1834 ed_reset(unit);
| 1842 ed_reset(unit, 0);
|
1835 } else {
1836
1837 /*
1838 * Receiver Error. One or more of: CRC error, frame
1839 * alignment error FIFO overrun, or missed packet.
1840 */
1841 if (isr & ED_ISR_RXE) {
1842 ++sc->arpcom.ac_if.if_ierrors;
1843#ifdef ED_DEBUG
1844 printf("ed%d: receive error %x\n", unit,
1845 inb(sc->nic_addr + ED_P0_RSR));
1846#endif
1847 }
1848
1849 /*
1850 * Go get the packet(s)
1851 * XXX - Doing this on an error is dubious
1852 * because there shouldn't be any data to
1853 * get (we've configured the interface to
1854 * not accept packets with errors).
1855 */
1856
1857 /*
1858 * Enable 16bit access to shared memory first
1859 * on WD/SMC boards.
1860 */
1861 if (sc->isa16bit &&
1862 (sc->vendor == ED_VENDOR_WD_SMC)) {
1863
1864 outb(sc->asic_addr + ED_WD_LAAR,
1865 (sc->wd_laar_proto |=
1866 ED_WD_LAAR_M16EN));
1867 }
1868
1869 ed_rint (unit);
1870
1871 /* disable 16bit access */
1872 if (sc->isa16bit &&
1873 (sc->vendor == ED_VENDOR_WD_SMC)) {
1874
1875 outb(sc->asic_addr + ED_WD_LAAR,
1876 (sc->wd_laar_proto &=
1877 ~ED_WD_LAAR_M16EN));
1878 }
1879 }
1880 }
1881
1882 /*
1883 * If it looks like the transmitter can take more data,
1884 * attempt to start output on the interface.
1885 * This is done after handling the receiver to
1886 * give the receiver priority.
1887 */
1888 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0)
1889 ed_start(&sc->arpcom.ac_if);
1890
1891 /*
1892 * return NIC CR to standard state: page 0, remote DMA complete,
1893 * start (toggling the TXP bit off, even if was just set
1894 * in the transmit routine, is *okay* - it is 'edge'
1895 * triggered from low to high)
1896 */
1897 if (sc->is790) {
1898 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1899 } else {
1900 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1901 }
1902 /*
1903 * If the Network Talley Counters overflow, read them to
1904 * reset them. It appears that old 8390's won't
1905 * clear the ISR flag otherwise - resulting in an
1906 * infinite loop.
1907 */
1908 if (isr & ED_ISR_CNT) {
1909 (void) inb(sc->nic_addr + ED_P0_CNTR0);
1910 (void) inb(sc->nic_addr + ED_P0_CNTR1);
1911 (void) inb(sc->nic_addr + ED_P0_CNTR2);
1912 }
1913 }
1914}
1915
1916/*
1917 * Process an ioctl request. This code needs some work - it looks
1918 * pretty ugly.
1919 */
1920int
1921ed_ioctl(ifp, command, data)
1922 register struct ifnet *ifp;
1923 int command;
1924 caddr_t data;
1925{
1926 register struct ifaddr *ifa = (struct ifaddr *)data;
1927 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1928 struct ifreq *ifr = (struct ifreq *)data;
1929 int s, error = 0;
1930
1931 s = splimp();
1932
1933 switch (command) {
1934
1935 case SIOCSIFADDR:
1936 ifp->if_flags |= IFF_UP;
1937
1938 switch (ifa->ifa_addr->sa_family) {
1939#ifdef INET
1940 case AF_INET:
1941 ed_init(ifp->if_unit); /* before arpwhohas */
1942 /*
1943 * See if another station has *our* IP address.
1944 * i.e.: There is an address conflict! If a
1945 * conflict exists, a message is sent to the
1946 * console.
1947 */
1948 ((struct arpcom *)ifp)->ac_ipaddr =
1949 IA_SIN(ifa)->sin_addr;
1950 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
1951 break;
1952#endif
1953#ifdef NS
1954 /*
1955 * XXX - This code is probably wrong
1956 */
1957 case AF_NS:
1958 {
1959 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
1960
1961 if (ns_nullhost(*ina))
1962 ina->x_host =
1963 *(union ns_host *)(sc->arpcom.ac_enaddr);
1964 else {
1965 /*
1966 *
1967 */
1968 bcopy((caddr_t)ina->x_host.c_host,
1969 (caddr_t)sc->arpcom.ac_enaddr,
1970 sizeof(sc->arpcom.ac_enaddr));
1971 }
1972 /*
1973 * Set new address
1974 */
1975 ed_init(ifp->if_unit);
1976 break;
1977 }
1978#endif
1979 default:
1980 ed_init(ifp->if_unit);
1981 break;
1982 }
1983 break;
1984
1985 case SIOCSIFFLAGS:
1986 /*
1987 * If interface is marked down and it is running, then stop it
1988 */
1989 if (((ifp->if_flags & IFF_UP) == 0) &&
1990 (ifp->if_flags & IFF_RUNNING)) {
1991 ed_stop(ifp->if_unit);
1992 ifp->if_flags &= ~IFF_RUNNING;
1993 } else {
1994 /*
1995 * If interface is marked up and it is stopped, then start it
1996 */
1997 if ((ifp->if_flags & IFF_UP) &&
1998 ((ifp->if_flags & IFF_RUNNING) == 0))
1999 ed_init(ifp->if_unit);
2000 }
2001#if NBPFILTER > 0
2002 if (ifp->if_flags & IFF_PROMISC) {
2003 /*
2004 * Set promiscuous mode on interface.
2005 * XXX - for multicasts to work, we would need to
2006 * write 1's in all bits of multicast
2007 * hashing array. For now we assume that
2008 * this was done in ed_init().
2009 */
2010 outb(sc->nic_addr + ED_P0_RCR,
2011 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB);
2012 } else {
2013 /*
2014 * XXX - for multicasts to work, we would need to
2015 * rewrite the multicast hashing array with the
2016 * proper hash (would have been destroyed above).
2017 */
2018 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
2019 }
2020#endif
2021 /*
2022 * An unfortunate hack to provide the (required) software control
2023 * of the tranceiver for 3Com boards. The ALTPHYS flag disables
2024 * the tranceiver if set.
2025 */
2026 if (sc->vendor == ED_VENDOR_3COM) {
2027 if (ifp->if_flags & IFF_ALTPHYS) {
2028 outb(sc->asic_addr + ED_3COM_CR, 0);
2029 } else {
2030 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2031 }
2032 }
2033
2034 break;
2035
2036 default:
2037 error = EINVAL;
2038 }
2039 (void) splx(s);
2040 return (error);
2041}
2042
2043/*
2044 * Macro to calculate a new address within shared memory when given an offset
2045 * from an address, taking into account ring-wrap.
2046 */
2047#define ringoffset(sc, start, off, type) \
2048 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \
2049 (((caddr_t)(start)+(off))) - (sc)->mem_end \
2050 + (sc)->mem_ring: \
2051 ((caddr_t)(start)+(off)) ))
2052
2053/*
2054 * Retreive packet from shared memory and send to the next level up via
2055 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2056 */
| 1843 } else {
1844
1845 /*
1846 * Receiver Error. One or more of: CRC error, frame
1847 * alignment error FIFO overrun, or missed packet.
1848 */
1849 if (isr & ED_ISR_RXE) {
1850 ++sc->arpcom.ac_if.if_ierrors;
1851#ifdef ED_DEBUG
1852 printf("ed%d: receive error %x\n", unit,
1853 inb(sc->nic_addr + ED_P0_RSR));
1854#endif
1855 }
1856
1857 /*
1858 * Go get the packet(s)
1859 * XXX - Doing this on an error is dubious
1860 * because there shouldn't be any data to
1861 * get (we've configured the interface to
1862 * not accept packets with errors).
1863 */
1864
1865 /*
1866 * Enable 16bit access to shared memory first
1867 * on WD/SMC boards.
1868 */
1869 if (sc->isa16bit &&
1870 (sc->vendor == ED_VENDOR_WD_SMC)) {
1871
1872 outb(sc->asic_addr + ED_WD_LAAR,
1873 (sc->wd_laar_proto |=
1874 ED_WD_LAAR_M16EN));
1875 }
1876
1877 ed_rint (unit);
1878
1879 /* disable 16bit access */
1880 if (sc->isa16bit &&
1881 (sc->vendor == ED_VENDOR_WD_SMC)) {
1882
1883 outb(sc->asic_addr + ED_WD_LAAR,
1884 (sc->wd_laar_proto &=
1885 ~ED_WD_LAAR_M16EN));
1886 }
1887 }
1888 }
1889
1890 /*
1891 * If it looks like the transmitter can take more data,
1892 * attempt to start output on the interface.
1893 * This is done after handling the receiver to
1894 * give the receiver priority.
1895 */
1896 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0)
1897 ed_start(&sc->arpcom.ac_if);
1898
1899 /*
1900 * return NIC CR to standard state: page 0, remote DMA complete,
1901 * start (toggling the TXP bit off, even if was just set
1902 * in the transmit routine, is *okay* - it is 'edge'
1903 * triggered from low to high)
1904 */
1905 if (sc->is790) {
1906 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1907 } else {
1908 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1909 }
1910 /*
1911 * If the Network Talley Counters overflow, read them to
1912 * reset them. It appears that old 8390's won't
1913 * clear the ISR flag otherwise - resulting in an
1914 * infinite loop.
1915 */
1916 if (isr & ED_ISR_CNT) {
1917 (void) inb(sc->nic_addr + ED_P0_CNTR0);
1918 (void) inb(sc->nic_addr + ED_P0_CNTR1);
1919 (void) inb(sc->nic_addr + ED_P0_CNTR2);
1920 }
1921 }
1922}
1923
1924/*
1925 * Process an ioctl request. This code needs some work - it looks
1926 * pretty ugly.
1927 */
1928int
1929ed_ioctl(ifp, command, data)
1930 register struct ifnet *ifp;
1931 int command;
1932 caddr_t data;
1933{
1934 register struct ifaddr *ifa = (struct ifaddr *)data;
1935 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1936 struct ifreq *ifr = (struct ifreq *)data;
1937 int s, error = 0;
1938
1939 s = splimp();
1940
1941 switch (command) {
1942
1943 case SIOCSIFADDR:
1944 ifp->if_flags |= IFF_UP;
1945
1946 switch (ifa->ifa_addr->sa_family) {
1947#ifdef INET
1948 case AF_INET:
1949 ed_init(ifp->if_unit); /* before arpwhohas */
1950 /*
1951 * See if another station has *our* IP address.
1952 * i.e.: There is an address conflict! If a
1953 * conflict exists, a message is sent to the
1954 * console.
1955 */
1956 ((struct arpcom *)ifp)->ac_ipaddr =
1957 IA_SIN(ifa)->sin_addr;
1958 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
1959 break;
1960#endif
1961#ifdef NS
1962 /*
1963 * XXX - This code is probably wrong
1964 */
1965 case AF_NS:
1966 {
1967 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
1968
1969 if (ns_nullhost(*ina))
1970 ina->x_host =
1971 *(union ns_host *)(sc->arpcom.ac_enaddr);
1972 else {
1973 /*
1974 *
1975 */
1976 bcopy((caddr_t)ina->x_host.c_host,
1977 (caddr_t)sc->arpcom.ac_enaddr,
1978 sizeof(sc->arpcom.ac_enaddr));
1979 }
1980 /*
1981 * Set new address
1982 */
1983 ed_init(ifp->if_unit);
1984 break;
1985 }
1986#endif
1987 default:
1988 ed_init(ifp->if_unit);
1989 break;
1990 }
1991 break;
1992
1993 case SIOCSIFFLAGS:
1994 /*
1995 * If interface is marked down and it is running, then stop it
1996 */
1997 if (((ifp->if_flags & IFF_UP) == 0) &&
1998 (ifp->if_flags & IFF_RUNNING)) {
1999 ed_stop(ifp->if_unit);
2000 ifp->if_flags &= ~IFF_RUNNING;
2001 } else {
2002 /*
2003 * If interface is marked up and it is stopped, then start it
2004 */
2005 if ((ifp->if_flags & IFF_UP) &&
2006 ((ifp->if_flags & IFF_RUNNING) == 0))
2007 ed_init(ifp->if_unit);
2008 }
2009#if NBPFILTER > 0
2010 if (ifp->if_flags & IFF_PROMISC) {
2011 /*
2012 * Set promiscuous mode on interface.
2013 * XXX - for multicasts to work, we would need to
2014 * write 1's in all bits of multicast
2015 * hashing array. For now we assume that
2016 * this was done in ed_init().
2017 */
2018 outb(sc->nic_addr + ED_P0_RCR,
2019 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB);
2020 } else {
2021 /*
2022 * XXX - for multicasts to work, we would need to
2023 * rewrite the multicast hashing array with the
2024 * proper hash (would have been destroyed above).
2025 */
2026 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
2027 }
2028#endif
2029 /*
2030 * An unfortunate hack to provide the (required) software control
2031 * of the tranceiver for 3Com boards. The ALTPHYS flag disables
2032 * the tranceiver if set.
2033 */
2034 if (sc->vendor == ED_VENDOR_3COM) {
2035 if (ifp->if_flags & IFF_ALTPHYS) {
2036 outb(sc->asic_addr + ED_3COM_CR, 0);
2037 } else {
2038 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2039 }
2040 }
2041
2042 break;
2043
2044 default:
2045 error = EINVAL;
2046 }
2047 (void) splx(s);
2048 return (error);
2049}
2050
2051/*
2052 * Macro to calculate a new address within shared memory when given an offset
2053 * from an address, taking into account ring-wrap.
2054 */
2055#define ringoffset(sc, start, off, type) \
2056 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \
2057 (((caddr_t)(start)+(off))) - (sc)->mem_end \
2058 + (sc)->mem_ring: \
2059 ((caddr_t)(start)+(off)) ))
2060
2061/*
2062 * Retreive packet from shared memory and send to the next level up via
2063 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2064 */
|
| 2065static void
|
2057ed_get_packet(sc, buf, len)
2058 struct ed_softc *sc;
2059 char *buf;
2060 u_short len;
2061{
2062 struct ether_header *eh;
| 2066ed_get_packet(sc, buf, len)
2067 struct ed_softc *sc;
2068 char *buf;
2069 u_short len;
2070{
2071 struct ether_header *eh;
|
2063 struct mbuf *m, *head, *ed_ring_to_mbuf();
| 2072 struct mbuf *m, *head = 0, *ed_ring_to_mbuf();
|
2064 u_short off;
2065 int resid;
2066 u_short etype;
2067 struct trailer_header trailer_header;
2068
2069 /* Allocate a header mbuf */
2070 MGETHDR(m, M_DONTWAIT, MT_DATA);
2071 if (m == 0)
2072 goto bad;
2073 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2074 m->m_pkthdr.len = len;
2075 m->m_len = 0;
2076 head = m;
2077
2078 /* The following sillines is to make NFS happy */
2079#define EROUND ((sizeof(struct ether_header) + 3) & ~3)
2080#define EOFF (EROUND - sizeof(struct ether_header))
2081
2082 /*
2083 * The following assumes there is room for
2084 * the ether header in the header mbuf
2085 */
2086 head->m_data += EOFF;
2087 eh = mtod(head, struct ether_header *);
2088
2089 if (sc->mem_shared)
2090 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
2091 else
2092 ed_pio_readmem(sc, buf, mtod(head, caddr_t),
2093 sizeof(struct ether_header));
2094 buf += sizeof(struct ether_header);
2095 head->m_len += sizeof(struct ether_header);
2096 len -= sizeof(struct ether_header);
2097
2098 etype = ntohs((u_short)eh->ether_type);
2099
2100 /*
2101 * Deal with trailer protocol:
2102 * If trailer protocol, calculate the datasize as 'off',
2103 * which is also the offset to the trailer header.
2104 * Set resid to the amount of packet data following the
2105 * trailer header.
2106 * Finally, copy residual data into mbuf chain.
2107 */
2108 if (etype >= ETHERTYPE_TRAIL &&
2109 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
2110
2111 off = (etype - ETHERTYPE_TRAIL) << 9;
2112 if ((off + sizeof(struct trailer_header)) > len)
2113 goto bad; /* insanity */
2114
2115 /*
2116 * If we have shared memory, we can get info directly from the
2117 * stored packet, otherwise we must get a local copy
2118 * of the trailer header using PIO.
2119 */
2120 if (sc->mem_shared) {
2121 eh->ether_type = *ringoffset(sc, buf, off, u_short *);
2122 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
2123 } else {
2124 struct trailer_header trailer_header;
2125 ed_pio_readmem(sc,
2126 ringoffset(sc, buf, off, caddr_t),
2127 (char *) &trailer_header,
2128 sizeof(trailer_header));
2129 eh->ether_type = trailer_header.ether_type;
2130 resid = trailer_header.ether_residual;
2131 }
2132
2133 if ((off + resid) > len) goto bad; /* insanity */
2134
2135 resid -= sizeof(struct trailer_header);
2136 if (resid < 0) goto bad; /* insanity */
2137
2138 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid);
2139 if (m == 0) goto bad;
2140
2141 len = off;
2142 head->m_pkthdr.len -= 4; /* subtract trailer header */
2143 }
2144
2145 /*
2146 * Pull packet off interface. Or if this was a trailer packet,
2147 * the data portion is appended.
2148 */
2149 m = ed_ring_to_mbuf(sc, buf, m, len);
2150 if (m == 0) goto bad;
2151
2152#if NBPFILTER > 0
2153 /*
2154 * Check if there's a BPF listener on this interface.
2155 * If so, hand off the raw packet to bpf.
2156 */
2157 if (sc->bpf) {
2158 bpf_mtap(sc->bpf, head);
2159
2160 /*
2161 * Note that the interface cannot be in promiscuous mode if
2162 * there are no BPF listeners. And if we are in promiscuous
2163 * mode, we have to check if this packet is really ours.
2164 *
2165 * XXX This test does not support multicasts.
2166 */
2167 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2168 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2169 sizeof(eh->ether_dhost)) != 0 &&
2170 bcmp(eh->ether_dhost, etherbroadcastaddr,
2171 sizeof(eh->ether_dhost)) != 0) {
2172
2173 m_freem(head);
2174 return;
2175 }
2176 }
2177#endif
2178
2179 /*
2180 * Fix up data start offset in mbuf to point past ether header
2181 */
2182 m_adj(head, sizeof(struct ether_header));
2183
2184 /*
2185 * silly ether_input routine needs 'type' in host byte order
2186 */
2187 eh->ether_type = ntohs(eh->ether_type);
2188
2189 ether_input(&sc->arpcom.ac_if, eh, head);
2190 return;
2191
2192bad: if (head)
2193 m_freem(head);
2194 return;
2195}
2196
2197/*
2198 * Supporting routines
2199 */
2200
2201/*
2202 * Given a NIC memory source address and a host memory destination
2203 * address, copy 'amount' from NIC to host using Programmed I/O.
2204 * The 'amount' is rounded up to a word - okay as long as mbufs
2205 * are word sized.
2206 * This routine is currently Novell-specific.
2207 */
2208void
2209ed_pio_readmem(sc,src,dst,amount)
2210 struct ed_softc *sc;
2211 unsigned short src;
2212 unsigned char *dst;
2213 unsigned short amount;
2214{
2215 unsigned short tmp_amount;
2216
2217 /* select page 0 registers */
2218 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2219
2220 /* round up to a word */
2221 tmp_amount = amount;
2222 if (amount & 1) ++amount;
2223
2224 /* set up DMA byte count */
2225 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2226 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8);
2227
2228 /* set up source address in NIC mem */
2229 outb(sc->nic_addr + ED_P0_RSAR0, src);
2230 outb(sc->nic_addr + ED_P0_RSAR1, src>>8);
2231
2232 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2233
2234 if (sc->isa16bit) {
2235 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2);
2236 } else
2237 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2238
2239}
2240
2241/*
2242 * Stripped down routine for writing a linear buffer to NIC memory.
2243 * Only used in the probe routine to test the memory. 'len' must
2244 * be even.
2245 */
2246void
2247ed_pio_writemem(sc,src,dst,len)
2248 struct ed_softc *sc;
2249 char *src;
2250 unsigned short dst;
2251 unsigned short len;
2252{
2253 int maxwait=100; /* about 120us */
2254
2255 /* select page 0 registers */
2256 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2257
2258 /* reset remote DMA complete flag */
2259 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2260
2261 /* set up DMA byte count */
2262 outb(sc->nic_addr + ED_P0_RBCR0, len);
2263 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2264
2265 /* set up destination address in NIC mem */
2266 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2267 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2268
2269 /* set remote DMA write */
2270 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2271
2272 if (sc->isa16bit)
2273 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2);
2274 else
2275 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2276 /*
2277 * Wait for remote DMA complete. This is necessary because on the
2278 * transmit side, data is handled internally by the NIC in bursts
2279 * and we can't start another remote DMA until this one completes.
2280 * Not waiting causes really bad things to happen - like the NIC
2281 * irrecoverably jamming the ISA bus.
2282 */
2283 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2284}
2285
2286/*
2287 * Write an mbuf chain to the destination NIC memory address using
2288 * programmed I/O.
2289 */
2290u_short
2291ed_pio_write_mbufs(sc,m,dst)
2292 struct ed_softc *sc;
2293 struct mbuf *m;
2294 unsigned short dst;
2295{
2296 unsigned short len, mb_offset;
2297 struct mbuf *mp;
2298 unsigned char residual[2];
2299 int maxwait=100; /* about 120us */
2300
2301 /* First, count up the total number of bytes to copy */
2302 for (len = 0, mp = m; mp; mp = mp->m_next)
2303 len += mp->m_len;
2304
2305 /* select page 0 registers */
2306 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2307
2308 /* reset remote DMA complete flag */
2309 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2310
2311 /* set up DMA byte count */
2312 outb(sc->nic_addr + ED_P0_RBCR0, len);
2313 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2314
2315 /* set up destination address in NIC mem */
2316 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2317 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2318
2319 /* set remote DMA write */
2320 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2321
2322 mb_offset = 0;
2323 /*
2324 * Transfer the mbuf chain to the NIC memory.
2325 * The following code isn't too pretty. The problem is that we can only
2326 * transfer words to the board, and if an mbuf has an odd number
2327 * of bytes in it, this is a problem. It's not a simple matter of
2328 * just removing a byte from the next mbuf (adjusting data++ and
2329 * len--) because this will hose-over the mbuf chain which might
2330 * be needed later for BPF. Instead, we maintain an offset
2331 * (mb_offset) which let's us skip over the first byte in the
2332 * following mbuf.
2333 */
2334 while (m) {
2335 if (m->m_len - mb_offset) {
2336 if (sc->isa16bit) {
2337 if ((m->m_len - mb_offset) > 1)
2338 outsw(sc->asic_addr + ED_NOVELL_DATA,
2339 mtod(m, caddr_t) + mb_offset,
2340 (m->m_len - mb_offset) / 2);
2341
2342 /*
2343 * if odd number of bytes, get the odd byte from
2344 * the next mbuf with data
2345 */
2346 if ((m->m_len - mb_offset) & 1) {
2347 /* first the last byte in current mbuf */
2348 residual[0] = *(mtod(m, caddr_t)
2349 + m->m_len - 1);
2350
2351 /* advance past any empty mbufs */
2352 while (m->m_next && (m->m_next->m_len == 0))
2353 m = m->m_next;
2354
2355 if (m->m_next) {
2356 /* remove first byte in next mbuf */
2357 residual[1] = *(mtod(m->m_next, caddr_t));
2358 mb_offset = 1;
2359 }
2360
2361 outw(sc->asic_addr + ED_NOVELL_DATA,
2362 *((unsigned short *) residual));
2363 } else
2364 mb_offset = 0;
2365 } else
2366 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len);
2367
2368 }
2369 m = m->m_next;
2370 }
2371
2372 /*
2373 * Wait for remote DMA complete. This is necessary because on the
2374 * transmit side, data is handled internally by the NIC in bursts
2375 * and we can't start another remote DMA until this one completes.
2376 * Not waiting causes really bad things to happen - like the NIC
2377 * irrecoverably jamming the ISA bus.
2378 */
2379 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2380
2381 if (!maxwait) {
2382 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2383 sc->arpcom.ac_if.if_unit);
| 2073 u_short off;
2074 int resid;
2075 u_short etype;
2076 struct trailer_header trailer_header;
2077
2078 /* Allocate a header mbuf */
2079 MGETHDR(m, M_DONTWAIT, MT_DATA);
2080 if (m == 0)
2081 goto bad;
2082 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2083 m->m_pkthdr.len = len;
2084 m->m_len = 0;
2085 head = m;
2086
2087 /* The following sillines is to make NFS happy */
2088#define EROUND ((sizeof(struct ether_header) + 3) & ~3)
2089#define EOFF (EROUND - sizeof(struct ether_header))
2090
2091 /*
2092 * The following assumes there is room for
2093 * the ether header in the header mbuf
2094 */
2095 head->m_data += EOFF;
2096 eh = mtod(head, struct ether_header *);
2097
2098 if (sc->mem_shared)
2099 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
2100 else
2101 ed_pio_readmem(sc, buf, mtod(head, caddr_t),
2102 sizeof(struct ether_header));
2103 buf += sizeof(struct ether_header);
2104 head->m_len += sizeof(struct ether_header);
2105 len -= sizeof(struct ether_header);
2106
2107 etype = ntohs((u_short)eh->ether_type);
2108
2109 /*
2110 * Deal with trailer protocol:
2111 * If trailer protocol, calculate the datasize as 'off',
2112 * which is also the offset to the trailer header.
2113 * Set resid to the amount of packet data following the
2114 * trailer header.
2115 * Finally, copy residual data into mbuf chain.
2116 */
2117 if (etype >= ETHERTYPE_TRAIL &&
2118 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
2119
2120 off = (etype - ETHERTYPE_TRAIL) << 9;
2121 if ((off + sizeof(struct trailer_header)) > len)
2122 goto bad; /* insanity */
2123
2124 /*
2125 * If we have shared memory, we can get info directly from the
2126 * stored packet, otherwise we must get a local copy
2127 * of the trailer header using PIO.
2128 */
2129 if (sc->mem_shared) {
2130 eh->ether_type = *ringoffset(sc, buf, off, u_short *);
2131 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
2132 } else {
2133 struct trailer_header trailer_header;
2134 ed_pio_readmem(sc,
2135 ringoffset(sc, buf, off, caddr_t),
2136 (char *) &trailer_header,
2137 sizeof(trailer_header));
2138 eh->ether_type = trailer_header.ether_type;
2139 resid = trailer_header.ether_residual;
2140 }
2141
2142 if ((off + resid) > len) goto bad; /* insanity */
2143
2144 resid -= sizeof(struct trailer_header);
2145 if (resid < 0) goto bad; /* insanity */
2146
2147 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid);
2148 if (m == 0) goto bad;
2149
2150 len = off;
2151 head->m_pkthdr.len -= 4; /* subtract trailer header */
2152 }
2153
2154 /*
2155 * Pull packet off interface. Or if this was a trailer packet,
2156 * the data portion is appended.
2157 */
2158 m = ed_ring_to_mbuf(sc, buf, m, len);
2159 if (m == 0) goto bad;
2160
2161#if NBPFILTER > 0
2162 /*
2163 * Check if there's a BPF listener on this interface.
2164 * If so, hand off the raw packet to bpf.
2165 */
2166 if (sc->bpf) {
2167 bpf_mtap(sc->bpf, head);
2168
2169 /*
2170 * Note that the interface cannot be in promiscuous mode if
2171 * there are no BPF listeners. And if we are in promiscuous
2172 * mode, we have to check if this packet is really ours.
2173 *
2174 * XXX This test does not support multicasts.
2175 */
2176 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2177 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2178 sizeof(eh->ether_dhost)) != 0 &&
2179 bcmp(eh->ether_dhost, etherbroadcastaddr,
2180 sizeof(eh->ether_dhost)) != 0) {
2181
2182 m_freem(head);
2183 return;
2184 }
2185 }
2186#endif
2187
2188 /*
2189 * Fix up data start offset in mbuf to point past ether header
2190 */
2191 m_adj(head, sizeof(struct ether_header));
2192
2193 /*
2194 * silly ether_input routine needs 'type' in host byte order
2195 */
2196 eh->ether_type = ntohs(eh->ether_type);
2197
2198 ether_input(&sc->arpcom.ac_if, eh, head);
2199 return;
2200
2201bad: if (head)
2202 m_freem(head);
2203 return;
2204}
2205
2206/*
2207 * Supporting routines
2208 */
2209
2210/*
2211 * Given a NIC memory source address and a host memory destination
2212 * address, copy 'amount' from NIC to host using Programmed I/O.
2213 * The 'amount' is rounded up to a word - okay as long as mbufs
2214 * are word sized.
2215 * This routine is currently Novell-specific.
2216 */
2217void
2218ed_pio_readmem(sc,src,dst,amount)
2219 struct ed_softc *sc;
2220 unsigned short src;
2221 unsigned char *dst;
2222 unsigned short amount;
2223{
2224 unsigned short tmp_amount;
2225
2226 /* select page 0 registers */
2227 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2228
2229 /* round up to a word */
2230 tmp_amount = amount;
2231 if (amount & 1) ++amount;
2232
2233 /* set up DMA byte count */
2234 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2235 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8);
2236
2237 /* set up source address in NIC mem */
2238 outb(sc->nic_addr + ED_P0_RSAR0, src);
2239 outb(sc->nic_addr + ED_P0_RSAR1, src>>8);
2240
2241 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2242
2243 if (sc->isa16bit) {
2244 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2);
2245 } else
2246 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2247
2248}
2249
2250/*
2251 * Stripped down routine for writing a linear buffer to NIC memory.
2252 * Only used in the probe routine to test the memory. 'len' must
2253 * be even.
2254 */
2255void
2256ed_pio_writemem(sc,src,dst,len)
2257 struct ed_softc *sc;
2258 char *src;
2259 unsigned short dst;
2260 unsigned short len;
2261{
2262 int maxwait=100; /* about 120us */
2263
2264 /* select page 0 registers */
2265 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2266
2267 /* reset remote DMA complete flag */
2268 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2269
2270 /* set up DMA byte count */
2271 outb(sc->nic_addr + ED_P0_RBCR0, len);
2272 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2273
2274 /* set up destination address in NIC mem */
2275 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2276 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2277
2278 /* set remote DMA write */
2279 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2280
2281 if (sc->isa16bit)
2282 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2);
2283 else
2284 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2285 /*
2286 * Wait for remote DMA complete. This is necessary because on the
2287 * transmit side, data is handled internally by the NIC in bursts
2288 * and we can't start another remote DMA until this one completes.
2289 * Not waiting causes really bad things to happen - like the NIC
2290 * irrecoverably jamming the ISA bus.
2291 */
2292 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2293}
2294
2295/*
2296 * Write an mbuf chain to the destination NIC memory address using
2297 * programmed I/O.
2298 */
2299u_short
2300ed_pio_write_mbufs(sc,m,dst)
2301 struct ed_softc *sc;
2302 struct mbuf *m;
2303 unsigned short dst;
2304{
2305 unsigned short len, mb_offset;
2306 struct mbuf *mp;
2307 unsigned char residual[2];
2308 int maxwait=100; /* about 120us */
2309
2310 /* First, count up the total number of bytes to copy */
2311 for (len = 0, mp = m; mp; mp = mp->m_next)
2312 len += mp->m_len;
2313
2314 /* select page 0 registers */
2315 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2316
2317 /* reset remote DMA complete flag */
2318 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2319
2320 /* set up DMA byte count */
2321 outb(sc->nic_addr + ED_P0_RBCR0, len);
2322 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2323
2324 /* set up destination address in NIC mem */
2325 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2326 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2327
2328 /* set remote DMA write */
2329 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2330
2331 mb_offset = 0;
2332 /*
2333 * Transfer the mbuf chain to the NIC memory.
2334 * The following code isn't too pretty. The problem is that we can only
2335 * transfer words to the board, and if an mbuf has an odd number
2336 * of bytes in it, this is a problem. It's not a simple matter of
2337 * just removing a byte from the next mbuf (adjusting data++ and
2338 * len--) because this will hose-over the mbuf chain which might
2339 * be needed later for BPF. Instead, we maintain an offset
2340 * (mb_offset) which let's us skip over the first byte in the
2341 * following mbuf.
2342 */
2343 while (m) {
2344 if (m->m_len - mb_offset) {
2345 if (sc->isa16bit) {
2346 if ((m->m_len - mb_offset) > 1)
2347 outsw(sc->asic_addr + ED_NOVELL_DATA,
2348 mtod(m, caddr_t) + mb_offset,
2349 (m->m_len - mb_offset) / 2);
2350
2351 /*
2352 * if odd number of bytes, get the odd byte from
2353 * the next mbuf with data
2354 */
2355 if ((m->m_len - mb_offset) & 1) {
2356 /* first the last byte in current mbuf */
2357 residual[0] = *(mtod(m, caddr_t)
2358 + m->m_len - 1);
2359
2360 /* advance past any empty mbufs */
2361 while (m->m_next && (m->m_next->m_len == 0))
2362 m = m->m_next;
2363
2364 if (m->m_next) {
2365 /* remove first byte in next mbuf */
2366 residual[1] = *(mtod(m->m_next, caddr_t));
2367 mb_offset = 1;
2368 }
2369
2370 outw(sc->asic_addr + ED_NOVELL_DATA,
2371 *((unsigned short *) residual));
2372 } else
2373 mb_offset = 0;
2374 } else
2375 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len);
2376
2377 }
2378 m = m->m_next;
2379 }
2380
2381 /*
2382 * Wait for remote DMA complete. This is necessary because on the
2383 * transmit side, data is handled internally by the NIC in bursts
2384 * and we can't start another remote DMA until this one completes.
2385 * Not waiting causes really bad things to happen - like the NIC
2386 * irrecoverably jamming the ISA bus.
2387 */
2388 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2389
2390 if (!maxwait) {
2391 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2392 sc->arpcom.ac_if.if_unit);
|
2384 ed_reset(sc->arpcom.ac_if.if_unit);
| 2393 ed_reset(sc->arpcom.ac_if.if_unit, 0);
|
2385 }
2386
2387 return(len);
2388}
2389
2390/*
2391 * Given a source and destination address, copy 'amount' of a packet from
2392 * the ring buffer into a linear destination buffer. Takes into account
2393 * ring-wrap.
2394 */
2395static inline char *
2396ed_ring_copy(sc,src,dst,amount)
2397 struct ed_softc *sc;
2398 char *src;
2399 char *dst;
2400 u_short amount;
2401{
2402 u_short tmp_amount;
2403
2404 /* does copy wrap to lower addr in ring buffer? */
2405 if (src + amount > sc->mem_end) {
2406 tmp_amount = sc->mem_end - src;
2407
2408 /* copy amount up to end of NIC memory */
2409 if (sc->mem_shared)
2410 bcopy(src,dst,tmp_amount);
2411 else
2412 ed_pio_readmem(sc,src,dst,tmp_amount);
2413
2414 amount -= tmp_amount;
2415 src = sc->mem_ring;
2416 dst += tmp_amount;
2417 }
2418
2419 if (sc->mem_shared)
2420 bcopy(src, dst, amount);
2421 else
2422 ed_pio_readmem(sc, src, dst, amount);
2423
2424 return(src + amount);
2425}
2426
2427/*
2428 * Copy data from receive buffer to end of mbuf chain
2429 * allocate additional mbufs as needed. return pointer
2430 * to last mbuf in chain.
2431 * sc = ed info (softc)
2432 * src = pointer in ed ring buffer
2433 * dst = pointer to last mbuf in mbuf chain to copy to
2434 * amount = amount of data to copy
2435 */
2436struct mbuf *
2437ed_ring_to_mbuf(sc,src,dst,total_len)
2438 struct ed_softc *sc;
2439 char *src;
2440 struct mbuf *dst;
2441 u_short total_len;
2442{
2443 register struct mbuf *m = dst;
2444
2445 while (total_len) {
2446 register u_short amount = min(total_len, M_TRAILINGSPACE(m));
2447
2448 if (amount == 0) { /* no more data in this mbuf, alloc another */
2449 /*
2450 * If there is enough data for an mbuf cluster, attempt
2451 * to allocate one of those, otherwise, a regular
2452 * mbuf will do.
2453 * Note that a regular mbuf is always required, even if
2454 * we get a cluster - getting a cluster does not
2455 * allocate any mbufs, and one is needed to assign
2456 * the cluster to. The mbuf that has a cluster
2457 * extension can not be used to contain data - only
2458 * the cluster can contain data.
2459 */
2460 dst = m;
2461 MGET(m, M_DONTWAIT, MT_DATA);
2462 if (m == 0)
2463 return (0);
2464
2465 if (total_len >= MINCLSIZE)
2466 MCLGET(m, M_DONTWAIT);
2467
2468 m->m_len = 0;
2469 dst->m_next = m;
2470 amount = min(total_len, M_TRAILINGSPACE(m));
2471 }
2472
2473 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
2474
2475 m->m_len += amount;
2476 total_len -= amount;
2477
2478 }
2479 return (m);
2480}
2481#endif
| 2394 }
2395
2396 return(len);
2397}
2398
2399/*
2400 * Given a source and destination address, copy 'amount' of a packet from
2401 * the ring buffer into a linear destination buffer. Takes into account
2402 * ring-wrap.
2403 */
2404static inline char *
2405ed_ring_copy(sc,src,dst,amount)
2406 struct ed_softc *sc;
2407 char *src;
2408 char *dst;
2409 u_short amount;
2410{
2411 u_short tmp_amount;
2412
2413 /* does copy wrap to lower addr in ring buffer? */
2414 if (src + amount > sc->mem_end) {
2415 tmp_amount = sc->mem_end - src;
2416
2417 /* copy amount up to end of NIC memory */
2418 if (sc->mem_shared)
2419 bcopy(src,dst,tmp_amount);
2420 else
2421 ed_pio_readmem(sc,src,dst,tmp_amount);
2422
2423 amount -= tmp_amount;
2424 src = sc->mem_ring;
2425 dst += tmp_amount;
2426 }
2427
2428 if (sc->mem_shared)
2429 bcopy(src, dst, amount);
2430 else
2431 ed_pio_readmem(sc, src, dst, amount);
2432
2433 return(src + amount);
2434}
2435
2436/*
2437 * Copy data from receive buffer to end of mbuf chain
2438 * allocate additional mbufs as needed. return pointer
2439 * to last mbuf in chain.
2440 * sc = ed info (softc)
2441 * src = pointer in ed ring buffer
2442 * dst = pointer to last mbuf in mbuf chain to copy to
2443 * amount = amount of data to copy
2444 */
2445struct mbuf *
2446ed_ring_to_mbuf(sc,src,dst,total_len)
2447 struct ed_softc *sc;
2448 char *src;
2449 struct mbuf *dst;
2450 u_short total_len;
2451{
2452 register struct mbuf *m = dst;
2453
2454 while (total_len) {
2455 register u_short amount = min(total_len, M_TRAILINGSPACE(m));
2456
2457 if (amount == 0) { /* no more data in this mbuf, alloc another */
2458 /*
2459 * If there is enough data for an mbuf cluster, attempt
2460 * to allocate one of those, otherwise, a regular
2461 * mbuf will do.
2462 * Note that a regular mbuf is always required, even if
2463 * we get a cluster - getting a cluster does not
2464 * allocate any mbufs, and one is needed to assign
2465 * the cluster to. The mbuf that has a cluster
2466 * extension can not be used to contain data - only
2467 * the cluster can contain data.
2468 */
2469 dst = m;
2470 MGET(m, M_DONTWAIT, MT_DATA);
2471 if (m == 0)
2472 return (0);
2473
2474 if (total_len >= MINCLSIZE)
2475 MCLGET(m, M_DONTWAIT);
2476
2477 m->m_len = 0;
2478 dst->m_next = m;
2479 amount = min(total_len, M_TRAILINGSPACE(m));
2480 }
2481
2482 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
2483
2484 m->m_len += amount;
2485 total_len -= amount;
2486
2487 }
2488 return (m);
2489}
2490#endif
|