1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: if_ed.c,v 1.128 1997/11/07 08:52:33 phk Exp $
28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include "ed.h"
41#include "bpfilter.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/conf.h>
46#include <sys/sockio.h>
47#include <sys/malloc.h>
48#include <sys/mbuf.h>
49#include <sys/socket.h>
50#include <sys/syslog.h>
51
52#include <net/if.h>
53#include <net/if_dl.h>
54#include <net/if_mib.h>
55
56#ifdef INET
57#include <netinet/in.h>
58#include <netinet/if_ether.h>
59#endif
60
61#ifdef NS
62#include <netns/ns.h>
63#include <netns/ns_if.h>
64#endif
65
66#if NBPFILTER > 0
67#include <net/bpf.h>
68#endif
69
70#include <machine/clock.h>
71#include <machine/md_var.h>
72
73#include <i386/isa/isa_device.h>
74#include <i386/isa/icu.h>
75#include <i386/isa/if_edreg.h>
76
77/*
78 * ed_softc: per line info and status
79 */
80struct ed_softc {
81 struct arpcom arpcom; /* ethernet common */
82
83 char *type_str; /* pointer to type string */
84 u_char vendor; /* interface vendor */
85 u_char type; /* interface type code */
86 u_char gone; /* HW missing, presumed having a good time */
87
88 u_short asic_addr; /* ASIC I/O bus address */
89 u_short nic_addr; /* NIC (DS8390) I/O bus address */
90
91/*
92 * The following 'proto' variable is part of a work-around for 8013EBT asics
93 * being write-only. It's sort of a prototype/shadow of the real thing.
94 */
95 u_char wd_laar_proto;
96 u_char cr_proto;
97 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
98 int is790; /* set by the probe code if the card is 790
99 * based */
100
101/*
102 * HP PC LAN PLUS card support.
103 */
104
105 u_short hpp_options; /* flags controlling behaviour of the HP card */
106 u_short hpp_id; /* software revision and other fields */
107 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
108
109 caddr_t mem_start; /* NIC memory start address */
110 caddr_t mem_end; /* NIC memory end address */
111 u_long mem_size; /* total NIC memory size */
112 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
113
114 u_char mem_shared; /* NIC memory is shared with host */
115 u_char xmit_busy; /* transmitter is busy */
116 u_char txb_cnt; /* number of transmit buffers */
117 u_char txb_inuse; /* number of TX buffers currently in-use */
118
119 u_char txb_new; /* pointer to where new buffer will be added */
120 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
121 u_short txb_len[8]; /* buffered xmit buffer lengths */
122 u_char tx_page_start; /* first page of TX buffer area */
123 u_char rec_page_start; /* first page of RX ring-buffer */
124 u_char rec_page_stop; /* last page of RX ring-buffer */
125 u_char next_packet; /* pointer to next unread RX packet */
126 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
127};
128
129static struct ed_softc ed_softc[NED];
130
131static int ed_attach __P((struct ed_softc *, int, int));
132static int ed_attach_isa __P((struct isa_device *));
133
134static void ed_init __P((void *));
135static int ed_ioctl __P((struct ifnet *, int, caddr_t));
136static int ed_probe __P((struct isa_device *));
137static void ed_start __P((struct ifnet *));
138static void ed_reset __P((struct ifnet *));
139static void ed_watchdog __P((struct ifnet *));
140
141static void ed_stop __P((struct ed_softc *));
142static int ed_probe_generic8390 __P((struct ed_softc *));
143static int ed_probe_WD80x3 __P((struct isa_device *));
144static int ed_probe_3Com __P((struct isa_device *));
145static int ed_probe_Novell __P((struct isa_device *));
146static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int));
147static int ed_probe_HP_pclanp __P((struct isa_device *));
148
149#include "pci.h"
150#if NPCI > 0
151void *ed_attach_NE2000_pci __P((int, int));
152#endif
153
154#include "card.h"
155#if NCARD > 0
156static int ed_probe_pccard __P((struct isa_device *, u_char *));
157#endif
158
159static void ds_getmcaf __P((struct ed_softc *, u_long *));
160
161static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int);
162
163static void ed_rint __P((struct ed_softc *));
164static void ed_xmit __P((struct ed_softc *));
165static char * ed_ring_copy __P((struct ed_softc *, char *, char *,
166 /* u_short */ int));
167static void ed_hpp_set_physical_link __P((struct ed_softc *));
168static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
169 /* u_short */ int));
170static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
171 int));
172
173static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
174 /* u_short */ int));
175static void ed_pio_writemem __P((struct ed_softc *, char *,
176 /* u_short */ int, /* u_short */ int));
177static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
178 int));
179void edintr_sc __P((struct ed_softc *));
180
181static void ed_setrcr(struct ed_softc *);
182
183static u_long ds_crc(u_char *ep);
184
185#if NCARD > 0
186#include <sys/kernel.h>
187#include <sys/select.h>
188#include <pccard/cardinfo.h>
189#include <pccard/driver.h>
190#include <pccard/slot.h>
191
192/*
193 * PC-Card (PCMCIA) specific code.
194 */
195static int edinit(struct pccard_devinfo *); /* init device */
196static void edunload(struct pccard_devinfo *); /* Disable driver */
197static int card_intr(struct pccard_devinfo *); /* Interrupt handler */
198
199static struct pccard_device ed_info = {
200 "ed",
201 edinit,
202 edunload,
203 card_intr,
204 0, /* Attributes - presently unused */
205 &net_imask /* Interrupt mask for device */
206 /* XXX - Should this also include net_imask? */
207};
208
209DATA_SET(pccarddrv_set, ed_info);
210
211/*
212 * Initialize the device - called from Slot manager.
213 */
214static int
215edinit(struct pccard_devinfo *devi)
216{
217 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
218
219 /* validate unit number. */
220 if (devi->isahd.id_unit >= NED)
221 return(ENODEV);
222 /*
223 * Probe the device. If a value is returned, the
224 * device was found at the location.
225 */
226 sc->gone = 0;
227 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0)
228 return(ENXIO);
229 if (ed_attach_isa(&devi->isahd) == 0)
230 return(ENXIO);
231
232 return(0);
233}
234
235/*
236 * edunload - unload the driver and clear the table.
237 * XXX TODO:
238 * This is usually called when the card is ejected, but
239 * can be caused by a modunload of a controller driver.
240 * The idea is to reset the driver's view of the device
241 * and ensure that any driver entry points such as
242 * read and write do not hang.
243 */
244static void
245edunload(struct pccard_devinfo *devi)
246{
247 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
248 struct ifnet *ifp = &sc->arpcom.ac_if;
249
250 if (sc->gone) {
251 printf("ed%d: already unloaded\n", devi->isahd.id_unit);
252 return;
253 }
254 ifp->if_flags &= ~IFF_RUNNING;
255 if_down(ifp);
256 sc->gone = 1;
257 printf("ed%d: unload\n", devi->isahd.id_unit);
258}
259
260/*
261 * card_intr - Shared interrupt called from
262 * front end of PC-Card handler.
263 */
264static int
265card_intr(struct pccard_devinfo *devi)
266{
267 edintr_sc(&ed_softc[devi->isahd.id_unit]);
268 return(1);
269}
270#endif /* NCARD > 0 */
271
272struct isa_driver eddriver = {
273 ed_probe,
274 ed_attach_isa,
275 "ed",
276 1 /* We are ultra sensitive */
277};
278
279/*
280 * Interrupt conversion table for WD/SMC ASIC/83C584
281 * (IRQ* are defined in icu.h)
282 */
283static unsigned short ed_intr_mask[] = {
284 IRQ9,
285 IRQ3,
286 IRQ5,
287 IRQ7,
288 IRQ10,
289 IRQ11,
290 IRQ15,
291 IRQ4
292};
293
294/*
295 * Interrupt conversion table for 83C790
296 */
297static unsigned short ed_790_intr_mask[] = {
298 0,
299 IRQ9,
300 IRQ3,
301 IRQ5,
302 IRQ7,
303 IRQ10,
304 IRQ11,
305 IRQ15
306};
307
308/*
309 * Interrupt conversion table for the HP PC LAN+
310 */
311
312static unsigned short ed_hpp_intr_mask[] = {
313 0, /* 0 */
314 0, /* 1 */
315 0, /* 2 */
316 IRQ3, /* 3 */
317 IRQ4, /* 4 */
318 IRQ5, /* 5 */
319 IRQ6, /* 6 */
320 IRQ7, /* 7 */
321 0, /* 8 */
322 IRQ9, /* 9 */
323 IRQ10, /* 10 */
324 IRQ11, /* 11 */
325 IRQ12, /* 12 */
326 0, /* 13 */
327 0, /* 14 */
328 IRQ15 /* 15 */
329};
330
331/*
332 * Determine if the device is present
333 *
334 * on entry:
335 * a pointer to an isa_device struct
336 * on exit:
337 * NULL if device not found
338 * or # of i/o addresses used (if found)
339 */
340static int
341ed_probe(isa_dev)
342 struct isa_device *isa_dev;
343{
344 int nports;
345
346 nports = ed_probe_WD80x3(isa_dev);
347 if (nports)
348 return (nports);
349
350 nports = ed_probe_3Com(isa_dev);
351 if (nports)
352 return (nports);
353
354 nports = ed_probe_Novell(isa_dev);
355 if (nports)
356 return (nports);
357
358 nports = ed_probe_HP_pclanp(isa_dev);
359 if (nports)
360 return (nports);
361
362 return (0);
363}
364
365/*
366 * Generic probe routine for testing for the existance of a DS8390.
367 * Must be called after the NIC has just been reset. This routine
368 * works by looking at certain register values that are guaranteed
369 * to be initialized a certain way after power-up or reset. Seems
370 * not to currently work on the 83C690.
371 *
372 * Specifically:
373 *
374 * Register reset bits set bits
375 * Command Register (CR) TXP, STA RD2, STP
376 * Interrupt Status (ISR) RST
377 * Interrupt Mask (IMR) All bits
378 * Data Control (DCR) LAS
379 * Transmit Config. (TCR) LB1, LB0
380 *
381 * We only look at the CR and ISR registers, however, because looking at
382 * the others would require changing register pages (which would be
383 * intrusive if this isn't an 8390).
384 *
385 * Return 1 if 8390 was found, 0 if not.
386 */
387
388static int
389ed_probe_generic8390(sc)
390 struct ed_softc *sc;
391{
392 if ((inb(sc->nic_addr + ED_P0_CR) &
393 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
394 (ED_CR_RD2 | ED_CR_STP))
395 return (0);
396 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
397 return (0);
398
399 return (1);
400}
401
402/*
403 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
404 */
405static int
406ed_probe_WD80x3(isa_dev)
407 struct isa_device *isa_dev;
408{
409 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
410 int i;
411 u_int memsize, maddr;
412 u_char iptr, isa16bit, sum;
413
414 sc->asic_addr = isa_dev->id_iobase;
415 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
416 sc->is790 = 0;
417
418#ifdef TOSH_ETHER
419 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
420 DELAY(10000);
421#endif
422
423 /*
424 * Attempt to do a checksum over the station address PROM. If it
425 * fails, it's probably not a SMC/WD board. There is a problem with
426 * this, though: some clone WD boards don't pass the checksum test.
427 * Danpex boards for one.
428 */
429 for (sum = 0, i = 0; i < 8; ++i)
430 sum += inb(sc->asic_addr + ED_WD_PROM + i);
431
432 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
433
434 /*
435 * Checksum is invalid. This often happens with cheap WD8003E
436 * clones. In this case, the checksum byte (the eighth byte)
437 * seems to always be zero.
438 */
439 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
440 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
441 return (0);
442 }
443 /* reset card to force it into a known state. */
444#ifdef TOSH_ETHER
445 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
446#else
447 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
448#endif
449 DELAY(100);
450 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
451 /* wait in the case this card is reading it's EEROM */
452 DELAY(5000);
453
454 sc->vendor = ED_VENDOR_WD_SMC;
455 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
456
457 /*
458 * Set initial values for width/size.
459 */
460 memsize = 8192;
461 isa16bit = 0;
462 switch (sc->type) {
463 case ED_TYPE_WD8003S:
464 sc->type_str = "WD8003S";
465 break;
466 case ED_TYPE_WD8003E:
467 sc->type_str = "WD8003E";
468 break;
469 case ED_TYPE_WD8003EB:
470 sc->type_str = "WD8003EB";
471 break;
472 case ED_TYPE_WD8003W:
473 sc->type_str = "WD8003W";
474 break;
475 case ED_TYPE_WD8013EBT:
476 sc->type_str = "WD8013EBT";
477 memsize = 16384;
478 isa16bit = 1;
479 break;
480 case ED_TYPE_WD8013W:
481 sc->type_str = "WD8013W";
482 memsize = 16384;
483 isa16bit = 1;
484 break;
485 case ED_TYPE_WD8013EP: /* also WD8003EP */
486 if (inb(sc->asic_addr + ED_WD_ICR)
487 & ED_WD_ICR_16BIT) {
488 isa16bit = 1;
489 memsize = 16384;
490 sc->type_str = "WD8013EP";
491 } else {
492 sc->type_str = "WD8003EP";
493 }
494 break;
495 case ED_TYPE_WD8013WC:
496 sc->type_str = "WD8013WC";
497 memsize = 16384;
498 isa16bit = 1;
499 break;
500 case ED_TYPE_WD8013EBP:
501 sc->type_str = "WD8013EBP";
502 memsize = 16384;
503 isa16bit = 1;
504 break;
505 case ED_TYPE_WD8013EPC:
506 sc->type_str = "WD8013EPC";
507 memsize = 16384;
508 isa16bit = 1;
509 break;
510 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
511 case ED_TYPE_SMC8216T:
512 if (sc->type == ED_TYPE_SMC8216C) {
513 sc->type_str = "SMC8216/SMC8216C";
514 } else {
515 sc->type_str = "SMC8216T";
516 }
517
518 outb(sc->asic_addr + ED_WD790_HWR,
519 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
520 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
521 case ED_WD790_RAR_SZ64:
522 memsize = 65536;
523 break;
524 case ED_WD790_RAR_SZ32:
525 memsize = 32768;
526 break;
527 case ED_WD790_RAR_SZ16:
528 memsize = 16384;
529 break;
530 case ED_WD790_RAR_SZ8:
531 /* 8216 has 16K shared mem -- 8416 has 8K */
532 if (sc->type == ED_TYPE_SMC8216C) {
533 sc->type_str = "SMC8416C/SMC8416BT";
534 } else {
535 sc->type_str = "SMC8416T";
536 }
537 memsize = 8192;
538 break;
539 }
540 outb(sc->asic_addr + ED_WD790_HWR,
541 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
542
543 isa16bit = 1;
544 sc->is790 = 1;
545 break;
546#ifdef TOSH_ETHER
547 case ED_TYPE_TOSHIBA1:
548 sc->type_str = "Toshiba1";
549 memsize = 32768;
550 isa16bit = 1;
551 break;
552 case ED_TYPE_TOSHIBA4:
553 sc->type_str = "Toshiba4";
554 memsize = 32768;
555 isa16bit = 1;
556 break;
557#endif
558 default:
559 sc->type_str = "";
560 break;
561 }
562
563 /*
564 * Make some adjustments to initial values depending on what is found
565 * in the ICR.
566 */
567 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
568#ifdef TOSH_ETHER
569 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
570#endif
571 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
572 isa16bit = 0;
573 memsize = 8192;
574 }
575
576#if ED_DEBUG
577 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
578 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
579 for (i = 0; i < 8; i++)
580 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
581#endif
582
583 /*
584 * Allow the user to override the autoconfiguration
585 */
586 if (isa_dev->id_msize)
587 memsize = isa_dev->id_msize;
588
589 maddr = (u_int) isa_dev->id_maddr & 0xffffff;
590 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
591 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n",
592 isa_dev->id_unit, maddr, maddr + memsize);
593 return 0;
594 }
595
596 /*
597 * (note that if the user specifies both of the following flags that
598 * '8bit' mode intentionally has precedence)
599 */
600 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
601 isa16bit = 1;
602 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
603 isa16bit = 0;
604
605 /*
606 * If possible, get the assigned interrupt number from the card and
607 * use it.
608 */
609 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
610
611 /*
612 * Assemble together the encoded interrupt number.
613 */
614 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
615 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
616 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
617
618 /*
619 * If no interrupt specified (or "?"), use what the board tells us.
620 */
621 if (isa_dev->id_irq <= 0)
622 isa_dev->id_irq = ed_intr_mask[iptr];
623
624 /*
625 * Enable the interrupt.
626 */
627 outb(isa_dev->id_iobase + ED_WD_IRR,
628 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
629 }
630 if (sc->is790) {
631 outb(isa_dev->id_iobase + ED_WD790_HWR,
632 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
633 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
634 (inb(isa_dev->id_iobase + ED_WD790_GCR) &
635 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
636 outb(isa_dev->id_iobase + ED_WD790_HWR,
637 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
638
639 /*
640 * If no interrupt specified (or "?"), use what the board tells us.
641 */
642 if (isa_dev->id_irq <= 0)
643 isa_dev->id_irq = ed_790_intr_mask[iptr];
644
645 /*
646 * Enable interrupts.
647 */
648 outb(isa_dev->id_iobase + ED_WD790_ICR,
649 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
650 }
651 if (isa_dev->id_irq <= 0) {
652 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n",
653 isa_dev->id_unit, sc->type_str);
654 return (0);
655 }
656 sc->isa16bit = isa16bit;
657 sc->mem_shared = 1;
658 isa_dev->id_msize = memsize;
659 sc->mem_start = (caddr_t) isa_dev->id_maddr;
660
661 /*
662 * allocate one xmit buffer if < 16k, two buffers otherwise
663 */
664 if ((memsize < 16384) ||
665 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
666 sc->txb_cnt = 1;
667 } else {
668 sc->txb_cnt = 2;
669 }
670 sc->tx_page_start = ED_WD_PAGE_OFFSET;
671 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
672 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
673 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
674 sc->mem_size = memsize;
675 sc->mem_end = sc->mem_start + memsize;
676
677 /*
678 * Get station address from on-board ROM
679 */
680 for (i = 0; i < ETHER_ADDR_LEN; ++i)
681 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
682
683 /*
684 * Set upper address bits and 8/16 bit access to shared memory.
685 */
686 if (isa16bit) {
687 if (sc->is790) {
688 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
689 } else {
690 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
691 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
692 }
693 /*
694 * Enable 16bit access
695 */
696 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
697 ED_WD_LAAR_M16EN);
698 } else {
699 if (((sc->type & ED_WD_SOFTCONFIG) ||
700#ifdef TOSH_ETHER
701 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
702#endif
703 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
704 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
705 ED_WD_LAAR_ADDRHI;
706 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
707 }
708 }
709
710 /*
711 * Set address and enable interface shared memory.
712 */
713 if (!sc->is790) {
714#ifdef TOSH_ETHER
715 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
716 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
717 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
718
719#else
720 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
721 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
722#endif
723 sc->cr_proto = ED_CR_RD2;
724 } else {
725 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
726 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
727 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
728 ((kvtop(sc->mem_start) >> 11) & 0x40) |
729 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
730 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
731 sc->cr_proto = 0;
732 }
733
734#if 0
735 printf("starting memory performance test at 0x%x, size %d...\n",
736 sc->mem_start, memsize*16384);
737 for (i = 0; i < 16384; i++)
738 bzero(sc->mem_start, memsize);
739 printf("***DONE***\n");
740#endif
741
742 /*
743 * Now zero memory and verify that it is clear
744 */
745 bzero(sc->mem_start, memsize);
746
747 for (i = 0; i < memsize; ++i) {
748 if (sc->mem_start[i]) {
749 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
750 isa_dev->id_unit, kvtop(sc->mem_start + i));
751
752 /*
753 * Disable 16 bit access to shared memory
754 */
755 if (isa16bit) {
756 if (sc->is790) {
757 outb(sc->asic_addr + ED_WD_MSR, 0x00);
758 }
759 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
760 ~ED_WD_LAAR_M16EN);
761 }
762 return (0);
763 }
764 }
765
766 /*
767 * Disable 16bit access to shared memory - we leave it
768 * disabled so that 1) machines reboot properly when the board
769 * is set 16 bit mode and there are conflicting 8bit
770 * devices/ROMS in the same 128k address space as this boards
771 * shared memory. and 2) so that other 8 bit devices with
772 * shared memory can be used in this 128k region, too.
773 */
774 if (isa16bit) {
775 if (sc->is790) {
776 outb(sc->asic_addr + ED_WD_MSR, 0x00);
777 }
778 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
779 ~ED_WD_LAAR_M16EN);
780 }
781 return (ED_WD_IO_PORTS);
782}
783
784/*
785 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
786 */
787static int
788ed_probe_3Com(isa_dev)
789 struct isa_device *isa_dev;
790{
791 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
792 int i;
793 u_int memsize;
794 u_char isa16bit;
795
796 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
797 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
798
799 /*
800 * Verify that the kernel configured I/O address matches the board
801 * configured address
802 */
803 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
804 case ED_3COM_BCFR_300:
805 if (isa_dev->id_iobase != 0x300)
806 return (0);
807 break;
808 case ED_3COM_BCFR_310:
809 if (isa_dev->id_iobase != 0x310)
810 return (0);
811 break;
812 case ED_3COM_BCFR_330:
813 if (isa_dev->id_iobase != 0x330)
814 return (0);
815 break;
816 case ED_3COM_BCFR_350:
817 if (isa_dev->id_iobase != 0x350)
818 return (0);
819 break;
820 case ED_3COM_BCFR_250:
821 if (isa_dev->id_iobase != 0x250)
822 return (0);
823 break;
824 case ED_3COM_BCFR_280:
825 if (isa_dev->id_iobase != 0x280)
826 return (0);
827 break;
828 case ED_3COM_BCFR_2A0:
829 if (isa_dev->id_iobase != 0x2a0)
830 return (0);
831 break;
832 case ED_3COM_BCFR_2E0:
833 if (isa_dev->id_iobase != 0x2e0)
834 return (0);
835 break;
836 default:
837 return (0);
838 }
839
840 /*
841 * Verify that the kernel shared memory address matches the board
842 * configured address.
843 */
844 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
845 case ED_3COM_PCFR_DC000:
846 if (kvtop(isa_dev->id_maddr) != 0xdc000)
847 return (0);
848 break;
849 case ED_3COM_PCFR_D8000:
850 if (kvtop(isa_dev->id_maddr) != 0xd8000)
851 return (0);
852 break;
853 case ED_3COM_PCFR_CC000:
854 if (kvtop(isa_dev->id_maddr) != 0xcc000)
855 return (0);
856 break;
857 case ED_3COM_PCFR_C8000:
858 if (kvtop(isa_dev->id_maddr) != 0xc8000)
859 return (0);
860 break;
861 default:
862 return (0);
863 }
864
865
866 /*
867 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
868 * sequence because it'll lock up if the cable isn't connected if we
869 * don't.
870 */
871 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
872
873 /*
874 * Wait for a while, then un-reset it
875 */
876 DELAY(50);
877
878 /*
879 * The 3Com ASIC defaults to rather strange settings for the CR after
880 * a reset - it's important to set it again after the following outb
881 * (this is done when we map the PROM below).
882 */
883 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
884
885 /*
886 * Wait a bit for the NIC to recover from the reset
887 */
888 DELAY(5000);
889
890 sc->vendor = ED_VENDOR_3COM;
891 sc->type_str = "3c503";
892 sc->mem_shared = 1;
893 sc->cr_proto = ED_CR_RD2;
894
895 /*
896 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
897 * to it.
898 */
899 memsize = 8192;
900
901 /*
902 * Get station address from on-board ROM
903 */
904
905 /*
906 * First, map ethernet address PROM over the top of where the NIC
907 * registers normally appear.
908 */
909 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
910
911 for (i = 0; i < ETHER_ADDR_LEN; ++i)
912 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
913
914 /*
915 * Unmap PROM - select NIC registers. The proper setting of the
916 * tranceiver is set in ed_init so that the attach code is given a
917 * chance to set the default based on a compile-time config option
918 */
919 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
920
921 /*
922 * Determine if this is an 8bit or 16bit board
923 */
924
925 /*
926 * select page 0 registers
927 */
928 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
929
930 /*
931 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
932 * board.
933 */
934 outb(sc->nic_addr + ED_P0_DCR, 0);
935
936 /*
937 * select page 2 registers
938 */
939 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
940
941 /*
942 * The 3c503 forces the WTS bit to a one if this is a 16bit board
943 */
944 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
945 isa16bit = 1;
946 else
947 isa16bit = 0;
948
949 /*
950 * select page 0 registers
951 */
952 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
953
954 sc->mem_start = (caddr_t) isa_dev->id_maddr;
955 sc->mem_size = memsize;
956 sc->mem_end = sc->mem_start + memsize;
957
958 /*
959 * We have an entire 8k window to put the transmit buffers on the
960 * 16bit boards. But since the 16bit 3c503's shared memory is only
961 * fast enough to overlap the loading of one full-size packet, trying
962 * to load more than 2 buffers can actually leave the transmitter idle
963 * during the load. So 2 seems the best value. (Although a mix of
964 * variable-sized packets might change this assumption. Nonetheless,
965 * we optimize for linear transfers of same-size packets.)
966 */
967 if (isa16bit) {
968 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
969 sc->txb_cnt = 1;
970 else
971 sc->txb_cnt = 2;
972
973 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
974 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
975 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
976 ED_3COM_RX_PAGE_OFFSET_16BIT;
977 sc->mem_ring = sc->mem_start;
978 } else {
979 sc->txb_cnt = 1;
980 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
981 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
982 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
983 ED_3COM_TX_PAGE_OFFSET_8BIT;
984 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
985 }
986
987 sc->isa16bit = isa16bit;
988
989 /*
990 * Initialize GA page start/stop registers. Probably only needed if
991 * doing DMA, but what the hell.
992 */
993 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
994 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
995
996 /*
997 * Set IRQ. 3c503 only allows a choice of irq 2-5.
998 */
999 switch (isa_dev->id_irq) {
1000 case IRQ2:
1001 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
1002 break;
1003 case IRQ3:
1004 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
1005 break;
1006 case IRQ4:
1007 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
1008 break;
1009 case IRQ5:
1010 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
1011 break;
1012 default:
1013 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n",
1014 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
1015 return (0);
1016 }
1017
1018 /*
1019 * Initialize GA configuration register. Set bank and enable shared
1020 * mem.
1021 */
1022 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
1023 ED_3COM_GACFR_MBS0);
1024
1025 /*
1026 * Initialize "Vector Pointer" registers. These gawd-awful things are
1027 * compared to 20 bits of the address on ISA, and if they match, the
1028 * shared memory is disabled. We set them to 0xffff0...allegedly the
1029 * reset vector.
1030 */
1031 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
1032 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
1033 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
1034
1035 /*
1036 * Zero memory and verify that it is clear
1037 */
1038 bzero(sc->mem_start, memsize);
1039
1040 for (i = 0; i < memsize; ++i)
1041 if (sc->mem_start[i]) {
1042 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
1043 isa_dev->id_unit, kvtop(sc->mem_start + i));
1044 return (0);
1045 }
1046 isa_dev->id_msize = memsize;
1047 return (ED_3COM_IO_PORTS);
1048}
1049
1050/*
1051 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1052 */
1053static int
1054ed_probe_Novell_generic(sc, port, unit, flags)
1055 struct ed_softc *sc;
1056 int port;
1057 int unit;
1058 int flags;
1059{
1060 u_int memsize, n;
1061 u_char romdata[16], tmp;
1062 static char test_pattern[32] = "THIS is A memory TEST pattern";
1063 char test_buffer[32];
1064
1065 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET;
1066 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
1067
1068 /* XXX - do Novell-specific probe here */
1069
1070 /* Reset the board */
1071#ifdef GWETHER
1072 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
1073 DELAY(200);
1074#endif /* GWETHER */
1075 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
1076
1077 /*
1078 * I don't know if this is necessary; probably cruft leftover from
1079 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1080 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
1081 * non-invasive...but some boards don't seem to reset and I don't have
1082 * complete documentation on what the 'right' thing to do is...so we
1083 * do the invasive thing for now. Yuck.]
1084 */
1085 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
1086 DELAY(5000);
1087
1088 /*
1089 * This is needed because some NE clones apparently don't reset the
1090 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1091 * - this makes the probe invasive! ...Done against my better
1092 * judgement. -DLG
1093 */
1094 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1095
1096 DELAY(5000);
1097
1098 /* Make sure that we really have an 8390 based board */
1099 if (!ed_probe_generic8390(sc))
1100 return (0);
1101
1102 sc->vendor = ED_VENDOR_NOVELL;
1103 sc->mem_shared = 0;
1104 sc->cr_proto = ED_CR_RD2;
1105
1106 /*
1107 * Test the ability to read and write to the NIC memory. This has the
1108 * side affect of determining if this is an NE1000 or an NE2000.
1109 */
1110
1111 /*
1112 * This prevents packets from being stored in the NIC memory when the
1113 * readmem routine turns on the start bit in the CR.
1114 */
1115 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1116
1117 /* Temporarily initialize DCR for byte operations */
1118 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1119
1120 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1121 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1122
1123 sc->isa16bit = 0;
1124
1125 /*
1126 * Write a test pattern in byte mode. If this fails, then there
1127 * probably isn't any memory at 8k - which likely means that the board
1128 * is an NE2000.
1129 */
1130 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1131 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1132
1133 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
1134 /* not an NE1000 - try NE2000 */
1135
1136 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1137 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1138 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1139
1140 sc->isa16bit = 1;
1141
1142 /*
1143 * Write a test pattern in word mode. If this also fails, then
1144 * we don't know what this board is.
1145 */
1146 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1147 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1148
1149 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
1150 return (0); /* not an NE2000 either */
1151
1152 sc->type = ED_TYPE_NE2000;
1153 sc->type_str = "NE2000";
1154 } else {
1155 sc->type = ED_TYPE_NE1000;
1156 sc->type_str = "NE1000";
1157 }
1158
1159 /* 8k of memory plus an additional 8k if 16bit */
1160 memsize = 8192 + sc->isa16bit * 8192;
1161
1162#if 0 /* probably not useful - NE boards only come two ways */
1163 /* allow kernel config file overrides */
1164 if (isa_dev->id_msize)
1165 memsize = isa_dev->id_msize;
1166#endif
1167
1168 sc->mem_size = memsize;
1169
1170 /* NIC memory doesn't start at zero on an NE board */
1171 /* The start address is tied to the bus width */
1172 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1173 sc->mem_end = sc->mem_start + memsize;
1174 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1175
1176#ifdef GWETHER
1177 {
1178 int x, i, mstart = 0, msize = 0;
1179 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1180
1181 for (i = 0; i < ED_PAGE_SIZE; i++)
1182 pbuf0[i] = 0;
1183
1184 /* Clear all the memory. */
1185 for (x = 1; x < 256; x++)
1186 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1187
1188 /* Search for the start of RAM. */
1189 for (x = 1; x < 256; x++) {
1190 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1191 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1192 for (i = 0; i < ED_PAGE_SIZE; i++)
1193 pbuf[i] = 255 - x;
1194 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1195 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1196 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1197 mstart = x * ED_PAGE_SIZE;
1198 msize = ED_PAGE_SIZE;
1199 break;
1200 }
1201 }
1202 }
1203
1204 if (mstart == 0) {
1205 printf("ed%d: Cannot find start of RAM.\n", unit);
1206 return 0;
1207 }
1208 /* Search for the start of RAM. */
1209 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1210 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1211 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1212 for (i = 0; i < ED_PAGE_SIZE; i++)
1213 pbuf[i] = 255 - x;
1214 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1215 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1216 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1217 msize += ED_PAGE_SIZE;
1218 else {
1219 break;
1220 }
1221 } else {
1222 break;
1223 }
1224 }
1225
1226 if (msize == 0) {
1227 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x);
1228 return 0;
1229 }
1230 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
1231
1232 sc->mem_size = msize;
1233 sc->mem_start = (char *) mstart;
1234 sc->mem_end = (char *) (msize + mstart);
1235 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1236 }
1237#endif /* GWETHER */
1238
1239 /*
1240 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1241 * otherwise).
1242 */
1243 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1244 sc->txb_cnt = 1;
1245 else
1246 sc->txb_cnt = 2;
1247
1248 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1249 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1250
1251 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1252
1253 ed_pio_readmem(sc, 0, romdata, 16);
1254 for (n = 0; n < ETHER_ADDR_LEN; n++)
1255 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1256
1257#ifdef GWETHER
1258 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1259 sc->type_str = "Gateway AT";
1260 }
1261#endif /* GWETHER */
1262
1263 /* clear any pending interrupts that might have occurred above */
1264 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1265
1266 return (ED_NOVELL_IO_PORTS);
1267}
1268
1269static int
1270ed_probe_Novell(isa_dev)
1271 struct isa_device *isa_dev;
1272{
1273 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1274
1275 isa_dev->id_maddr = 0;
1276 return ed_probe_Novell_generic(sc, isa_dev->id_iobase,
1277 isa_dev->id_unit, isa_dev->id_flags);
1278}
1279
1280#if NCARD > 0
1281/*
1282 * Probe framework for pccards. Replicates the standard framework,
1283 * minus the pccard driver registration and ignores the ether address
1284 * supplied (from the CIS), relying on the probe to find it instead.
1285 */
1286static int
1287ed_probe_pccard(isa_dev, ether)
1288 struct isa_device *isa_dev;
1289 u_char *ether;
1290{
1291 int nports;
1292
1293 nports = ed_probe_WD80x3(isa_dev);
1294 if (nports)
1295 return (nports);
1296
1297 nports = ed_probe_Novell(isa_dev);
1298 if (nports)
1299 return (nports);
1300
1301 return (0);
1302}
1303
1304#endif /* NCARD > 0 */
1305
1306#define ED_HPP_TEST_SIZE 16
1307
1308/*
1309 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1310 * (HP Part nos: 27247B and 27252A).
1311 *
1312 * The card has an asic wrapper around a DS8390 core. The asic handles
1313 * host accesses and offers both standard register IO and memory mapped
1314 * IO. Memory mapped I/O allows better performance at the expense of greater
1315 * chance of an incompatibility with existing ISA cards.
1316 *
1317 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1318 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1319 * don't allow 32 bit accesses; these are indicated by a bit in the software
1320 * ID register (see if_edreg.h).
1321 *
1322 * Other caveats are: we should read the MAC address only when the card
1323 * is inactive.
1324 *
1325 * For more information; please consult the CRYNWR packet driver.
1326 *
1327 * The AUI port is turned on using the "link2" option on the ifconfig
1328 * command line.
1329 */
1330static int
1331ed_probe_HP_pclanp(isa_dev)
1332 struct isa_device *isa_dev;
1333{
1334 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1335 int n; /* temp var */
1336 int memsize; /* mem on board */
1337 u_char checksum; /* checksum of board address */
1338 u_char irq; /* board configured IRQ */
1339 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1340 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1341
1342
1343 /* Fill in basic information */
1344 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET;
1345 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
1346 sc->is790 = 0;
1347 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1348
1349 /*
1350 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1351 */
1352
1353 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1354 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1355 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1356 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1357 return 0;
1358
1359 /*
1360 * Read the MAC address and verify checksum on the address.
1361 */
1362
1363 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1364 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1365 checksum += (sc->arpcom.ac_enaddr[n] =
1366 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1367
1368 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1369
1370 if (checksum != 0xFF)
1371 return 0;
1372
1373 /*
1374 * Verify that the software model number is 0.
1375 */
1376
1377 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1378 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1379 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1380 return 0;
1381
1382 /*
1383 * Read in and save the current options configured on card.
1384 */
1385
1386 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1387
1388 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1389 ED_HPP_OPTION_CHIP_RESET |
1390 ED_HPP_OPTION_ENABLE_IRQ);
1391
1392 /*
1393 * Reset the chip. This requires writing to the option register
1394 * so take care to preserve the other bits.
1395 */
1396
1397 outw(sc->asic_addr + ED_HPP_OPTION,
1398 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1399 ED_HPP_OPTION_CHIP_RESET)));
1400
1401 DELAY(5000); /* wait for chip reset to complete */
1402
1403 outw(sc->asic_addr + ED_HPP_OPTION,
1404 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1405 ED_HPP_OPTION_CHIP_RESET |
1406 ED_HPP_OPTION_ENABLE_IRQ)));
1407
1408 DELAY(5000);
1409
1410 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1411 return 0; /* reset did not complete */
1412
1413 /*
1414 * Read out configuration information.
1415 */
1416
1417 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1418
1419 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1420
1421 /*
1422 * Check for impossible IRQ.
1423 */
1424
1425 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
1426 return 0;
1427
1428 /*
1429 * If the kernel IRQ was specified with a '?' use the cards idea
1430 * of the IRQ. If the kernel IRQ was explicitly specified, it
1431 * should match that of the hardware.
1432 */
1433
1434 if (isa_dev->id_irq <= 0)
1435 isa_dev->id_irq = ed_hpp_intr_mask[irq];
1436 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq])
1437 return 0;
1438
1439 /*
1440 * Fill in softconfig info.
1441 */
1442
1443 sc->vendor = ED_VENDOR_HP;
1444 sc->type = ED_TYPE_HP_PCLANPLUS;
1445 sc->type_str = "HP-PCLAN+";
1446
1447 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1448 sc->mem_start = 0; /* we use offsets inside the card RAM */
1449
1450 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1451
1452 /*
1453 * Check if memory mapping of the I/O registers possible.
1454 */
1455
1456 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1457 {
1458 u_long mem_addr;
1459
1460 /*
1461 * determine the memory address from the board.
1462 */
1463
1464 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1465 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1466
1467 /*
1468 * Check that the kernel specified start of memory and
1469 * hardware's idea of it match.
1470 */
1471
1472 if (mem_addr != kvtop(isa_dev->id_maddr))
1473 return 0;
1474
1475 sc->hpp_mem_start = isa_dev->id_maddr;
1476 }
1477
1478 /*
1479 * The board has 32KB of memory. Is there a way to determine
1480 * this programmatically?
1481 */
1482
1483 memsize = 32768;
1484
1485 /*
1486 * Fill in the rest of the soft config structure.
1487 */
1488
1489 /*
1490 * The transmit page index.
1491 */
1492
1493 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1494
1495 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1496 sc->txb_cnt = 1;
1497 else
1498 sc->txb_cnt = 2;
1499
1500 /*
1501 * Memory description
1502 */
1503
1504 sc->mem_size = memsize;
1505 sc->mem_ring = sc->mem_start +
1506 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1507 sc->mem_end = sc->mem_start + sc->mem_size;
1508
1509 /*
1510 * Receive area starts after the transmit area and
1511 * continues till the end of memory.
1512 */
1513
1514 sc->rec_page_start = sc->tx_page_start +
1515 (sc->txb_cnt * ED_TXBUF_SIZE);
1516 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1517
1518
1519 sc->cr_proto = 0; /* value works */
1520
1521 /*
1522 * Set the wrap registers for string I/O reads.
1523 */
1524
1525 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1526 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1527 ((sc->rec_page_start / ED_PAGE_SIZE) |
1528 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1529
1530 /*
1531 * Reset the register page to normal operation.
1532 */
1533
1534 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1535
1536 /*
1537 * Verify that we can read/write from adapter memory.
1538 * Create test pattern.
1539 */
1540
1541 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1542 {
1543 test_pattern[n] = (n*n) ^ ~n;
1544 }
1545
1546#undef ED_HPP_TEST_SIZE
1547
1548 /*
1549 * Check that the memory is accessible thru the I/O ports.
1550 * Write out the contents of "test_pattern", read back
1551 * into "test_buffer" and compare the two for any
1552 * mismatch.
1553 */
1554
1555 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1556
1557 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1558 sizeof(test_pattern));
1559 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1560 test_buffer, sizeof(test_pattern));
1561
1562 if (bcmp(test_pattern, test_buffer,
1563 sizeof(test_pattern)))
1564 return 0;
1565 }
1566
1567 return (ED_HPP_IO_PORTS);
1568
1569}
1570
1571/*
1572 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1573 */
1574
1575void
1576ed_hpp_set_physical_link(struct ed_softc *sc)
1577{
1578 struct ifnet *ifp = &sc->arpcom.ac_if;
1579 int lan_page;
1580
1581 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1582 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1583
1584 if (ifp->if_flags & IFF_ALTPHYS) {
1585
1586 /*
1587 * Use the AUI port.
1588 */
1589
1590 lan_page |= ED_HPP_LAN_AUI;
1591
1592 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1593 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1594
1595
1596 } else {
1597
1598 /*
1599 * Use the ThinLan interface
1600 */
1601
1602 lan_page &= ~ED_HPP_LAN_AUI;
1603
1604 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1605 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1606
1607 }
1608
1609 /*
1610 * Wait for the lan card to re-initialize itself
1611 */
1612
1613 DELAY(150000); /* wait 150 ms */
1614
1615 /*
1616 * Restore normal pages.
1617 */
1618
1619 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1620
1621}
1622
1623
1624/*
1625 * Install interface into kernel networking data structures
1626 */
1627static int
1628ed_attach(sc, unit, flags)
1629 struct ed_softc *sc;
1630 int unit;
1631 int flags;
1632{
1633 struct ifnet *ifp = &sc->arpcom.ac_if;
1634
1635 /*
1636 * Set interface to stopped condition (reset)
1637 */
1638 ed_stop(sc);
1639
1640 if (!ifp->if_name) {
1641 /*
1642 * Initialize ifnet structure
1643 */
1644 ifp->if_softc = sc;
1645 ifp->if_unit = unit;
1646 ifp->if_name = "ed";
1647 ifp->if_output = ether_output;
1648 ifp->if_start = ed_start;
1649 ifp->if_ioctl = ed_ioctl;
1650 ifp->if_watchdog = ed_watchdog;
1651 ifp->if_init = ed_init;
1652 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1653 ifp->if_linkmib = &sc->mibdata;
1654 ifp->if_linkmiblen = sizeof sc->mibdata;
1655 /*
1656 * XXX - should do a better job.
1657 */
1658 if (sc->is790)
1659 sc->mibdata.dot3StatsEtherChipSet =
1660 DOT3CHIPSET(dot3VendorWesternDigital,
1661 dot3ChipSetWesternDigital83C790);
1662 else
1663 sc->mibdata.dot3StatsEtherChipSet =
1664 DOT3CHIPSET(dot3VendorNational,
1665 dot3ChipSetNational8390);
1666 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1667
1668 /*
1669 * Set default state for ALTPHYS flag (used to disable the
1670 * tranceiver for AUI operation), based on compile-time
1671 * config option.
1672 */
1673 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1674 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1675 IFF_MULTICAST | IFF_ALTPHYS);
1676 else
1677 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1678 IFF_MULTICAST);
1679
1680 /*
1681 * Attach the interface
1682 */
1683 if_attach(ifp);
1684 ether_ifattach(ifp);
1685 }
1686 /* device attach does transition from UNCONFIGURED to IDLE state */
1687
1688 /*
1689 * Print additional info when attached
1690 */
1691 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1692 sc->arpcom.ac_enaddr, ":");
1693
1694 if (sc->type_str && (*sc->type_str != 0))
1695 printf("type %s ", sc->type_str);
1696 else
1697 printf("type unknown (0x%x) ", sc->type);
1698
1699 if (sc->vendor == ED_VENDOR_HP)
1700 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1701 "16-bit" : "32-bit",
1702 sc->hpp_mem_start ? "memory mapped" : "regular");
1703 else
1704 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1705
1706 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1707 (sc->vendor == ED_VENDOR_HP)) &&
1708 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1709
1710 /*
1711 * If BPF is in the kernel, call the attach for it
1712 */
1713#if NBPFILTER > 0
1714 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1715#endif
1716 return 1;
1717}
1718
1719static int
1720ed_attach_isa(isa_dev)
1721 struct isa_device *isa_dev;
1722{
1723 int unit = isa_dev->id_unit;
1724 struct ed_softc *sc = &ed_softc[unit];
1725 int flags = isa_dev->id_flags;
1726
1727 return ed_attach(sc, unit, flags);
1728}
1729
1730#if NPCI > 0
1731void *
1732ed_attach_NE2000_pci(unit, port)
1733 int unit;
1734 int port;
1735{
1736 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT);
1737 int isa_flags = 0;
1738
1739 if (!sc)
1740 return sc;
1741
1742 bzero(sc, sizeof *sc);
1743 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0
1744 || ed_attach(sc, unit, isa_flags) == 0) {
1745 free(sc, M_DEVBUF);
1746 return NULL;
1747 }
1748 return sc;
1749}
1750#endif
1751
1752/*
1753 * Reset interface.
1754 */
1755static void
1756ed_reset(ifp)
1757 struct ifnet *ifp;
1758{
1759 struct ed_softc *sc = ifp->if_softc;
1760 int s;
1761
1762 if (sc->gone)
1763 return;
1764 s = splimp();
1765
1766 /*
1767 * Stop interface and re-initialize.
1768 */
1769 ed_stop(sc);
1770 ed_init(sc);
1771
1772 (void) splx(s);
1773}
1774
1775/*
1776 * Take interface offline.
1777 */
1778static void
1779ed_stop(sc)
1780 struct ed_softc *sc;
1781{
1782 int n = 5000;
1783
1784 if (sc->gone)
1785 return;
1786 /*
1787 * Stop everything on the interface, and select page 0 registers.
1788 */
1789 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1790
1791 /*
1792 * Wait for interface to enter stopped state, but limit # of checks to
1793 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1794 * just in case it's an old one.
1795 */
1796 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1797}
1798
1799/*
1800 * Device timeout/watchdog routine. Entered if the device neglects to
1801 * generate an interrupt after a transmit has been started on it.
1802 */
1803static void
1804ed_watchdog(ifp)
1805 struct ifnet *ifp;
1806{
1807 struct ed_softc *sc = ifp->if_softc;
1808
1809 if (sc->gone)
1810 return;
1811 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1812 ifp->if_oerrors++;
1813
1814 ed_reset(ifp);
1815}
1816
1817/*
1818 * Initialize device.
1819 */
1820static void
1821ed_init(xsc)
1822 void *xsc;
1823{
1824 struct ed_softc *sc = xsc;
1825 struct ifnet *ifp = &sc->arpcom.ac_if;
1826 int i, s;
1827
1828 if (sc->gone)
1829 return;
1830
1831 /* address not known */
1832 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1833 return;
1834
1835 /*
1836 * Initialize the NIC in the exact order outlined in the NS manual.
1837 * This init procedure is "mandatory"...don't change what or when
1838 * things happen.
1839 */
1840 s = splimp();
1841
1842 /* reset transmitter flags */
1843 sc->xmit_busy = 0;
1844 ifp->if_timer = 0;
1845
1846 sc->txb_inuse = 0;
1847 sc->txb_new = 0;
1848 sc->txb_next_tx = 0;
1849
1850 /* This variable is used below - don't move this assignment */
1851 sc->next_packet = sc->rec_page_start + 1;
1852
1853 /*
1854 * Set interface for page 0, Remote DMA complete, Stopped
1855 */
1856 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1857
1858 if (sc->isa16bit) {
1859
1860 /*
1861 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1862 * order=80x86, word-wide DMA xfers,
1863 */
1864 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1865 } else {
1866
1867 /*
1868 * Same as above, but byte-wide DMA xfers
1869 */
1870 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1871 }
1872
1873 /*
1874 * Clear Remote Byte Count Registers
1875 */
1876 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1877 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1878
1879 /*
1880 * For the moment, don't store incoming packets in memory.
1881 */
1882 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1883
1884 /*
1885 * Place NIC in internal loopback mode
1886 */
1887 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1888
1889 /*
1890 * Initialize transmit/receive (ring-buffer) Page Start
1891 */
1892 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1893 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1894 /* Set lower bits of byte addressable framing to 0 */
1895 if (sc->is790)
1896 outb(sc->nic_addr + 0x09, 0);
1897
1898 /*
1899 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1900 */
1901 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1902 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1903
1904 /*
1905 * Clear all interrupts. A '1' in each bit position clears the
1906 * corresponding flag.
1907 */
1908 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1909
1910 /*
1911 * Enable the following interrupts: receive/transmit complete,
1912 * receive/transmit error, and Receiver OverWrite.
1913 *
1914 * Counter overflow and Remote DMA complete are *not* enabled.
1915 */
1916 outb(sc->nic_addr + ED_P0_IMR,
1917 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1918
1919 /*
1920 * Program Command Register for page 1
1921 */
1922 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1923
1924 /*
1925 * Copy out our station address
1926 */
1927 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1928 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1929
1930 /*
1931 * Set Current Page pointer to next_packet (initialized above)
1932 */
1933 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1934
1935 /*
1936 * Program Receiver Configuration Register and multicast filter. CR is
1937 * set to page 0 on return.
1938 */
1939 ed_setrcr(sc);
1940
1941 /*
1942 * Take interface out of loopback
1943 */
1944 outb(sc->nic_addr + ED_P0_TCR, 0);
1945
1946 /*
1947 * If this is a 3Com board, the tranceiver must be software enabled
1948 * (there is no settable hardware default).
1949 */
1950 if (sc->vendor == ED_VENDOR_3COM) {
1951 if (ifp->if_flags & IFF_ALTPHYS) {
1952 outb(sc->asic_addr + ED_3COM_CR, 0);
1953 } else {
1954 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1955 }
1956 }
1957
1958 /*
1959 * Set 'running' flag, and clear output active flag.
1960 */
1961 ifp->if_flags |= IFF_RUNNING;
1962 ifp->if_flags &= ~IFF_OACTIVE;
1963
1964 /*
1965 * ...and attempt to start output
1966 */
1967 ed_start(ifp);
1968
1969 (void) splx(s);
1970}
1971
1972/*
1973 * This routine actually starts the transmission on the interface
1974 */
1975static inline void
1976ed_xmit(sc)
1977 struct ed_softc *sc;
1978{
1979 struct ifnet *ifp = (struct ifnet *)sc;
1980 unsigned short len;
1981
1982 if (sc->gone)
1983 return;
1984 len = sc->txb_len[sc->txb_next_tx];
1985
1986 /*
1987 * Set NIC for page 0 register access
1988 */
1989 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
1990
1991 /*
1992 * Set TX buffer start page
1993 */
1994 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1995 sc->txb_next_tx * ED_TXBUF_SIZE);
1996
1997 /*
1998 * Set TX length
1999 */
2000 outb(sc->nic_addr + ED_P0_TBCR0, len);
2001 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
2002
2003 /*
2004 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2005 */
2006 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2007 sc->xmit_busy = 1;
2008
2009 /*
2010 * Point to next transmit buffer slot and wrap if necessary.
2011 */
2012 sc->txb_next_tx++;
2013 if (sc->txb_next_tx == sc->txb_cnt)
2014 sc->txb_next_tx = 0;
2015
2016 /*
2017 * Set a timer just in case we never hear from the board again
2018 */
2019 ifp->if_timer = 2;
2020}
2021
2022/*
2023 * Start output on interface.
2024 * We make two assumptions here:
2025 * 1) that the current priority is set to splimp _before_ this code
2026 * is called *and* is returned to the appropriate priority after
2027 * return
2028 * 2) that the IFF_OACTIVE flag is checked before this code is called
2029 * (i.e. that the output part of the interface is idle)
2030 */
2031static void
2032ed_start(ifp)
2033 struct ifnet *ifp;
2034{
2035 struct ed_softc *sc = ifp->if_softc;
2036 struct mbuf *m0, *m;
2037 caddr_t buffer;
2038 int len;
2039
2040 if (sc->gone) {
2041 printf("ed_start(%p) GONE\n",ifp);
2042 return;
2043 }
2044outloop:
2045
2046 /*
2047 * First, see if there are buffered packets and an idle transmitter -
2048 * should never happen at this point.
2049 */
2050 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2051 printf("ed: packets buffered, but transmitter idle\n");
2052 ed_xmit(sc);
2053 }
2054
2055 /*
2056 * See if there is room to put another packet in the buffer.
2057 */
2058 if (sc->txb_inuse == sc->txb_cnt) {
2059
2060 /*
2061 * No room. Indicate this to the outside world and exit.
2062 */
2063 ifp->if_flags |= IFF_OACTIVE;
2064 return;
2065 }
2066 IF_DEQUEUE(&ifp->if_snd, m);
2067 if (m == 0) {
2068
2069 /*
2070 * We are using the !OACTIVE flag to indicate to the outside
2071 * world that we can accept an additional packet rather than
2072 * that the transmitter is _actually_ active. Indeed, the
2073 * transmitter may be active, but if we haven't filled all the
2074 * buffers with data then we still want to accept more.
2075 */
2076 ifp->if_flags &= ~IFF_OACTIVE;
2077 return;
2078 }
2079
2080 /*
2081 * Copy the mbuf chain into the transmit buffer
2082 */
2083
2084 m0 = m;
2085
2086 /* txb_new points to next open buffer slot */
2087 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2088
2089 if (sc->mem_shared) {
2090
2091 /*
2092 * Special case setup for 16 bit boards...
2093 */
2094 if (sc->isa16bit) {
2095 switch (sc->vendor) {
2096
2097 /*
2098 * For 16bit 3Com boards (which have 16k of
2099 * memory), we have the xmit buffers in a
2100 * different page of memory ('page 0') - so
2101 * change pages.
2102 */
2103 case ED_VENDOR_3COM:
2104 outb(sc->asic_addr + ED_3COM_GACFR,
2105 ED_3COM_GACFR_RSEL);
2106 break;
2107
2108 /*
2109 * Enable 16bit access to shared memory on
2110 * WD/SMC boards.
2111 */
2112 case ED_VENDOR_WD_SMC:{
2113 outb(sc->asic_addr + ED_WD_LAAR,
2114 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2115 if (sc->is790) {
2116 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2117 }
2118 break;
2119 }
2120 }
2121 }
2122 for (len = 0; m != 0; m = m->m_next) {
2123 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2124 buffer += m->m_len;
2125 len += m->m_len;
2126 }
2127
2128 /*
2129 * Restore previous shared memory access
2130 */
2131 if (sc->isa16bit) {
2132 switch (sc->vendor) {
2133 case ED_VENDOR_3COM:
2134 outb(sc->asic_addr + ED_3COM_GACFR,
2135 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2136 break;
2137 case ED_VENDOR_WD_SMC:{
2138 if (sc->is790) {
2139 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2140 }
2141 outb(sc->asic_addr + ED_WD_LAAR,
2142 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2143 break;
2144 }
2145 }
2146 }
2147 } else {
2148 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2149 if (len == 0)
2150 goto outloop;
2151 }
2152
2153 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2154
2155 sc->txb_inuse++;
2156
2157 /*
2158 * Point to next buffer slot and wrap if necessary.
2159 */
2160 sc->txb_new++;
2161 if (sc->txb_new == sc->txb_cnt)
2162 sc->txb_new = 0;
2163
2164 if (sc->xmit_busy == 0)
2165 ed_xmit(sc);
2166
2167 /*
2168 * Tap off here if there is a bpf listener.
2169 */
2170#if NBPFILTER > 0
2171 if (ifp->if_bpf) {
2172 bpf_mtap(ifp, m0);
2173 }
2174#endif
2175
2176 m_freem(m0);
2177
2178 /*
2179 * Loop back to the top to possibly buffer more packets
2180 */
2181 goto outloop;
2182}
2183
2184/*
2185 * Ethernet interface receiver interrupt.
2186 */
2187static inline void
2188ed_rint(sc)
2189 struct ed_softc *sc;
2190{
2191 struct ifnet *ifp = &sc->arpcom.ac_if;
2192 u_char boundry;
2193 u_short len;
2194 struct ed_ring packet_hdr;
2195 char *packet_ptr;
2196
2197 if (sc->gone)
2198 return;
2199
2200 /*
2201 * Set NIC to page 1 registers to get 'current' pointer
2202 */
2203 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2204
2205 /*
2206 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2207 * i.e. it points to where new data has been buffered. The 'CURR'
2208 * (current) register points to the logical end of the ring-buffer -
2209 * i.e. it points to where additional new data will be added. We loop
2210 * here until the logical beginning equals the logical end (or in
2211 * other words, until the ring-buffer is empty).
2212 */
2213 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2214
2215 /* get pointer to this buffer's header structure */
2216 packet_ptr = sc->mem_ring +
2217 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2218
2219 /*
2220 * The byte count includes a 4 byte header that was added by
2221 * the NIC.
2222 */
2223 if (sc->mem_shared)
2224 packet_hdr = *(struct ed_ring *) packet_ptr;
2225 else
2226 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2227 sizeof(packet_hdr));
2228 len = packet_hdr.count;
2229 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2230 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2231 /*
2232 * Length is a wild value. There's a good chance that
2233 * this was caused by the NIC being old and buggy.
2234 * The bug is that the length low byte is duplicated in
2235 * the high byte. Try to recalculate the length based on
2236 * the pointer to the next packet.
2237 */
2238 /*
2239 * NOTE: sc->next_packet is pointing at the current packet.
2240 */
2241 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2242 if (packet_hdr.next_packet >= sc->next_packet) {
2243 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2244 } else {
2245 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2246 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2247 }
2248 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2249 + sizeof(struct ed_ring)))
2250 sc->mibdata.dot3StatsFrameTooLongs++;
2251 }
2252 /*
2253 * Be fairly liberal about what we allow as a "reasonable" length
2254 * so that a [crufty] packet will make it to BPF (and can thus
2255 * be analyzed). Note that all that is really important is that
2256 * we have a length that will fit into one mbuf cluster or less;
2257 * the upper layer protocols can then figure out the length from
2258 * their own length field(s).
2259 */
2260 if ((len > sizeof(struct ed_ring)) &&
2261 (len <= MCLBYTES) &&
2262 (packet_hdr.next_packet >= sc->rec_page_start) &&
2263 (packet_hdr.next_packet < sc->rec_page_stop)) {
2264 /*
2265 * Go get packet.
2266 */
2267 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2268 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY);
2269 ifp->if_ipackets++;
2270 } else {
2271 /*
2272 * Really BAD. The ring pointers are corrupted.
2273 */
2274 log(LOG_ERR,
2275 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2276 ifp->if_unit, len);
2277 ifp->if_ierrors++;
2278 ed_reset(ifp);
2279 return;
2280 }
2281
2282 /*
2283 * Update next packet pointer
2284 */
2285 sc->next_packet = packet_hdr.next_packet;
2286
2287 /*
2288 * Update NIC boundry pointer - being careful to keep it one
2289 * buffer behind. (as recommended by NS databook)
2290 */
2291 boundry = sc->next_packet - 1;
2292 if (boundry < sc->rec_page_start)
2293 boundry = sc->rec_page_stop - 1;
2294
2295 /*
2296 * Set NIC to page 0 registers to update boundry register
2297 */
2298 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2299
2300 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2301
2302 /*
2303 * Set NIC to page 1 registers before looping to top (prepare
2304 * to get 'CURR' current pointer)
2305 */
2306 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2307 }
2308}
2309
2310/*
2311 * Ethernet interface interrupt processor
2312 */
2313void
2314edintr_sc(sc)
2315 struct ed_softc *sc;
2316{
2317 struct ifnet *ifp = (struct ifnet *)sc;
2318 u_char isr;
2319
2320 if (sc->gone)
2321 return;
2322 /*
2323 * Set NIC to page 0 registers
2324 */
2325 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2326
2327 /*
2328 * loop until there are no more new interrupts
2329 */
2330 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2331
2332 /*
2333 * reset all the bits that we are 'acknowledging' by writing a
2334 * '1' to each bit position that was set (writing a '1'
2335 * *clears* the bit)
2336 */
2337 outb(sc->nic_addr + ED_P0_ISR, isr);
2338
2339 /*
2340 * Handle transmitter interrupts. Handle these first because
2341 * the receiver will reset the board under some conditions.
2342 */
2343 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2344 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2345
2346 /*
2347 * Check for transmit error. If a TX completed with an
2348 * error, we end up throwing the packet away. Really
2349 * the only error that is possible is excessive
2350 * collisions, and in this case it is best to allow
2351 * the automatic mechanisms of TCP to backoff the
2352 * flow. Of course, with UDP we're screwed, but this
2353 * is expected when a network is heavily loaded.
2354 */
2355 (void) inb(sc->nic_addr + ED_P0_TSR);
2356 if (isr & ED_ISR_TXE) {
2357 u_char tsr;
2358
2359 /*
2360 * Excessive collisions (16)
2361 */
2362 tsr = inb(sc->nic_addr + ED_P0_TSR);
2363 if ((tsr & ED_TSR_ABT)
2364 && (collisions == 0)) {
2365
2366 /*
2367 * When collisions total 16, the
2368 * P0_NCR will indicate 0, and the
2369 * TSR_ABT is set.
2370 */
2371 collisions = 16;
2372 sc->mibdata.dot3StatsExcessiveCollisions++;
2373 sc->mibdata.dot3StatsCollFrequencies[15]++;
2374 }
2375 if (tsr & ED_TSR_OWC)
2376 sc->mibdata.dot3StatsLateCollisions++;
2377 if (tsr & ED_TSR_CDH)
2378 sc->mibdata.dot3StatsSQETestErrors++;
2379 if (tsr & ED_TSR_CRS)
2380 sc->mibdata.dot3StatsCarrierSenseErrors++;
2381 if (tsr & ED_TSR_FU)
2382 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2383
2384 /*
2385 * update output errors counter
2386 */
2387 ifp->if_oerrors++;
2388 } else {
2389
2390 /*
2391 * Update total number of successfully
2392 * transmitted packets.
2393 */
2394 ifp->if_opackets++;
2395 }
2396
2397 /*
2398 * reset tx busy and output active flags
2399 */
2400 sc->xmit_busy = 0;
2401 ifp->if_flags &= ~IFF_OACTIVE;
2402
2403 /*
2404 * clear watchdog timer
2405 */
2406 ifp->if_timer = 0;
2407
2408 /*
2409 * Add in total number of collisions on last
2410 * transmission.
2411 */
2412 ifp->if_collisions += collisions;
2413 switch(collisions) {
2414 case 0:
2415 case 16:
2416 break;
2417 case 1:
2418 sc->mibdata.dot3StatsSingleCollisionFrames++;
2419 sc->mibdata.dot3StatsCollFrequencies[0]++;
2420 break;
2421 default:
2422 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2423 sc->mibdata.
2424 dot3StatsCollFrequencies[collisions-1]
2425 ++;
2426 break;
2427 }
2428
2429 /*
2430 * Decrement buffer in-use count if not zero (can only
2431 * be zero if a transmitter interrupt occured while
2432 * not actually transmitting). If data is ready to
2433 * transmit, start it transmitting, otherwise defer
2434 * until after handling receiver
2435 */
2436 if (sc->txb_inuse && --sc->txb_inuse)
2437 ed_xmit(sc);
2438 }
2439
2440 /*
2441 * Handle receiver interrupts
2442 */
2443 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2444
2445 /*
2446 * Overwrite warning. In order to make sure that a
2447 * lockup of the local DMA hasn't occurred, we reset
2448 * and re-init the NIC. The NSC manual suggests only a
2449 * partial reset/re-init is necessary - but some chips
2450 * seem to want more. The DMA lockup has been seen
2451 * only with early rev chips - Methinks this bug was
2452 * fixed in later revs. -DG
2453 */
2454 if (isr & ED_ISR_OVW) {
2455 ifp->if_ierrors++;
2456#ifdef DIAGNOSTIC
2457 log(LOG_WARNING,
2458 "ed%d: warning - receiver ring buffer overrun\n",
2459 ifp->if_unit);
2460#endif
2461
2462 /*
2463 * Stop/reset/re-init NIC
2464 */
2465 ed_reset(ifp);
2466 } else {
2467
2468 /*
2469 * Receiver Error. One or more of: CRC error,
2470 * frame alignment error FIFO overrun, or
2471 * missed packet.
2472 */
2473 if (isr & ED_ISR_RXE) {
2474 u_char rsr;
2475 rsr = inb(sc->nic_addr + ED_P0_RSR);
2476 if (rsr & ED_RSR_CRC)
2477 sc->mibdata.dot3StatsFCSErrors++;
2478 if (rsr & ED_RSR_FAE)
2479 sc->mibdata.dot3StatsAlignmentErrors++;
2480 if (rsr & ED_RSR_FO)
2481 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2482 ifp->if_ierrors++;
2483#ifdef ED_DEBUG
2484 printf("ed%d: receive error %x\n", ifp->if_unit,
2485 inb(sc->nic_addr + ED_P0_RSR));
2486#endif
2487 }
2488
2489 /*
2490 * Go get the packet(s) XXX - Doing this on an
2491 * error is dubious because there shouldn't be
2492 * any data to get (we've configured the
2493 * interface to not accept packets with
2494 * errors).
2495 */
2496
2497 /*
2498 * Enable 16bit access to shared memory first
2499 * on WD/SMC boards.
2500 */
2501 if (sc->isa16bit &&
2502 (sc->vendor == ED_VENDOR_WD_SMC)) {
2503
2504 outb(sc->asic_addr + ED_WD_LAAR,
2505 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2506 if (sc->is790) {
2507 outb(sc->asic_addr + ED_WD_MSR,
2508 ED_WD_MSR_MENB);
2509 }
2510 }
2511 ed_rint(sc);
2512
2513 /* disable 16bit access */
2514 if (sc->isa16bit &&
2515 (sc->vendor == ED_VENDOR_WD_SMC)) {
2516
2517 if (sc->is790) {
2518 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2519 }
2520 outb(sc->asic_addr + ED_WD_LAAR,
2521 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2522 }
2523 }
2524 }
2525
2526 /*
2527 * If it looks like the transmitter can take more data,
2528 * attempt to start output on the interface. This is done
2529 * after handling the receiver to give the receiver priority.
2530 */
2531 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2532 ed_start(ifp);
2533
2534 /*
2535 * return NIC CR to standard state: page 0, remote DMA
2536 * complete, start (toggling the TXP bit off, even if was just
2537 * set in the transmit routine, is *okay* - it is 'edge'
2538 * triggered from low to high)
2539 */
2540 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2541
2542 /*
2543 * If the Network Talley Counters overflow, read them to reset
2544 * them. It appears that old 8390's won't clear the ISR flag
2545 * otherwise - resulting in an infinite loop.
2546 */
2547 if (isr & ED_ISR_CNT) {
2548 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2549 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2550 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2551 }
2552 }
2553}
2554
2555void
2556edintr(unit)
2557 int unit;
2558{
2559 edintr_sc (&ed_softc[unit]);
2560}
2561
2562/*
2563 * Process an ioctl request. This code needs some work - it looks
2564 * pretty ugly.
2565 */
2566static int
2567ed_ioctl(ifp, command, data)
2568 register struct ifnet *ifp;
2569 int command;
2570 caddr_t data;
2571{
2572 struct ed_softc *sc = ifp->if_softc;
2573 int s, error = 0;
2574
2575 if (sc->gone) {
2576 ifp->if_flags &= ~IFF_RUNNING;
2577 return ENXIO;
2578 }
2579 s = splimp();
2580
2581 switch (command) {
2582
2583 case SIOCSIFADDR:
2584 case SIOCGIFADDR:
2585 case SIOCSIFMTU:
2586 error = ether_ioctl(ifp, command, data);
2587 break;
2588
2589 case SIOCSIFFLAGS:
2590
2591 /*
2592 * If the interface is marked up and stopped, then start it.
2593 * If it is marked down and running, then stop it.
2594 */
2595 if (ifp->if_flags & IFF_UP) {
2596 if ((ifp->if_flags & IFF_RUNNING) == 0)
2597 ed_init(sc);
2598 } else {
2599 if (ifp->if_flags & IFF_RUNNING) {
2600 ed_stop(sc);
2601 ifp->if_flags &= ~IFF_RUNNING;
2602 }
2603 }
2604
2605#if NBPFILTER > 0
2606
2607 /*
2608 * Promiscuous flag may have changed, so reprogram the RCR.
2609 */
2610 ed_setrcr(sc);
2611#endif
2612
2613 /*
2614 * An unfortunate hack to provide the (required) software
2615 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2616 * disables the tranceiver if set.
2617 */
2618 if (sc->vendor == ED_VENDOR_3COM) {
2619 if (ifp->if_flags & IFF_ALTPHYS) {
2620 outb(sc->asic_addr + ED_3COM_CR, 0);
2621 } else {
2622 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2623 }
2624 } else if (sc->vendor == ED_VENDOR_HP)
2625 ed_hpp_set_physical_link(sc);
2626 break;
2627
2628 case SIOCADDMULTI:
2629 case SIOCDELMULTI:
2630 /*
2631 * Multicast list has changed; set the hardware filter
2632 * accordingly.
2633 */
2634 ed_setrcr(sc);
2635 error = 0;
2636 break;
2637
2638 default:
2639 error = EINVAL;
2640 }
2641 (void) splx(s);
2642 return (error);
2643}
2644
2645/*
2646 * Given a source and destination address, copy 'amount' of a packet from
2647 * the ring buffer into a linear destination buffer. Takes into account
2648 * ring-wrap.
2649 */
2650static inline char *
2651ed_ring_copy(sc, src, dst, amount)
2652 struct ed_softc *sc;
2653 char *src;
2654 char *dst;
2655 u_short amount;
2656{
2657 u_short tmp_amount;
2658
2659 /* does copy wrap to lower addr in ring buffer? */
2660 if (src + amount > sc->mem_end) {
2661 tmp_amount = sc->mem_end - src;
2662
2663 /* copy amount up to end of NIC memory */
2664 if (sc->mem_shared)
2665 bcopy(src, dst, tmp_amount);
2666 else
2667 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2668
2669 amount -= tmp_amount;
2670 src = sc->mem_ring;
2671 dst += tmp_amount;
2672 }
2673 if (sc->mem_shared)
2674 bcopy(src, dst, amount);
2675 else
2676 ed_pio_readmem(sc, (int)src, dst, amount);
2677
2678 return (src + amount);
2679}
2680
2681/*
2682 * Retreive packet from shared memory and send to the next level up via
2683 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2684 */
2685static void
2686ed_get_packet(sc, buf, len, multicast)
2687 struct ed_softc *sc;
2688 char *buf;
2689 u_short len;
2690 int multicast;
2691{
2692 struct ether_header *eh;
2693 struct mbuf *m;
2694
2695 /* Allocate a header mbuf */
2696 MGETHDR(m, M_DONTWAIT, MT_DATA);
2697 if (m == NULL)
2698 return;
2699 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2700 m->m_pkthdr.len = m->m_len = len;
2701
2702 /*
2703 * We always put the received packet in a single buffer -
2704 * either with just an mbuf header or in a cluster attached
2705 * to the header. The +2 is to compensate for the alignment
2706 * fixup below.
2707 */
2708 if ((len + 2) > MHLEN) {
2709 /* Attach an mbuf cluster */
2710 MCLGET(m, M_DONTWAIT);
2711
2712 /* Insist on getting a cluster */
2713 if ((m->m_flags & M_EXT) == 0) {
2714 m_freem(m);
2715 return;
2716 }
2717 }
2718
2719 /*
2720 * The +2 is to longword align the start of the real packet.
2721 * This is important for NFS.
2722 */
2723 m->m_data += 2;
2724 eh = mtod(m, struct ether_header *);
2725
2726 /*
2727 * Get packet, including link layer address, from interface.
2728 */
2729 ed_ring_copy(sc, buf, (char *)eh, len);
2730
2731#if NBPFILTER > 0
2732
2733 /*
2734 * Check if there's a BPF listener on this interface. If so, hand off
2735 * the raw packet to bpf.
2736 */
2737 if (sc->arpcom.ac_if.if_bpf) {
2738 bpf_mtap(&sc->arpcom.ac_if, m);
2739
2740 /*
2741 * Note that the interface cannot be in promiscuous mode if
2742 * there are no BPF listeners. And if we are in promiscuous
2743 * mode, we have to check if this packet is really ours.
2744 */
2745 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2746 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2747 sizeof(eh->ether_dhost)) != 0 && multicast == 0) {
2748 m_freem(m);
2749 return;
2750 }
2751 }
2752#endif
2753
2754 /*
2755 * Remove link layer address.
2756 */
2757 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2758 m->m_data += sizeof(struct ether_header);
2759
2760 ether_input(&sc->arpcom.ac_if, eh, m);
2761 return;
2762}
2763
2764/*
2765 * Supporting routines
2766 */
2767
2768/*
2769 * Given a NIC memory source address and a host memory destination
2770 * address, copy 'amount' from NIC to host using Programmed I/O.
2771 * The 'amount' is rounded up to a word - okay as long as mbufs
2772 * are word sized.
2773 * This routine is currently Novell-specific.
2774 */
2775static void
2776ed_pio_readmem(sc, src, dst, amount)
2777 struct ed_softc *sc;
2778 int src;
2779 unsigned char *dst;
2780 unsigned short amount;
2781{
2782 /* HP cards need special handling */
2783 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2784 ed_hpp_readmem(sc, src, dst, amount);
2785 return;
2786 }
2787
2788 /* Regular Novell cards */
2789 /* select page 0 registers */
2790 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2791
2792 /* round up to a word */
2793 if (amount & 1)
2794 ++amount;
2795
2796 /* set up DMA byte count */
2797 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2798 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2799
2800 /* set up source address in NIC mem */
2801 outb(sc->nic_addr + ED_P0_RSAR0, src);
2802 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2803
2804 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2805
2806 if (sc->isa16bit) {
2807 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2808 } else
2809 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2810
2811}
2812
2813/*
2814 * Stripped down routine for writing a linear buffer to NIC memory.
2815 * Only used in the probe routine to test the memory. 'len' must
2816 * be even.
2817 */
2818static void
2819ed_pio_writemem(sc, src, dst, len)
2820 struct ed_softc *sc;
2821 char *src;
2822 unsigned short dst;
2823 unsigned short len;
2824{
2825 int maxwait = 200; /* about 240us */
2826
2827 if (sc->vendor == ED_VENDOR_NOVELL) {
2828
2829 /* select page 0 registers */
2830 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2831
2832 /* reset remote DMA complete flag */
2833 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2834
2835 /* set up DMA byte count */
2836 outb(sc->nic_addr + ED_P0_RBCR0, len);
2837 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2838
2839 /* set up destination address in NIC mem */
2840 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2841 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2842
2843 /* set remote DMA write */
2844 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2845
2846 if (sc->isa16bit)
2847 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2848 else
2849 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2850
2851 /*
2852 * Wait for remote DMA complete. This is necessary because on the
2853 * transmit side, data is handled internally by the NIC in bursts and
2854 * we can't start another remote DMA until this one completes. Not
2855 * waiting causes really bad things to happen - like the NIC
2856 * irrecoverably jamming the ISA bus.
2857 */
2858 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2859
2860 } else if ((sc->vendor == ED_VENDOR_HP) &&
2861 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2862
2863 /* HP PCLAN+ */
2864
2865 /* reset remote DMA complete flag */
2866 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2867
2868 /* program the write address in RAM */
2869 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2870
2871 if (sc->hpp_mem_start) {
2872 u_short *s = (u_short *) src;
2873 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2874 u_short *const fence = s + (len >> 1);
2875
2876 /*
2877 * Enable memory mapped access.
2878 */
2879
2880 outw(sc->asic_addr + ED_HPP_OPTION,
2881 sc->hpp_options &
2882 ~(ED_HPP_OPTION_MEM_DISABLE |
2883 ED_HPP_OPTION_BOOT_ROM_ENB));
2884
2885 /*
2886 * Copy to NIC memory.
2887 */
2888
2889 while (s < fence)
2890 *d = *s++;
2891
2892 /*
2893 * Restore Boot ROM access.
2894 */
2895
2896 outw(sc->asic_addr + ED_HPP_OPTION,
2897 sc->hpp_options);
2898
2899 } else {
2900 /* write data using I/O writes */
2901 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2902 }
2903
2904 }
2905}
2906
2907/*
2908 * Write an mbuf chain to the destination NIC memory address using
2909 * programmed I/O.
2910 */
2911static u_short
2912ed_pio_write_mbufs(sc, m, dst)
2913 struct ed_softc *sc;
2914 struct mbuf *m;
2915 int dst;
2916{
2917 struct ifnet *ifp = (struct ifnet *)sc;
2918 unsigned short total_len, dma_len;
2919 struct mbuf *mp;
2920 int maxwait = 200; /* about 240us */
2921
2922 /* HP PC Lan+ cards need special handling */
2923 if ((sc->vendor == ED_VENDOR_HP) &&
2924 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2925 return ed_hpp_write_mbufs(sc, m, dst);
2926 }
2927
2928 /* First, count up the total number of bytes to copy */
2929 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2930 total_len += mp->m_len;
2931
2932 dma_len = total_len;
2933 if (sc->isa16bit && (dma_len & 1))
2934 dma_len++;
2935
2936 /* select page 0 registers */
2937 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2938
2939 /* reset remote DMA complete flag */
2940 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2941
2942 /* set up DMA byte count */
2943 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2944 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
2945
2946 /* set up destination address in NIC mem */
2947 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2948 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2949
2950 /* set remote DMA write */
2951 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2952
2953 /*
2954 * Transfer the mbuf chain to the NIC memory.
2955 * 16-bit cards require that data be transferred as words, and only words.
2956 * So that case requires some extra code to patch over odd-length mbufs.
2957 */
2958
2959 if (!sc->isa16bit) {
2960 /* NE1000s are easy */
2961 while (m) {
2962 if (m->m_len) {
2963 outsb(sc->asic_addr + ED_NOVELL_DATA,
2964 m->m_data, m->m_len);
2965 }
2966 m = m->m_next;
2967 }
2968 } else {
2969 /* NE2000s are a pain */
2970 unsigned char *data;
2971 int len, wantbyte;
2972 unsigned char savebyte[2];
2973
2974 wantbyte = 0;
2975
2976 while (m) {
2977 len = m->m_len;
2978 if (len) {
2979 data = mtod(m, caddr_t);
2980 /* finish the last word */
2981 if (wantbyte) {
2982 savebyte[1] = *data;
2983 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
2984 data++;
2985 len--;
2986 wantbyte = 0;
2987 }
2988 /* output contiguous words */
2989 if (len > 1) {
2990 outsw(sc->asic_addr + ED_NOVELL_DATA,
2991 data, len >> 1);
2992 data += len & ~1;
2993 len &= 1;
2994 }
2995 /* save last byte, if necessary */
2996 if (len == 1) {
2997 savebyte[0] = *data;
2998 wantbyte = 1;
2999 }
3000 }
3001 m = m->m_next;
3002 }
3003 /* spit last byte */
3004 if (wantbyte) {
3005 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3006 }
3007 }
3008
3009 /*
3010 * Wait for remote DMA complete. This is necessary because on the
3011 * transmit side, data is handled internally by the NIC in bursts and
3012 * we can't start another remote DMA until this one completes. Not
3013 * waiting causes really bad things to happen - like the NIC
3014 * irrecoverably jamming the ISA bus.
3015 */
3016 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3017
3018 if (!maxwait) {
3019 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
3020 ifp->if_unit);
3021 ed_reset(ifp);
3022 return(0);
3023 }
3024 return (total_len);
3025}
3026
3027/*
3028 * Support routines to handle the HP PC Lan+ card.
3029 */
3030
3031/*
3032 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3033 * IO.
3034 */
3035
3036static void
3037ed_hpp_readmem(sc, src, dst, amount)
3038 struct ed_softc *sc;
3039 unsigned short src;
3040 unsigned char *dst;
3041 unsigned short amount;
3042{
3043
3044 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3045
3046
3047 /* Program the source address in RAM */
3048 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
3049
3050 /*
3051 * The HP PC Lan+ card supports word reads as well as
3052 * a memory mapped i/o port that is aliased to every
3053 * even address on the board.
3054 */
3055
3056 if (sc->hpp_mem_start) {
3057
3058 /* Enable memory mapped access. */
3059 outw(sc->asic_addr + ED_HPP_OPTION,
3060 sc->hpp_options &
3061 ~(ED_HPP_OPTION_MEM_DISABLE |
3062 ED_HPP_OPTION_BOOT_ROM_ENB));
3063
3064 if (use_32bit_access && (amount > 3)) {
3065 u_long *dl = (u_long *) dst;
3066 volatile u_long *const sl =
3067 (u_long *) sc->hpp_mem_start;
3068 u_long *const fence = dl + (amount >> 2);
3069
3070 /* Copy out NIC data. We could probably write this
3071 as a `movsl'. The currently generated code is lousy.
3072 */
3073
3074 while (dl < fence)
3075 *dl++ = *sl;
3076
3077 dst += (amount & ~3);
3078 amount &= 3;
3079
3080 }
3081
3082 /* Finish off any words left, as a series of short reads */
3083 if (amount > 1) {
3084 u_short *d = (u_short *) dst;
3085 volatile u_short *const s =
3086 (u_short *) sc->hpp_mem_start;
3087 u_short *const fence = d + (amount >> 1);
3088
3089 /* Copy out NIC data. */
3090
3091 while (d < fence)
3092 *d++ = *s;
3093
3094 dst += (amount & ~1);
3095 amount &= 1;
3096 }
3097
3098 /*
3099 * read in a byte; however we need to always read 16 bits
3100 * at a time or the hardware gets into a funny state
3101 */
3102
3103 if (amount == 1) {
3104 /* need to read in a short and copy LSB */
3105 volatile u_short *const s =
3106 (volatile u_short *) sc->hpp_mem_start;
3107
3108 *dst = (*s) & 0xFF;
3109 }
3110
3111 /* Restore Boot ROM access. */
3112
3113 outw(sc->asic_addr + ED_HPP_OPTION,
3114 sc->hpp_options);
3115
3116
3117 } else {
3118 /* Read in data using the I/O port */
3119 if (use_32bit_access && (amount > 3)) {
3120 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3121 dst += (amount & ~3);
3122 amount &= 3;
3123 }
3124 if (amount > 1) {
3125 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3126 dst += (amount & ~1);
3127 amount &= 1;
3128 }
3129 if (amount == 1) { /* read in a short and keep the LSB */
3130 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3131 }
3132 }
3133}
3134
3135/*
3136 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3137 * outsw() or via the memory mapped interface to the same register.
3138 * Writes have to be in word units; byte accesses won't work and may cause
3139 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3140 * allows it.
3141 */
3142
3143static u_short
3144ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3145{
3146 int len, wantbyte;
3147 unsigned short total_len;
3148 unsigned char savebyte[2];
3149 volatile u_short * const d =
3150 (volatile u_short *) sc->hpp_mem_start;
3151 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3152
3153 /* select page 0 registers */
3154 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3155
3156 /* reset remote DMA complete flag */
3157 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3158
3159 /* program the write address in RAM */
3160 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3161
3162 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3163 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3164 ~(ED_HPP_OPTION_MEM_DISABLE |
3165 ED_HPP_OPTION_BOOT_ROM_ENB));
3166
3167 wantbyte = 0;
3168 total_len = 0;
3169
3170 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3171 while (m) {
3172 total_len += (len = m->m_len);
3173 if (len) {
3174 caddr_t data = mtod(m, caddr_t);
3175 /* finish the last word of the previous mbuf */
3176 if (wantbyte) {
3177 savebyte[1] = *data;
3178 *d = *((ushort *) savebyte);
3179 data++; len--; wantbyte = 0;
3180 }
3181 /* output contiguous words */
3182 if ((len > 3) && (use_32bit_accesses)) {
3183 volatile u_long *const dl =
3184 (volatile u_long *) d;
3185 u_long *sl = (u_long *) data;
3186 u_long *fence = sl + (len >> 2);
3187
3188 while (sl < fence)
3189 *dl = *sl++;
3190
3191 data += (len & ~3);
3192 len &= 3;
3193 }
3194 /* finish off remain 16 bit writes */
3195 if (len > 1) {
3196 u_short *s = (u_short *) data;
3197 u_short *fence = s + (len >> 1);
3198
3199 while (s < fence)
3200 *d = *s++;
3201
3202 data += (len & ~1);
3203 len &= 1;
3204 }
3205 /* save last byte if needed */
3206 if (wantbyte = (len == 1))
3207 savebyte[0] = *data;
3208 }
3209 m = m->m_next; /* to next mbuf */
3210 }
3211 if (wantbyte) /* write last byte */
3212 *d = *((u_short *) savebyte);
3213 } else {
3214 /* use programmed I/O */
3215 while (m) {
3216 total_len += (len = m->m_len);
3217 if (len) {
3218 caddr_t data = mtod(m, caddr_t);
3219 /* finish the last word of the previous mbuf */
3220 if (wantbyte) {
3221 savebyte[1] = *data;
3222 outw(sc->asic_addr + ED_HPP_PAGE_4,
3223 *((u_short *)savebyte));
3224 data++;
3225 len--;
3226 wantbyte = 0;
3227 }
3228 /* output contiguous words */
3229 if ((len > 3) && use_32bit_accesses) {
3230 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3231 data, len >> 2);
3232 data += (len & ~3);
3233 len &= 3;
3234 }
3235 /* finish off remaining 16 bit accesses */
3236 if (len > 1) {
3237 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3238 data, len >> 1);
3239 data += (len & ~1);
3240 len &= 1;
3241 }
3242 if (wantbyte = (len == 1))
3243 savebyte[0] = *data;
3244
3245 } /* if len != 0 */
3246 m = m->m_next;
3247 }
3248 if (wantbyte) /* spit last byte */
3249 outw(sc->asic_addr + ED_HPP_PAGE_4,
3250 *(u_short *)savebyte);
3251
3252 }
3253
3254 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3255 outw(sc->asic_addr + ED_HPP_OPTION,
3256 sc->hpp_options);
3257
3258 return (total_len);
3259}
3260
3261static void
3262ed_setrcr(sc)
3263 struct ed_softc *sc;
3264{
3265 struct ifnet *ifp = (struct ifnet *)sc;
3266 int i;
3267
3268 /* set page 1 registers */
3269 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3270
3271 if (ifp->if_flags & IFF_PROMISC) {
3272
3273 /*
3274 * Reconfigure the multicast filter.
3275 */
3276 for (i = 0; i < 8; i++)
3277 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
3278
3279 /*
3280 * And turn on promiscuous mode. Also enable reception of
3281 * runts and packets with CRC & alignment errors.
3282 */
3283 /* Set page 0 registers */
3284 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3285
3286 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3287 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3288 } else {
3289 /* set up multicast addresses and filter modes */
3290 if (ifp->if_flags & IFF_MULTICAST) {
3291 u_long mcaf[2];
3292
3293 if (ifp->if_flags & IFF_ALLMULTI) {
3294 mcaf[0] = 0xffffffff;
3295 mcaf[1] = 0xffffffff;
3296 } else
3297 ds_getmcaf(sc, mcaf);
3298
3299 /*
3300 * Set multicast filter on chip.
3301 */
3302 for (i = 0; i < 8; i++)
3303 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]);
3304
3305 /* Set page 0 registers */
3306 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3307
3308 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3309 } else {
3310
3311 /*
3312 * Initialize multicast address hashing registers to
3313 * not accept multicasts.
3314 */
3315 for (i = 0; i < 8; ++i)
3316 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00);
3317
3318 /* Set page 0 registers */
3319 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3320
3321 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3322 }
3323 }
3324
3325 /*
3326 * Start interface.
3327 */
3328 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3329}
3330
3331/*
3332 * Compute crc for ethernet address
3333 */
3334static u_long
3335ds_crc(ep)
3336 u_char *ep;
3337{
3338#define POLYNOMIAL 0x04c11db6
3339 register u_long crc = 0xffffffffL;
3340 register int carry, i, j;
3341 register u_char b;
3342
3343 for (i = 6; --i >= 0;) {
3344 b = *ep++;
3345 for (j = 8; --j >= 0;) {
3346 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3347 crc <<= 1;
3348 b >>= 1;
3349 if (carry)
3350 crc = ((crc ^ POLYNOMIAL) | carry);
3351 }
3352 }
3353 return crc;
3354#undef POLYNOMIAL
3355}
3356
3357/*
3358 * Compute the multicast address filter from the
3359 * list of multicast addresses we need to listen to.
3360 */
3361static void
3362ds_getmcaf(sc, mcaf)
3363 struct ed_softc *sc;
3364 u_long *mcaf;
3365{
3366 register u_int index;
3367 register u_char *af = (u_char *) mcaf;
3368 struct ifmultiaddr *ifma;
3369
3370 mcaf[0] = 0;
3371 mcaf[1] = 0;
3372
3373 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3374 ifma = ifma->ifma_link.le_next) {
3375 if (ifma->ifma_addr->sa_family != AF_LINK)
3376 continue;
3377 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3378 >> 26;
3379 af[index >> 3] |= 1 << (index & 7);
3380 }
3381}