4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
| 4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
|
34
35
36#ifndef _LEM_H_DEFINED_
37#define _LEM_H_DEFINED_
38
39
40/* Tunables */
41
42/*
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
45 * 80-4096 for others
46 * Default Value: 256
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
53 */
54#define EM_MIN_TXD 80
55#define EM_MAX_TXD_82543 256
56#define EM_MAX_TXD 4096
57#define EM_DEFAULT_TXD EM_MAX_TXD_82543
58
59/*
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
62 * 80-4096 for others
63 * Default Value: 256
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
71 */
72#define EM_MIN_RXD 80
73#define EM_MAX_RXD_82543 256
74#define EM_MAX_RXD 4096
75#define EM_DEFAULT_RXD EM_MAX_RXD_82543
76
77/*
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
80 * Default Value: 64
81 * This value delays the generation of transmit interrupts in units of
82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
83 * efficiency if properly tuned for specific network traffic. If the
84 * system is reporting dropped transmits, this value may be set too high
85 * causing the driver to run out of available transmit descriptors.
86 */
87#define EM_TIDV 64
88
89/*
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
93 * Default Value: 64
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
99 * network conditions.
100 */
101#define EM_TADV 64
102
103/*
104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
105 * Valid Range: 0-65535 (0=off)
106 * Default Value: 0
107 * This value delays the generation of receive interrupts in units of 1.024
108 * microseconds. Receive interrupt reduction can improve CPU efficiency if
109 * properly tuned for specific network traffic. Increasing this value adds
110 * extra latency to frame reception and can end up decreasing the throughput
111 * of TCP traffic. If the system is reporting dropped receives, this value
112 * may be set too high, causing the driver to run out of available receive
113 * descriptors.
114 *
115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
116 * may hang (stop transmitting) under certain network conditions.
117 * If this occurs a WATCHDOG message is logged in the system
118 * event log. In addition, the controller is automatically reset,
119 * restoring the network connection. To eliminate the potential
120 * for the hang ensure that EM_RDTR is set to 0.
121 */
122#define EM_RDTR 0
123
124/*
125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
126 * Valid Range: 0-65535 (0=off)
127 * Default Value: 64
128 * This value, in units of 1.024 microseconds, limits the delay in which a
129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
130 * this value ensures that an interrupt is generated after the initial
131 * packet is received within the set amount of time. Proper tuning,
132 * along with EM_RDTR, may improve traffic throughput in specific network
133 * conditions.
134 */
135#define EM_RADV 64
136
137/*
138 * This parameter controls the max duration of transmit watchdog.
139 */
140#define EM_WATCHDOG (10 * hz)
141
142/*
143 * This parameter controls when the driver calls the routine to reclaim
144 * transmit descriptors.
145 */
146#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
147#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
148
149/*
150 * This parameter controls whether or not autonegotation is enabled.
151 * 0 - Disable autonegotiation
152 * 1 - Enable autonegotiation
153 */
154#define DO_AUTO_NEG 1
155
156/*
157 * This parameter control whether or not the driver will wait for
158 * autonegotiation to complete.
159 * 1 - Wait for autonegotiation to complete
160 * 0 - Don't wait for autonegotiation to complete
161 */
162#define WAIT_FOR_AUTO_NEG_DEFAULT 0
163
164/* Tunables -- End */
165
166#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
167 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
168 ADVERTISE_1000_FULL)
169
170#define AUTO_ALL_MODES 0
171
172/* PHY master/slave setting */
173#define EM_MASTER_SLAVE e1000_ms_hw_default
174
175/*
176 * Micellaneous constants
177 */
178#define EM_VENDOR_ID 0x8086
179#define EM_FLASH 0x0014
180
181#define EM_JUMBO_PBA 0x00000028
182#define EM_DEFAULT_PBA 0x00000030
183#define EM_SMARTSPEED_DOWNSHIFT 3
184#define EM_SMARTSPEED_MAX 15
185#define EM_MAX_LOOP 10
186
187#define MAX_NUM_MULTICAST_ADDRESSES 128
188#define PCI_ANY_ID (~0U)
189#define ETHER_ALIGN 2
190#define EM_FC_PAUSE_TIME 0x0680
191#define EM_EEPROM_APME 0x400;
192#define EM_82544_APME 0x0004;
193
194/* Code compatilbility between 6 and 7 */
195#ifndef ETHER_BPF_MTAP
196#define ETHER_BPF_MTAP BPF_MTAP
197#endif
198
199/*
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
203 */
204#define EM_DBA_ALIGN 128
205
206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
207
208/* PCI Config defines */
209#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210#define EM_BAR_TYPE_MASK 0x00000001
211#define EM_BAR_TYPE_MMEM 0x00000000
212#define EM_BAR_TYPE_IO 0x00000001
213#define EM_BAR_TYPE_FLASH 0x0014
214#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
215#define EM_BAR_MEM_TYPE_MASK 0x00000006
216#define EM_BAR_MEM_TYPE_32BIT 0x00000000
217#define EM_BAR_MEM_TYPE_64BIT 0x00000004
218#define EM_MSIX_BAR 3 /* On 82575 */
219
220#if __FreeBSD_version < 900000
221#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
222#endif
223
224/* Defines for printing debug information */
225#define DEBUG_INIT 0
226#define DEBUG_IOCTL 0
227#define DEBUG_HW 0
228
229#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
230#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
231#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
232#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
233#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
234#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
235#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
236#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
237#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
238
239#define EM_MAX_SCATTER 64
240#define EM_VFTA_SIZE 128
241#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
242#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
243#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
244#define ETH_ZLEN 60
245#define ETH_ADDR_LEN 6
246#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
247
248/*
249 * 82574 has a nonstandard address for EIAC
250 * and since its only used in MSIX, and in
251 * the em driver only 82574 uses MSIX we can
252 * solve it just using this define.
253 */
254#define EM_EIAC 0x000DC
255
256/* Used in for 82547 10Mb Half workaround */
257#define EM_PBA_BYTES_SHIFT 0xA
258#define EM_TX_HEAD_ADDR_SHIFT 7
259#define EM_PBA_TX_MASK 0xFFFF0000
260#define EM_FIFO_HDR 0x10
261#define EM_82547_PKT_THRESH 0x3e0
262
263/* Precision Time Sync (IEEE 1588) defines */
264#define ETHERTYPE_IEEE1588 0x88F7
265#define PICOSECS_PER_TICK 20833
266#define TSYNC_PORT 319 /* UDP port for the protocol */
267
268#ifdef NIC_PARAVIRT
269#define E1000_PARA_SUBDEV 0x1101 /* special id */
270#define E1000_CSBAL 0x02830 /* csb phys. addr. low */
271#define E1000_CSBAH 0x02834 /* csb phys. addr. hi */
272#include <net/paravirt.h>
273#endif /* NIC_PARAVIRT */
274
275/*
276 * Bus dma allocation structure used by
277 * e1000_dma_malloc and e1000_dma_free.
278 */
279struct em_dma_alloc {
280 bus_addr_t dma_paddr;
281 caddr_t dma_vaddr;
282 bus_dma_tag_t dma_tag;
283 bus_dmamap_t dma_map;
284 bus_dma_segment_t dma_seg;
285 int dma_nseg;
286};
287
288struct adapter;
289
290struct em_int_delay_info {
291 struct adapter *adapter; /* Back-pointer to the adapter struct */
292 int offset; /* Register offset to read/write */
293 int value; /* Current value in usecs */
294};
295
296/* Our adapter structure */
297struct adapter {
298 if_t ifp;
299 struct e1000_hw hw;
300
301 /* FreeBSD operating-system-specific structures. */
302 struct e1000_osdep osdep;
303 struct device *dev;
304 struct cdev *led_dev;
305
306 struct resource *memory;
307 struct resource *flash;
308 struct resource *msix;
309
310 struct resource *ioport;
311 int io_rid;
312
313 /* 82574 may use 3 int vectors */
314 struct resource *res[3];
315 void *tag[3];
316 int rid[3];
317
318 struct ifmedia media;
319 struct callout timer;
320 struct callout tx_fifo_timer;
321 bool watchdog_check;
322 int watchdog_time;
323 int msi;
324 int if_flags;
325 int max_frame_size;
326 int min_frame_size;
327 struct mtx core_mtx;
328 struct mtx tx_mtx;
329 struct mtx rx_mtx;
330 int em_insert_vlan_header;
331
332 /* Task for FAST handling */
333 struct task link_task;
334 struct task rxtx_task;
335 struct task rx_task;
336 struct task tx_task;
337 struct taskqueue *tq; /* private task queue */
338
339 eventhandler_tag vlan_attach;
340 eventhandler_tag vlan_detach;
341 u32 num_vlans;
342
343 /* Management and WOL features */
344 u32 wol;
345 bool has_manage;
346 bool has_amt;
347
348 /* Multicast array memory */
349 u8 *mta;
350
351 /*
352 ** Shadow VFTA table, this is needed because
353 ** the real vlan filter table gets cleared during
354 ** a soft reset and the driver needs to be able
355 ** to repopulate it.
356 */
357 u32 shadow_vfta[EM_VFTA_SIZE];
358
359 /* Info about the interface */
360 uint8_t link_active;
361 uint16_t link_speed;
362 uint16_t link_duplex;
363 uint32_t smartspeed;
364 uint32_t fc_setting;
365
366 struct em_int_delay_info tx_int_delay;
367 struct em_int_delay_info tx_abs_int_delay;
368 struct em_int_delay_info rx_int_delay;
369 struct em_int_delay_info rx_abs_int_delay;
370 struct em_int_delay_info tx_itr;
371
372 /*
373 * Transmit definitions
374 *
375 * We have an array of num_tx_desc descriptors (handled
376 * by the controller) paired with an array of tx_buffers
377 * (at tx_buffer_area).
378 * The index of the next available descriptor is next_avail_tx_desc.
379 * The number of remaining tx_desc is num_tx_desc_avail.
380 */
381 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
382 struct e1000_tx_desc *tx_desc_base;
383 uint32_t next_avail_tx_desc;
384 uint32_t next_tx_to_clean;
385 volatile uint16_t num_tx_desc_avail;
386 uint16_t num_tx_desc;
387 uint16_t last_hw_offload;
388 uint32_t txd_cmd;
389 struct em_buffer *tx_buffer_area;
390 bus_dma_tag_t txtag; /* dma tag for tx */
391 uint32_t tx_tso; /* last tx was tso */
392
393 /*
394 * Receive definitions
395 *
396 * we have an array of num_rx_desc rx_desc (handled by the
397 * controller), and paired with an array of rx_buffers
398 * (at rx_buffer_area).
399 * The next pair to check on receive is at offset next_rx_desc_to_check
400 */
401 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
402 struct e1000_rx_desc *rx_desc_base;
403 uint32_t next_rx_desc_to_check;
404 uint32_t rx_buffer_len;
405 uint16_t num_rx_desc;
406 int rx_process_limit;
407 struct em_buffer *rx_buffer_area;
408 bus_dma_tag_t rxtag;
409 bus_dmamap_t rx_sparemap;
410
411 /*
412 * First/last mbuf pointers, for
413 * collecting multisegment RX packets.
414 */
415 struct mbuf *fmp;
416 struct mbuf *lmp;
417
418 /* Misc stats maintained by the driver */
419 unsigned long dropped_pkts;
420 unsigned long mbuf_alloc_failed;
421 unsigned long mbuf_cluster_failed;
422 unsigned long no_tx_desc_avail1;
423 unsigned long no_tx_desc_avail2;
424 unsigned long no_tx_map_avail;
425 unsigned long no_tx_dma_setup;
426 unsigned long watchdog_events;
427 unsigned long rx_overruns;
428 unsigned long rx_irq;
429 unsigned long tx_irq;
430 unsigned long link_irq;
431
432 /* 82547 workaround */
433 uint32_t tx_fifo_size;
434 uint32_t tx_fifo_head;
435 uint32_t tx_fifo_head_addr;
436 uint64_t tx_fifo_reset_cnt;
437 uint64_t tx_fifo_wrk_cnt;
438 uint32_t tx_head_addr;
439
440 /* For 82544 PCIX Workaround */
441 boolean_t pcix_82544;
442 boolean_t in_detach;
443
444#ifdef NIC_SEND_COMBINING
445 /* 0 = idle; 1xxxx int-pending; 3xxxx int + d pending + tdt */
446#define MIT_PENDING_INT 0x10000 /* pending interrupt */
447#define MIT_PENDING_TDT 0x30000 /* both intr and tdt write are pending */
448 uint32_t shadow_tdt;
449 uint32_t sc_enable;
450#endif /* NIC_SEND_COMBINING */
451#ifdef BATCH_DISPATCH
452 uint32_t batch_enable;
453#endif /* BATCH_DISPATCH */
454
455#ifdef NIC_PARAVIRT
456 struct em_dma_alloc csb_mem; /* phys address */
457 struct paravirt_csb *csb; /* virtual addr */
458 uint32_t rx_retries; /* optimize rx loop */
459 uint32_t tdt_csb_count;// XXX stat
460 uint32_t tdt_reg_count;// XXX stat
461 uint32_t tdt_int_count;// XXX stat
462 uint32_t guest_need_kick_count;// XXX stat
463#endif /* NIC_PARAVIRT */
464
465 struct e1000_hw_stats stats;
466};
467
468/* ******************************************************************************
469 * vendor_info_array
470 *
471 * This array contains the list of Subvendor/Subdevice IDs on which the driver
472 * should load.
473 *
474 * ******************************************************************************/
475typedef struct _em_vendor_info_t {
476 unsigned int vendor_id;
477 unsigned int device_id;
478 unsigned int subvendor_id;
479 unsigned int subdevice_id;
480 unsigned int index;
481} em_vendor_info_t;
482
483struct em_buffer {
484 int next_eop; /* Index of the desc to watch */
485 struct mbuf *m_head;
486 bus_dmamap_t map; /* bus_dma map for packet */
487};
488
489/* For 82544 PCIX Workaround */
490typedef struct _ADDRESS_LENGTH_PAIR
491{
492 uint64_t address;
493 uint32_t length;
494} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
495
496typedef struct _DESCRIPTOR_PAIR
497{
498 ADDRESS_LENGTH_PAIR descriptor[4];
499 uint32_t elements;
500} DESC_ARRAY, *PDESC_ARRAY;
501
502#define EM_CORE_LOCK_INIT(_sc, _name) \
503 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
504#define EM_TX_LOCK_INIT(_sc, _name) \
505 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
506#define EM_RX_LOCK_INIT(_sc, _name) \
507 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
508#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
509#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
510#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
511#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
512#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
513#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
514#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
515#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
516#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
517#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
518#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
519#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
520
521#endif /* _LEM_H_DEFINED_ */
| 34
35
36#ifndef _LEM_H_DEFINED_
37#define _LEM_H_DEFINED_
38
39
40/* Tunables */
41
42/*
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
45 * 80-4096 for others
46 * Default Value: 256
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
53 */
54#define EM_MIN_TXD 80
55#define EM_MAX_TXD_82543 256
56#define EM_MAX_TXD 4096
57#define EM_DEFAULT_TXD EM_MAX_TXD_82543
58
59/*
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
62 * 80-4096 for others
63 * Default Value: 256
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
71 */
72#define EM_MIN_RXD 80
73#define EM_MAX_RXD_82543 256
74#define EM_MAX_RXD 4096
75#define EM_DEFAULT_RXD EM_MAX_RXD_82543
76
77/*
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
80 * Default Value: 64
81 * This value delays the generation of transmit interrupts in units of
82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
83 * efficiency if properly tuned for specific network traffic. If the
84 * system is reporting dropped transmits, this value may be set too high
85 * causing the driver to run out of available transmit descriptors.
86 */
87#define EM_TIDV 64
88
89/*
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
93 * Default Value: 64
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
99 * network conditions.
100 */
101#define EM_TADV 64
102
103/*
104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
105 * Valid Range: 0-65535 (0=off)
106 * Default Value: 0
107 * This value delays the generation of receive interrupts in units of 1.024
108 * microseconds. Receive interrupt reduction can improve CPU efficiency if
109 * properly tuned for specific network traffic. Increasing this value adds
110 * extra latency to frame reception and can end up decreasing the throughput
111 * of TCP traffic. If the system is reporting dropped receives, this value
112 * may be set too high, causing the driver to run out of available receive
113 * descriptors.
114 *
115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
116 * may hang (stop transmitting) under certain network conditions.
117 * If this occurs a WATCHDOG message is logged in the system
118 * event log. In addition, the controller is automatically reset,
119 * restoring the network connection. To eliminate the potential
120 * for the hang ensure that EM_RDTR is set to 0.
121 */
122#define EM_RDTR 0
123
124/*
125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
126 * Valid Range: 0-65535 (0=off)
127 * Default Value: 64
128 * This value, in units of 1.024 microseconds, limits the delay in which a
129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
130 * this value ensures that an interrupt is generated after the initial
131 * packet is received within the set amount of time. Proper tuning,
132 * along with EM_RDTR, may improve traffic throughput in specific network
133 * conditions.
134 */
135#define EM_RADV 64
136
137/*
138 * This parameter controls the max duration of transmit watchdog.
139 */
140#define EM_WATCHDOG (10 * hz)
141
142/*
143 * This parameter controls when the driver calls the routine to reclaim
144 * transmit descriptors.
145 */
146#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
147#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
148
149/*
150 * This parameter controls whether or not autonegotation is enabled.
151 * 0 - Disable autonegotiation
152 * 1 - Enable autonegotiation
153 */
154#define DO_AUTO_NEG 1
155
156/*
157 * This parameter control whether or not the driver will wait for
158 * autonegotiation to complete.
159 * 1 - Wait for autonegotiation to complete
160 * 0 - Don't wait for autonegotiation to complete
161 */
162#define WAIT_FOR_AUTO_NEG_DEFAULT 0
163
164/* Tunables -- End */
165
166#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
167 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
168 ADVERTISE_1000_FULL)
169
170#define AUTO_ALL_MODES 0
171
172/* PHY master/slave setting */
173#define EM_MASTER_SLAVE e1000_ms_hw_default
174
175/*
176 * Micellaneous constants
177 */
178#define EM_VENDOR_ID 0x8086
179#define EM_FLASH 0x0014
180
181#define EM_JUMBO_PBA 0x00000028
182#define EM_DEFAULT_PBA 0x00000030
183#define EM_SMARTSPEED_DOWNSHIFT 3
184#define EM_SMARTSPEED_MAX 15
185#define EM_MAX_LOOP 10
186
187#define MAX_NUM_MULTICAST_ADDRESSES 128
188#define PCI_ANY_ID (~0U)
189#define ETHER_ALIGN 2
190#define EM_FC_PAUSE_TIME 0x0680
191#define EM_EEPROM_APME 0x400;
192#define EM_82544_APME 0x0004;
193
194/* Code compatilbility between 6 and 7 */
195#ifndef ETHER_BPF_MTAP
196#define ETHER_BPF_MTAP BPF_MTAP
197#endif
198
199/*
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
203 */
204#define EM_DBA_ALIGN 128
205
206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
207
208/* PCI Config defines */
209#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210#define EM_BAR_TYPE_MASK 0x00000001
211#define EM_BAR_TYPE_MMEM 0x00000000
212#define EM_BAR_TYPE_IO 0x00000001
213#define EM_BAR_TYPE_FLASH 0x0014
214#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
215#define EM_BAR_MEM_TYPE_MASK 0x00000006
216#define EM_BAR_MEM_TYPE_32BIT 0x00000000
217#define EM_BAR_MEM_TYPE_64BIT 0x00000004
218#define EM_MSIX_BAR 3 /* On 82575 */
219
220#if __FreeBSD_version < 900000
221#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
222#endif
223
224/* Defines for printing debug information */
225#define DEBUG_INIT 0
226#define DEBUG_IOCTL 0
227#define DEBUG_HW 0
228
229#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
230#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
231#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
232#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
233#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
234#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
235#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
236#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
237#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
238
239#define EM_MAX_SCATTER 64
240#define EM_VFTA_SIZE 128
241#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
242#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
243#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
244#define ETH_ZLEN 60
245#define ETH_ADDR_LEN 6
246#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
247
248/*
249 * 82574 has a nonstandard address for EIAC
250 * and since its only used in MSIX, and in
251 * the em driver only 82574 uses MSIX we can
252 * solve it just using this define.
253 */
254#define EM_EIAC 0x000DC
255
256/* Used in for 82547 10Mb Half workaround */
257#define EM_PBA_BYTES_SHIFT 0xA
258#define EM_TX_HEAD_ADDR_SHIFT 7
259#define EM_PBA_TX_MASK 0xFFFF0000
260#define EM_FIFO_HDR 0x10
261#define EM_82547_PKT_THRESH 0x3e0
262
263/* Precision Time Sync (IEEE 1588) defines */
264#define ETHERTYPE_IEEE1588 0x88F7
265#define PICOSECS_PER_TICK 20833
266#define TSYNC_PORT 319 /* UDP port for the protocol */
267
268#ifdef NIC_PARAVIRT
269#define E1000_PARA_SUBDEV 0x1101 /* special id */
270#define E1000_CSBAL 0x02830 /* csb phys. addr. low */
271#define E1000_CSBAH 0x02834 /* csb phys. addr. hi */
272#include <net/paravirt.h>
273#endif /* NIC_PARAVIRT */
274
275/*
276 * Bus dma allocation structure used by
277 * e1000_dma_malloc and e1000_dma_free.
278 */
279struct em_dma_alloc {
280 bus_addr_t dma_paddr;
281 caddr_t dma_vaddr;
282 bus_dma_tag_t dma_tag;
283 bus_dmamap_t dma_map;
284 bus_dma_segment_t dma_seg;
285 int dma_nseg;
286};
287
288struct adapter;
289
290struct em_int_delay_info {
291 struct adapter *adapter; /* Back-pointer to the adapter struct */
292 int offset; /* Register offset to read/write */
293 int value; /* Current value in usecs */
294};
295
296/* Our adapter structure */
297struct adapter {
298 if_t ifp;
299 struct e1000_hw hw;
300
301 /* FreeBSD operating-system-specific structures. */
302 struct e1000_osdep osdep;
303 struct device *dev;
304 struct cdev *led_dev;
305
306 struct resource *memory;
307 struct resource *flash;
308 struct resource *msix;
309
310 struct resource *ioport;
311 int io_rid;
312
313 /* 82574 may use 3 int vectors */
314 struct resource *res[3];
315 void *tag[3];
316 int rid[3];
317
318 struct ifmedia media;
319 struct callout timer;
320 struct callout tx_fifo_timer;
321 bool watchdog_check;
322 int watchdog_time;
323 int msi;
324 int if_flags;
325 int max_frame_size;
326 int min_frame_size;
327 struct mtx core_mtx;
328 struct mtx tx_mtx;
329 struct mtx rx_mtx;
330 int em_insert_vlan_header;
331
332 /* Task for FAST handling */
333 struct task link_task;
334 struct task rxtx_task;
335 struct task rx_task;
336 struct task tx_task;
337 struct taskqueue *tq; /* private task queue */
338
339 eventhandler_tag vlan_attach;
340 eventhandler_tag vlan_detach;
341 u32 num_vlans;
342
343 /* Management and WOL features */
344 u32 wol;
345 bool has_manage;
346 bool has_amt;
347
348 /* Multicast array memory */
349 u8 *mta;
350
351 /*
352 ** Shadow VFTA table, this is needed because
353 ** the real vlan filter table gets cleared during
354 ** a soft reset and the driver needs to be able
355 ** to repopulate it.
356 */
357 u32 shadow_vfta[EM_VFTA_SIZE];
358
359 /* Info about the interface */
360 uint8_t link_active;
361 uint16_t link_speed;
362 uint16_t link_duplex;
363 uint32_t smartspeed;
364 uint32_t fc_setting;
365
366 struct em_int_delay_info tx_int_delay;
367 struct em_int_delay_info tx_abs_int_delay;
368 struct em_int_delay_info rx_int_delay;
369 struct em_int_delay_info rx_abs_int_delay;
370 struct em_int_delay_info tx_itr;
371
372 /*
373 * Transmit definitions
374 *
375 * We have an array of num_tx_desc descriptors (handled
376 * by the controller) paired with an array of tx_buffers
377 * (at tx_buffer_area).
378 * The index of the next available descriptor is next_avail_tx_desc.
379 * The number of remaining tx_desc is num_tx_desc_avail.
380 */
381 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
382 struct e1000_tx_desc *tx_desc_base;
383 uint32_t next_avail_tx_desc;
384 uint32_t next_tx_to_clean;
385 volatile uint16_t num_tx_desc_avail;
386 uint16_t num_tx_desc;
387 uint16_t last_hw_offload;
388 uint32_t txd_cmd;
389 struct em_buffer *tx_buffer_area;
390 bus_dma_tag_t txtag; /* dma tag for tx */
391 uint32_t tx_tso; /* last tx was tso */
392
393 /*
394 * Receive definitions
395 *
396 * we have an array of num_rx_desc rx_desc (handled by the
397 * controller), and paired with an array of rx_buffers
398 * (at rx_buffer_area).
399 * The next pair to check on receive is at offset next_rx_desc_to_check
400 */
401 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
402 struct e1000_rx_desc *rx_desc_base;
403 uint32_t next_rx_desc_to_check;
404 uint32_t rx_buffer_len;
405 uint16_t num_rx_desc;
406 int rx_process_limit;
407 struct em_buffer *rx_buffer_area;
408 bus_dma_tag_t rxtag;
409 bus_dmamap_t rx_sparemap;
410
411 /*
412 * First/last mbuf pointers, for
413 * collecting multisegment RX packets.
414 */
415 struct mbuf *fmp;
416 struct mbuf *lmp;
417
418 /* Misc stats maintained by the driver */
419 unsigned long dropped_pkts;
420 unsigned long mbuf_alloc_failed;
421 unsigned long mbuf_cluster_failed;
422 unsigned long no_tx_desc_avail1;
423 unsigned long no_tx_desc_avail2;
424 unsigned long no_tx_map_avail;
425 unsigned long no_tx_dma_setup;
426 unsigned long watchdog_events;
427 unsigned long rx_overruns;
428 unsigned long rx_irq;
429 unsigned long tx_irq;
430 unsigned long link_irq;
431
432 /* 82547 workaround */
433 uint32_t tx_fifo_size;
434 uint32_t tx_fifo_head;
435 uint32_t tx_fifo_head_addr;
436 uint64_t tx_fifo_reset_cnt;
437 uint64_t tx_fifo_wrk_cnt;
438 uint32_t tx_head_addr;
439
440 /* For 82544 PCIX Workaround */
441 boolean_t pcix_82544;
442 boolean_t in_detach;
443
444#ifdef NIC_SEND_COMBINING
445 /* 0 = idle; 1xxxx int-pending; 3xxxx int + d pending + tdt */
446#define MIT_PENDING_INT 0x10000 /* pending interrupt */
447#define MIT_PENDING_TDT 0x30000 /* both intr and tdt write are pending */
448 uint32_t shadow_tdt;
449 uint32_t sc_enable;
450#endif /* NIC_SEND_COMBINING */
451#ifdef BATCH_DISPATCH
452 uint32_t batch_enable;
453#endif /* BATCH_DISPATCH */
454
455#ifdef NIC_PARAVIRT
456 struct em_dma_alloc csb_mem; /* phys address */
457 struct paravirt_csb *csb; /* virtual addr */
458 uint32_t rx_retries; /* optimize rx loop */
459 uint32_t tdt_csb_count;// XXX stat
460 uint32_t tdt_reg_count;// XXX stat
461 uint32_t tdt_int_count;// XXX stat
462 uint32_t guest_need_kick_count;// XXX stat
463#endif /* NIC_PARAVIRT */
464
465 struct e1000_hw_stats stats;
466};
467
468/* ******************************************************************************
469 * vendor_info_array
470 *
471 * This array contains the list of Subvendor/Subdevice IDs on which the driver
472 * should load.
473 *
474 * ******************************************************************************/
475typedef struct _em_vendor_info_t {
476 unsigned int vendor_id;
477 unsigned int device_id;
478 unsigned int subvendor_id;
479 unsigned int subdevice_id;
480 unsigned int index;
481} em_vendor_info_t;
482
483struct em_buffer {
484 int next_eop; /* Index of the desc to watch */
485 struct mbuf *m_head;
486 bus_dmamap_t map; /* bus_dma map for packet */
487};
488
489/* For 82544 PCIX Workaround */
490typedef struct _ADDRESS_LENGTH_PAIR
491{
492 uint64_t address;
493 uint32_t length;
494} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
495
496typedef struct _DESCRIPTOR_PAIR
497{
498 ADDRESS_LENGTH_PAIR descriptor[4];
499 uint32_t elements;
500} DESC_ARRAY, *PDESC_ARRAY;
501
502#define EM_CORE_LOCK_INIT(_sc, _name) \
503 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
504#define EM_TX_LOCK_INIT(_sc, _name) \
505 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
506#define EM_RX_LOCK_INIT(_sc, _name) \
507 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
508#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
509#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
510#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
511#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
512#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
513#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
514#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
515#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
516#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
517#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
518#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
519#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
520
521#endif /* _LEM_H_DEFINED_ */
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