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if_em.h (164546) if_em.h (169240)
1/**************************************************************************
2
1/**************************************************************************
2
3Copyright (c) 2001-2006, Intel Corporation
3Copyright (c) 2001-2007, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33$FreeBSD: head/sys/dev/em/if_em.h 169240 2007-05-04 00:00:12Z jfv $
33
34
34/*$FreeBSD: head/sys/dev/em/if_em.h 164546 2006-11-23 05:43:39Z kmacy $*/
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39/* Tunables */
40
41/*
42 * EM_TXD: Maximum number of Transmit Descriptors
43 * Valid Range: 80-256 for 82542 and 82543-based adapters
44 * 80-4096 for others
45 * Default Value: 256
46 * This value is the number of transmit descriptors allocated by the driver.
47 * Increasing this value allows the driver to queue more transmits. Each
48 * descriptor is 16 bytes.
49 * Since TDLEN should be multiple of 128bytes, the number of transmit
50 * desscriptors should meet the following condition.
35#ifndef _EM_H_DEFINED_
36#define _EM_H_DEFINED_
37
38/* Tunables */
39
40/*
41 * EM_TXD: Maximum number of Transmit Descriptors
42 * Valid Range: 80-256 for 82542 and 82543-based adapters
43 * 80-4096 for others
44 * Default Value: 256
45 * This value is the number of transmit descriptors allocated by the driver.
46 * Increasing this value allows the driver to queue more transmits. Each
47 * descriptor is 16 bytes.
48 * Since TDLEN should be multiple of 128bytes, the number of transmit
49 * desscriptors should meet the following condition.
51 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0
50 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
52 */
53#define EM_MIN_TXD 80
54#define EM_MAX_TXD_82543 256
55#define EM_MAX_TXD 4096
56#define EM_DEFAULT_TXD EM_MAX_TXD_82543
57
58/*
59 * EM_RXD - Maximum number of receive Descriptors
60 * Valid Range: 80-256 for 82542 and 82543-based adapters
61 * 80-4096 for others
62 * Default Value: 256
63 * This value is the number of receive descriptors allocated by the driver.
64 * Increasing this value allows the driver to buffer more incoming packets.
65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
66 * descriptor. The maximum MTU size is 16110.
67 * Since TDLEN should be multiple of 128bytes, the number of transmit
68 * desscriptors should meet the following condition.
51 */
52#define EM_MIN_TXD 80
53#define EM_MAX_TXD_82543 256
54#define EM_MAX_TXD 4096
55#define EM_DEFAULT_TXD EM_MAX_TXD_82543
56
57/*
58 * EM_RXD - Maximum number of receive Descriptors
59 * Valid Range: 80-256 for 82542 and 82543-based adapters
60 * 80-4096 for others
61 * Default Value: 256
62 * This value is the number of receive descriptors allocated by the driver.
63 * Increasing this value allows the driver to buffer more incoming packets.
64 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
65 * descriptor. The maximum MTU size is 16110.
66 * Since TDLEN should be multiple of 128bytes, the number of transmit
67 * desscriptors should meet the following condition.
69 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0
68 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
70 */
71#define EM_MIN_RXD 80
72#define EM_MAX_RXD_82543 256
73#define EM_MAX_RXD 4096
69 */
70#define EM_MIN_RXD 80
71#define EM_MAX_RXD_82543 256
72#define EM_MAX_RXD 4096
74#define EM_DEFAULT_RXD EM_MAX_RXD_82543
73#define EM_DEFAULT_RXD EM_MAX_RXD_82543
75
76/*
77 * EM_TIDV - Transmit Interrupt Delay Value
78 * Valid Range: 0-65535 (0=off)
79 * Default Value: 64
80 * This value delays the generation of transmit interrupts in units of
81 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
82 * efficiency if properly tuned for specific network traffic. If the

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136/*
137 * Inform the stack about transmit checksum offload capabilities.
138 */
139#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP)
140
141/*
142 * Inform the stack about transmit segmentation offload capabilities.
143 */
74
75/*
76 * EM_TIDV - Transmit Interrupt Delay Value
77 * Valid Range: 0-65535 (0=off)
78 * Default Value: 64
79 * This value delays the generation of transmit interrupts in units of
80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
81 * efficiency if properly tuned for specific network traffic. If the

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135/*
136 * Inform the stack about transmit checksum offload capabilities.
137 */
138#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP)
139
140/*
141 * Inform the stack about transmit segmentation offload capabilities.
142 */
144#define EM_TCPSEG_FEATURES CSUM_TSO
143#define EM_TCPSEG_FEATURES CSUM_TSO
145
146/*
147 * This parameter controls the duration of transmit watchdog timer.
148 */
149#define EM_TX_TIMEOUT 5 /* set to 5 seconds */
150
151/*
152 * This parameter controls when the driver calls the routine to reclaim
153 * transmit descriptors.
154 */
144
145/*
146 * This parameter controls the duration of transmit watchdog timer.
147 */
148#define EM_TX_TIMEOUT 5 /* set to 5 seconds */
149
150/*
151 * This parameter controls when the driver calls the routine to reclaim
152 * transmit descriptors.
153 */
155#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
154#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
155#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
156
157/*
158 * This parameter controls whether or not autonegotation is enabled.
159 * 0 - Disable autonegotiation
160 * 1 - Enable autonegotiation
161 */
162#define DO_AUTO_NEG 1
163
164/*
165 * This parameter control whether or not the driver will wait for
166 * autonegotiation to complete.
167 * 1 - Wait for autonegotiation to complete
168 * 0 - Don't wait for autonegotiation to complete
169 */
170#define WAIT_FOR_AUTO_NEG_DEFAULT 0
171
156
157/*
158 * This parameter controls whether or not autonegotation is enabled.
159 * 0 - Disable autonegotiation
160 * 1 - Enable autonegotiation
161 */
162#define DO_AUTO_NEG 1
163
164/*
165 * This parameter control whether or not the driver will wait for
166 * autonegotiation to complete.
167 * 1 - Wait for autonegotiation to complete
168 * 0 - Don't wait for autonegotiation to complete
169 */
170#define WAIT_FOR_AUTO_NEG_DEFAULT 0
171
172/*
173 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
174 * with 82541/82547 devices and some switches. See the "Known Limitations" section of
175 * the README file for a complete description and a list of affected switches.
176 *
177 * 0 = Hardware default
178 * 1 = Master mode
179 * 2 = Slave mode
180 * 3 = Auto master/slave
181 */
182/* #define EM_MASTER_SLAVE 2 */
172/* Tunables -- End */
183
173
174#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
175 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
176 ADVERTISE_1000_FULL)
184
177
185/*
186 * Limitation of some PCIe chipsets when using TSO
187 */
188#define EM_TSO_PCIE_SEGMENT_SIZE 4096
178#define AUTO_ALL_MODES 0
189
179
190/* Tunables -- End */
180/* PHY master/slave setting */
181#define EM_MASTER_SLAVE e1000_ms_hw_default
191
182
192#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
193 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
194 ADVERTISE_1000_FULL)
195
183/*
184 * Micellaneous constants
185 */
196#define EM_VENDOR_ID 0x8086
186#define EM_VENDOR_ID 0x8086
197#define EM_FLASH 0x0014 /* Flash memory on ICH8 */
187#define EM_FLASH 0x0014
198
199#define EM_JUMBO_PBA 0x00000028
200#define EM_DEFAULT_PBA 0x00000030
201#define EM_SMARTSPEED_DOWNSHIFT 3
202#define EM_SMARTSPEED_MAX 15
188
189#define EM_JUMBO_PBA 0x00000028
190#define EM_DEFAULT_PBA 0x00000030
191#define EM_SMARTSPEED_DOWNSHIFT 3
192#define EM_SMARTSPEED_MAX 15
193#define EM_MAX_INTR 10
194#define EM_TSO_SEG_SIZE 4096 /* Max dma seg size */
203
204#define MAX_NUM_MULTICAST_ADDRESSES 128
205#define PCI_ANY_ID (~0U)
206#define ETHER_ALIGN 2
195
196#define MAX_NUM_MULTICAST_ADDRESSES 128
197#define PCI_ANY_ID (~0U)
198#define ETHER_ALIGN 2
199#define EM_TX_BUFFER_SIZE ((uint32_t) 1514)
200#define EM_FC_PAUSE_TIME 0x0680
201#define EM_EEPROM_APME 0x400;
207
208/*
209 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
210 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
211 * also optimize cache line size effect. H/W supports up to cache line size 128.
212 */
213#define EM_DBA_ALIGN 128
214
215#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
216
217/* PCI Config defines */
202
203/*
204 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
205 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
206 * also optimize cache line size effect. H/W supports up to cache line size 128.
207 */
208#define EM_DBA_ALIGN 128
209
210#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
211
212/* PCI Config defines */
218#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
219#define EM_BAR_TYPE_MASK 0x00000001
220#define EM_BAR_TYPE_MMEM 0x00000000
221#define EM_BAR_TYPE_IO 0x00000001
222#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
223#define EM_BAR_MEM_TYPE_MASK 0x00000006
224#define EM_BAR_MEM_TYPE_32BIT 0x00000000
225#define EM_BAR_MEM_TYPE_64BIT 0x00000004
213#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
214#define EM_BAR_TYPE_MASK 0x00000001
215#define EM_BAR_TYPE_MMEM 0x00000000
216#define EM_BAR_TYPE_IO 0x00000001
217#define EM_BAR_TYPE_FLASH 0x0014
218#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
219#define EM_BAR_MEM_TYPE_MASK 0x00000006
220#define EM_BAR_MEM_TYPE_32BIT 0x00000000
221#define EM_BAR_MEM_TYPE_64BIT 0x00000004
226
227/* Defines for printing debug information */
228#define DEBUG_INIT 0
229#define DEBUG_IOCTL 0
230#define DEBUG_HW 0
231
232#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
233#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
234#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
235#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
236#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
237#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
238#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
239#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
240#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
241
222
223/* Defines for printing debug information */
224#define DEBUG_INIT 0
225#define DEBUG_IOCTL 0
226#define DEBUG_HW 0
227
228#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
229#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
230#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
231#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
232#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
233#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
234#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
235#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
236#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
237
238#define EM_MAX_SCATTER 64
239#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */
240#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
241#define ETH_ZLEN 60
242#define ETH_ADDR_LEN 6
242
243
243/* Supported RX Buffer Sizes */
244#define EM_RXBUFFER_2048 2048
245#define EM_RXBUFFER_4096 4096
246#define EM_RXBUFFER_8192 8192
247#define EM_RXBUFFER_16384 16384
248
249#define EM_MAX_SCATTER 64
250#define EM_TSO_SIZE 65535
251
252typedef enum _XSUM_CONTEXT_T {
253 OFFLOAD_NONE,
254 OFFLOAD_TCP_IP,
255 OFFLOAD_UDP_IP
256} XSUM_CONTEXT_T;
257
258struct adapter;
259
260struct em_int_delay_info {
244struct adapter;
245
246struct em_int_delay_info {
261 struct adapter *adapter; /* Back-pointer to the adapter struct */
262 int offset; /* Register offset to read/write */
263 int value; /* Current value in usecs */
247 struct adapter *adapter; /* Back-pointer to the adapter struct */
248 int offset; /* Register offset to read/write */
249 int value; /* Current value in usecs */
264};
265
266/*
267 * Bus dma allocation structure used by
250};
251
252/*
253 * Bus dma allocation structure used by
268 * em_dma_malloc() and em_dma_free().
254 * e1000_dma_malloc and e1000_dma_free.
269 */
270struct em_dma_alloc {
255 */
256struct em_dma_alloc {
271 bus_addr_t dma_paddr;
272 caddr_t dma_vaddr;
273 bus_dma_tag_t dma_tag;
274 bus_dmamap_t dma_map;
275 bus_dma_segment_t dma_seg;
276 int dma_nseg;
257 bus_addr_t dma_paddr;
258 caddr_t dma_vaddr;
259 bus_dma_tag_t dma_tag;
260 bus_dmamap_t dma_map;
261 bus_dma_segment_t dma_seg;
262 int dma_nseg;
277};
278
263};
264
279/* Driver softc. */
265/* Our adapter structure */
280struct adapter {
281 struct ifnet *ifp;
266struct adapter {
267 struct ifnet *ifp;
282 struct em_hw hw;
268 struct e1000_hw hw;
283
284 /* FreeBSD operating-system-specific structures. */
269
270 /* FreeBSD operating-system-specific structures. */
285 struct em_osdep osdep;
271 struct e1000_osdep osdep;
286 struct device *dev;
287 struct resource *res_memory;
288 struct resource *flash_mem;
289 struct resource *res_ioport;
290 struct resource *res_interrupt;
291 void *int_handler_tag;
292 struct ifmedia media;
293 struct callout timer;
294 struct callout tx_fifo_timer;
295 int watchdog_timer;
296 int io_rid;
297 int msi;
298 int if_flags;
299 struct mtx mtx;
300 int em_insert_vlan_header;
272 struct device *dev;
273 struct resource *res_memory;
274 struct resource *flash_mem;
275 struct resource *res_ioport;
276 struct resource *res_interrupt;
277 void *int_handler_tag;
278 struct ifmedia media;
279 struct callout timer;
280 struct callout tx_fifo_timer;
281 int watchdog_timer;
282 int io_rid;
283 int msi;
284 int if_flags;
285 struct mtx mtx;
286 int em_insert_vlan_header;
301 struct task link_task;
302 struct task rxtx_task;
303 struct taskqueue *tq; /* private task queue */
287 struct task link_task;
288 struct task rxtx_task;
289 struct taskqueue *tq; /* private task queue */
290 /* Management and WOL features */
291 int wol;
292 int has_manage;
304
305 /* Info about the board itself */
306 uint32_t part_num;
307 uint8_t link_active;
308 uint16_t link_speed;
309 uint16_t link_duplex;
310 uint32_t smartspeed;
311 struct em_int_delay_info tx_int_delay;
312 struct em_int_delay_info tx_abs_int_delay;
313 struct em_int_delay_info rx_int_delay;
314 struct em_int_delay_info rx_abs_int_delay;
315
293
294 /* Info about the board itself */
295 uint32_t part_num;
296 uint8_t link_active;
297 uint16_t link_speed;
298 uint16_t link_duplex;
299 uint32_t smartspeed;
300 struct em_int_delay_info tx_int_delay;
301 struct em_int_delay_info tx_abs_int_delay;
302 struct em_int_delay_info rx_int_delay;
303 struct em_int_delay_info rx_abs_int_delay;
304
316 XSUM_CONTEXT_T active_checksum_context;
317
318 /*
319 * Transmit definitions
320 *
321 * We have an array of num_tx_desc descriptors (handled
322 * by the controller) paired with an array of tx_buffers
323 * (at tx_buffer_area).
324 * The index of the next available descriptor is next_avail_tx_desc.
325 * The number of remaining tx_desc is num_tx_desc_avail.
326 */
327 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
305 /*
306 * Transmit definitions
307 *
308 * We have an array of num_tx_desc descriptors (handled
309 * by the controller) paired with an array of tx_buffers
310 * (at tx_buffer_area).
311 * The index of the next available descriptor is next_avail_tx_desc.
312 * The number of remaining tx_desc is num_tx_desc_avail.
313 */
314 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
328 struct em_tx_desc *tx_desc_base;
315 struct e1000_tx_desc *tx_desc_base;
329 uint32_t next_avail_tx_desc;
330 uint32_t next_tx_to_clean;
331 volatile uint16_t num_tx_desc_avail;
332 uint16_t num_tx_desc;
333 uint32_t txd_cmd;
334 struct em_buffer *tx_buffer_area;
335 bus_dma_tag_t txtag; /* dma tag for tx */
316 uint32_t next_avail_tx_desc;
317 uint32_t next_tx_to_clean;
318 volatile uint16_t num_tx_desc_avail;
319 uint16_t num_tx_desc;
320 uint32_t txd_cmd;
321 struct em_buffer *tx_buffer_area;
322 bus_dma_tag_t txtag; /* dma tag for tx */
336 uint32_t tx_tso; /* last tx was tso */
323 uint32_t tx_tso; /* last tx was tso */
337
324
325 /*
326 * Transmit function pointer:
327 * legacy or advanced (82575 and later)
328 */
329 int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp);
330
338 /*
339 * Receive definitions
340 *
341 * we have an array of num_rx_desc rx_desc (handled by the
342 * controller), and paired with an array of rx_buffers
343 * (at rx_buffer_area).
344 * The next pair to check on receive is at offset next_rx_desc_to_check
345 */
346 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
331 /*
332 * Receive definitions
333 *
334 * we have an array of num_rx_desc rx_desc (handled by the
335 * controller), and paired with an array of rx_buffers
336 * (at rx_buffer_area).
337 * The next pair to check on receive is at offset next_rx_desc_to_check
338 */
339 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
347 struct em_rx_desc *rx_desc_base;
340 struct e1000_rx_desc *rx_desc_base;
348 uint32_t next_rx_desc_to_check;
349 uint32_t rx_buffer_len;
350 uint16_t num_rx_desc;
351 int rx_process_limit;
352 struct em_buffer *rx_buffer_area;
353 bus_dma_tag_t rxtag;
354 bus_dmamap_t rx_sparemap;
355
341 uint32_t next_rx_desc_to_check;
342 uint32_t rx_buffer_len;
343 uint16_t num_rx_desc;
344 int rx_process_limit;
345 struct em_buffer *rx_buffer_area;
346 bus_dma_tag_t rxtag;
347 bus_dmamap_t rx_sparemap;
348
356 /* First/last mbuf pointers, for collecting multisegment RX packets. */
349 /*
350 * First/last mbuf pointers, for
351 * collecting multisegment RX packets.
352 */
357 struct mbuf *fmp;
358 struct mbuf *lmp;
359
360 /* Misc stats maintained by the driver */
353 struct mbuf *fmp;
354 struct mbuf *lmp;
355
356 /* Misc stats maintained by the driver */
357 unsigned long dropped_pkts;
361 unsigned long mbuf_alloc_failed;
362 unsigned long mbuf_cluster_failed;
363 unsigned long no_tx_desc_avail1;
364 unsigned long no_tx_desc_avail2;
365 unsigned long no_tx_map_avail;
366 unsigned long no_tx_dma_setup;
367 unsigned long watchdog_events;
368 unsigned long rx_overruns;

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381 uint64_t tx_fifo_reset_cnt;
382 uint64_t tx_fifo_wrk_cnt;
383 uint32_t tx_head_addr;
384
385 /* For 82544 PCIX Workaround */
386 boolean_t pcix_82544;
387 boolean_t in_detach;
388
358 unsigned long mbuf_alloc_failed;
359 unsigned long mbuf_cluster_failed;
360 unsigned long no_tx_desc_avail1;
361 unsigned long no_tx_desc_avail2;
362 unsigned long no_tx_map_avail;
363 unsigned long no_tx_dma_setup;
364 unsigned long watchdog_events;
365 unsigned long rx_overruns;

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378 uint64_t tx_fifo_reset_cnt;
379 uint64_t tx_fifo_wrk_cnt;
380 uint32_t tx_head_addr;
381
382 /* For 82544 PCIX Workaround */
383 boolean_t pcix_82544;
384 boolean_t in_detach;
385
389 struct em_hw_stats stats;
386 struct e1000_hw_stats stats;
390};
391
392/* ******************************************************************************
393 * vendor_info_array
394 *
395 * This array contains the list of Subvendor/Subdevice IDs on which the driver
396 * should load.
397 *
398 * ******************************************************************************/
399typedef struct _em_vendor_info_t {
400 unsigned int vendor_id;
401 unsigned int device_id;
402 unsigned int subvendor_id;
403 unsigned int subdevice_id;
404 unsigned int index;
405} em_vendor_info_t;
406
407
408struct em_buffer {
387};
388
389/* ******************************************************************************
390 * vendor_info_array
391 *
392 * This array contains the list of Subvendor/Subdevice IDs on which the driver
393 * should load.
394 *
395 * ******************************************************************************/
396typedef struct _em_vendor_info_t {
397 unsigned int vendor_id;
398 unsigned int device_id;
399 unsigned int subvendor_id;
400 unsigned int subdevice_id;
401 unsigned int index;
402} em_vendor_info_t;
403
404
405struct em_buffer {
409 int next_eop; /* Index of the desc to watch */
406 int next_eop; /* Index of the desc to watch */
410 struct mbuf *m_head;
411 bus_dmamap_t map; /* bus_dma map for packet */
412};
413
414/* For 82544 PCIX Workaround */
415typedef struct _ADDRESS_LENGTH_PAIR
416{
407 struct mbuf *m_head;
408 bus_dmamap_t map; /* bus_dma map for packet */
409};
410
411/* For 82544 PCIX Workaround */
412typedef struct _ADDRESS_LENGTH_PAIR
413{
417 uint64_t address;
418 uint32_t length;
414 uint64_t address;
415 uint32_t length;
419} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
420
421typedef struct _DESCRIPTOR_PAIR
422{
416} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
417
418typedef struct _DESCRIPTOR_PAIR
419{
423 ADDRESS_LENGTH_PAIR descriptor[4];
424 uint32_t elements;
420 ADDRESS_LENGTH_PAIR descriptor[4];
421 uint32_t elements;
425} DESC_ARRAY, *PDESC_ARRAY;
426
427#define EM_LOCK_INIT(_sc, _name) \
428 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
429#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
430#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx)
431#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
432#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
433
434#endif /* _EM_H_DEFINED_ */
422} DESC_ARRAY, *PDESC_ARRAY;
423
424#define EM_LOCK_INIT(_sc, _name) \
425 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
426#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
427#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx)
428#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
429#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
430
431#endif /* _EM_H_DEFINED_ */