| e1000_regs.h (194865) | e1000_regs.h (200243) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 194865 2009-06-24 17:41:29Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 200243 2009-12-08 01:07:44Z jfv $*/ |
| 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 42#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 43#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 44#define E1000_FLA 0x0001C /* Flash Access - RW */ 45#define E1000_MDIC 0x00020 /* MDI Control - RW */ | 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 42#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 43#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 44#define E1000_FLA 0x0001C /* Flash Access - RW */ 45#define E1000_MDIC 0x00020 /* MDI Control - RW */ |
| 46#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ 47#define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */ 48#define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */ 49#define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */ 50#define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ 51#define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ |
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| 46#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 47#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 48#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 49#define E1000_FEXT 0x0002C /* Future Extended - RW */ 50#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 51#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 52#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 53#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ --- 62 unchanged lines hidden (view full) --- 116/* Split and Replication Rx Control - RW */ 117#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ 118#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ 119#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ 120#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ 121#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ 122#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ 123#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ | 52#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 53#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 54#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 55#define E1000_FEXT 0x0002C /* Future Extended - RW */ 56#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 57#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 58#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 59#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ --- 62 unchanged lines hidden (view full) --- 122/* Split and Replication Rx Control - RW */ 123#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ 124#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ 125#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ 126#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ 127#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ 128#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ 129#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ |
| 124#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) 125#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) 126#define E1000_TXCTL(_n) (0x0E014 + (0x40 * (_n))) 127#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) 128#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) | 130#define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer adapters - RW */ |
| 129#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 130#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 131/* 132 * Convenience macros 133 * 134 * Note: "_n" is the queue number of the register to be written to. 135 * 136 * Example usage: --- 4 unchanged lines hidden (view full) --- 141#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 142 (0x0C004 + ((_n) * 0x40))) 143#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 144 (0x0C008 + ((_n) * 0x40))) 145#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 146 (0x0C00C + ((_n) * 0x40))) 147#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 148 (0x0C010 + ((_n) * 0x40))) | 131#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 132#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 133/* 134 * Convenience macros 135 * 136 * Note: "_n" is the queue number of the register to be written to. 137 * 138 * Example usage: --- 4 unchanged lines hidden (view full) --- 143#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 144 (0x0C004 + ((_n) * 0x40))) 145#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 146 (0x0C008 + ((_n) * 0x40))) 147#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 148 (0x0C00C + ((_n) * 0x40))) 149#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 150 (0x0C010 + ((_n) * 0x40))) |
| 151#define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \ 152 (0x0C014 + ((_n) * 0x40))) 153#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n) |
|
| 149#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 150 (0x0C018 + ((_n) * 0x40))) 151#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 152 (0x0C028 + ((_n) * 0x40))) | 154#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 155 (0x0C018 + ((_n) * 0x40))) 156#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 157 (0x0C028 + ((_n) * 0x40))) |
| 158#define E1000_RQDPC(_n) ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \ 159 (0x0C030 + ((_n) * 0x40))) |
|
| 153#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 154 (0x0E000 + ((_n) * 0x40))) 155#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 156 (0x0E004 + ((_n) * 0x40))) 157#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 158 (0x0E008 + ((_n) * 0x40))) 159#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 160 (0x0E010 + ((_n) * 0x40))) | 160#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 161 (0x0E000 + ((_n) * 0x40))) 162#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 163 (0x0E004 + ((_n) * 0x40))) 164#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 165 (0x0E008 + ((_n) * 0x40))) 166#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 167 (0x0E010 + ((_n) * 0x40))) |
| 168#define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \ 169 (0x0E014 + ((_n) * 0x40))) 170#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n) |
|
| 161#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 162 (0x0E018 + ((_n) * 0x40))) 163#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 164 (0x0E028 + ((_n) * 0x40))) | 171#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 172 (0x0E018 + ((_n) * 0x40))) 173#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 174 (0x0E028 + ((_n) * 0x40))) |
| 165#define E1000_TARC(_n) (0x03840 + (_n << 8)) 166#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) 167#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) | |
| 168#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ 169 (0x0E038 + ((_n) * 0x40))) 170#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ 171 (0x0E03C + ((_n) * 0x40))) | 175#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ 176 (0x0E038 + ((_n) * 0x40))) 177#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ 178 (0x0E03C + ((_n) * 0x40))) |
| 179#define E1000_TARC(_n) (0x03840 + ((_n) * 0x100)) |
|
| 172#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ 173#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 174#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ 175#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 176#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) 177#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 178 (0x054E0 + ((_i - 16) * 8))) 179#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 180 (0x054E4 + ((_i - 16) * 8))) 181#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) 182#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) 183#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) 184#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) 185#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) 186#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) 187#define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */ 188#define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Packet Buffer DWORD (_n) */ 189#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ | 180#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ 181#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 182#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ 183#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 184#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) 185#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 186 (0x054E0 + ((_i - 16) * 8))) 187#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 188 (0x054E4 + ((_i - 16) * 8))) 189#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) 190#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) 191#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) 192#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) 193#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) 194#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) 195#define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */ 196#define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Packet Buffer DWORD (_n) */ 197#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ |
| 198#define E1000_ITPBS 0x03404 /* Same as TXPBS, renamed for newer adpaters - RW */ |
|
| 190#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 191#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 192#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 193#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 194#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 195#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ 196#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ 197#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ --- 68 unchanged lines hidden (view full) --- 266#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 267#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 268#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 269#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 270#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 271#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 272#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 273#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ | 199#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 200#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 201#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 202#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 203#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 204#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ 205#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ 206#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ --- 68 unchanged lines hidden (view full) --- 275#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 276#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 277#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 278#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 279#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 280#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 281#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 282#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ |
| 283#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ |
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| 274 275#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */ 276#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */ 277#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */ 278#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */ 279#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */ 280#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */ 281#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */ --- 105 unchanged lines hidden (view full) --- 387#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 388#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 389#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 390#define E1000_SWSM 0x05B50 /* SW Semaphore */ 391#define E1000_FWSM 0x05B54 /* FW Semaphore */ 392#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ 393#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 394#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ | 284 285#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */ 286#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */ 287#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */ 288#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */ 289#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */ 290#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */ 291#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */ --- 105 unchanged lines hidden (view full) --- 397#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 398#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 399#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 400#define E1000_SWSM 0x05B50 /* SW Semaphore */ 401#define E1000_FWSM 0x05B54 /* FW Semaphore */ 402#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ 403#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 404#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ |
| 405#define E1000_UFUSE 0x05B78 /* UFUSE - RO */ |
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| 395#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 396#define E1000_HICR 0x08F00 /* Host Interface Control */ 397 398/* RSS registers */ 399#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 400#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 401#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ 402#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ --- 29 unchanged lines hidden (view full) --- 432/* These act per VF so an array friendly macro is used */ 433#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 434#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) 435#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 436#define E1000_VFVMBMEM(_n) (0x00800 + (_n)) 437#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) 438#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine 439 * Filter - RW */ | 406#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 407#define E1000_HICR 0x08F00 /* Host Interface Control */ 408 409/* RSS registers */ 410#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 411#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 412#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ 413#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ --- 29 unchanged lines hidden (view full) --- 443/* These act per VF so an array friendly macro is used */ 444#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 445#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) 446#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 447#define E1000_VFVMBMEM(_n) (0x00800 + (_n)) 448#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) 449#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine 450 * Filter - RW */ |
| 451#define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) |
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| 440/* Time Sync */ 441#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 442#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 443#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ 444#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 445#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 446#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ 447#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ 448#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 449#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 450#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 451#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 452#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ | 452/* Time Sync */ 453#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 454#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 455#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ 456#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 457#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 458#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ 459#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ 460#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 461#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 462#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 463#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 464#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ |
| 465#define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ 466#define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ |
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| 453#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 454#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 455 456/* Filtering Registers */ 457#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ 458#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ 459#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ 460#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ --- 27 unchanged lines hidden (view full) --- 488#define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ 489#define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */ 490#define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ 491#define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ 492#define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ 493#define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */ 494#define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ 495 | 467#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 468#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 469 470/* Filtering Registers */ 471#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ 472#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ 473#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ 474#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ --- 27 unchanged lines hidden (view full) --- 502#define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ 503#define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */ 504#define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ 505#define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ 506#define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ 507#define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */ 508#define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ 509 |
| 510/* DMA Coalescing registers */ 511#define E1000_DMACR 0x02508 /* Control Register */ 512#define E1000_DMCTXTH 0x03550 /* Transmit Threshold */ 513#define E1000_DMCTLX 0x02514 /* Time to Lx Request */ 514#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ 515#define E1000_DMCCNT 0x05DD4 /* Current RX Count */ 516#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ 517#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 518 519/* PCIe Parity Status Register */ 520#define E1000_PCIEERRSTS 0x05BA8 521#define E1000_ERFUSE 0x00000400 |
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| 496#endif | 522#endif |