Deleted Added
sdiff udiff text old ( 218530 ) new ( 228386 )
full compact
e1000_phy.h (218530) e1000_phy.h (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.h 218530 2011-02-11 01:00:26Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.h 228386 2011-12-10 06:55:02Z jfv $*/
34
35#ifndef _E1000_PHY_H_
36#define _E1000_PHY_H_
37
38void e1000_init_phy_ops_generic(struct e1000_hw *hw);
39s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
40void e1000_null_phy_generic(struct e1000_hw *hw);
41s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
42s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
34
35#ifndef _E1000_PHY_H_
36#define _E1000_PHY_H_
37
38void e1000_init_phy_ops_generic(struct e1000_hw *hw);
39s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
40void e1000_null_phy_generic(struct e1000_hw *hw);
41s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
42s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
43s32 e1000_null_set_page(struct e1000_hw *hw, u16 data);
43s32 e1000_check_downshift_generic(struct e1000_hw *hw);
44s32 e1000_check_polarity_m88(struct e1000_hw *hw);
45s32 e1000_check_polarity_igp(struct e1000_hw *hw);
46s32 e1000_check_polarity_ife(struct e1000_hw *hw);
47s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
48s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
49s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
50s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);

--- 11 unchanged lines hidden (view full) ---

62s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
63s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
64s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
65void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
66s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
67s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
68s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
69s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
44s32 e1000_check_downshift_generic(struct e1000_hw *hw);
45s32 e1000_check_polarity_m88(struct e1000_hw *hw);
46s32 e1000_check_polarity_igp(struct e1000_hw *hw);
47s32 e1000_check_polarity_ife(struct e1000_hw *hw);
48s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
49s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
50s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
51s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);

--- 11 unchanged lines hidden (view full) ---

63s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
64s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
65s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
66void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
67s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
68s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
69s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
70s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
71s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
70s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
71s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
72s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
73s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
74s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
75s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
76s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
77s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
78s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
79s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
80s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
81s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
82s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
72s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
73s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
74s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
75s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
76s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
77s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
78s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
79s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
80s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
81s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
82s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
83s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
84s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
83 u32 usec_interval, bool *success);
85 u32 usec_interval, bool *success);
84s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
85enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
86s32 e1000_determine_phy_address(struct e1000_hw *hw);
87s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
88s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
86s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
87enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
88s32 e1000_determine_phy_address(struct e1000_hw *hw);
89s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
90s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
91s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
92s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
89s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
90s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
91void e1000_power_up_phy_copper(struct e1000_hw *hw);
92void e1000_power_down_phy_copper(struct e1000_hw *hw);
93s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
94s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
95s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
96s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
93s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
94s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
95void e1000_power_up_phy_copper(struct e1000_hw *hw);
96void e1000_power_down_phy_copper(struct e1000_hw *hw);
97s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
98s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
99s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
100s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
101s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
102s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);
97s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
98s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
103s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
104s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
105s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
99s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
100s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
106s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
107s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
108s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
101s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
102s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
103s32 e1000_check_polarity_82577(struct e1000_hw *hw);
104s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
105s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
106s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
107
109s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
110s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
111s32 e1000_check_polarity_82577(struct e1000_hw *hw);
112s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
113s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
114s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
115
108#define E1000_MAX_PHY_ADDR 4
116#define E1000_MAX_PHY_ADDR 8
109
110/* IGP01E1000 Specific Registers */
117
118/* IGP01E1000 Specific Registers */
111#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
112#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
113#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
114#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
115#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
116#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
117#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
118#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
119#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
120#define IGP_PAGE_SHIFT 5
121#define PHY_REG_MASK 0x1F
119#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
120#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
121#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
122#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
123#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
124#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
125#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
126#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
127#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
128#define IGP_PAGE_SHIFT 5
129#define PHY_REG_MASK 0x1F
122
123/* BM/HV Specific Registers */
130
131/* BM/HV Specific Registers */
124#define BM_PORT_CTRL_PAGE 769
125#define BM_PORT_GEN_CFG_REG PHY_REG(BM_PORT_CTRL_PAGE, 17)
126#define BM_PCIE_PAGE 770
127#define BM_WUC_PAGE 800
128#define BM_WUC_ADDRESS_OPCODE 0x11
129#define BM_WUC_DATA_OPCODE 0x12
130#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
131#define BM_WUC_ENABLE_REG 17
132#define BM_WUC_ENABLE_BIT (1 << 2)
133#define BM_WUC_HOST_WU_BIT (1 << 4)
132#define BM_PORT_CTRL_PAGE 769
133#define BM_PCIE_PAGE 770
134#define BM_WUC_PAGE 800
135#define BM_WUC_ADDRESS_OPCODE 0x11
136#define BM_WUC_DATA_OPCODE 0x12
137#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
138#define BM_WUC_ENABLE_REG 17
139#define BM_WUC_ENABLE_BIT (1 << 2)
140#define BM_WUC_HOST_WU_BIT (1 << 4)
141#define BM_WUC_ME_WU_BIT (1 << 5)
134
142
135#define PHY_UPPER_SHIFT 21
143#define PHY_UPPER_SHIFT 21
136#define BM_PHY_REG(page, reg) \
137 (((reg) & MAX_PHY_REG_ADDRESS) |\
138 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
139 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
140#define BM_PHY_REG_PAGE(offset) \
141 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
142#define BM_PHY_REG_NUM(offset) \
143 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
144 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
145 ~MAX_PHY_REG_ADDRESS)))
146
144#define BM_PHY_REG(page, reg) \
145 (((reg) & MAX_PHY_REG_ADDRESS) |\
146 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
147 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
148#define BM_PHY_REG_PAGE(offset) \
149 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
150#define BM_PHY_REG_NUM(offset) \
151 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
152 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
153 ~MAX_PHY_REG_ADDRESS)))
154
147#define HV_INTC_FC_PAGE_START 768
148#define I82578_ADDR_REG 29
149#define I82577_ADDR_REG 16
150#define I82577_CFG_REG 22
151#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
152#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
153#define I82577_CTRL_REG 23
155#define HV_INTC_FC_PAGE_START 768
156#define I82578_ADDR_REG 29
157#define I82577_ADDR_REG 16
158#define I82577_CFG_REG 22
159#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
160#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
161#define I82577_CTRL_REG 23
154
155/* 82577 specific PHY registers */
162
163/* 82577 specific PHY registers */
156#define I82577_PHY_CTRL_2 18
157#define I82577_PHY_LBK_CTRL 19
158#define I82577_PHY_STATUS_2 26
159#define I82577_PHY_DIAG_STATUS 31
164#define I82577_PHY_CTRL_2 18
165#define I82577_PHY_LBK_CTRL 19
166#define I82577_PHY_STATUS_2 26
167#define I82577_PHY_DIAG_STATUS 31
160
161/* I82577 PHY Status 2 */
168
169/* I82577 PHY Status 2 */
162#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
163#define I82577_PHY_STATUS2_MDIX 0x0800
164#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
165#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
166#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100
170#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
171#define I82577_PHY_STATUS2_MDIX 0x0800
172#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
173#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
174#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100
167
168/* I82577 PHY Control 2 */
175
176/* I82577 PHY Control 2 */
169#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
170#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
177#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
178#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
171
172/* I82577 PHY Diagnostics Status */
179
180/* I82577 PHY Diagnostics Status */
173#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
174#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
181#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
182#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
175
176/* 82580 PHY Power Management */
183
184/* 82580 PHY Power Management */
177#define E1000_82580_PHY_POWER_MGMT 0xE14
178#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
179#define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
180#define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
185#define E1000_82580_PHY_POWER_MGMT 0xE14
186#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
187#define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
188#define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
181
182/* BM PHY Copper Specific Control 1 */
189
190/* BM PHY Copper Specific Control 1 */
183#define BM_CS_CTRL1 16
184#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */
191#define BM_CS_CTRL1 16
192#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */
185
186/* BM PHY Copper Specific Status */
193
194/* BM PHY Copper Specific Status */
187#define BM_CS_STATUS 17
188#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */
189#define BM_CS_STATUS_LINK_UP 0x0400
190#define BM_CS_STATUS_RESOLVED 0x0800
191#define BM_CS_STATUS_SPEED_MASK 0xC000
192#define BM_CS_STATUS_SPEED_1000 0x8000
195#define BM_CS_STATUS 17
196#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */
197#define BM_CS_STATUS_LINK_UP 0x0400
198#define BM_CS_STATUS_RESOLVED 0x0800
199#define BM_CS_STATUS_SPEED_MASK 0xC000
200#define BM_CS_STATUS_SPEED_1000 0x8000
193
194/* 82577 Mobile Phy Status Register */
201
202/* 82577 Mobile Phy Status Register */
195#define HV_M_STATUS 26
196#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
197#define HV_M_STATUS_SPEED_MASK 0x0300
198#define HV_M_STATUS_SPEED_1000 0x0200
199#define HV_M_STATUS_LINK_UP 0x0040
203#define HV_M_STATUS 26
204#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
205#define HV_M_STATUS_SPEED_MASK 0x0300
206#define HV_M_STATUS_SPEED_1000 0x0200
207#define HV_M_STATUS_LINK_UP 0x0040
200
208
201#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
202#define IGP01E1000_PHY_POLARITY_MASK 0x0078
209#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
210#define IGP01E1000_PHY_POLARITY_MASK 0x0078
203
211
204#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
205#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
212#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
213#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
206
214
207#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
215#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
208
209/* Enable flexible speed on link-up */
216
217/* Enable flexible speed on link-up */
210#define IGP01E1000_GMII_FLEX_SPD 0x0010
211#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
218#define IGP01E1000_GMII_FLEX_SPD 0x0010
219#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
212
220
213#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
214#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
215#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
221#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
222#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
223#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
216
224
217#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
225#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
218
226
219#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
220#define IGP01E1000_PSSR_MDIX 0x0800
221#define IGP01E1000_PSSR_SPEED_MASK 0xC000
222#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
227#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
228#define IGP01E1000_PSSR_MDIX 0x0800
229#define IGP01E1000_PSSR_SPEED_MASK 0xC000
230#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
223
231
224#define IGP02E1000_PHY_CHANNEL_NUM 4
225#define IGP02E1000_PHY_AGC_A 0x11B1
226#define IGP02E1000_PHY_AGC_B 0x12B1
227#define IGP02E1000_PHY_AGC_C 0x14B1
228#define IGP02E1000_PHY_AGC_D 0x18B1
232#define IGP02E1000_PHY_CHANNEL_NUM 4
233#define IGP02E1000_PHY_AGC_A 0x11B1
234#define IGP02E1000_PHY_AGC_B 0x12B1
235#define IGP02E1000_PHY_AGC_C 0x14B1
236#define IGP02E1000_PHY_AGC_D 0x18B1
229
237
230#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
231#define IGP02E1000_AGC_LENGTH_MASK 0x7F
232#define IGP02E1000_AGC_RANGE 15
238#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
239#define IGP02E1000_AGC_LENGTH_MASK 0x7F
240#define IGP02E1000_AGC_RANGE 15
233
241
234#define IGP03E1000_PHY_MISC_CTRL 0x1B
235#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
242#define IGP03E1000_PHY_MISC_CTRL 0x1B
243#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
236
244
237#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
245#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
238
246
239#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
240#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
241#define E1000_KMRNCTRLSTA_REN 0x00200000
242#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
243#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
244#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
245#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
246#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
247#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
248#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
249#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
250#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
247#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
248#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
249#define E1000_KMRNCTRLSTA_REN 0x00200000
250#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
251#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
252#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
253#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
254#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
255#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
256#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
257#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
258#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
251
259
252#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
253#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
254#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
255#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
260#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
261#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
262#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
263#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
256
257/* IFE PHY Extended Status Control */
264
265/* IFE PHY Extended Status Control */
258#define IFE_PESC_POLARITY_REVERSED 0x0100
266#define IFE_PESC_POLARITY_REVERSED 0x0100
259
260/* IFE PHY Special Control */
267
268/* IFE PHY Special Control */
261#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
262#define IFE_PSC_FORCE_POLARITY 0x0020
263#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
269#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
270#define IFE_PSC_FORCE_POLARITY 0x0020
271#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
264
265/* IFE PHY Special Control and LED Control */
272
273/* IFE PHY Special Control and LED Control */
266#define IFE_PSCL_PROBE_MODE 0x0020
267#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
268#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
274#define IFE_PSCL_PROBE_MODE 0x0020
275#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
276#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
269
270/* IFE PHY MDIX Control */
277
278/* IFE PHY MDIX Control */
271#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
272#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
273#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
279#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
280#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
281#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
274
282
283/* SFP modules ID memory locations */
284#define E1000_SFF_IDENTIFIER_OFFSET 0x00
285#define E1000_SFF_IDENTIFIER_SFF 0x02
286#define E1000_SFF_IDENTIFIER_SFP 0x03
287
288#define E1000_SFF_ETH_FLAGS_OFFSET 0x06
289/* Flags for SFP modules compatible with ETH up to 1Gb */
290struct sfp_e1000_flags {
291 u8 e1000_base_sx:1;
292 u8 e1000_base_lx:1;
293 u8 e1000_base_cx:1;
294 u8 e1000_base_t:1;
295 u8 e100_base_lx:1;
296 u8 e100_base_fx:1;
297 u8 e10_base_bx10:1;
298 u8 e10_base_px:1;
299};
300
301/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
302#define E1000_SFF_VENDOR_OUI_TYCO 0x00407600
303#define E1000_SFF_VENDOR_OUI_FTL 0x00906500
304#define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00
305#define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100
306
275#endif
307#endif