| e1000_phy.h (169589) | e1000_phy.h (173788) |
|---|---|
| 1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ | 1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/em/e1000_phy.h 169589 2007-05-16 00:14:23Z jfv $*/ | 33/* $FreeBSD: head/sys/dev/em/e1000_phy.h 173788 2007-11-20 21:41:22Z jfv $ */ |
| 34 35 36#ifndef _E1000_PHY_H_ 37#define _E1000_PHY_H_ 38 39typedef enum { 40 e1000_ms_hw_default = 0, 41 e1000_ms_force_master, --- 26 unchanged lines hidden (view full) --- 68s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 69void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 70s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 71s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 72s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 73s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 74s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 75s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); | 34 35 36#ifndef _E1000_PHY_H_ 37#define _E1000_PHY_H_ 38 39typedef enum { 40 e1000_ms_hw_default = 0, 41 e1000_ms_force_master, --- 26 unchanged lines hidden (view full) --- 68s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 69void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 70s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 71s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 72s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 73s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 74s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 75s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); |
| 76s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active); | 76s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); |
| 77s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 78s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); 79s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 80s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 81s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 82s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 83s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | 77s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 78s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); 79s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 80s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 81s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 82s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 83s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
| 84 u32 usec_interval, boolean_t *success); | 84 u32 usec_interval, bool *success); |
| 85s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 86e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); | 85s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 86e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); |
| 87void e1000_power_up_phy_copper(struct e1000_hw *hw); 88void e1000_power_down_phy_copper(struct e1000_hw *hw); 89 |
|
| 87#define E1000_MAX_PHY_ADDR 4 88 89/* IGP01E1000 Specific Registers */ 90#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 91#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 92#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 93#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 94#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 95#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 96#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 97#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ | 90#define E1000_MAX_PHY_ADDR 4 91 92/* IGP01E1000 Specific Registers */ 93#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 94#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 95#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 96#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 97#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 98#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 99#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 100#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
| 98#define IGP4_PHY_PAGE_SELECT 22 /* Page Select for IGP 4 */ | 101#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ |
| 99#define IGP_PAGE_SHIFT 5 100#define PHY_REG_MASK 0x1F 101 | 102#define IGP_PAGE_SHIFT 5 103#define PHY_REG_MASK 0x1F 104 |
| 102#define IGP4_WUC_PAGE 800 103#define IGP4_WUC_ADDRESS_OPCODE 0x11 104#define IGP4_WUC_DATA_OPCODE 0x12 105#define IGP4_WUC_ENABLE_PAGE 769 106#define IGP4_WUC_ENABLE_REG 17 107#define IGP4_WUC_ENABLE_BIT (1 << 2) 108#define IGP4_WUC_HOST_WU_BIT (1 << 4) | |
| 109 110#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 111#define IGP01E1000_PHY_POLARITY_MASK 0x0078 112 113#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 114#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 115 116#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 117 | 105 106#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 107#define IGP01E1000_PHY_POLARITY_MASK 0x0078 108 109#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 110#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 111 112#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 113 |
| 118#define IGP01E1000_GMII_FLEX_SPD 0x0010 /* Enable flexible speed 119 * on link-up */ | 114/* Enable flexible speed on link-up */ 115#define IGP01E1000_GMII_FLEX_SPD 0x0010 |
| 120#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 121 122#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 123#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 124#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 125 126#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 127 --- 50 unchanged lines hidden --- | 116#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 117 118#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 119#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 120#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 121 122#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 123 --- 50 unchanged lines hidden --- |