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e1000_phy.h (169248) e1000_phy.h (169589)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_phy.h 169589 2007-05-16 00:14:23Z jfv $*/
33
34
34/*
35 * $FreeBSD: head/sys/dev/em/e1000_phy.h 169248 2007-05-04 13:30:44Z rwatson $
36 */
37
35
38
39#ifndef _E1000_PHY_H_
40#define _E1000_PHY_H_
41
42typedef enum {
43 e1000_ms_hw_default = 0,
44 e1000_ms_force_master,
45 e1000_ms_force_slave,
46 e1000_ms_auto
47} e1000_ms_type;
48
49typedef enum {
50 e1000_smart_speed_default = 0,
51 e1000_smart_speed_on,
52 e1000_smart_speed_off
53} e1000_smart_speed;
54
36#ifndef _E1000_PHY_H_
37#define _E1000_PHY_H_
38
39typedef enum {
40 e1000_ms_hw_default = 0,
41 e1000_ms_force_master,
42 e1000_ms_force_slave,
43 e1000_ms_auto
44} e1000_ms_type;
45
46typedef enum {
47 e1000_smart_speed_default = 0,
48 e1000_smart_speed_on,
49 e1000_smart_speed_off
50} e1000_smart_speed;
51
55#include "e1000_api.h"
56
57s32 e1000_check_downshift_generic(struct e1000_hw *hw);
58s32 e1000_check_polarity_m88(struct e1000_hw *hw);
59s32 e1000_check_polarity_igp(struct e1000_hw *hw);
60s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
61s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
62s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
64s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);

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83s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
84s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
85s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
86s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
87s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
88s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
89 u32 usec_interval, boolean_t *success);
90s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
52s32 e1000_check_downshift_generic(struct e1000_hw *hw);
53s32 e1000_check_polarity_m88(struct e1000_hw *hw);
54s32 e1000_check_polarity_igp(struct e1000_hw *hw);
55s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
56s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
57s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
58s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
59s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);

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78s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
79s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
80s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
81s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
82s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
83s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
84 u32 usec_interval, boolean_t *success);
85s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
86e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
87#define E1000_MAX_PHY_ADDR 4
91
88
92
93
94/* IGP01E1000 Specific Registers */
95#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
96#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
97#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
98#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
99#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
100#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
101#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
102#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
89/* IGP01E1000 Specific Registers */
90#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
91#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
92#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
93#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
94#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
95#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
96#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
97#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
98#define IGP4_PHY_PAGE_SELECT 22 /* Page Select for IGP 4 */
99#define IGP_PAGE_SHIFT 5
100#define PHY_REG_MASK 0x1F
103
101
102#define IGP4_WUC_PAGE 800
103#define IGP4_WUC_ADDRESS_OPCODE 0x11
104#define IGP4_WUC_DATA_OPCODE 0x12
105#define IGP4_WUC_ENABLE_PAGE 769
106#define IGP4_WUC_ENABLE_REG 17
107#define IGP4_WUC_ENABLE_BIT (1 << 2)
108#define IGP4_WUC_HOST_WU_BIT (1 << 4)
109
104#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
105#define IGP01E1000_PHY_POLARITY_MASK 0x0078
106
107#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
108#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
109
110#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
111

--- 60 unchanged lines hidden --- 		110#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
111#define IGP01E1000_PHY_POLARITY_MASK 0x0078
112
113#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
114#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
115
116#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
117

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