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e1000_nvm.c (218530) e1000_nvm.c (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_nvm.c 218530 2011-02-11 01:00:26Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_nvm.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35#include "e1000_api.h"
36
37static void e1000_reload_nvm_generic(struct e1000_hw *hw);
38
39/**
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure

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308
309 /* Select EEPROM */
310 eecd |= E1000_EECD_CS;
311 E1000_WRITE_REG(hw, E1000_EECD, eecd);
312 E1000_WRITE_FLUSH(hw);
313 usec_delay(nvm->delay_usec);
314
315 e1000_lower_eec_clk(hw, &eecd);
34
35#include "e1000_api.h"
36
37static void e1000_reload_nvm_generic(struct e1000_hw *hw);
38
39/**
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure

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308
309 /* Select EEPROM */
310 eecd |= E1000_EECD_CS;
311 E1000_WRITE_REG(hw, E1000_EECD, eecd);
312 E1000_WRITE_FLUSH(hw);
313 usec_delay(nvm->delay_usec);
314
315 e1000_lower_eec_clk(hw, &eecd);
316 } else
317 if (nvm->type == e1000_nvm_eeprom_spi) {
316 } else if (nvm->type == e1000_nvm_eeprom_spi) {
318 /* Toggle CS to flush commands */
319 eecd |= E1000_EECD_CS;
320 E1000_WRITE_REG(hw, E1000_EECD, eecd);
321 E1000_WRITE_FLUSH(hw);
322 usec_delay(nvm->delay_usec);
323 eecd &= ~E1000_EECD_CS;
324 E1000_WRITE_REG(hw, E1000_EECD, eecd);
325 E1000_WRITE_FLUSH(hw);

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389
390 if (nvm->type == e1000_nvm_eeprom_microwire) {
391 /* Clear SK and DI */
392 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
393 E1000_WRITE_REG(hw, E1000_EECD, eecd);
394 /* Set CS */
395 eecd |= E1000_EECD_CS;
396 E1000_WRITE_REG(hw, E1000_EECD, eecd);
317 /* Toggle CS to flush commands */
318 eecd |= E1000_EECD_CS;
319 E1000_WRITE_REG(hw, E1000_EECD, eecd);
320 E1000_WRITE_FLUSH(hw);
321 usec_delay(nvm->delay_usec);
322 eecd &= ~E1000_EECD_CS;
323 E1000_WRITE_REG(hw, E1000_EECD, eecd);
324 E1000_WRITE_FLUSH(hw);

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388
389 if (nvm->type == e1000_nvm_eeprom_microwire) {
390 /* Clear SK and DI */
391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
392 E1000_WRITE_REG(hw, E1000_EECD, eecd);
393 /* Set CS */
394 eecd |= E1000_EECD_CS;
395 E1000_WRITE_REG(hw, E1000_EECD, eecd);
397 } else
398 if (nvm->type == e1000_nvm_eeprom_spi) {
396 } else if (nvm->type == e1000_nvm_eeprom_spi) {
399 u16 timeout = NVM_MAX_RETRY_SPI;
400
401 /* Clear SK and CS */
402 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
403 E1000_WRITE_REG(hw, E1000_EECD, eecd);
397 u16 timeout = NVM_MAX_RETRY_SPI;
398
399 /* Clear SK and CS */
400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
401 E1000_WRITE_REG(hw, E1000_EECD, eecd);
402 E1000_WRITE_FLUSH(hw);
404 usec_delay(1);
405
406 /*
407 * Read "Status Register" repeatedly until the LSB is cleared.
408 * The EEPROM will signal that the command has been completed
409 * by clearing bit 0 of the internal status register. If it's
410 * not cleared within 'timeout', then error out.
411 */
412 while (timeout) {
413 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
403 usec_delay(1);
404
405 /*
406 * Read "Status Register" repeatedly until the LSB is cleared.
407 * The EEPROM will signal that the command has been completed
408 * by clearing bit 0 of the internal status register. If it's
409 * not cleared within 'timeout', then error out.
410 */
411 while (timeout) {
412 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
414 hw->nvm.opcode_bits);
413 hw->nvm.opcode_bits);
415 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
416 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
417 break;
418
419 usec_delay(5);
420 e1000_standby_nvm(hw);
421 timeout--;
422 }

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501 * @hw: pointer to the HW structure
502 * @offset: offset of word in the EEPROM to read
503 * @words: number of words to read
504 * @data: word read from the EEPROM
505 *
506 * Reads a 16 bit word from the EEPROM.
507 **/
508s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
414 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
415 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
416 break;
417
418 usec_delay(5);
419 e1000_standby_nvm(hw);
420 timeout--;
421 }

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500 * @hw: pointer to the HW structure
501 * @offset: offset of word in the EEPROM to read
502 * @words: number of words to read
503 * @data: word read from the EEPROM
504 *
505 * Reads a 16 bit word from the EEPROM.
506 **/
507s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
509 u16 *data)
508 u16 *data)
510{
511 struct e1000_nvm_info *nvm = &hw->nvm;
512 u32 i = 0;
513 s32 ret_val;
514 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
515
516 DEBUGFUNC("e1000_read_nvm_microwire");
517

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588 E1000_NVM_RW_REG_START;
589
590 E1000_WRITE_REG(hw, E1000_EERD, eerd);
591 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
592 if (ret_val)
593 break;
594
595 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
509{
510 struct e1000_nvm_info *nvm = &hw->nvm;
511 u32 i = 0;
512 s32 ret_val;
513 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
514
515 DEBUGFUNC("e1000_read_nvm_microwire");
516

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587 E1000_NVM_RW_REG_START;
588
589 E1000_WRITE_REG(hw, E1000_EERD, eerd);
590 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
591 if (ret_val)
592 break;
593
594 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
596 E1000_NVM_RW_REG_DATA);
595 E1000_NVM_RW_REG_DATA);
597 }
598
599out:
600 return ret_val;
601}
602
603/**
604 * e1000_write_nvm_spi - Write to EEPROM using SPI

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641 ret_val = e1000_ready_nvm_eeprom(hw);
642 if (ret_val)
643 goto release;
644
645 e1000_standby_nvm(hw);
646
647 /* Send the WRITE ENABLE command (8 bit opcode) */
648 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
596 }
597
598out:
599 return ret_val;
600}
601
602/**
603 * e1000_write_nvm_spi - Write to EEPROM using SPI

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640 ret_val = e1000_ready_nvm_eeprom(hw);
641 if (ret_val)
642 goto release;
643
644 e1000_standby_nvm(hw);
645
646 /* Send the WRITE ENABLE command (8 bit opcode) */
647 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
649 nvm->opcode_bits);
648 nvm->opcode_bits);
650
651 e1000_standby_nvm(hw);
652
653 /*
654 * Some SPI eeproms use the 8th address bit embedded in the
655 * opcode
656 */
657 if ((nvm->address_bits == 8) && (offset >= 128))
658 write_opcode |= NVM_A8_OPCODE_SPI;
659
660 /* Send the Write command (8-bit opcode + addr) */
661 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
662 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
649
650 e1000_standby_nvm(hw);
651
652 /*
653 * Some SPI eeproms use the 8th address bit embedded in the
654 * opcode
655 */
656 if ((nvm->address_bits == 8) && (offset >= 128))
657 write_opcode |= NVM_A8_OPCODE_SPI;
658
659 /* Send the Write command (8-bit opcode + addr) */
660 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
661 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
663 nvm->address_bits);
662 nvm->address_bits);
664
665 /* Loop to allow for up to whole page write of eeprom */
666 while (widx < words) {
667 u16 word_out = data[widx];
668 word_out = (word_out >> 8) | (word_out << 8);
669 e1000_shift_out_eec_bits(hw, word_out, 16);
670 widx++;
671

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692 * @data: 16 bit word(s) to be written to the EEPROM
693 *
694 * Writes data to EEPROM at offset using microwire interface.
695 *
696 * If e1000_update_nvm_checksum is not called after this function , the
697 * EEPROM will most likely contain an invalid checksum.
698 **/
699s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
663
664 /* Loop to allow for up to whole page write of eeprom */
665 while (widx < words) {
666 u16 word_out = data[widx];
667 word_out = (word_out >> 8) | (word_out << 8);
668 e1000_shift_out_eec_bits(hw, word_out, 16);
669 widx++;
670

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691 * @data: 16 bit word(s) to be written to the EEPROM
692 *
693 * Writes data to EEPROM at offset using microwire interface.
694 *
695 * If e1000_update_nvm_checksum is not called after this function , the
696 * EEPROM will most likely contain an invalid checksum.
697 **/
698s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
700 u16 *data)
699 u16 *data)
701{
702 struct e1000_nvm_info *nvm = &hw->nvm;
703 s32 ret_val;
704 u32 eecd;
705 u16 words_written = 0;
706 u16 widx = 0;
707
708 DEBUGFUNC("e1000_write_nvm_microwire");

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722 if (ret_val)
723 goto out;
724
725 ret_val = e1000_ready_nvm_eeprom(hw);
726 if (ret_val)
727 goto release;
728
729 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
700{
701 struct e1000_nvm_info *nvm = &hw->nvm;
702 s32 ret_val;
703 u32 eecd;
704 u16 words_written = 0;
705 u16 widx = 0;
706
707 DEBUGFUNC("e1000_write_nvm_microwire");

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721 if (ret_val)
722 goto out;
723
724 ret_val = e1000_ready_nvm_eeprom(hw);
725 if (ret_val)
726 goto release;
727
728 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
730 (u16)(nvm->opcode_bits + 2));
729 (u16)(nvm->opcode_bits + 2));
731
732 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
733
734 e1000_standby_nvm(hw);
735
736 while (words_written < words) {
737 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
730
731 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
732
733 e1000_standby_nvm(hw);
734
735 while (words_written < words) {
736 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
738 nvm->opcode_bits);
737 nvm->opcode_bits);
739
740 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
738
739 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
741 nvm->address_bits);
740 nvm->address_bits);
742
743 e1000_shift_out_eec_bits(hw, data[words_written], 16);
744
745 e1000_standby_nvm(hw);
746
747 for (widx = 0; widx < 200; widx++) {
748 eecd = E1000_READ_REG(hw, E1000_EECD);
749 if (eecd & E1000_EECD_DO)

--- 8 unchanged lines hidden (view full) ---

758 }
759
760 e1000_standby_nvm(hw);
761
762 words_written++;
763 }
764
765 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
741
742 e1000_shift_out_eec_bits(hw, data[words_written], 16);
743
744 e1000_standby_nvm(hw);
745
746 for (widx = 0; widx < 200; widx++) {
747 eecd = E1000_READ_REG(hw, E1000_EECD);
748 if (eecd & E1000_EECD_DO)

--- 8 unchanged lines hidden (view full) ---

757 }
758
759 e1000_standby_nvm(hw);
760
761 words_written++;
762 }
763
764 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
766 (u16)(nvm->opcode_bits + 2));
765 (u16)(nvm->opcode_bits + 2));
767
768 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
769
770release:
771 nvm->ops.release(hw);
772
773out:
774 return ret_val;

--- 4 unchanged lines hidden (view full) ---

779 * @hw: pointer to the HW structure
780 * @pba_num: pointer to device part number
781 * @pba_num_size: size of part number buffer
782 *
783 * Reads the product board assembly (PBA) number from the EEPROM and stores
784 * the value in pba_num.
785 **/
786s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
766
767 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
768
769release:
770 nvm->ops.release(hw);
771
772out:
773 return ret_val;

--- 4 unchanged lines hidden (view full) ---

778 * @hw: pointer to the HW structure
779 * @pba_num: pointer to device part number
780 * @pba_num_size: size of part number buffer
781 *
782 * Reads the product board assembly (PBA) number from the EEPROM and stores
783 * the value in pba_num.
784 **/
785s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
787 u32 pba_num_size)
786 u32 pba_num_size)
788{
789 s32 ret_val;
790 u16 nvm_data;
791 u16 pba_ptr;
792 u16 offset;
793 u16 length;
794
795 DEBUGFUNC("e1000_read_pba_string_generic");

--- 275 unchanged lines hidden --- 		787{
788 s32 ret_val;
789 u16 nvm_data;
790 u16 pba_ptr;
791 u16 offset;
792 u16 length;
793
794 DEBUGFUNC("e1000_read_pba_string_generic");

--- 275 unchanged lines hidden ---