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e1000_mac.c (218581) e1000_mac.c (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 218581 2011-02-11 17:18:42Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35#include "e1000_api.h"
36
37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39
40/**
41 * e1000_init_mac_ops_generic - Initialize MAC function pointers

--- 130 unchanged lines hidden (view full) ---

172 /* PCI or PCI-X? */
173 bus->type = (status & E1000_STATUS_PCIX_MODE)
174 ? e1000_bus_type_pcix
175 : e1000_bus_type_pci;
176
177 /* Bus speed */
178 if (bus->type == e1000_bus_type_pci) {
179 bus->speed = (status & E1000_STATUS_PCI66)
34
35#include "e1000_api.h"
36
37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39
40/**
41 * e1000_init_mac_ops_generic - Initialize MAC function pointers

--- 130 unchanged lines hidden (view full) ---

172 /* PCI or PCI-X? */
173 bus->type = (status & E1000_STATUS_PCIX_MODE)
174 ? e1000_bus_type_pcix
175 : e1000_bus_type_pci;
176
177 /* Bus speed */
178 if (bus->type == e1000_bus_type_pci) {
179 bus->speed = (status & E1000_STATUS_PCI66)
180 ? e1000_bus_speed_66
181 : e1000_bus_speed_33;
180 ? e1000_bus_speed_66
181 : e1000_bus_speed_33;
182 } else {
183 switch (status & E1000_STATUS_PCIX_SPEED) {
184 case E1000_STATUS_PCIX_SPEED_66:
185 bus->speed = e1000_bus_speed_66;
186 break;
187 case E1000_STATUS_PCIX_SPEED_100:
188 bus->speed = e1000_bus_speed_100;
189 break;
190 case E1000_STATUS_PCIX_SPEED_133:
191 bus->speed = e1000_bus_speed_133;
192 break;
193 default:
194 bus->speed = e1000_bus_speed_reserved;
195 break;
196 }
197 }
198
199 /* Bus width */
200 bus->width = (status & E1000_STATUS_BUS64)
182 } else {
183 switch (status & E1000_STATUS_PCIX_SPEED) {
184 case E1000_STATUS_PCIX_SPEED_66:
185 bus->speed = e1000_bus_speed_66;
186 break;
187 case E1000_STATUS_PCIX_SPEED_100:
188 bus->speed = e1000_bus_speed_100;
189 break;
190 case E1000_STATUS_PCIX_SPEED_133:
191 bus->speed = e1000_bus_speed_133;
192 break;
193 default:
194 bus->speed = e1000_bus_speed_reserved;
195 break;
196 }
197 }
198
199 /* Bus width */
200 bus->width = (status & E1000_STATUS_BUS64)
201 ? e1000_bus_width_64
202 : e1000_bus_width_32;
201 ? e1000_bus_width_64
202 : e1000_bus_width_32;
203
204 /* Which PCI(-X) function? */
205 mac->ops.set_lan_id(hw);
206
207 return ret_val;
208}
209
210/**

--- 10 unchanged lines hidden (view full) ---

221 struct e1000_bus_info *bus = &hw->bus;
222 s32 ret_val;
223 u16 pcie_link_status;
224
225 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
226
227 bus->type = e1000_bus_type_pci_express;
228
203
204 /* Which PCI(-X) function? */
205 mac->ops.set_lan_id(hw);
206
207 return ret_val;
208}
209
210/**

--- 10 unchanged lines hidden (view full) ---

221 struct e1000_bus_info *bus = &hw->bus;
222 s32 ret_val;
223 u16 pcie_link_status;
224
225 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
226
227 bus->type = e1000_bus_type_pci_express;
228
229 ret_val = e1000_read_pcie_cap_reg(hw,
230 PCIE_LINK_STATUS,
231 &pcie_link_status);
229 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
230 &pcie_link_status);
232 if (ret_val) {
233 bus->width = e1000_bus_width_unknown;
234 bus->speed = e1000_bus_speed_unknown;
235 } else {
236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
237 case PCIE_LINK_SPEED_2500:
238 bus->speed = e1000_bus_speed_2500;
239 break;
240 case PCIE_LINK_SPEED_5000:
241 bus->speed = e1000_bus_speed_5000;
242 break;
243 default:
244 bus->speed = e1000_bus_speed_unknown;
245 break;
246 }
247
248 bus->width = (enum e1000_bus_width)((pcie_link_status &
231 if (ret_val) {
232 bus->width = e1000_bus_width_unknown;
233 bus->speed = e1000_bus_speed_unknown;
234 } else {
235 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
236 case PCIE_LINK_SPEED_2500:
237 bus->speed = e1000_bus_speed_2500;
238 break;
239 case PCIE_LINK_SPEED_5000:
240 bus->speed = e1000_bus_speed_5000;
241 break;
242 default:
243 bus->speed = e1000_bus_speed_unknown;
244 break;
245 }
246
247 bus->width = (enum e1000_bus_width)((pcie_link_status &
249 PCIE_LINK_WIDTH_MASK) >>
250 PCIE_LINK_WIDTH_SHIFT);
248 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
251 }
252
253 mac->ops.set_lan_id(hw);
254
255 return E1000_SUCCESS;
256}
257
258/**

--- 28 unchanged lines hidden (view full) ---

287 struct e1000_bus_info *bus = &hw->bus;
288 u16 pci_header_type;
289 u32 status;
290
291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
293 status = E1000_READ_REG(hw, E1000_STATUS);
294 bus->func = (status & E1000_STATUS_FUNC_MASK)
249 }
250
251 mac->ops.set_lan_id(hw);
252
253 return E1000_SUCCESS;
254}
255
256/**

--- 28 unchanged lines hidden (view full) ---

285 struct e1000_bus_info *bus = &hw->bus;
286 u16 pci_header_type;
287 u32 status;
288
289 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
290 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
291 status = E1000_READ_REG(hw, E1000_STATUS);
292 bus->func = (status & E1000_STATUS_FUNC_MASK)
295 >> E1000_STATUS_FUNC_SHIFT;
293 >> E1000_STATUS_FUNC_SHIFT;
296 } else {
297 bus->func = 0;
298 }
299}
300
301/**
302 * e1000_set_lan_id_single_port - Set LAN id for a single port device
303 * @hw: pointer to the HW structure

--- 43 unchanged lines hidden (view full) ---

347 E1000_WRITE_FLUSH(hw);
348}
349
350/**
351 * e1000_init_rx_addrs_generic - Initialize receive address's
352 * @hw: pointer to the HW structure
353 * @rar_count: receive address registers
354 *
294 } else {
295 bus->func = 0;
296 }
297}
298
299/**
300 * e1000_set_lan_id_single_port - Set LAN id for a single port device
301 * @hw: pointer to the HW structure

--- 43 unchanged lines hidden (view full) ---

345 E1000_WRITE_FLUSH(hw);
346}
347
348/**
349 * e1000_init_rx_addrs_generic - Initialize receive address's
350 * @hw: pointer to the HW structure
351 * @rar_count: receive address registers
352 *
355 * Setups the receive address registers by setting the base receive address
353 * Setup the receive address registers by setting the base receive address
356 * register to the devices MAC address and clearing all the other receive
357 * address registers to 0.
358 **/
359void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
360{
361 u32 i;
362 u8 mac_addr[ETH_ADDR_LEN] = {0};
363

--- 30 unchanged lines hidden (view full) ---

394 u8 alt_mac_addr[ETH_ADDR_LEN];
395
396 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
397
398 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
399 if (ret_val)
400 goto out;
401
354 * register to the devices MAC address and clearing all the other receive
355 * address registers to 0.
356 **/
357void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
358{
359 u32 i;
360 u8 mac_addr[ETH_ADDR_LEN] = {0};
361

--- 30 unchanged lines hidden (view full) ---

392 u8 alt_mac_addr[ETH_ADDR_LEN];
393
394 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
395
396 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
397 if (ret_val)
398 goto out;
399
402 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
403 if (!((nvm_data & NVM_COMPAT_LOM) ||
404 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
405 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_QUAD)))
400 /* not supported on older hardware or 82573 */
401 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
406 goto out;
407
402 goto out;
403
404 /*
405 * Alternate MAC address is handled by the option ROM for 82580
406 * and newer. SW support not required.
407 */
408 if (hw->mac.type >= e1000_82580)
409 goto out;
410
408 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
409 &nvm_alt_mac_addr_offset);
412 &nvm_alt_mac_addr_offset);
410 if (ret_val) {
411 DEBUGOUT("NVM Read Error\n");
412 goto out;
413 }
414
413 if (ret_val) {
414 DEBUGOUT("NVM Read Error\n");
415 goto out;
416 }
417
415 if (nvm_alt_mac_addr_offset == 0xFFFF) {
418 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
419 (nvm_alt_mac_addr_offset == 0x0000))
416 /* There is no Alternate MAC Address */
417 goto out;
420 /* There is no Alternate MAC Address */
421 goto out;
418 }
419
420 if (hw->bus.func == E1000_FUNC_1)
421 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
422 if (hw->bus.func == E1000_FUNC_2)
423 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
424
425 if (hw->bus.func == E1000_FUNC_3)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;

--- 40 unchanged lines hidden (view full) ---

467 u32 rar_low, rar_high;
468
469 DEBUGFUNC("e1000_rar_set_generic");
470
471 /*
472 * HW expects these in little endian so we reverse the byte order
473 * from network order (big endian) to little endian
474 */
422
423 if (hw->bus.func == E1000_FUNC_1)
424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
425 if (hw->bus.func == E1000_FUNC_2)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
427
428 if (hw->bus.func == E1000_FUNC_3)
429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;

--- 40 unchanged lines hidden (view full) ---

470 u32 rar_low, rar_high;
471
472 DEBUGFUNC("e1000_rar_set_generic");
473
474 /*
475 * HW expects these in little endian so we reverse the byte order
476 * from network order (big endian) to little endian
477 */
475 rar_low = ((u32) addr[0] |
476 ((u32) addr[1] << 8) |
477 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
478 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
479 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
478
479 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
480
481 /* If MAC address zero, no need to set the AV bit */
482 if (rar_low || rar_high)
483 rar_high |= E1000_RAH_AV;
484
485 /*

--- 12 unchanged lines hidden (view full) ---

498 * @hw: pointer to the HW structure
499 * @mc_addr_list: array of multicast addresses to program
500 * @mc_addr_count: number of multicast addresses to program
501 *
502 * Updates entire Multicast Table Array.
503 * The caller must have a packed mc_addr_list of multicast addresses.
504 **/
505void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
480
481 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
482
483 /* If MAC address zero, no need to set the AV bit */
484 if (rar_low || rar_high)
485 rar_high |= E1000_RAH_AV;
486
487 /*

--- 12 unchanged lines hidden (view full) ---

500 * @hw: pointer to the HW structure
501 * @mc_addr_list: array of multicast addresses to program
502 * @mc_addr_count: number of multicast addresses to program
503 *
504 * Updates entire Multicast Table Array.
505 * The caller must have a packed mc_addr_list of multicast addresses.
506 **/
507void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
506 u8 *mc_addr_list, u32 mc_addr_count)
508 u8 *mc_addr_list, u32 mc_addr_count)
507{
508 u32 hash_value, hash_bit, hash_reg;
509 int i;
510
511 DEBUGFUNC("e1000_update_mc_addr_list_generic");
512
513 /* clear mta_shadow */
514 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

--- 54 unchanged lines hidden (view full) ---

569 * 8-bit shifting total.
570 *
571 * For example, given the following Destination MAC Address and an
572 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
573 * we can see that the bit_shift for case 0 is 4. These are the hash
574 * values resulting from each mc_filter_type...
575 * [0] [1] [2] [3] [4] [5]
576 * 01 AA 00 12 34 56
509{
510 u32 hash_value, hash_bit, hash_reg;
511 int i;
512
513 DEBUGFUNC("e1000_update_mc_addr_list_generic");
514
515 /* clear mta_shadow */
516 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

--- 54 unchanged lines hidden (view full) ---

571 * 8-bit shifting total.
572 *
573 * For example, given the following Destination MAC Address and an
574 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
575 * we can see that the bit_shift for case 0 is 4. These are the hash
576 * values resulting from each mc_filter_type...
577 * [0] [1] [2] [3] [4] [5]
578 * 01 AA 00 12 34 56
577 * LSB MSB
579 * LSB MSB
578 *
579 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
580 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
581 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
582 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
583 */
584 switch (hw->mac.mc_filter_type) {
585 default:

--- 6 unchanged lines hidden (view full) ---

592 bit_shift += 2;
593 break;
594 case 3:
595 bit_shift += 4;
596 break;
597 }
598
599 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
580 *
581 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
582 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
583 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
584 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
585 */
586 switch (hw->mac.mc_filter_type) {
587 default:

--- 6 unchanged lines hidden (view full) ---

594 bit_shift += 2;
595 break;
596 case 3:
597 bit_shift += 4;
598 break;
599 }
600
601 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
600 (((u16) mc_addr[5]) << bit_shift)));
602 (((u16) mc_addr[5]) << bit_shift)));
601
602 return hash_value;
603}
604
605/**
606 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
607 * @hw: pointer to the HW structure
608 *

--- 13 unchanged lines hidden (view full) ---

622
623 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
624 if (hw->bus.type != e1000_bus_type_pcix)
625 return;
626
627 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
628 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
629 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
603
604 return hash_value;
605}
606
607/**
608 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
609 * @hw: pointer to the HW structure
610 *

--- 13 unchanged lines hidden (view full) ---

624
625 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
626 if (hw->bus.type != e1000_bus_type_pcix)
627 return;
628
629 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
630 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
631 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
630 PCIX_COMMAND_MMRBC_SHIFT;
632 PCIX_COMMAND_MMRBC_SHIFT;
631 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
633 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
632 PCIX_STATUS_HI_MMRBC_SHIFT;
634 PCIX_STATUS_HI_MMRBC_SHIFT;
633 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
634 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
635 if (cmd_mmrbc > stat_mmrbc) {
636 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
637 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
638 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
639 }
640}

--- 280 unchanged lines hidden (view full) ---

921 status = E1000_READ_REG(hw, E1000_STATUS);
922 if (status & E1000_STATUS_LU) {
923 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
924 usec_delay(10);
925 rxcw = E1000_READ_REG(hw, E1000_RXCW);
926 if (rxcw & E1000_RXCW_SYNCH) {
927 if (!(rxcw & E1000_RXCW_IV)) {
928 mac->serdes_has_link = TRUE;
635 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
636 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
637 if (cmd_mmrbc > stat_mmrbc) {
638 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
639 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
640 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
641 }
642}

--- 280 unchanged lines hidden (view full) ---

923 status = E1000_READ_REG(hw, E1000_STATUS);
924 if (status & E1000_STATUS_LU) {
925 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
926 usec_delay(10);
927 rxcw = E1000_READ_REG(hw, E1000_RXCW);
928 if (rxcw & E1000_RXCW_SYNCH) {
929 if (!(rxcw & E1000_RXCW_IV)) {
930 mac->serdes_has_link = TRUE;
929 DEBUGOUT("SERDES: Link up - autoneg "
930 "completed sucessfully.\n");
931 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
931 } else {
932 mac->serdes_has_link = FALSE;
932 } else {
933 mac->serdes_has_link = FALSE;
933 DEBUGOUT("SERDES: Link down - invalid"
934 "codewords detected in autoneg.\n");
934 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
935 }
936 } else {
937 mac->serdes_has_link = FALSE;
938 DEBUGOUT("SERDES: Link down - no sync.\n");
939 }
940 } else {
941 mac->serdes_has_link = FALSE;
942 DEBUGOUT("SERDES: Link down - autoneg failed\n");

--- 475 unchanged lines hidden (view full) ---

1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1419 if (ret_val)
1420 goto out;
1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1422 if (ret_val)
1423 goto out;
1424
1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
935 }
936 } else {
937 mac->serdes_has_link = FALSE;
938 DEBUGOUT("SERDES: Link down - no sync.\n");
939 }
940 } else {
941 mac->serdes_has_link = FALSE;
942 DEBUGOUT("SERDES: Link down - autoneg failed\n");

--- 475 unchanged lines hidden (view full) ---

1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1419 if (ret_val)
1420 goto out;
1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1422 if (ret_val)
1423 goto out;
1424
1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1426 DEBUGOUT("Copper PHY and Auto Neg "
1427 "has not completed.\n");
1426 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1428 goto out;
1429 }
1430
1431 /*
1432 * The AutoNeg process has completed, so we now need to
1433 * read both the Auto Negotiation Advertisement
1434 * Register (Address 4) and the Auto_Negotiation Base
1435 * Page Ability Register (Address 5) to determine how
1436 * flow control was negotiated.
1437 */
1438 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1427 goto out;
1428 }
1429
1430 /*
1431 * The AutoNeg process has completed, so we now need to
1432 * read both the Auto Negotiation Advertisement
1433 * Register (Address 4) and the Auto_Negotiation Base
1434 * Page Ability Register (Address 5) to determine how
1435 * flow control was negotiated.
1436 */
1437 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1439 &mii_nway_adv_reg);
1438 &mii_nway_adv_reg);
1440 if (ret_val)
1441 goto out;
1442 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1439 if (ret_val)
1440 goto out;
1441 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1443 &mii_nway_lp_ability_reg);
1442 &mii_nway_lp_ability_reg);
1444 if (ret_val)
1445 goto out;
1446
1447 /*
1448 * Two bits in the Auto Negotiation Advertisement Register
1449 * (Address 4) and two bits in the Auto Negotiation Base
1450 * Page Ability Register (Address 5) determine flow control
1451 * for both the PHY and the link partner. The following

--- 28 unchanged lines hidden (view full) ---

1480 */
1481 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1482 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1483 /*
1484 * Now we need to check if the user selected Rx ONLY
1485 * of pause frames. In this case, we had to advertise
1486 * FULL flow control because we could not advertise Rx
1487 * ONLY. Hence, we must now check to see if we need to
1443 if (ret_val)
1444 goto out;
1445
1446 /*
1447 * Two bits in the Auto Negotiation Advertisement Register
1448 * (Address 4) and two bits in the Auto Negotiation Base
1449 * Page Ability Register (Address 5) determine flow control
1450 * for both the PHY and the link partner. The following

--- 28 unchanged lines hidden (view full) ---

1479 */
1480 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1481 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1482 /*
1483 * Now we need to check if the user selected Rx ONLY
1484 * of pause frames. In this case, we had to advertise
1485 * FULL flow control because we could not advertise Rx
1486 * ONLY. Hence, we must now check to see if we need to
1488 * turn OFF the TRANSMISSION of PAUSE frames.
1487 * turn OFF the TRANSMISSION of PAUSE frames.
1489 */
1490 if (hw->fc.requested_mode == e1000_fc_full) {
1491 hw->fc.current_mode = e1000_fc_full;
1488 */
1489 if (hw->fc.requested_mode == e1000_fc_full) {
1490 hw->fc.current_mode = e1000_fc_full;
1492 DEBUGOUT("Flow Control = FULL.\r\n");
1491 DEBUGOUT("Flow Control = FULL.\n");
1493 } else {
1494 hw->fc.current_mode = e1000_fc_rx_pause;
1492 } else {
1493 hw->fc.current_mode = e1000_fc_rx_pause;
1495 DEBUGOUT("Flow Control = "
1496 "Rx PAUSE frames only.\r\n");
1494 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1497 }
1498 }
1499 /*
1500 * For receiving PAUSE frames ONLY.
1501 *
1502 * LOCAL DEVICE | LINK PARTNER
1503 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1504 *-------|---------|-------|---------|--------------------
1505 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1506 */
1507 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1495 }
1496 }
1497 /*
1498 * For receiving PAUSE frames ONLY.
1499 *
1500 * LOCAL DEVICE | LINK PARTNER
1501 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1502 *-------|---------|-------|---------|--------------------
1503 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1504 */
1505 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1508 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1509 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1510 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1506 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1507 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1508 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1511 hw->fc.current_mode = e1000_fc_tx_pause;
1509 hw->fc.current_mode = e1000_fc_tx_pause;
1512 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
1510 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1513 }
1514 /*
1515 * For transmitting PAUSE frames ONLY.
1516 *
1517 * LOCAL DEVICE | LINK PARTNER
1518 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1519 *-------|---------|-------|---------|--------------------
1520 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1521 */
1522 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1511 }
1512 /*
1513 * For transmitting PAUSE frames ONLY.
1514 *
1515 * LOCAL DEVICE | LINK PARTNER
1516 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1517 *-------|---------|-------|---------|--------------------
1518 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1519 */
1520 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1523 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1524 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1525 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1521 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1522 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1523 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1526 hw->fc.current_mode = e1000_fc_rx_pause;
1524 hw->fc.current_mode = e1000_fc_rx_pause;
1527 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
1525 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1528 } else {
1529 /*
1530 * Per the IEEE spec, at this point flow control
1531 * should be disabled.
1532 */
1533 hw->fc.current_mode = e1000_fc_none;
1526 } else {
1527 /*
1528 * Per the IEEE spec, at this point flow control
1529 * should be disabled.
1530 */
1531 hw->fc.current_mode = e1000_fc_none;
1534 DEBUGOUT("Flow Control = NONE.\r\n");
1532 DEBUGOUT("Flow Control = NONE.\n");
1535 }
1536
1537 /*
1538 * Now we need to do one last check... If we auto-
1539 * negotiated to HALF DUPLEX, flow control should not be
1540 * enabled per IEEE 802.3 spec.
1541 */
1542 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);

--- 25 unchanged lines hidden (view full) ---

1568 * @hw: pointer to the HW structure
1569 * @speed: stores the current speed
1570 * @duplex: stores the current duplex
1571 *
1572 * Read the status register for the current speed/duplex and store the current
1573 * speed and duplex for copper connections.
1574 **/
1575s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1533 }
1534
1535 /*
1536 * Now we need to do one last check... If we auto-
1537 * negotiated to HALF DUPLEX, flow control should not be
1538 * enabled per IEEE 802.3 spec.
1539 */
1540 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);

--- 25 unchanged lines hidden (view full) ---

1566 * @hw: pointer to the HW structure
1567 * @speed: stores the current speed
1568 * @duplex: stores the current duplex
1569 *
1570 * Read the status register for the current speed/duplex and store the current
1571 * speed and duplex for copper connections.
1572 **/
1573s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1576 u16 *duplex)
1574 u16 *duplex)
1577{
1578 u32 status;
1579
1580 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1581
1582 status = E1000_READ_REG(hw, E1000_STATUS);
1583 if (status & E1000_STATUS_SPEED_1000) {
1584 *speed = SPEED_1000;

--- 22 unchanged lines hidden (view full) ---

1607 * @hw: pointer to the HW structure
1608 * @speed: stores the current speed
1609 * @duplex: stores the current duplex
1610 *
1611 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1612 * for fiber/serdes links.
1613 **/
1614s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1575{
1576 u32 status;
1577
1578 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1579
1580 status = E1000_READ_REG(hw, E1000_STATUS);
1581 if (status & E1000_STATUS_SPEED_1000) {
1582 *speed = SPEED_1000;

--- 22 unchanged lines hidden (view full) ---

1605 * @hw: pointer to the HW structure
1606 * @speed: stores the current speed
1607 * @duplex: stores the current duplex
1608 *
1609 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1610 * for fiber/serdes links.
1611 **/
1612s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1615 u16 *speed, u16 *duplex)
1613 u16 *speed, u16 *duplex)
1616{
1617 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1618
1619 *speed = SPEED_1000;
1620 *duplex = FULL_DUPLEX;
1621
1622 return E1000_SUCCESS;
1623}

--- 214 unchanged lines hidden (view full) ---

1838 ret_val = -E1000_ERR_CONFIG;
1839 goto out;
1840 }
1841
1842 if (hw->phy.media_type == e1000_media_type_fiber) {
1843 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1844 hw->mac.ledctl_default = ledctl;
1845 /* Turn off LED0 */
1614{
1615 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1616
1617 *speed = SPEED_1000;
1618 *duplex = FULL_DUPLEX;
1619
1620 return E1000_SUCCESS;
1621}

--- 214 unchanged lines hidden (view full) ---

1836 ret_val = -E1000_ERR_CONFIG;
1837 goto out;
1838 }
1839
1840 if (hw->phy.media_type == e1000_media_type_fiber) {
1841 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1842 hw->mac.ledctl_default = ledctl;
1843 /* Turn off LED0 */
1846 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1847 E1000_LEDCTL_LED0_BLINK |
1848 E1000_LEDCTL_LED0_MODE_MASK);
1844 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1845 E1000_LEDCTL_LED0_MODE_MASK);
1849 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1846 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1850 E1000_LEDCTL_LED0_MODE_SHIFT);
1847 E1000_LEDCTL_LED0_MODE_SHIFT);
1851 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1852 } else if (hw->phy.media_type == e1000_media_type_copper) {
1853 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1854 }
1855
1856out:
1857 return ret_val;
1858}

--- 35 unchanged lines hidden (view full) ---

1894 * set the blink bit for each LED that's "on" (0x0E)
1895 * in ledctl_mode2
1896 */
1897 ledctl_blink = hw->mac.ledctl_mode2;
1898 for (i = 0; i < 4; i++)
1899 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1900 E1000_LEDCTL_MODE_LED_ON)
1901 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1848 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1849 } else if (hw->phy.media_type == e1000_media_type_copper) {
1850 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1851 }
1852
1853out:
1854 return ret_val;
1855}

--- 35 unchanged lines hidden (view full) ---

1891 * set the blink bit for each LED that's "on" (0x0E)
1892 * in ledctl_mode2
1893 */
1894 ledctl_blink = hw->mac.ledctl_mode2;
1895 for (i = 0; i < 4; i++)
1896 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1897 E1000_LEDCTL_MODE_LED_ON)
1898 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1902 (i * 8));
1899 (i * 8));
1903 }
1904
1905 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1906
1907 return E1000_SUCCESS;
1908}
1909
1910/**

--- 174 unchanged lines hidden (view full) ---

2085 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2086 mac->in_ifs_mode = TRUE;
2087 if (mac->current_ifs_val < mac->ifs_max_val) {
2088 if (!mac->current_ifs_val)
2089 mac->current_ifs_val = mac->ifs_min_val;
2090 else
2091 mac->current_ifs_val +=
2092 mac->ifs_step_size;
1900 }
1901
1902 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1903
1904 return E1000_SUCCESS;
1905}
1906
1907/**

--- 174 unchanged lines hidden (view full) ---

2082 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2083 mac->in_ifs_mode = TRUE;
2084 if (mac->current_ifs_val < mac->ifs_max_val) {
2085 if (!mac->current_ifs_val)
2086 mac->current_ifs_val = mac->ifs_min_val;
2087 else
2088 mac->current_ifs_val +=
2089 mac->ifs_step_size;
2093 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2090 E1000_WRITE_REG(hw, E1000_AIT,
2091 mac->current_ifs_val);
2094 }
2095 }
2096 } else {
2097 if (mac->in_ifs_mode &&
2098 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2099 mac->current_ifs_val = 0;
2100 mac->in_ifs_mode = FALSE;
2101 E1000_WRITE_REG(hw, E1000_AIT, 0);

--- 34 unchanged lines hidden (view full) ---

2136 * @offset: register offset to write to
2137 * @data: data to write at register offset
2138 *
2139 * Writes an address/data control type register. There are several of these
2140 * and they all have the format address << 8 | data and bit 31 is polled for
2141 * completion.
2142 **/
2143s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2092 }
2093 }
2094 } else {
2095 if (mac->in_ifs_mode &&
2096 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2097 mac->current_ifs_val = 0;
2098 mac->in_ifs_mode = FALSE;
2099 E1000_WRITE_REG(hw, E1000_AIT, 0);

--- 34 unchanged lines hidden (view full) ---

2134 * @offset: register offset to write to
2135 * @data: data to write at register offset
2136 *
2137 * Writes an address/data control type register. There are several of these
2138 * and they all have the format address << 8 | data and bit 31 is polled for
2139 * completion.
2140 **/
2141s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2144 u32 offset, u8 data)
2142 u32 offset, u8 data)
2145{
2146 u32 i, regvalue = 0;
2147 s32 ret_val = E1000_SUCCESS;
2148
2149 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2150
2151 /* Set up the address and data */
2152 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);

--- 18 unchanged lines hidden --- 		2143{
2144 u32 i, regvalue = 0;
2145 s32 ret_val = E1000_SUCCESS;
2146
2147 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2148
2149 /* Set up the address and data */
2150 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);

--- 18 unchanged lines hidden ---