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e1000_mac.c (169589) e1000_mac.c (173788)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_mac.c 169589 2007-05-16 00:14:23Z jfv $*/
33/* $FreeBSD: head/sys/dev/em/e1000_mac.c 173788 2007-11-20 21:41:22Z jfv $ */
34
35
36#include "e1000_api.h"
37#include "e1000_mac.h"
38
39/**
40 * e1000_remove_device_generic - Free device specific structure
41 * @hw: pointer to the HW structure
42 *
43 * If a device specific structure was allocated, this function will
44 * free it.
45 **/
34
35
36#include "e1000_api.h"
37#include "e1000_mac.h"
38
39/**
40 * e1000_remove_device_generic - Free device specific structure
41 * @hw: pointer to the HW structure
42 *
43 * If a device specific structure was allocated, this function will
44 * free it.
45 **/
46void
47e1000_remove_device_generic(struct e1000_hw *hw)
46void e1000_remove_device_generic(struct e1000_hw *hw)
48{
49 DEBUGFUNC("e1000_remove_device_generic");
50
51 /* Freeing the dev_spec member of e1000_hw structure */
52 e1000_free_dev_spec_struct(hw);
53}
54
55/**
56 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
57 * @hw: pointer to the HW structure
58 *
59 * Determines and stores the system bus information for a particular
60 * network interface. The following bus information is determined and stored:
61 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
62 **/
47{
48 DEBUGFUNC("e1000_remove_device_generic");
49
50 /* Freeing the dev_spec member of e1000_hw structure */
51 e1000_free_dev_spec_struct(hw);
52}
53
54/**
55 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
56 * @hw: pointer to the HW structure
57 *
58 * Determines and stores the system bus information for a particular
59 * network interface. The following bus information is determined and stored:
60 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
61 **/
63s32
64e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
62s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
65{
66 struct e1000_bus_info *bus = &hw->bus;
67 u32 status = E1000_READ_REG(hw, E1000_STATUS);
68 s32 ret_val = E1000_SUCCESS;
69 u16 pci_header_type;
70
71 DEBUGFUNC("e1000_get_bus_info_pci_generic");
72

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116/**
117 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
118 * @hw: pointer to the HW structure
119 *
120 * Determines and stores the system bus information for a particular
121 * network interface. The following bus information is determined and stored:
122 * bus speed, bus width, type (PCIe), and PCIe function.
123 **/
63{
64 struct e1000_bus_info *bus = &hw->bus;
65 u32 status = E1000_READ_REG(hw, E1000_STATUS);
66 s32 ret_val = E1000_SUCCESS;
67 u16 pci_header_type;
68
69 DEBUGFUNC("e1000_get_bus_info_pci_generic");
70

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114/**
115 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
116 * @hw: pointer to the HW structure
117 *
118 * Determines and stores the system bus information for a particular
119 * network interface. The following bus information is determined and stored:
120 * bus speed, bus width, type (PCIe), and PCIe function.
121 **/
124s32
125e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
122s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
126{
127 struct e1000_bus_info *bus = &hw->bus;
128 s32 ret_val;
129 u32 status;
130 u16 pcie_link_status, pci_header_type;
131
132 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
133

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144 PCIE_LINK_WIDTH_MASK) >>
145 PCIE_LINK_WIDTH_SHIFT);
146
147 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
148 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
149 status = E1000_READ_REG(hw, E1000_STATUS);
150 bus->func = (status & E1000_STATUS_FUNC_MASK)
151 >> E1000_STATUS_FUNC_SHIFT;
123{
124 struct e1000_bus_info *bus = &hw->bus;
125 s32 ret_val;
126 u32 status;
127 u16 pcie_link_status, pci_header_type;
128
129 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
130

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141 PCIE_LINK_WIDTH_MASK) >>
142 PCIE_LINK_WIDTH_SHIFT);
143
144 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
145 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
146 status = E1000_READ_REG(hw, E1000_STATUS);
147 bus->func = (status & E1000_STATUS_FUNC_MASK)
148 >> E1000_STATUS_FUNC_SHIFT;
152 } else
149 } else {
153 bus->func = 0;
150 bus->func = 0;
151 }
154
155 return E1000_SUCCESS;
156}
157
158/**
159 * e1000_clear_vfta_generic - Clear VLAN filter table
160 * @hw: pointer to the HW structure
161 *
162 * Clears the register array which contains the VLAN filter table by
163 * setting all the values to 0.
164 **/
152
153 return E1000_SUCCESS;
154}
155
156/**
157 * e1000_clear_vfta_generic - Clear VLAN filter table
158 * @hw: pointer to the HW structure
159 *
160 * Clears the register array which contains the VLAN filter table by
161 * setting all the values to 0.
162 **/
165void
166e1000_clear_vfta_generic(struct e1000_hw *hw)
163void e1000_clear_vfta_generic(struct e1000_hw *hw)
167{
168 u32 offset;
169
170 DEBUGFUNC("e1000_clear_vfta_generic");
171
172 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
173 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
174 E1000_WRITE_FLUSH(hw);

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179 * e1000_write_vfta_generic - Write value to VLAN filter table
180 * @hw: pointer to the HW structure
181 * @offset: register offset in VLAN filter table
182 * @value: register value written to VLAN filter table
183 *
184 * Writes value at the given offset in the register array which stores
185 * the VLAN filter table.
186 **/
164{
165 u32 offset;
166
167 DEBUGFUNC("e1000_clear_vfta_generic");
168
169 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
170 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
171 E1000_WRITE_FLUSH(hw);

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176 * e1000_write_vfta_generic - Write value to VLAN filter table
177 * @hw: pointer to the HW structure
178 * @offset: register offset in VLAN filter table
179 * @value: register value written to VLAN filter table
180 *
181 * Writes value at the given offset in the register array which stores
182 * the VLAN filter table.
183 **/
187void
188e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
184void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
189{
190 DEBUGFUNC("e1000_write_vfta_generic");
191
192 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
193 E1000_WRITE_FLUSH(hw);
194}
195
196/**
197 * e1000_init_rx_addrs_generic - Initialize receive address's
198 * @hw: pointer to the HW structure
199 * @rar_count: receive address registers
200 *
201 * Setups the receive address registers by setting the base receive address
202 * register to the devices MAC address and clearing all the other receive
203 * address registers to 0.
204 **/
185{
186 DEBUGFUNC("e1000_write_vfta_generic");
187
188 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
189 E1000_WRITE_FLUSH(hw);
190}
191
192/**
193 * e1000_init_rx_addrs_generic - Initialize receive address's
194 * @hw: pointer to the HW structure
195 * @rar_count: receive address registers
196 *
197 * Setups the receive address registers by setting the base receive address
198 * register to the devices MAC address and clearing all the other receive
199 * address registers to 0.
200 **/
205void
206e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
201void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
207{
208 u32 i;
209
210 DEBUGFUNC("e1000_init_rx_addrs_generic");
211
212 /* Setup the receive address */
213 DEBUGOUT("Programming MAC Address into RAR[0]\n");
214

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220 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
221 E1000_WRITE_FLUSH(hw);
222 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
223 E1000_WRITE_FLUSH(hw);
224 }
225}
226
227/**
202{
203 u32 i;
204
205 DEBUGFUNC("e1000_init_rx_addrs_generic");
206
207 /* Setup the receive address */
208 DEBUGOUT("Programming MAC Address into RAR[0]\n");
209

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215 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
216 E1000_WRITE_FLUSH(hw);
217 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
218 E1000_WRITE_FLUSH(hw);
219 }
220}
221
222/**
223 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
224 * @hw: pointer to the HW structure
225 *
226 * Checks the nvm for an alternate MAC address. An alternate MAC address
227 * can be setup by pre-boot software and must be treated like a permanent
228 * address and must override the actual permanent MAC address. If an
229 * alternate MAC address is found it is saved in the hw struct and
230 * programmed into RAR0 and the function returns success, otherwise the
231 * function returns an error.
232 **/
233s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
234{
235 u32 i;
236 s32 ret_val = E1000_SUCCESS;
237 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
238 u8 alt_mac_addr[ETH_ADDR_LEN];
239
240 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
241
242 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, &nvm_alt_mac_addr_offset);
243 if (ret_val) {
244 DEBUGOUT("NVM Read Error\n");
245 goto out;
246 }
247
248 if (nvm_alt_mac_addr_offset == 0xFFFF) {
249 ret_val = -(E1000_NOT_IMPLEMENTED);
250 goto out;
251 }
252
253 if (hw->bus.func == E1000_FUNC_1)
254 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16);
255
256 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
257 offset = nvm_alt_mac_addr_offset + (i >> 1);
258 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
259 if (ret_val) {
260 DEBUGOUT("NVM Read Error\n");
261 goto out;
262 }
263
264 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
265 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
266 }
267
268 /* if multicast bit is set, the alternate address will not be used */
269 if (alt_mac_addr[0] & 0x01) {
270 ret_val = -(E1000_NOT_IMPLEMENTED);
271 goto out;
272 }
273
274 for (i = 0; i < ETH_ADDR_LEN; i++)
275 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
276
277 e1000_rar_set(hw, hw->mac.perm_addr, 0);
278
279out:
280 return ret_val;
281}
282
283/**
228 * e1000_rar_set_generic - Set receive address register
229 * @hw: pointer to the HW structure
230 * @addr: pointer to the receive address
231 * @index: receive address array register
232 *
233 * Sets the receive address array register at index to the address passed
234 * in by addr.
235 **/
284 * e1000_rar_set_generic - Set receive address register
285 * @hw: pointer to the HW structure
286 * @addr: pointer to the receive address
287 * @index: receive address array register
288 *
289 * Sets the receive address array register at index to the address passed
290 * in by addr.
291 **/
236void
237e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
292void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
238{
239 u32 rar_low, rar_high;
240
241 DEBUGFUNC("e1000_rar_set_generic");
242
293{
294 u32 rar_low, rar_high;
295
296 DEBUGFUNC("e1000_rar_set_generic");
297
243 /* HW expects these in little endian so we reverse the byte order
298 /*
299 * HW expects these in little endian so we reverse the byte order
244 * from network order (big endian) to little endian
245 */
246 rar_low = ((u32) addr[0] |
247 ((u32) addr[1] << 8) |
248 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
249
250 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
251
300 * from network order (big endian) to little endian
301 */
302 rar_low = ((u32) addr[0] |
303 ((u32) addr[1] << 8) |
304 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
305
306 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
307
252 if (!hw->mac.disable_av)
253 rar_high |= E1000_RAH_AV;
308 /* If MAC address zero, no need to set the AV bit */
309 if (rar_low || rar_high) {
310 if (!hw->mac.disable_av)
311 rar_high |= E1000_RAH_AV;
312 }
254
255 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
256 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
257}
258
259/**
260 * e1000_mta_set_generic - Set multicast filter table address
261 * @hw: pointer to the HW structure
262 * @hash_value: determines the MTA register and bit to set
263 *
264 * The multicast table address is a register array of 32-bit registers.
265 * The hash_value is used to determine what register the bit is in, the
266 * current value is read, the new bit is OR'd in and the new value is
267 * written back into the register.
268 **/
313
314 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
315 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
316}
317
318/**
319 * e1000_mta_set_generic - Set multicast filter table address
320 * @hw: pointer to the HW structure
321 * @hash_value: determines the MTA register and bit to set
322 *
323 * The multicast table address is a register array of 32-bit registers.
324 * The hash_value is used to determine what register the bit is in, the
325 * current value is read, the new bit is OR'd in and the new value is
326 * written back into the register.
327 **/
269void
270e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
328void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
271{
272 u32 hash_bit, hash_reg, mta;
273
274 DEBUGFUNC("e1000_mta_set_generic");
329{
330 u32 hash_bit, hash_reg, mta;
331
332 DEBUGFUNC("e1000_mta_set_generic");
275 /* The MTA is a register array of 32-bit registers. It is
333 /*
334 * The MTA is a register array of 32-bit registers. It is
276 * treated like an array of (32*mta_reg_count) bits. We want to
277 * set bit BitArray[hash_value]. So we figure out what register
278 * the bit is in, read it, OR in the new bit, then write
279 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
280 * mask to bits 31:5 of the hash value which gives us the
281 * register we're modifying. The hash bit within that register
282 * is determined by the lower 5 bits of the hash value.
283 */

--- 4 unchanged lines hidden (view full) ---

288
289 mta |= (1 << hash_bit);
290
291 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
292 E1000_WRITE_FLUSH(hw);
293}
294
295/**
335 * treated like an array of (32*mta_reg_count) bits. We want to
336 * set bit BitArray[hash_value]. So we figure out what register
337 * the bit is in, read it, OR in the new bit, then write
338 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
339 * mask to bits 31:5 of the hash value which gives us the
340 * register we're modifying. The hash bit within that register
341 * is determined by the lower 5 bits of the hash value.
342 */

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347
348 mta |= (1 << hash_bit);
349
350 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
351 E1000_WRITE_FLUSH(hw);
352}
353
354/**
296 * e1000_mc_addr_list_update_generic - Update Multicast addresses
355 * e1000_update_mc_addr_list_generic - Update Multicast addresses
297 * @hw: pointer to the HW structure
298 * @mc_addr_list: array of multicast addresses to program
299 * @mc_addr_count: number of multicast addresses to program
300 * @rar_used_count: the first RAR register free to program
301 * @rar_count: total number of supported Receive Address Registers
302 *
303 * Updates the Receive Address Registers and Multicast Table Array.
304 * The caller must have a packed mc_addr_list of multicast addresses.
305 * The parameter rar_count will usually be hw->mac.rar_entry_count
306 * unless there are workarounds that change this.
307 **/
356 * @hw: pointer to the HW structure
357 * @mc_addr_list: array of multicast addresses to program
358 * @mc_addr_count: number of multicast addresses to program
359 * @rar_used_count: the first RAR register free to program
360 * @rar_count: total number of supported Receive Address Registers
361 *
362 * Updates the Receive Address Registers and Multicast Table Array.
363 * The caller must have a packed mc_addr_list of multicast addresses.
364 * The parameter rar_count will usually be hw->mac.rar_entry_count
365 * unless there are workarounds that change this.
366 **/
308void
309e1000_mc_addr_list_update_generic(struct e1000_hw *hw,
310 u8 *mc_addr_list, u32 mc_addr_count,
311 u32 rar_used_count, u32 rar_count)
367void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
368 u8 *mc_addr_list, u32 mc_addr_count,
369 u32 rar_used_count, u32 rar_count)
312{
313 u32 hash_value;
314 u32 i;
315
370{
371 u32 hash_value;
372 u32 i;
373
316 DEBUGFUNC("e1000_mc_addr_list_update_generic");
374 DEBUGFUNC("e1000_update_mc_addr_list_generic");
317
375
318 /* Load the first set of multicast addresses into the exact
376 /*
377 * Load the first set of multicast addresses into the exact
319 * filters (RAR). If there are not enough to fill the RAR
320 * array, clear the filters.
321 */
322 for (i = rar_used_count; i < rar_count; i++) {
323 if (mc_addr_count) {
324 e1000_rar_set(hw, mc_addr_list, i);
325 mc_addr_count--;
326 mc_addr_list += ETH_ADDR_LEN;

--- 25 unchanged lines hidden (view full) ---

352 * e1000_hash_mc_addr_generic - Generate a multicast hash value
353 * @hw: pointer to the HW structure
354 * @mc_addr: pointer to a multicast address
355 *
356 * Generates a multicast address hash value which is used to determine
357 * the multicast filter table array address and new table value. See
358 * e1000_mta_set_generic()
359 **/
378 * filters (RAR). If there are not enough to fill the RAR
379 * array, clear the filters.
380 */
381 for (i = rar_used_count; i < rar_count; i++) {
382 if (mc_addr_count) {
383 e1000_rar_set(hw, mc_addr_list, i);
384 mc_addr_count--;
385 mc_addr_list += ETH_ADDR_LEN;

--- 25 unchanged lines hidden (view full) ---

411 * e1000_hash_mc_addr_generic - Generate a multicast hash value
412 * @hw: pointer to the HW structure
413 * @mc_addr: pointer to a multicast address
414 *
415 * Generates a multicast address hash value which is used to determine
416 * the multicast filter table array address and new table value. See
417 * e1000_mta_set_generic()
418 **/
360u32
361e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
419u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
362{
363 u32 hash_value, hash_mask;
364 u8 bit_shift = 0;
365
366 DEBUGFUNC("e1000_hash_mc_addr_generic");
367
368 /* Register count multiplied by bits per register */
369 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
370
420{
421 u32 hash_value, hash_mask;
422 u8 bit_shift = 0;
423
424 DEBUGFUNC("e1000_hash_mc_addr_generic");
425
426 /* Register count multiplied by bits per register */
427 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
428
371 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
372 * where 0xFF would still fall within the hash mask. */
429 /*
430 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
431 * where 0xFF would still fall within the hash mask.
432 */
373 while (hash_mask >> bit_shift != 0xFF)
374 bit_shift++;
375
433 while (hash_mask >> bit_shift != 0xFF)
434 bit_shift++;
435
376 /* The portion of the address that is used for the hash table
436 /*
437 * The portion of the address that is used for the hash table
377 * is determined by the mc_filter_type setting.
378 * The algorithm is such that there is a total of 8 bits of shifting.
379 * The bit_shift for a mc_filter_type of 0 represents the number of
380 * left-shifts where the MSB of mc_addr[5] would still fall within
381 * the hash_mask. Case 0 does this exactly. Since there are a total
382 * of 8 bits of shifting, then mc_addr[4] will shift right the
383 * remaining number of bits. Thus 8 - bit_shift. The rest of the
384 * cases are a variation of this algorithm...essentially raising the
385 * number of bits to shift mc_addr[5] left, while still keeping the
386 * 8-bit shifting total.
438 * is determined by the mc_filter_type setting.
439 * The algorithm is such that there is a total of 8 bits of shifting.
440 * The bit_shift for a mc_filter_type of 0 represents the number of
441 * left-shifts where the MSB of mc_addr[5] would still fall within
442 * the hash_mask. Case 0 does this exactly. Since there are a total
443 * of 8 bits of shifting, then mc_addr[4] will shift right the
444 * remaining number of bits. Thus 8 - bit_shift. The rest of the
445 * cases are a variation of this algorithm...essentially raising the
446 * number of bits to shift mc_addr[5] left, while still keeping the
447 * 8-bit shifting total.
387 */
388 /* For example, given the following Destination MAC Address and an
448 *
449 * For example, given the following Destination MAC Address and an
389 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
390 * we can see that the bit_shift for case 0 is 4. These are the hash
391 * values resulting from each mc_filter_type...
392 * [0] [1] [2] [3] [4] [5]
393 * 01 AA 00 12 34 56
394 * LSB MSB
395 *
396 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

--- 26 unchanged lines hidden (view full) ---

423 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
424 * @hw: pointer to the HW structure
425 *
426 * In certain situations, a system BIOS may report that the PCIx maximum
427 * memory read byte count (MMRBC) value is higher than than the actual
428 * value. We check the PCIx command regsiter with the current PCIx status
429 * regsiter.
430 **/
450 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
451 * we can see that the bit_shift for case 0 is 4. These are the hash
452 * values resulting from each mc_filter_type...
453 * [0] [1] [2] [3] [4] [5]
454 * 01 AA 00 12 34 56
455 * LSB MSB
456 *
457 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

--- 26 unchanged lines hidden (view full) ---

484 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
485 * @hw: pointer to the HW structure
486 *
487 * In certain situations, a system BIOS may report that the PCIx maximum
488 * memory read byte count (MMRBC) value is higher than than the actual
489 * value. We check the PCIx command regsiter with the current PCIx status
490 * regsiter.
491 **/
431void
432e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
492void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
433{
434 u16 cmd_mmrbc;
435 u16 pcix_cmd;
436 u16 pcix_stat_hi_word;
437 u16 stat_mmrbc;
438
439 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
440

--- 17 unchanged lines hidden (view full) ---

458}
459
460/**
461 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
462 * @hw: pointer to the HW structure
463 *
464 * Clears the base hardware counters by reading the counter registers.
465 **/
493{
494 u16 cmd_mmrbc;
495 u16 pcix_cmd;
496 u16 pcix_stat_hi_word;
497 u16 stat_mmrbc;
498
499 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
500

--- 17 unchanged lines hidden (view full) ---

518}
519
520/**
521 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
522 * @hw: pointer to the HW structure
523 *
524 * Clears the base hardware counters by reading the counter registers.
525 **/
466void
467e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
526void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
468{
469 volatile u32 temp;
470
471 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
472
473 temp = E1000_READ_REG(hw, E1000_CRCERRS);
474 temp = E1000_READ_REG(hw, E1000_SYMERRS);
475 temp = E1000_READ_REG(hw, E1000_MPC);

--- 36 unchanged lines hidden (view full) ---

512/**
513 * e1000_check_for_copper_link_generic - Check for link (Copper)
514 * @hw: pointer to the HW structure
515 *
516 * Checks to see of the link status of the hardware has changed. If a
517 * change in link status has been detected, then we read the PHY registers
518 * to get the current speed/duplex if link exists.
519 **/
527{
528 volatile u32 temp;
529
530 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
531
532 temp = E1000_READ_REG(hw, E1000_CRCERRS);
533 temp = E1000_READ_REG(hw, E1000_SYMERRS);
534 temp = E1000_READ_REG(hw, E1000_MPC);

--- 36 unchanged lines hidden (view full) ---

571/**
572 * e1000_check_for_copper_link_generic - Check for link (Copper)
573 * @hw: pointer to the HW structure
574 *
575 * Checks to see of the link status of the hardware has changed. If a
576 * change in link status has been detected, then we read the PHY registers
577 * to get the current speed/duplex if link exists.
578 **/
520s32
521e1000_check_for_copper_link_generic(struct e1000_hw *hw)
579s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
522{
523 struct e1000_mac_info *mac = &hw->mac;
524 s32 ret_val;
580{
581 struct e1000_mac_info *mac = &hw->mac;
582 s32 ret_val;
525 boolean_t link;
583 bool link;
526
527 DEBUGFUNC("e1000_check_for_copper_link");
528
584
585 DEBUGFUNC("e1000_check_for_copper_link");
586
529 /* We only want to go out to the PHY registers to see if Auto-Neg
587 /*
588 * We only want to go out to the PHY registers to see if Auto-Neg
530 * has completed and/or if our link status has changed. The
531 * get_link_status flag is set upon receiving a Link Status
532 * Change or Rx Sequence Error interrupt.
533 */
534 if (!mac->get_link_status) {
535 ret_val = E1000_SUCCESS;
536 goto out;
537 }
538
589 * has completed and/or if our link status has changed. The
590 * get_link_status flag is set upon receiving a Link Status
591 * Change or Rx Sequence Error interrupt.
592 */
593 if (!mac->get_link_status) {
594 ret_val = E1000_SUCCESS;
595 goto out;
596 }
597
539 /* First we want to see if the MII Status Register reports
598 /*
599 * First we want to see if the MII Status Register reports
540 * link. If so, then we want to get the current speed/duplex
541 * of the PHY.
542 */
543 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
544 if (ret_val)
545 goto out;
546
547 if (!link)
548 goto out; /* No link detected */
549
550 mac->get_link_status = FALSE;
551
600 * link. If so, then we want to get the current speed/duplex
601 * of the PHY.
602 */
603 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
604 if (ret_val)
605 goto out;
606
607 if (!link)
608 goto out; /* No link detected */
609
610 mac->get_link_status = FALSE;
611
552 /* Check if there was DownShift, must be checked
553 * immediately after link-up */
612 /*
613 * Check if there was DownShift, must be checked
614 * immediately after link-up
615 */
554 e1000_check_downshift_generic(hw);
555
616 e1000_check_downshift_generic(hw);
617
556 /* If we are forcing speed/duplex, then we simply return since
618 /*
619 * If we are forcing speed/duplex, then we simply return since
557 * we have already determined whether we have link or not.
558 */
559 if (!mac->autoneg) {
560 ret_val = -E1000_ERR_CONFIG;
561 goto out;
562 }
563
620 * we have already determined whether we have link or not.
621 */
622 if (!mac->autoneg) {
623 ret_val = -E1000_ERR_CONFIG;
624 goto out;
625 }
626
564 /* Auto-Neg is enabled. Auto Speed Detection takes care
627 /*
628 * Auto-Neg is enabled. Auto Speed Detection takes care
565 * of MAC speed/duplex configuration. So we only need to
566 * configure Collision Distance in the MAC.
567 */
568 e1000_config_collision_dist_generic(hw);
569
629 * of MAC speed/duplex configuration. So we only need to
630 * configure Collision Distance in the MAC.
631 */
632 e1000_config_collision_dist_generic(hw);
633
570 /* Configure Flow Control now that Auto-Neg has completed.
634 /*
635 * Configure Flow Control now that Auto-Neg has completed.
571 * First, we need to restore the desired flow control
572 * settings because we may have had to re-autoneg with a
573 * different link partner.
574 */
575 ret_val = e1000_config_fc_after_link_up_generic(hw);
576 if (ret_val) {
577 DEBUGOUT("Error configuring flow control\n");
578 }

--- 4 unchanged lines hidden (view full) ---

583
584/**
585 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
586 * @hw: pointer to the HW structure
587 *
588 * Checks for link up on the hardware. If link is not up and we have
589 * a signal, then we need to force link up.
590 **/
636 * First, we need to restore the desired flow control
637 * settings because we may have had to re-autoneg with a
638 * different link partner.
639 */
640 ret_val = e1000_config_fc_after_link_up_generic(hw);
641 if (ret_val) {
642 DEBUGOUT("Error configuring flow control\n");
643 }

--- 4 unchanged lines hidden (view full) ---

648
649/**
650 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
651 * @hw: pointer to the HW structure
652 *
653 * Checks for link up on the hardware. If link is not up and we have
654 * a signal, then we need to force link up.
655 **/
591s32
592e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
656s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
593{
594 struct e1000_mac_info *mac = &hw->mac;
595 u32 rxcw;
596 u32 ctrl;
597 u32 status;
598 s32 ret_val = E1000_SUCCESS;
599
600 DEBUGFUNC("e1000_check_for_fiber_link_generic");
601
602 ctrl = E1000_READ_REG(hw, E1000_CTRL);
603 status = E1000_READ_REG(hw, E1000_STATUS);
604 rxcw = E1000_READ_REG(hw, E1000_RXCW);
605
657{
658 struct e1000_mac_info *mac = &hw->mac;
659 u32 rxcw;
660 u32 ctrl;
661 u32 status;
662 s32 ret_val = E1000_SUCCESS;
663
664 DEBUGFUNC("e1000_check_for_fiber_link_generic");
665
666 ctrl = E1000_READ_REG(hw, E1000_CTRL);
667 status = E1000_READ_REG(hw, E1000_STATUS);
668 rxcw = E1000_READ_REG(hw, E1000_RXCW);
669
606 /* If we don't have link (auto-negotiation failed or link partner
670 /*
671 * If we don't have link (auto-negotiation failed or link partner
607 * cannot auto-negotiate), the cable is plugged in (we have signal),
608 * and our link partner is not trying to auto-negotiate with us (we
609 * are receiving idles or data), we need to force link up. We also
610 * need to give auto-negotiation time to complete, in case the cable
611 * was just plugged in. The autoneg_failed flag does this.
612 */
613 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
614 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&

--- 14 unchanged lines hidden (view full) ---

629
630 /* Configure Flow Control after forcing link up. */
631 ret_val = e1000_config_fc_after_link_up_generic(hw);
632 if (ret_val) {
633 DEBUGOUT("Error configuring flow control\n");
634 goto out;
635 }
636 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
672 * cannot auto-negotiate), the cable is plugged in (we have signal),
673 * and our link partner is not trying to auto-negotiate with us (we
674 * are receiving idles or data), we need to force link up. We also
675 * need to give auto-negotiation time to complete, in case the cable
676 * was just plugged in. The autoneg_failed flag does this.
677 */
678 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
679 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&

--- 14 unchanged lines hidden (view full) ---

694
695 /* Configure Flow Control after forcing link up. */
696 ret_val = e1000_config_fc_after_link_up_generic(hw);
697 if (ret_val) {
698 DEBUGOUT("Error configuring flow control\n");
699 goto out;
700 }
701 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
637 /* If we are forcing link and we are receiving /C/ ordered
702 /*
703 * If we are forcing link and we are receiving /C/ ordered
638 * sets, re-enable auto-negotiation in the TXCW register
639 * and disable forced link in the Device Control register
640 * in an attempt to auto-negotiate with our link partner.
641 */
642 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
643 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
644 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
645

--- 6 unchanged lines hidden (view full) ---

652
653/**
654 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
655 * @hw: pointer to the HW structure
656 *
657 * Checks for link up on the hardware. If link is not up and we have
658 * a signal, then we need to force link up.
659 **/
704 * sets, re-enable auto-negotiation in the TXCW register
705 * and disable forced link in the Device Control register
706 * in an attempt to auto-negotiate with our link partner.
707 */
708 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
709 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
710 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
711

--- 6 unchanged lines hidden (view full) ---

718
719/**
720 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
721 * @hw: pointer to the HW structure
722 *
723 * Checks for link up on the hardware. If link is not up and we have
724 * a signal, then we need to force link up.
725 **/
660s32
661e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
726s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
662{
663 struct e1000_mac_info *mac = &hw->mac;
664 u32 rxcw;
665 u32 ctrl;
666 u32 status;
667 s32 ret_val = E1000_SUCCESS;
668
669 DEBUGFUNC("e1000_check_for_serdes_link_generic");
670
671 ctrl = E1000_READ_REG(hw, E1000_CTRL);
672 status = E1000_READ_REG(hw, E1000_STATUS);
673 rxcw = E1000_READ_REG(hw, E1000_RXCW);
674
727{
728 struct e1000_mac_info *mac = &hw->mac;
729 u32 rxcw;
730 u32 ctrl;
731 u32 status;
732 s32 ret_val = E1000_SUCCESS;
733
734 DEBUGFUNC("e1000_check_for_serdes_link_generic");
735
736 ctrl = E1000_READ_REG(hw, E1000_CTRL);
737 status = E1000_READ_REG(hw, E1000_STATUS);
738 rxcw = E1000_READ_REG(hw, E1000_RXCW);
739
675 /* If we don't have link (auto-negotiation failed or link partner
740 /*
741 * If we don't have link (auto-negotiation failed or link partner
676 * cannot auto-negotiate), and our link partner is not trying to
677 * auto-negotiate with us (we are receiving idles or data),
678 * we need to force link up. We also need to give auto-negotiation
679 * time to complete.
680 */
681 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
682 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
683 if (mac->autoneg_failed == 0) {

--- 12 unchanged lines hidden (view full) ---

696
697 /* Configure Flow Control after forcing link up. */
698 ret_val = e1000_config_fc_after_link_up_generic(hw);
699 if (ret_val) {
700 DEBUGOUT("Error configuring flow control\n");
701 goto out;
702 }
703 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
742 * cannot auto-negotiate), and our link partner is not trying to
743 * auto-negotiate with us (we are receiving idles or data),
744 * we need to force link up. We also need to give auto-negotiation
745 * time to complete.
746 */
747 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
748 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
749 if (mac->autoneg_failed == 0) {

--- 12 unchanged lines hidden (view full) ---

762
763 /* Configure Flow Control after forcing link up. */
764 ret_val = e1000_config_fc_after_link_up_generic(hw);
765 if (ret_val) {
766 DEBUGOUT("Error configuring flow control\n");
767 goto out;
768 }
769 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
704 /* If we are forcing link and we are receiving /C/ ordered
770 /*
771 * If we are forcing link and we are receiving /C/ ordered
705 * sets, re-enable auto-negotiation in the TXCW register
706 * and disable forced link in the Device Control register
707 * in an attempt to auto-negotiate with our link partner.
708 */
709 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
710 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
711 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
712
713 mac->serdes_has_link = TRUE;
714 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
772 * sets, re-enable auto-negotiation in the TXCW register
773 * and disable forced link in the Device Control register
774 * in an attempt to auto-negotiate with our link partner.
775 */
776 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
777 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
778 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
779
780 mac->serdes_has_link = TRUE;
781 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
715 /* If we force link for non-auto-negotiation switch, check
782 /*
783 * If we force link for non-auto-negotiation switch, check
716 * link status based on MAC synchronization for internal
717 * serdes media type.
718 */
719 /* SYNCH bit and IV bit are sticky. */
720 usec_delay(10);
721 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) {
722 if (!(rxcw & E1000_RXCW_IV)) {
723 mac->serdes_has_link = TRUE;

--- 21 unchanged lines hidden (view full) ---

745 * @hw: pointer to the HW structure
746 *
747 * Determines which flow control settings to use, then configures flow
748 * control. Calls the appropriate media-specific link configuration
749 * function. Assuming the adapter has a valid link partner, a valid link
750 * should be established. Assumes the hardware has previously been reset
751 * and the transmitter and receiver are not enabled.
752 **/
784 * link status based on MAC synchronization for internal
785 * serdes media type.
786 */
787 /* SYNCH bit and IV bit are sticky. */
788 usec_delay(10);
789 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) {
790 if (!(rxcw & E1000_RXCW_IV)) {
791 mac->serdes_has_link = TRUE;

--- 21 unchanged lines hidden (view full) ---

813 * @hw: pointer to the HW structure
814 *
815 * Determines which flow control settings to use, then configures flow
816 * control. Calls the appropriate media-specific link configuration
817 * function. Assuming the adapter has a valid link partner, a valid link
818 * should be established. Assumes the hardware has previously been reset
819 * and the transmitter and receiver are not enabled.
820 **/
753s32
754e1000_setup_link_generic(struct e1000_hw *hw)
821s32 e1000_setup_link_generic(struct e1000_hw *hw)
755{
822{
756 struct e1000_mac_info *mac = &hw->mac;
757 struct e1000_functions *func = &hw->func;
758 s32 ret_val = E1000_SUCCESS;
759
760 DEBUGFUNC("e1000_setup_link_generic");
761
823 struct e1000_functions *func = &hw->func;
824 s32 ret_val = E1000_SUCCESS;
825
826 DEBUGFUNC("e1000_setup_link_generic");
827
762 /* In the case of the phy reset being blocked, we already have a link.
828 /*
829 * In the case of the phy reset being blocked, we already have a link.
763 * We do not need to set it up again.
764 */
765 if (e1000_check_reset_block(hw))
766 goto out;
767
830 * We do not need to set it up again.
831 */
832 if (e1000_check_reset_block(hw))
833 goto out;
834
768 ret_val = e1000_set_default_fc_generic(hw);
769 if (ret_val)
770 goto out;
835 /*
836 * If flow control is set to default, set flow control based on
837 * the EEPROM flow control settings.
838 */
839 if (hw->fc.type == e1000_fc_default) {
840 ret_val = e1000_set_default_fc_generic(hw);
841 if (ret_val)
842 goto out;
843 }
771
844
772 /* We want to save off the original Flow Control configuration just
845 /*
846 * We want to save off the original Flow Control configuration just
773 * in case we get disconnected and then reconnected into a different
774 * hub or switch with different Flow Control capabilities.
775 */
847 * in case we get disconnected and then reconnected into a different
848 * hub or switch with different Flow Control capabilities.
849 */
776 mac->original_fc = mac->fc;
850 hw->fc.original_type = hw->fc.type;
777
851
778 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc);
852 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
779
780 /* Call the necessary media_type subroutine to configure the link. */
781 ret_val = func->setup_physical_interface(hw);
782 if (ret_val)
783 goto out;
784
853
854 /* Call the necessary media_type subroutine to configure the link. */
855 ret_val = func->setup_physical_interface(hw);
856 if (ret_val)
857 goto out;
858
785 /* Initialize the flow control address, type, and PAUSE timer
859 /*
860 * Initialize the flow control address, type, and PAUSE timer
786 * registers to their default values. This is done even if flow
787 * control is disabled, because it does not hurt anything to
788 * initialize these registers.
789 */
790 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
791 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
792 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
793 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
794
861 * registers to their default values. This is done even if flow
862 * control is disabled, because it does not hurt anything to
863 * initialize these registers.
864 */
865 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
866 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
867 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
868 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
869
795 E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time);
870 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
796
797 ret_val = e1000_set_fc_watermarks_generic(hw);
798
799out:
800 return ret_val;
801}
802
803/**
804 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
805 * @hw: pointer to the HW structure
806 *
807 * Configures collision distance and flow control for fiber and serdes
808 * links. Upon successful setup, poll for link.
809 **/
871
872 ret_val = e1000_set_fc_watermarks_generic(hw);
873
874out:
875 return ret_val;
876}
877
878/**
879 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
880 * @hw: pointer to the HW structure
881 *
882 * Configures collision distance and flow control for fiber and serdes
883 * links. Upon successful setup, poll for link.
884 **/
810s32
811e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
885s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
812{
813 u32 ctrl;
814 s32 ret_val = E1000_SUCCESS;
815
816 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
817
818 ctrl = E1000_READ_REG(hw, E1000_CTRL);
819
820 /* Take the link out of reset */
821 ctrl &= ~E1000_CTRL_LRST;
822
823 e1000_config_collision_dist_generic(hw);
824
825 ret_val = e1000_commit_fc_settings_generic(hw);
826 if (ret_val)
827 goto out;
828
886{
887 u32 ctrl;
888 s32 ret_val = E1000_SUCCESS;
889
890 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
891
892 ctrl = E1000_READ_REG(hw, E1000_CTRL);
893
894 /* Take the link out of reset */
895 ctrl &= ~E1000_CTRL_LRST;
896
897 e1000_config_collision_dist_generic(hw);
898
899 ret_val = e1000_commit_fc_settings_generic(hw);
900 if (ret_val)
901 goto out;
902
829 /* Since auto-negotiation is enabled, take the link out of reset (the
903 /*
904 * Since auto-negotiation is enabled, take the link out of reset (the
830 * link will be in reset, because we previously reset the chip). This
831 * will restart auto-negotiation. If auto-negotiation is successful
832 * then the link-up status bit will be set and the flow control enable
833 * bits (RFCE and TFCE) will be set according to their negotiated value.
834 */
835 DEBUGOUT("Auto-negotiation enabled\n");
836
837 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
838 E1000_WRITE_FLUSH(hw);
839 msec_delay(1);
840
905 * link will be in reset, because we previously reset the chip). This
906 * will restart auto-negotiation. If auto-negotiation is successful
907 * then the link-up status bit will be set and the flow control enable
908 * bits (RFCE and TFCE) will be set according to their negotiated value.
909 */
910 DEBUGOUT("Auto-negotiation enabled\n");
911
912 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
913 E1000_WRITE_FLUSH(hw);
914 msec_delay(1);
915
841 /* For these adapters, the SW defineable pin 1 is set when the optics
916 /*
917 * For these adapters, the SW defineable pin 1 is set when the optics
842 * detect a signal. If we have a signal, then poll for a "Link-Up"
843 * indication.
844 */
918 * detect a signal. If we have a signal, then poll for a "Link-Up"
919 * indication.
920 */
845 if (hw->media_type == e1000_media_type_internal_serdes ||
921 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
846 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
847 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
848 } else {
849 DEBUGOUT("No signal detected\n");
850 }
851
852out:
853 return ret_val;
854}
855
856/**
857 * e1000_config_collision_dist_generic - Configure collision distance
858 * @hw: pointer to the HW structure
859 *
860 * Configures the collision distance to the default value and is used
861 * during link setup. Currently no func pointer exists and all
862 * implementations are handled in the generic version of this function.
863 **/
922 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
923 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
924 } else {
925 DEBUGOUT("No signal detected\n");
926 }
927
928out:
929 return ret_val;
930}
931
932/**
933 * e1000_config_collision_dist_generic - Configure collision distance
934 * @hw: pointer to the HW structure
935 *
936 * Configures the collision distance to the default value and is used
937 * during link setup. Currently no func pointer exists and all
938 * implementations are handled in the generic version of this function.
939 **/
864void
865e1000_config_collision_dist_generic(struct e1000_hw *hw)
940void e1000_config_collision_dist_generic(struct e1000_hw *hw)
866{
867 u32 tctl;
868
869 DEBUGFUNC("e1000_config_collision_dist_generic");
870
871 tctl = E1000_READ_REG(hw, E1000_TCTL);
872
873 tctl &= ~E1000_TCTL_COLD;

--- 5 unchanged lines hidden (view full) ---

879
880/**
881 * e1000_poll_fiber_serdes_link_generic - Poll for link up
882 * @hw: pointer to the HW structure
883 *
884 * Polls for link up by reading the status register, if link fails to come
885 * up with auto-negotiation, then the link is forced if a signal is detected.
886 **/
941{
942 u32 tctl;
943
944 DEBUGFUNC("e1000_config_collision_dist_generic");
945
946 tctl = E1000_READ_REG(hw, E1000_TCTL);
947
948 tctl &= ~E1000_TCTL_COLD;

--- 5 unchanged lines hidden (view full) ---

954
955/**
956 * e1000_poll_fiber_serdes_link_generic - Poll for link up
957 * @hw: pointer to the HW structure
958 *
959 * Polls for link up by reading the status register, if link fails to come
960 * up with auto-negotiation, then the link is forced if a signal is detected.
961 **/
887s32
888e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
962s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
889{
890 struct e1000_mac_info *mac = &hw->mac;
891 u32 i, status;
892 s32 ret_val = E1000_SUCCESS;
893
894 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
895
963{
964 struct e1000_mac_info *mac = &hw->mac;
965 u32 i, status;
966 s32 ret_val = E1000_SUCCESS;
967
968 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
969
896 /* If we have a signal (the cable is plugged in, or assumed true for
970 /*
971 * If we have a signal (the cable is plugged in, or assumed true for
897 * serdes media) then poll for a "Link-Up" indication in the Device
898 * Status Register. Time-out if a link isn't seen in 500 milliseconds
899 * seconds (Auto-negotiation should complete in less than 500
900 * milliseconds even if the other end is doing it in SW).
901 */
902 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
903 msec_delay(10);
904 status = E1000_READ_REG(hw, E1000_STATUS);
905 if (status & E1000_STATUS_LU)
906 break;
907 }
908 if (i == FIBER_LINK_UP_LIMIT) {
909 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
910 mac->autoneg_failed = 1;
972 * serdes media) then poll for a "Link-Up" indication in the Device
973 * Status Register. Time-out if a link isn't seen in 500 milliseconds
974 * seconds (Auto-negotiation should complete in less than 500
975 * milliseconds even if the other end is doing it in SW).
976 */
977 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
978 msec_delay(10);
979 status = E1000_READ_REG(hw, E1000_STATUS);
980 if (status & E1000_STATUS_LU)
981 break;
982 }
983 if (i == FIBER_LINK_UP_LIMIT) {
984 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
985 mac->autoneg_failed = 1;
911 /* AutoNeg failed to achieve a link, so we'll call
986 /*
987 * AutoNeg failed to achieve a link, so we'll call
912 * mac->check_for_link. This routine will force the
913 * link up if we detect a signal. This will allow us to
914 * communicate with non-autonegotiating link partners.
915 */
916 ret_val = e1000_check_for_link(hw);
917 if (ret_val) {
918 DEBUGOUT("Error while checking for link\n");
919 goto out;

--- 10 unchanged lines hidden (view full) ---

930
931/**
932 * e1000_commit_fc_settings_generic - Configure flow control
933 * @hw: pointer to the HW structure
934 *
935 * Write the flow control settings to the Transmit Config Word Register (TXCW)
936 * base on the flow control settings in e1000_mac_info.
937 **/
988 * mac->check_for_link. This routine will force the
989 * link up if we detect a signal. This will allow us to
990 * communicate with non-autonegotiating link partners.
991 */
992 ret_val = e1000_check_for_link(hw);
993 if (ret_val) {
994 DEBUGOUT("Error while checking for link\n");
995 goto out;

--- 10 unchanged lines hidden (view full) ---

1006
1007/**
1008 * e1000_commit_fc_settings_generic - Configure flow control
1009 * @hw: pointer to the HW structure
1010 *
1011 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1012 * base on the flow control settings in e1000_mac_info.
1013 **/
938s32
939e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1014s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
940{
941 struct e1000_mac_info *mac = &hw->mac;
942 u32 txcw;
943 s32 ret_val = E1000_SUCCESS;
944
945 DEBUGFUNC("e1000_commit_fc_settings_generic");
946
1015{
1016 struct e1000_mac_info *mac = &hw->mac;
1017 u32 txcw;
1018 s32 ret_val = E1000_SUCCESS;
1019
1020 DEBUGFUNC("e1000_commit_fc_settings_generic");
1021
947 /* Check for a software override of the flow control settings, and
1022 /*
1023 * Check for a software override of the flow control settings, and
948 * setup the device accordingly. If auto-negotiation is enabled, then
949 * software will have to set the "PAUSE" bits to the correct value in
950 * the Transmit Config Word Register (TXCW) and re-start auto-
951 * negotiation. However, if auto-negotiation is disabled, then
952 * software will have to manually configure the two flow control enable
953 * bits in the CTRL register.
954 *
955 * The possible values of the "fc" parameter are:
956 * 0: Flow control is completely disabled
957 * 1: Rx flow control is enabled (we can receive pause frames,
958 * but not send pause frames).
959 * 2: Tx flow control is enabled (we can send pause frames but we
960 * do not support receiving pause frames).
1024 * setup the device accordingly. If auto-negotiation is enabled, then
1025 * software will have to set the "PAUSE" bits to the correct value in
1026 * the Transmit Config Word Register (TXCW) and re-start auto-
1027 * negotiation. However, if auto-negotiation is disabled, then
1028 * software will have to manually configure the two flow control enable
1029 * bits in the CTRL register.
1030 *
1031 * The possible values of the "fc" parameter are:
1032 * 0: Flow control is completely disabled
1033 * 1: Rx flow control is enabled (we can receive pause frames,
1034 * but not send pause frames).
1035 * 2: Tx flow control is enabled (we can send pause frames but we
1036 * do not support receiving pause frames).
961 * 3: Both Rx and TX flow control (symmetric) are enabled.
1037 * 3: Both Rx and Tx flow control (symmetric) are enabled.
962 */
1038 */
963 switch (mac->fc) {
1039 switch (hw->fc.type) {
964 case e1000_fc_none:
965 /* Flow control completely disabled by a software over-ride. */
966 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
967 break;
968 case e1000_fc_rx_pause:
1040 case e1000_fc_none:
1041 /* Flow control completely disabled by a software over-ride. */
1042 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1043 break;
1044 case e1000_fc_rx_pause:
969 /* RX Flow control is enabled and TX Flow control is disabled
1045 /*
1046 * Rx Flow control is enabled and Tx Flow control is disabled
970 * by a software over-ride. Since there really isn't a way to
1047 * by a software over-ride. Since there really isn't a way to
971 * advertise that we are capable of RX Pause ONLY, we will
1048 * advertise that we are capable of Rx Pause ONLY, we will
972 * advertise that we support both symmetric and asymmetric RX
973 * PAUSE. Later, we will disable the adapter's ability to send
974 * PAUSE frames.
975 */
976 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
977 break;
978 case e1000_fc_tx_pause:
1049 * advertise that we support both symmetric and asymmetric RX
1050 * PAUSE. Later, we will disable the adapter's ability to send
1051 * PAUSE frames.
1052 */
1053 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1054 break;
1055 case e1000_fc_tx_pause:
979 /* TX Flow control is enabled, and RX Flow control is disabled,
1056 /*
1057 * Tx Flow control is enabled, and Rx Flow control is disabled,
980 * by a software over-ride.
981 */
982 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
983 break;
984 case e1000_fc_full:
1058 * by a software over-ride.
1059 */
1060 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1061 break;
1062 case e1000_fc_full:
985 /* Flow control (both RX and TX) is enabled by a software
1063 /*
1064 * Flow control (both Rx and Tx) is enabled by a software
986 * over-ride.
987 */
988 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
989 break;
990 default:
991 DEBUGOUT("Flow control param set incorrectly\n");
992 ret_val = -E1000_ERR_CONFIG;
993 goto out;

--- 10 unchanged lines hidden (view full) ---

1004/**
1005 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1006 * @hw: pointer to the HW structure
1007 *
1008 * Sets the flow control high/low threshold (watermark) registers. If
1009 * flow control XON frame transmission is enabled, then set XON frame
1010 * tansmission as well.
1011 **/
1065 * over-ride.
1066 */
1067 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1068 break;
1069 default:
1070 DEBUGOUT("Flow control param set incorrectly\n");
1071 ret_val = -E1000_ERR_CONFIG;
1072 goto out;

--- 10 unchanged lines hidden (view full) ---

1083/**
1084 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1085 * @hw: pointer to the HW structure
1086 *
1087 * Sets the flow control high/low threshold (watermark) registers. If
1088 * flow control XON frame transmission is enabled, then set XON frame
1089 * tansmission as well.
1090 **/
1012s32
1013e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1091s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1014{
1092{
1015 struct e1000_mac_info *mac = &hw->mac;
1016 s32 ret_val = E1000_SUCCESS;
1017 u32 fcrtl = 0, fcrth = 0;
1018
1019 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1020
1093 s32 ret_val = E1000_SUCCESS;
1094 u32 fcrtl = 0, fcrth = 0;
1095
1096 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1097
1021 /* Set the flow control receive threshold registers. Normally,
1098 /*
1099 * Set the flow control receive threshold registers. Normally,
1022 * these registers will be set to a default threshold that may be
1023 * adjusted later by the driver's runtime code. However, if the
1024 * ability to transmit pause frames is not enabled, then these
1025 * registers will be set to 0.
1026 */
1100 * these registers will be set to a default threshold that may be
1101 * adjusted later by the driver's runtime code. However, if the
1102 * ability to transmit pause frames is not enabled, then these
1103 * registers will be set to 0.
1104 */
1027 if (mac->fc & e1000_fc_tx_pause) {
1028 /* We need to set up the Receive Threshold high and low water
1105 if (hw->fc.type & e1000_fc_tx_pause) {
1106 /*
1107 * We need to set up the Receive Threshold high and low water
1029 * marks as well as (optionally) enabling the transmission of
1030 * XON frames.
1031 */
1108 * marks as well as (optionally) enabling the transmission of
1109 * XON frames.
1110 */
1032 fcrtl = mac->fc_low_water;
1033 if (mac->fc_send_xon)
1111 fcrtl = hw->fc.low_water;
1112 if (hw->fc.send_xon)
1034 fcrtl |= E1000_FCRTL_XONE;
1035
1113 fcrtl |= E1000_FCRTL_XONE;
1114
1036 fcrth = mac->fc_high_water;
1115 fcrth = hw->fc.high_water;
1037 }
1038 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1039 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1040
1041 return ret_val;
1042}
1043
1044/**
1045 * e1000_set_default_fc_generic - Set flow control default values
1046 * @hw: pointer to the HW structure
1047 *
1048 * Read the EEPROM for the default values for flow control and store the
1049 * values.
1050 **/
1116 }
1117 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1118 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1119
1120 return ret_val;
1121}
1122
1123/**
1124 * e1000_set_default_fc_generic - Set flow control default values
1125 * @hw: pointer to the HW structure
1126 *
1127 * Read the EEPROM for the default values for flow control and store the
1128 * values.
1129 **/
1051s32
1052e1000_set_default_fc_generic(struct e1000_hw *hw)
1130s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1053{
1131{
1054 struct e1000_mac_info *mac = &hw->mac;
1055 s32 ret_val = E1000_SUCCESS;
1056 u16 nvm_data;
1057
1058 DEBUGFUNC("e1000_set_default_fc_generic");
1059
1132 s32 ret_val = E1000_SUCCESS;
1133 u16 nvm_data;
1134
1135 DEBUGFUNC("e1000_set_default_fc_generic");
1136
1060 if (mac->fc != e1000_fc_default)
1061 goto out;
1062
1063 /* Read and store word 0x0F of the EEPROM. This word contains bits
1137 /*
1138 * Read and store word 0x0F of the EEPROM. This word contains bits
1064 * that determine the hardware's default PAUSE (flow control) mode,
1065 * a bit that determines whether the HW defaults to enabling or
1066 * disabling auto-negotiation, and the direction of the
1067 * SW defined pins. If there is no SW over-ride of the flow
1068 * control setting, then the variable hw->fc will
1069 * be initialized based on a value in the EEPROM.
1070 */
1071 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1072
1073 if (ret_val) {
1074 DEBUGOUT("NVM Read Error\n");
1075 goto out;
1076 }
1077
1078 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1139 * that determine the hardware's default PAUSE (flow control) mode,
1140 * a bit that determines whether the HW defaults to enabling or
1141 * disabling auto-negotiation, and the direction of the
1142 * SW defined pins. If there is no SW over-ride of the flow
1143 * control setting, then the variable hw->fc will
1144 * be initialized based on a value in the EEPROM.
1145 */
1146 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1147
1148 if (ret_val) {
1149 DEBUGOUT("NVM Read Error\n");
1150 goto out;
1151 }
1152
1153 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1079 mac->fc = e1000_fc_none;
1154 hw->fc.type = e1000_fc_none;
1080 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1081 NVM_WORD0F_ASM_DIR)
1155 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1156 NVM_WORD0F_ASM_DIR)
1082 mac->fc = e1000_fc_tx_pause;
1157 hw->fc.type = e1000_fc_tx_pause;
1083 else
1158 else
1084 mac->fc = e1000_fc_full;
1159 hw->fc.type = e1000_fc_full;
1085
1086out:
1087 return ret_val;
1088}
1089
1090/**
1091 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1092 * @hw: pointer to the HW structure
1093 *
1094 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1095 * device control register to reflect the adapter settings. TFCE and RFCE
1096 * need to be explicitly set by software when a copper PHY is used because
1097 * autonegotiation is managed by the PHY rather than the MAC. Software must
1098 * also configure these bits when link is forced on a fiber connection.
1099 **/
1160
1161out:
1162 return ret_val;
1163}
1164
1165/**
1166 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1167 * @hw: pointer to the HW structure
1168 *
1169 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1170 * device control register to reflect the adapter settings. TFCE and RFCE
1171 * need to be explicitly set by software when a copper PHY is used because
1172 * autonegotiation is managed by the PHY rather than the MAC. Software must
1173 * also configure these bits when link is forced on a fiber connection.
1174 **/
1100s32
1101e1000_force_mac_fc_generic(struct e1000_hw *hw)
1175s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1102{
1176{
1103 struct e1000_mac_info *mac = &hw->mac;
1104 u32 ctrl;
1105 s32 ret_val = E1000_SUCCESS;
1106
1107 DEBUGFUNC("e1000_force_mac_fc_generic");
1108
1109 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1110
1177 u32 ctrl;
1178 s32 ret_val = E1000_SUCCESS;
1179
1180 DEBUGFUNC("e1000_force_mac_fc_generic");
1181
1182 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1183
1111 /* Because we didn't get link via the internal auto-negotiation
1184 /*
1185 * Because we didn't get link via the internal auto-negotiation
1112 * mechanism (we either forced link or we got link via PHY
1113 * auto-neg), we have to manually enable/disable transmit an
1114 * receive flow control.
1115 *
1116 * The "Case" statement below enables/disable flow control
1186 * mechanism (we either forced link or we got link via PHY
1187 * auto-neg), we have to manually enable/disable transmit an
1188 * receive flow control.
1189 *
1190 * The "Case" statement below enables/disable flow control
1117 * according to the "mac->fc" parameter.
1191 * according to the "hw->fc.type" parameter.
1118 *
1119 * The possible values of the "fc" parameter are:
1120 * 0: Flow control is completely disabled
1121 * 1: Rx flow control is enabled (we can receive pause
1122 * frames but not send pause frames).
1123 * 2: Tx flow control is enabled (we can send pause frames
1124 * frames but we do not receive pause frames).
1192 *
1193 * The possible values of the "fc" parameter are:
1194 * 0: Flow control is completely disabled
1195 * 1: Rx flow control is enabled (we can receive pause
1196 * frames but not send pause frames).
1197 * 2: Tx flow control is enabled (we can send pause frames
1198 * frames but we do not receive pause frames).
1125 * 3: Both Rx and TX flow control (symmetric) is enabled.
1199 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1126 * other: No other values should be possible at this point.
1127 */
1200 * other: No other values should be possible at this point.
1201 */
1128 DEBUGOUT1("mac->fc = %u\n", mac->fc);
1202 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type);
1129
1203
1130 switch (mac->fc) {
1204 switch (hw->fc.type) {
1131 case e1000_fc_none:
1132 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1133 break;
1134 case e1000_fc_rx_pause:
1135 ctrl &= (~E1000_CTRL_TFCE);
1136 ctrl |= E1000_CTRL_RFCE;
1137 break;
1138 case e1000_fc_tx_pause:

--- 20 unchanged lines hidden (view full) ---

1159 * @hw: pointer to the HW structure
1160 *
1161 * Checks the status of auto-negotiation after link up to ensure that the
1162 * speed and duplex were not forced. If the link needed to be forced, then
1163 * flow control needs to be forced also. If auto-negotiation is enabled
1164 * and did not fail, then we configure flow control based on our link
1165 * partner.
1166 **/
1205 case e1000_fc_none:
1206 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1207 break;
1208 case e1000_fc_rx_pause:
1209 ctrl &= (~E1000_CTRL_TFCE);
1210 ctrl |= E1000_CTRL_RFCE;
1211 break;
1212 case e1000_fc_tx_pause:

--- 20 unchanged lines hidden (view full) ---

1233 * @hw: pointer to the HW structure
1234 *
1235 * Checks the status of auto-negotiation after link up to ensure that the
1236 * speed and duplex were not forced. If the link needed to be forced, then
1237 * flow control needs to be forced also. If auto-negotiation is enabled
1238 * and did not fail, then we configure flow control based on our link
1239 * partner.
1240 **/
1167s32
1168e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1241s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1169{
1170 struct e1000_mac_info *mac = &hw->mac;
1171 s32 ret_val = E1000_SUCCESS;
1172 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1173 u16 speed, duplex;
1174
1175 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1176
1242{
1243 struct e1000_mac_info *mac = &hw->mac;
1244 s32 ret_val = E1000_SUCCESS;
1245 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1246 u16 speed, duplex;
1247
1248 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1249
1177 /* Check for the case where we have fiber media and auto-neg failed
1250 /*
1251 * Check for the case where we have fiber media and auto-neg failed
1178 * so we had to force link. In this case, we need to force the
1179 * configuration of the MAC to match the "fc" parameter.
1180 */
1181 if (mac->autoneg_failed) {
1252 * so we had to force link. In this case, we need to force the
1253 * configuration of the MAC to match the "fc" parameter.
1254 */
1255 if (mac->autoneg_failed) {
1182 if (hw->media_type == e1000_media_type_fiber ||
1183 hw->media_type == e1000_media_type_internal_serdes)
1256 if (hw->phy.media_type == e1000_media_type_fiber ||
1257 hw->phy.media_type == e1000_media_type_internal_serdes)
1184 ret_val = e1000_force_mac_fc_generic(hw);
1185 } else {
1258 ret_val = e1000_force_mac_fc_generic(hw);
1259 } else {
1186 if (hw->media_type == e1000_media_type_copper)
1260 if (hw->phy.media_type == e1000_media_type_copper)
1187 ret_val = e1000_force_mac_fc_generic(hw);
1188 }
1189
1190 if (ret_val) {
1191 DEBUGOUT("Error forcing flow control settings\n");
1192 goto out;
1193 }
1194
1261 ret_val = e1000_force_mac_fc_generic(hw);
1262 }
1263
1264 if (ret_val) {
1265 DEBUGOUT("Error forcing flow control settings\n");
1266 goto out;
1267 }
1268
1195 /* Check for the case where we have copper media and auto-neg is
1269 /*
1270 * Check for the case where we have copper media and auto-neg is
1196 * enabled. In this case, we need to check and see if Auto-Neg
1197 * has completed, and if so, how the PHY and link partner has
1198 * flow control configured.
1199 */
1271 * enabled. In this case, we need to check and see if Auto-Neg
1272 * has completed, and if so, how the PHY and link partner has
1273 * flow control configured.
1274 */
1200 if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) {
1201 /* Read the MII Status Register and check to see if AutoNeg
1275 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1276 /*
1277 * Read the MII Status Register and check to see if AutoNeg
1202 * has completed. We read this twice because this reg has
1203 * some "sticky" (latched) bits.
1204 */
1205 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1206 if (ret_val)
1207 goto out;
1208 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1209 if (ret_val)
1210 goto out;
1211
1212 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1213 DEBUGOUT("Copper PHY and Auto Neg "
1214 "has not completed.\n");
1215 goto out;
1216 }
1217
1278 * has completed. We read this twice because this reg has
1279 * some "sticky" (latched) bits.
1280 */
1281 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1282 if (ret_val)
1283 goto out;
1284 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1285 if (ret_val)
1286 goto out;
1287
1288 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1289 DEBUGOUT("Copper PHY and Auto Neg "
1290 "has not completed.\n");
1291 goto out;
1292 }
1293
1218 /* The AutoNeg process has completed, so we now need to
1294 /*
1295 * The AutoNeg process has completed, so we now need to
1219 * read both the Auto Negotiation Advertisement
1220 * Register (Address 4) and the Auto_Negotiation Base
1221 * Page Ability Register (Address 5) to determine how
1222 * flow control was negotiated.
1223 */
1224 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1225 &mii_nway_adv_reg);
1226 if (ret_val)
1227 goto out;
1228 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1229 &mii_nway_lp_ability_reg);
1230 if (ret_val)
1231 goto out;
1232
1296 * read both the Auto Negotiation Advertisement
1297 * Register (Address 4) and the Auto_Negotiation Base
1298 * Page Ability Register (Address 5) to determine how
1299 * flow control was negotiated.
1300 */
1301 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1302 &mii_nway_adv_reg);
1303 if (ret_val)
1304 goto out;
1305 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1306 &mii_nway_lp_ability_reg);
1307 if (ret_val)
1308 goto out;
1309
1233 /* Two bits in the Auto Negotiation Advertisement Register
1310 /*
1311 * Two bits in the Auto Negotiation Advertisement Register
1234 * (Address 4) and two bits in the Auto Negotiation Base
1235 * Page Ability Register (Address 5) determine flow control
1236 * for both the PHY and the link partner. The following
1237 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1238 * 1999, describes these PAUSE resolution bits and how flow
1239 * control is determined based upon these settings.
1240 * NOTE: DC = Don't Care
1241 *

--- 4 unchanged lines hidden (view full) ---

1246 * 0 | 1 | 0 | DC | e1000_fc_none
1247 * 0 | 1 | 1 | 0 | e1000_fc_none
1248 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1249 * 1 | 0 | 0 | DC | e1000_fc_none
1250 * 1 | DC | 1 | DC | e1000_fc_full
1251 * 1 | 1 | 0 | 0 | e1000_fc_none
1252 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1253 *
1312 * (Address 4) and two bits in the Auto Negotiation Base
1313 * Page Ability Register (Address 5) determine flow control
1314 * for both the PHY and the link partner. The following
1315 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1316 * 1999, describes these PAUSE resolution bits and how flow
1317 * control is determined based upon these settings.
1318 * NOTE: DC = Don't Care
1319 *

--- 4 unchanged lines hidden (view full) ---

1324 * 0 | 1 | 0 | DC | e1000_fc_none
1325 * 0 | 1 | 1 | 0 | e1000_fc_none
1326 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1327 * 1 | 0 | 0 | DC | e1000_fc_none
1328 * 1 | DC | 1 | DC | e1000_fc_full
1329 * 1 | 1 | 0 | 0 | e1000_fc_none
1330 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1331 *
1254 */
1255 /* Are both PAUSE bits set to 1? If so, this implies
1332 * Are both PAUSE bits set to 1? If so, this implies
1256 * Symmetric Flow Control is enabled at both ends. The
1257 * ASM_DIR bits are irrelevant per the spec.
1258 *
1259 * For Symmetric Flow Control:
1260 *
1261 * LOCAL DEVICE | LINK PARTNER
1262 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1263 *-------|---------|-------|---------|--------------------
1264 * 1 | DC | 1 | DC | E1000_fc_full
1265 *
1266 */
1267 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1268 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1333 * Symmetric Flow Control is enabled at both ends. The
1334 * ASM_DIR bits are irrelevant per the spec.
1335 *
1336 * For Symmetric Flow Control:
1337 *
1338 * LOCAL DEVICE | LINK PARTNER
1339 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1340 *-------|---------|-------|---------|--------------------
1341 * 1 | DC | 1 | DC | E1000_fc_full
1342 *
1343 */
1344 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1345 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1269 /* Now we need to check if the user selected RX ONLY
1346 /*
1347 * Now we need to check if the user selected Rx ONLY
1270 * of pause frames. In this case, we had to advertise
1271 * FULL flow control because we could not advertise RX
1272 * ONLY. Hence, we must now check to see if we need to
1273 * turn OFF the TRANSMISSION of PAUSE frames.
1274 */
1348 * of pause frames. In this case, we had to advertise
1349 * FULL flow control because we could not advertise RX
1350 * ONLY. Hence, we must now check to see if we need to
1351 * turn OFF the TRANSMISSION of PAUSE frames.
1352 */
1275 if (mac->original_fc == e1000_fc_full) {
1276 mac->fc = e1000_fc_full;
1353 if (hw->fc.original_type == e1000_fc_full) {
1354 hw->fc.type = e1000_fc_full;
1277 DEBUGOUT("Flow Control = FULL.\r\n");
1278 } else {
1355 DEBUGOUT("Flow Control = FULL.\r\n");
1356 } else {
1279 mac->fc = e1000_fc_rx_pause;
1357 hw->fc.type = e1000_fc_rx_pause;
1280 DEBUGOUT("Flow Control = "
1281 "RX PAUSE frames only.\r\n");
1282 }
1283 }
1358 DEBUGOUT("Flow Control = "
1359 "RX PAUSE frames only.\r\n");
1360 }
1361 }
1284 /* For receiving PAUSE frames ONLY.
1362 /*
1363 * For receiving PAUSE frames ONLY.
1285 *
1286 * LOCAL DEVICE | LINK PARTNER
1287 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1288 *-------|---------|-------|---------|--------------------
1289 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1364 *
1365 * LOCAL DEVICE | LINK PARTNER
1366 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1367 *-------|---------|-------|---------|--------------------
1368 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1290 *
1291 */
1292 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1293 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1294 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1295 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1369 */
1370 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1371 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1372 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1373 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1296 mac->fc = e1000_fc_tx_pause;
1374 hw->fc.type = e1000_fc_tx_pause;
1297 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1298 }
1375 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1376 }
1299 /* For transmitting PAUSE frames ONLY.
1377 /*
1378 * For transmitting PAUSE frames ONLY.
1300 *
1301 * LOCAL DEVICE | LINK PARTNER
1302 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1303 *-------|---------|-------|---------|--------------------
1304 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1379 *
1380 * LOCAL DEVICE | LINK PARTNER
1381 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1382 *-------|---------|-------|---------|--------------------
1383 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1305 *
1306 */
1307 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1308 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1309 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1310 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1384 */
1385 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1386 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1387 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1388 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1311 mac->fc = e1000_fc_rx_pause;
1389 hw->fc.type = e1000_fc_rx_pause;
1312 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1390 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1313 }
1314 /* Per the IEEE spec, at this point flow control should be
1315 * disabled. However, we want to consider that we could
1316 * be connected to a legacy switch that doesn't advertise
1317 * desired flow control, but can be forced on the link
1318 * partner. So if we advertised no flow control, that is
1319 * what we will resolve to. If we advertised some kind of
1320 * receive capability (Rx Pause Only or Full Flow Control)
1321 * and the link partner advertised none, we will configure
1322 * ourselves to enable Rx Flow Control only. We can do
1323 * this safely for two reasons: If the link partner really
1324 * didn't want flow control enabled, and we enable Rx, no
1325 * harm done since we won't be receiving any PAUSE frames
1326 * anyway. If the intent on the link partner was to have
1327 * flow control enabled, then by us enabling RX only, we
1328 * can at least receive pause frames and process them.
1329 * This is a good idea because in most cases, since we are
1330 * predominantly a server NIC, more times than not we will
1331 * be asked to delay transmission of packets than asking
1332 * our link partner to pause transmission of frames.
1333 */
1334 else if ((mac->original_fc == e1000_fc_none ||
1335 mac->original_fc == e1000_fc_tx_pause) ||
1336 mac->fc_strict_ieee) {
1337 mac->fc = e1000_fc_none;
1338 DEBUGOUT("Flow Control = NONE.\r\n");
1339 } else {
1391 } else {
1340 mac->fc = e1000_fc_rx_pause;
1341 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1392 /*
1393 * Per the IEEE spec, at this point flow control
1394 * should be disabled.
1395 */
1396 hw->fc.type = e1000_fc_none;
1397 DEBUGOUT("Flow Control = NONE.\r\n");
1342 }
1343
1398 }
1399
1344 /* Now we need to do one last check... If we auto-
1400 /*
1401 * Now we need to do one last check... If we auto-
1345 * negotiated to HALF DUPLEX, flow control should not be
1346 * enabled per IEEE 802.3 spec.
1347 */
1348 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1349 if (ret_val) {
1350 DEBUGOUT("Error getting link speed and duplex\n");
1351 goto out;
1352 }
1353
1354 if (duplex == HALF_DUPLEX)
1402 * negotiated to HALF DUPLEX, flow control should not be
1403 * enabled per IEEE 802.3 spec.
1404 */
1405 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1406 if (ret_val) {
1407 DEBUGOUT("Error getting link speed and duplex\n");
1408 goto out;
1409 }
1410
1411 if (duplex == HALF_DUPLEX)
1355 mac->fc = e1000_fc_none;
1412 hw->fc.type = e1000_fc_none;
1356
1413
1357 /* Now we call a subroutine to actually force the MAC
1414 /*
1415 * Now we call a subroutine to actually force the MAC
1358 * controller to use the correct flow control settings.
1359 */
1360 ret_val = e1000_force_mac_fc_generic(hw);
1361 if (ret_val) {
1362 DEBUGOUT("Error forcing flow control settings\n");
1363 goto out;
1364 }
1365 }

--- 6 unchanged lines hidden (view full) ---

1372 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex
1373 * @hw: pointer to the HW structure
1374 * @speed: stores the current speed
1375 * @duplex: stores the current duplex
1376 *
1377 * Read the status register for the current speed/duplex and store the current
1378 * speed and duplex for copper connections.
1379 **/
1416 * controller to use the correct flow control settings.
1417 */
1418 ret_val = e1000_force_mac_fc_generic(hw);
1419 if (ret_val) {
1420 DEBUGOUT("Error forcing flow control settings\n");
1421 goto out;
1422 }
1423 }

--- 6 unchanged lines hidden (view full) ---

1430 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex
1431 * @hw: pointer to the HW structure
1432 * @speed: stores the current speed
1433 * @duplex: stores the current duplex
1434 *
1435 * Read the status register for the current speed/duplex and store the current
1436 * speed and duplex for copper connections.
1437 **/
1380s32
1381e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1382 u16 *duplex)
1438s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1439 u16 *duplex)
1383{
1384 u32 status;
1385
1386 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1387
1388 status = E1000_READ_REG(hw, E1000_STATUS);
1389 if (status & E1000_STATUS_SPEED_1000) {
1390 *speed = SPEED_1000;

--- 21 unchanged lines hidden (view full) ---

1412 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex
1413 * @hw: pointer to the HW structure
1414 * @speed: stores the current speed
1415 * @duplex: stores the current duplex
1416 *
1417 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1418 * for fiber/serdes links.
1419 **/
1440{
1441 u32 status;
1442
1443 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1444
1445 status = E1000_READ_REG(hw, E1000_STATUS);
1446 if (status & E1000_STATUS_SPEED_1000) {
1447 *speed = SPEED_1000;

--- 21 unchanged lines hidden (view full) ---

1469 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex
1470 * @hw: pointer to the HW structure
1471 * @speed: stores the current speed
1472 * @duplex: stores the current duplex
1473 *
1474 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1475 * for fiber/serdes links.
1476 **/
1420s32
1421e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, u16 *speed,
1422 u16 *duplex)
1477s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1478 u16 *speed, u16 *duplex)
1423{
1424 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1479{
1480 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1481 UNREFERENCED_PARAMETER(hw);
1425
1426 *speed = SPEED_1000;
1427 *duplex = FULL_DUPLEX;
1428
1429 return E1000_SUCCESS;
1430}
1431
1432/**
1433 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1434 * @hw: pointer to the HW structure
1435 *
1436 * Acquire the HW semaphore to access the PHY or NVM
1437 **/
1482
1483 *speed = SPEED_1000;
1484 *duplex = FULL_DUPLEX;
1485
1486 return E1000_SUCCESS;
1487}
1488
1489/**
1490 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1491 * @hw: pointer to the HW structure
1492 *
1493 * Acquire the HW semaphore to access the PHY or NVM
1494 **/
1438s32
1439e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1495s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1440{
1441 u32 swsm;
1442 s32 ret_val = E1000_SUCCESS;
1443 s32 timeout = hw->nvm.word_size + 1;
1444 s32 i = 0;
1445
1446 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1447

--- 38 unchanged lines hidden (view full) ---

1486}
1487
1488/**
1489 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1490 * @hw: pointer to the HW structure
1491 *
1492 * Release hardware semaphore used to access the PHY or NVM
1493 **/
1496{
1497 u32 swsm;
1498 s32 ret_val = E1000_SUCCESS;
1499 s32 timeout = hw->nvm.word_size + 1;
1500 s32 i = 0;
1501
1502 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1503

--- 38 unchanged lines hidden (view full) ---

1542}
1543
1544/**
1545 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1546 * @hw: pointer to the HW structure
1547 *
1548 * Release hardware semaphore used to access the PHY or NVM
1549 **/
1494void
1495e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1550void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1496{
1497 u32 swsm;
1498
1499 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1500
1501 swsm = E1000_READ_REG(hw, E1000_SWSM);
1502
1503 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1504
1505 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1506}
1507
1508/**
1509 * e1000_get_auto_rd_done_generic - Check for auto read completion
1510 * @hw: pointer to the HW structure
1511 *
1512 * Check EEPROM for Auto Read done bit.
1513 **/
1551{
1552 u32 swsm;
1553
1554 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1555
1556 swsm = E1000_READ_REG(hw, E1000_SWSM);
1557
1558 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1559
1560 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1561}
1562
1563/**
1564 * e1000_get_auto_rd_done_generic - Check for auto read completion
1565 * @hw: pointer to the HW structure
1566 *
1567 * Check EEPROM for Auto Read done bit.
1568 **/
1514s32
1515e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1569s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1516{
1517 s32 i = 0;
1518 s32 ret_val = E1000_SUCCESS;
1519
1520 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1521
1522 while (i < AUTO_READ_DONE_TIMEOUT) {
1523 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)

--- 15 unchanged lines hidden (view full) ---

1539/**
1540 * e1000_valid_led_default_generic - Verify a valid default LED config
1541 * @hw: pointer to the HW structure
1542 * @data: pointer to the NVM (EEPROM)
1543 *
1544 * Read the EEPROM for the current default LED configuration. If the
1545 * LED configuration is not valid, set to a valid LED configuration.
1546 **/
1570{
1571 s32 i = 0;
1572 s32 ret_val = E1000_SUCCESS;
1573
1574 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1575
1576 while (i < AUTO_READ_DONE_TIMEOUT) {
1577 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)

--- 15 unchanged lines hidden (view full) ---

1593/**
1594 * e1000_valid_led_default_generic - Verify a valid default LED config
1595 * @hw: pointer to the HW structure
1596 * @data: pointer to the NVM (EEPROM)
1597 *
1598 * Read the EEPROM for the current default LED configuration. If the
1599 * LED configuration is not valid, set to a valid LED configuration.
1600 **/
1547s32
1548e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1601s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1549{
1550 s32 ret_val;
1551
1552 DEBUGFUNC("e1000_valid_led_default_generic");
1553
1554 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1555 if (ret_val) {
1556 DEBUGOUT("NVM Read Error\n");

--- 7 unchanged lines hidden (view full) ---

1564 return ret_val;
1565}
1566
1567/**
1568 * e1000_id_led_init_generic -
1569 * @hw: pointer to the HW structure
1570 *
1571 **/
1602{
1603 s32 ret_val;
1604
1605 DEBUGFUNC("e1000_valid_led_default_generic");
1606
1607 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1608 if (ret_val) {
1609 DEBUGOUT("NVM Read Error\n");

--- 7 unchanged lines hidden (view full) ---

1617 return ret_val;
1618}
1619
1620/**
1621 * e1000_id_led_init_generic -
1622 * @hw: pointer to the HW structure
1623 *
1624 **/
1572s32
1573e1000_id_led_init_generic(struct e1000_hw * hw)
1625s32 e1000_id_led_init_generic(struct e1000_hw * hw)
1574{
1575 struct e1000_mac_info *mac = &hw->mac;
1576 s32 ret_val;
1577 const u32 ledctl_mask = 0x000000FF;
1578 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1579 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1580 u16 data, i, temp;
1581 const u16 led_mask = 0x0F;

--- 52 unchanged lines hidden (view full) ---

1634
1635/**
1636 * e1000_setup_led_generic - Configures SW controllable LED
1637 * @hw: pointer to the HW structure
1638 *
1639 * This prepares the SW controllable LED for use and saves the current state
1640 * of the LED so it can be later restored.
1641 **/
1626{
1627 struct e1000_mac_info *mac = &hw->mac;
1628 s32 ret_val;
1629 const u32 ledctl_mask = 0x000000FF;
1630 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1631 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1632 u16 data, i, temp;
1633 const u16 led_mask = 0x0F;

--- 52 unchanged lines hidden (view full) ---

1686
1687/**
1688 * e1000_setup_led_generic - Configures SW controllable LED
1689 * @hw: pointer to the HW structure
1690 *
1691 * This prepares the SW controllable LED for use and saves the current state
1692 * of the LED so it can be later restored.
1693 **/
1642s32
1643e1000_setup_led_generic(struct e1000_hw *hw)
1694s32 e1000_setup_led_generic(struct e1000_hw *hw)
1644{
1645 u32 ledctl;
1646 s32 ret_val = E1000_SUCCESS;
1647
1648 DEBUGFUNC("e1000_setup_led_generic");
1649
1650 if (hw->func.setup_led != e1000_setup_led_generic) {
1651 ret_val = -E1000_ERR_CONFIG;
1652 goto out;
1653 }
1654
1695{
1696 u32 ledctl;
1697 s32 ret_val = E1000_SUCCESS;
1698
1699 DEBUGFUNC("e1000_setup_led_generic");
1700
1701 if (hw->func.setup_led != e1000_setup_led_generic) {
1702 ret_val = -E1000_ERR_CONFIG;
1703 goto out;
1704 }
1705
1655 if (hw->media_type == e1000_media_type_fiber) {
1706 if (hw->phy.media_type == e1000_media_type_fiber) {
1656 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1657 hw->mac.ledctl_default = ledctl;
1658 /* Turn off LED0 */
1659 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1660 E1000_LEDCTL_LED0_BLINK |
1661 E1000_LEDCTL_LED0_MODE_MASK);
1662 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1663 E1000_LEDCTL_LED0_MODE_SHIFT);
1664 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1707 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1708 hw->mac.ledctl_default = ledctl;
1709 /* Turn off LED0 */
1710 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1711 E1000_LEDCTL_LED0_BLINK |
1712 E1000_LEDCTL_LED0_MODE_MASK);
1713 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1714 E1000_LEDCTL_LED0_MODE_SHIFT);
1715 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1665 } else if (hw->media_type == e1000_media_type_copper) {
1716 } else if (hw->phy.media_type == e1000_media_type_copper) {
1666 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1667 }
1668
1669out:
1670 return ret_val;
1671}
1672
1673/**
1674 * e1000_cleanup_led_generic - Set LED config to default operation
1675 * @hw: pointer to the HW structure
1676 *
1677 * Remove the current LED configuration and set the LED configuration
1678 * to the default value, saved from the EEPROM.
1679 **/
1717 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1718 }
1719
1720out:
1721 return ret_val;
1722}
1723
1724/**
1725 * e1000_cleanup_led_generic - Set LED config to default operation
1726 * @hw: pointer to the HW structure
1727 *
1728 * Remove the current LED configuration and set the LED configuration
1729 * to the default value, saved from the EEPROM.
1730 **/
1680s32
1681e1000_cleanup_led_generic(struct e1000_hw *hw)
1731s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1682{
1683 s32 ret_val = E1000_SUCCESS;
1684
1685 DEBUGFUNC("e1000_cleanup_led_generic");
1686
1687 if (hw->func.cleanup_led != e1000_cleanup_led_generic) {
1688 ret_val = -E1000_ERR_CONFIG;
1689 goto out;

--- 6 unchanged lines hidden (view full) ---

1696}
1697
1698/**
1699 * e1000_blink_led_generic - Blink LED
1700 * @hw: pointer to the HW structure
1701 *
1702 * Blink the led's which are set to be on.
1703 **/
1732{
1733 s32 ret_val = E1000_SUCCESS;
1734
1735 DEBUGFUNC("e1000_cleanup_led_generic");
1736
1737 if (hw->func.cleanup_led != e1000_cleanup_led_generic) {
1738 ret_val = -E1000_ERR_CONFIG;
1739 goto out;

--- 6 unchanged lines hidden (view full) ---

1746}
1747
1748/**
1749 * e1000_blink_led_generic - Blink LED
1750 * @hw: pointer to the HW structure
1751 *
1752 * Blink the led's which are set to be on.
1753 **/
1704s32
1705e1000_blink_led_generic(struct e1000_hw *hw)
1754s32 e1000_blink_led_generic(struct e1000_hw *hw)
1706{
1707 u32 ledctl_blink = 0;
1708 u32 i;
1709
1710 DEBUGFUNC("e1000_blink_led_generic");
1711
1755{
1756 u32 ledctl_blink = 0;
1757 u32 i;
1758
1759 DEBUGFUNC("e1000_blink_led_generic");
1760
1712 if (hw->media_type == e1000_media_type_fiber) {
1761 if (hw->phy.media_type == e1000_media_type_fiber) {
1713 /* always blink LED0 for PCI-E fiber */
1714 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1715 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1716 } else {
1762 /* always blink LED0 for PCI-E fiber */
1763 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1764 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1765 } else {
1717 /* set the blink bit for each LED that's "on" (0x0E)
1718 * in ledctl_mode2 */
1766 /*
1767 * set the blink bit for each LED that's "on" (0x0E)
1768 * in ledctl_mode2
1769 */
1719 ledctl_blink = hw->mac.ledctl_mode2;
1720 for (i = 0; i < 4; i++)
1721 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1722 E1000_LEDCTL_MODE_LED_ON)
1723 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1724 (i * 8));
1725 }
1726
1727 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1728
1729 return E1000_SUCCESS;
1730}
1731
1732/**
1733 * e1000_led_on_generic - Turn LED on
1734 * @hw: pointer to the HW structure
1735 *
1736 * Turn LED on.
1737 **/
1770 ledctl_blink = hw->mac.ledctl_mode2;
1771 for (i = 0; i < 4; i++)
1772 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1773 E1000_LEDCTL_MODE_LED_ON)
1774 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1775 (i * 8));
1776 }
1777
1778 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1779
1780 return E1000_SUCCESS;
1781}
1782
1783/**
1784 * e1000_led_on_generic - Turn LED on
1785 * @hw: pointer to the HW structure
1786 *
1787 * Turn LED on.
1788 **/
1738s32
1739e1000_led_on_generic(struct e1000_hw *hw)
1789s32 e1000_led_on_generic(struct e1000_hw *hw)
1740{
1741 u32 ctrl;
1742
1743 DEBUGFUNC("e1000_led_on_generic");
1744
1790{
1791 u32 ctrl;
1792
1793 DEBUGFUNC("e1000_led_on_generic");
1794
1745 switch (hw->media_type) {
1795 switch (hw->phy.media_type) {
1746 case e1000_media_type_fiber:
1747 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1748 ctrl &= ~E1000_CTRL_SWDPIN0;
1749 ctrl |= E1000_CTRL_SWDPIO0;
1750 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1751 break;
1752 case e1000_media_type_copper:
1753 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);

--- 6 unchanged lines hidden (view full) ---

1760}
1761
1762/**
1763 * e1000_led_off_generic - Turn LED off
1764 * @hw: pointer to the HW structure
1765 *
1766 * Turn LED off.
1767 **/
1796 case e1000_media_type_fiber:
1797 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1798 ctrl &= ~E1000_CTRL_SWDPIN0;
1799 ctrl |= E1000_CTRL_SWDPIO0;
1800 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1801 break;
1802 case e1000_media_type_copper:
1803 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);

--- 6 unchanged lines hidden (view full) ---

1810}
1811
1812/**
1813 * e1000_led_off_generic - Turn LED off
1814 * @hw: pointer to the HW structure
1815 *
1816 * Turn LED off.
1817 **/
1768s32
1769e1000_led_off_generic(struct e1000_hw *hw)
1818s32 e1000_led_off_generic(struct e1000_hw *hw)
1770{
1771 u32 ctrl;
1772
1773 DEBUGFUNC("e1000_led_off_generic");
1774
1819{
1820 u32 ctrl;
1821
1822 DEBUGFUNC("e1000_led_off_generic");
1823
1775 switch (hw->media_type) {
1824 switch (hw->phy.media_type) {
1776 case e1000_media_type_fiber:
1777 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1778 ctrl |= E1000_CTRL_SWDPIN0;
1779 ctrl |= E1000_CTRL_SWDPIO0;
1780 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1781 break;
1782 case e1000_media_type_copper:
1783 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);

--- 7 unchanged lines hidden (view full) ---

1791
1792/**
1793 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1794 * @hw: pointer to the HW structure
1795 * @no_snoop: bitmap of snoop events
1796 *
1797 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1798 **/
1825 case e1000_media_type_fiber:
1826 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1827 ctrl |= E1000_CTRL_SWDPIN0;
1828 ctrl |= E1000_CTRL_SWDPIO0;
1829 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1830 break;
1831 case e1000_media_type_copper:
1832 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);

--- 7 unchanged lines hidden (view full) ---

1840
1841/**
1842 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1843 * @hw: pointer to the HW structure
1844 * @no_snoop: bitmap of snoop events
1845 *
1846 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1847 **/
1799void
1800e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1848void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1801{
1802 u32 gcr;
1803
1804 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1805
1806 if (hw->bus.type != e1000_bus_type_pci_express)
1807 goto out;
1808

--- 13 unchanged lines hidden (view full) ---

1822 *
1823 * Returns 0 (E1000_SUCCESS) if successful, else returns -10
1824 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1825 * the master requests to be disabled.
1826 *
1827 * Disables PCI-Express master access and verifies there are no pending
1828 * requests.
1829 **/
1849{
1850 u32 gcr;
1851
1852 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1853
1854 if (hw->bus.type != e1000_bus_type_pci_express)
1855 goto out;
1856

--- 13 unchanged lines hidden (view full) ---

1870 *
1871 * Returns 0 (E1000_SUCCESS) if successful, else returns -10
1872 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1873 * the master requests to be disabled.
1874 *
1875 * Disables PCI-Express master access and verifies there are no pending
1876 * requests.
1877 **/
1830s32
1831e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1878s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1832{
1833 u32 ctrl;
1834 s32 timeout = MASTER_DISABLE_TIMEOUT;
1835 s32 ret_val = E1000_SUCCESS;
1836
1837 DEBUGFUNC("e1000_disable_pcie_master_generic");
1838
1839 if (hw->bus.type != e1000_bus_type_pci_express)

--- 22 unchanged lines hidden (view full) ---

1862}
1863
1864/**
1865 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1866 * @hw: pointer to the HW structure
1867 *
1868 * Reset the Adaptive Interframe Spacing throttle to default values.
1869 **/
1879{
1880 u32 ctrl;
1881 s32 timeout = MASTER_DISABLE_TIMEOUT;
1882 s32 ret_val = E1000_SUCCESS;
1883
1884 DEBUGFUNC("e1000_disable_pcie_master_generic");
1885
1886 if (hw->bus.type != e1000_bus_type_pci_express)

--- 22 unchanged lines hidden (view full) ---

1909}
1910
1911/**
1912 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1913 * @hw: pointer to the HW structure
1914 *
1915 * Reset the Adaptive Interframe Spacing throttle to default values.
1916 **/
1870void
1871e1000_reset_adaptive_generic(struct e1000_hw *hw)
1917void e1000_reset_adaptive_generic(struct e1000_hw *hw)
1872{
1873 struct e1000_mac_info *mac = &hw->mac;
1874
1875 DEBUGFUNC("e1000_reset_adaptive_generic");
1876
1877 if (!mac->adaptive_ifs) {
1878 DEBUGOUT("Not in Adaptive IFS mode!\n");
1879 goto out;

--- 15 unchanged lines hidden (view full) ---

1895
1896/**
1897 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
1898 * @hw: pointer to the HW structure
1899 *
1900 * Update the Adaptive Interframe Spacing Throttle value based on the
1901 * time between transmitted packets and time between collisions.
1902 **/
1918{
1919 struct e1000_mac_info *mac = &hw->mac;
1920
1921 DEBUGFUNC("e1000_reset_adaptive_generic");
1922
1923 if (!mac->adaptive_ifs) {
1924 DEBUGOUT("Not in Adaptive IFS mode!\n");
1925 goto out;

--- 15 unchanged lines hidden (view full) ---

1941
1942/**
1943 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
1944 * @hw: pointer to the HW structure
1945 *
1946 * Update the Adaptive Interframe Spacing Throttle value based on the
1947 * time between transmitted packets and time between collisions.
1948 **/
1903void
1904e1000_update_adaptive_generic(struct e1000_hw *hw)
1949void e1000_update_adaptive_generic(struct e1000_hw *hw)
1905{
1906 struct e1000_mac_info *mac = &hw->mac;
1907
1908 DEBUGFUNC("e1000_update_adaptive_generic");
1909
1910 if (!mac->adaptive_ifs) {
1911 DEBUGOUT("Not in Adaptive IFS mode!\n");
1912 goto out;

--- 25 unchanged lines hidden (view full) ---

1938
1939/**
1940 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
1941 * @hw: pointer to the HW structure
1942 *
1943 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1944 * set, which is forced to MDI mode only.
1945 **/
1950{
1951 struct e1000_mac_info *mac = &hw->mac;
1952
1953 DEBUGFUNC("e1000_update_adaptive_generic");
1954
1955 if (!mac->adaptive_ifs) {
1956 DEBUGOUT("Not in Adaptive IFS mode!\n");
1957 goto out;

--- 25 unchanged lines hidden (view full) ---

1983
1984/**
1985 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
1986 * @hw: pointer to the HW structure
1987 *
1988 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1989 * set, which is forced to MDI mode only.
1990 **/
1946s32
1947e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
1991s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
1948{
1949 s32 ret_val = E1000_SUCCESS;
1950
1951 DEBUGFUNC("e1000_validate_mdi_setting_generic");
1952
1953 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1954 DEBUGOUT("Invalid MDI setting detected\n");
1955 hw->phy.mdix = 1;

--- 11 unchanged lines hidden (view full) ---

1967 * @reg: 32bit register offset such as E1000_SCTL
1968 * @offset: register offset to write to
1969 * @data: data to write at register offset
1970 *
1971 * Writes an address/data control type register. There are several of these
1972 * and they all have the format address << 8 | data and bit 31 is polled for
1973 * completion.
1974 **/
1992{
1993 s32 ret_val = E1000_SUCCESS;
1994
1995 DEBUGFUNC("e1000_validate_mdi_setting_generic");
1996
1997 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1998 DEBUGOUT("Invalid MDI setting detected\n");
1999 hw->phy.mdix = 1;

--- 11 unchanged lines hidden (view full) ---

2011 * @reg: 32bit register offset such as E1000_SCTL
2012 * @offset: register offset to write to
2013 * @data: data to write at register offset
2014 *
2015 * Writes an address/data control type register. There are several of these
2016 * and they all have the format address << 8 | data and bit 31 is polled for
2017 * completion.
2018 **/
1975s32
1976e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
1977 u32 offset, u8 data)
2019s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2020 u32 offset, u8 data)
1978{
1979 u32 i, regvalue = 0;
1980 s32 ret_val = E1000_SUCCESS;
1981
1982 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
1983
1984 /* Set up the address and data */
1985 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);

--- 18 unchanged lines hidden --- 		2021{
2022 u32 i, regvalue = 0;
2023 s32 ret_val = E1000_SUCCESS;
2024
2025 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2026
2027 /* Set up the address and data */
2028 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);

--- 18 unchanged lines hidden ---