| e1000_ich8lan.h (287990) | e1000_ich8lan.h (295323) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 287990 2015-09-19 18:22:59Z sbruno $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 295323 2016-02-05 17:14:37Z erj $*/ |
| 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 --- 60 unchanged lines hidden (view full) --- 102#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 103 104#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 105#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 106#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 107 108#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 109#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 | 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 --- 60 unchanged lines hidden (view full) --- 102#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 103 104#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 105#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 106#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 107 108#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 109#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 |
| 110 | 110#define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000 111/* bit for disabling packet buffer read */ 112#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000 113#define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 |
| 111#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 | 114#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 |
| 115#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 116#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 117#define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200 118#define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 |
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| 112 | 119 |
| 120/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */ 121#define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000 122 123#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/ 124#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/ 125#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ 126#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29) |
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| 113#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 114 115#define E1000_ICH_RAR_ENTRIES 7 116#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 117#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 118 119#define PHY_PAGE_SHIFT 5 120#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ --- 45 unchanged lines hidden (view full) --- 166#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 167#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 168#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 169 170#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 171 172#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 173#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ | 127#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 128 129#define E1000_ICH_RAR_ENTRIES 7 130#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 131#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 132 133#define PHY_PAGE_SHIFT 5 134#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ --- 45 unchanged lines hidden (view full) --- 180#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 181#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 182#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 183 184#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 185 186#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 187#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ |
| 188#define K1_ENTRY_LATENCY 0 189#define K1_MIN_TIME 1 |
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| 174 175/* SMBus Control Phy Register */ 176#define CV_SMB_CTRL PHY_REG(769, 23) 177#define CV_SMB_CTRL_FORCE_SMBUS 0x0001 178 179/* I218 Ultra Low Power Configuration 1 Register */ 180#define I218_ULP_CONFIG1 PHY_REG(779, 16) 181#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 182#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 183#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 184#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 185#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 186#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ | 190 191/* SMBus Control Phy Register */ 192#define CV_SMB_CTRL PHY_REG(769, 23) 193#define CV_SMB_CTRL_FORCE_SMBUS 0x0001 194 195/* I218 Ultra Low Power Configuration 1 Register */ 196#define I218_ULP_CONFIG1 PHY_REG(779, 16) 197#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 198#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 199#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 200#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 201#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 202#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ |
| 203/* enable ULP even if when phy powered down via lanphypc */ 204#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 205/* disable clear of sticky ULP on PERST */ 206#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 |
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| 187#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 188 189/* SMBus Address Phy Register */ 190#define HV_SMB_ADDR PHY_REG(768, 26) 191#define HV_SMB_ADDR_MASK 0x007F 192#define HV_SMB_ADDR_PEC_EN 0x0200 193#define HV_SMB_ADDR_VALID 0x0080 194#define HV_SMB_ADDR_FREQ_MASK 0x1100 --- 22 unchanged lines hidden (view full) --- 217#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 218#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 219 220/* PHY Power Management Control */ 221#define HV_PM_CTRL PHY_REG(770, 17) 222#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 223#define HV_PM_CTRL_K1_ENABLE 0x4000 224 | 207#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 208 209/* SMBus Address Phy Register */ 210#define HV_SMB_ADDR PHY_REG(768, 26) 211#define HV_SMB_ADDR_MASK 0x007F 212#define HV_SMB_ADDR_PEC_EN 0x0200 213#define HV_SMB_ADDR_VALID 0x0080 214#define HV_SMB_ADDR_FREQ_MASK 0x1100 --- 22 unchanged lines hidden (view full) --- 237#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 238#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 239 240/* PHY Power Management Control */ 241#define HV_PM_CTRL PHY_REG(770, 17) 242#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 243#define HV_PM_CTRL_K1_ENABLE 0x4000 244 |
| 245#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) 246#define I217_PLL_CLOCK_GATE_MASK 0x07FF 247 |
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| 225#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 226 227/* Inband Control */ 228#define I217_INBAND_CTRL PHY_REG(770, 18) 229#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 230#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 231 232/* Low Power Idle GPIO Control */ --- 64 unchanged lines hidden (view full) --- 297 298/* OBFF Control & Threshold Defines */ 299#define E1000_SVCR_OFF_EN 0x00000001 300#define E1000_SVCR_OFF_MASKINT 0x00001000 301#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 302#define E1000_SVCR_OFF_TIMER_SHIFT 16 303#define E1000_SVT_OFF_HWM_MASK 0x0000001F 304 | 248#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 249 250/* Inband Control */ 251#define I217_INBAND_CTRL PHY_REG(770, 18) 252#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 253#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 254 255/* Low Power Idle GPIO Control */ --- 64 unchanged lines hidden (view full) --- 320 321/* OBFF Control & Threshold Defines */ 322#define E1000_SVCR_OFF_EN 0x00000001 323#define E1000_SVCR_OFF_MASKINT 0x00001000 324#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 325#define E1000_SVCR_OFF_TIMER_SHIFT 16 326#define E1000_SVT_OFF_HWM_MASK 0x0000001F 327 |
| 305#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) 306#define E1000_PCI_REVISION_ID_REG 0x08 307#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */ | |
| 308void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 309 bool state); 310void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 311void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 312void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); | 328void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 329 bool state); 330void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 331void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 332void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); |
| 313void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); | 333u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw); |
| 314s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 315void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 316s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 317s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 318s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 319s32 e1000_set_eee_pchlan(struct e1000_hw *hw); 320s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); 321s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 322#endif /* _E1000_ICH8LAN_H_ */ | 334s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 335void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 336s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 337s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 338s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 339s32 e1000_set_eee_pchlan(struct e1000_hw *hw); 340s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); 341s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 342#endif /* _E1000_ICH8LAN_H_ */ |