| e1000_ich8lan.h (218588) | e1000_ich8lan.h (228386) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2001-2010, Intel Corporation | 3 Copyright (c) 2001-2011, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 218588 2011-02-12 00:07:40Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 228386 2011-12-10 06:55:02Z jfv $*/ |
| 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 | 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 |
| 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 42#define ICH_FLASH_FDATA0 0x0010 | 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 42#define ICH_FLASH_FDATA0 0x0010 |
| 43 44/* Requires up to 10 seconds when MNG might be accessing part. */ | 43 44/* Requires up to 10 seconds when MNG might be accessing part. */ |
| 45#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 46#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 47#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 48#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 49#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | 45#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 46#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 47#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 48#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 49#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 |
| 50 | 50 |
| 51#define ICH_CYCLE_READ 0 52#define ICH_CYCLE_WRITE 2 53#define ICH_CYCLE_ERASE 3 | 51#define ICH_CYCLE_READ 0 52#define ICH_CYCLE_WRITE 2 53#define ICH_CYCLE_ERASE 3 |
| 54 | 54 |
| 55#define FLASH_GFPREG_BASE_MASK 0x1FFF 56#define FLASH_SECTOR_ADDR_SHIFT 12 | 55#define FLASH_GFPREG_BASE_MASK 0x1FFF 56#define FLASH_SECTOR_ADDR_SHIFT 12 |
| 57 | 57 |
| 58#define ICH_FLASH_SEG_SIZE_256 256 59#define ICH_FLASH_SEG_SIZE_4K 4096 60#define ICH_FLASH_SEG_SIZE_8K 8192 61#define ICH_FLASH_SEG_SIZE_64K 65536 62#define ICH_FLASH_SECTOR_SIZE 4096 | 58#define ICH_FLASH_SEG_SIZE_256 256 59#define ICH_FLASH_SEG_SIZE_4K 4096 60#define ICH_FLASH_SEG_SIZE_8K 8192 61#define ICH_FLASH_SEG_SIZE_64K 65536 62#define ICH_FLASH_SECTOR_SIZE 4096 |
| 63 | 63 |
| 64#define ICH_FLASH_REG_MAPSIZE 0x00A0 | 64#define ICH_FLASH_REG_MAPSIZE 0x00A0 |
| 65 | 65 |
| 66#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 67#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ | 66#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 67#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ |
| 68/* FW established a valid mode */ | 68/* FW established a valid mode */ |
| 69#define E1000_ICH_FWSM_FW_VALID 0x00008000 | 69#define E1000_ICH_FWSM_FW_VALID 0x00008000 70#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 71#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 |
| 70 | 72 |
| 71#define E1000_ICH_MNG_IAMT_MODE 0x2 | 73#define E1000_ICH_MNG_IAMT_MODE 0x2 |
| 72 | 74 |
| 73#define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */ | 75#define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */ 76#define E1000_FWSM_MEMC 0x00000010 /* ME Messaging capable */ |
| 74 75/* Shared Receive Address Registers */ | 77 78/* Shared Receive Address Registers */ |
| 76#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 77#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 78#define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */ 79#define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */ | 79#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 80#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 81#define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */ 82#define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */ |
| 80 | 83 |
| 81#define E1000_H2ME 0x05B50 /* Host to ME */ 82#define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */ 83#define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */ 84#define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */ 85#define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */ 86#define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */ 87#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */ 88#define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */ | 84#define E1000_H2ME 0x05B50 /* Host to ME */ 85#define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */ 86#define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */ 87#define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */ 88#define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */ 89#define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */ 90#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */ 91#define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */ |
| 89 | 92 |
| 90#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 91 (ID_LED_OFF1_OFF2 << 8) | \ 92 (ID_LED_OFF1_ON2 << 4) | \ 93 (ID_LED_DEF1_DEF2)) | 93#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 94 (ID_LED_OFF1_OFF2 << 8) | \ 95 (ID_LED_OFF1_ON2 << 4) | \ 96 (ID_LED_DEF1_DEF2)) |
| 94 | 97 |
| 95#define E1000_ICH_NVM_SIG_WORD 0x13 96#define E1000_ICH_NVM_SIG_MASK 0xC000 97#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 98#define E1000_ICH_NVM_SIG_VALUE 0x80 | 98#define E1000_ICH_NVM_SIG_WORD 0x13 99#define E1000_ICH_NVM_SIG_MASK 0xC000 100#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 101#define E1000_ICH_NVM_SIG_VALUE 0x80 |
| 99 | 102 |
| 100#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | 103#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 |
| 101 | 104 |
| 102#define E1000_FEXTNVM_SW_CONFIG 1 103#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ | 105#define E1000_FEXTNVM_SW_CONFIG 1 106#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ |
| 104 | 107 |
| 105#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 106#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 107#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 | 108#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 109#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 110#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 |
| 108 | 111 |
| 109#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL | 112#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL |
| 110 | 113 |
| 111#define E1000_ICH_RAR_ENTRIES 7 112#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ | 114#define E1000_ICH_RAR_ENTRIES 7 115#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ |
| 113 | 116 |
| 114#define PHY_PAGE_SHIFT 5 115#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 116 ((reg) & MAX_PHY_REG_ADDRESS)) 117#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 118#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 119#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ 120#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ | 117#define PHY_PAGE_SHIFT 5 118#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 119 ((reg) & MAX_PHY_REG_ADDRESS)) 120#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 121#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 122#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ 123#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ |
| 121 | 124 |
| 122#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 123#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 124#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 125#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 | 125#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 126#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 127#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 128#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 |
| 126 127/* PHY Wakeup Registers and defines */ | 129 130/* PHY Wakeup Registers and defines */ |
| 128#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 129#define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 130#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 131#define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 132#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 133#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 134#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 135#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 136#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 137#define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64)) 138#define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2))) 139#define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2))) | 131#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 132#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 133#define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 134#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 135#define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 136#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 137#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 138#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 139#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 140#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 141#define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64)) 142#define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2))) 143#define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2))) |
| 140 | 144 |
| 141#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4))) 142#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4))) 143#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4))) 144#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4))) | 145#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4))) 146#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4))) 147#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4))) 148#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4))) |
| 145 | 149 |
| 146#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 147#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 148#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 149#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 150#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 151#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 152#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ | 150#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 151#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 152#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 153#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 154#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 155#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 156#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ |
| 153 | 157 |
| 154#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 155#define HV_MUX_DATA_CTRL PHY_REG(776, 16) 156#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 157#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 158#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ 159#define HV_SCC_LOWER PHY_REG(778, 17) 160#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ 161#define HV_ECOL_LOWER PHY_REG(778, 19) 162#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ 163#define HV_MCC_LOWER PHY_REG(778, 21) 164#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ 165#define HV_LATECOL_LOWER PHY_REG(778, 24) 166#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 167#define HV_COLC_LOWER PHY_REG(778, 26) 168#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 169#define HV_DC_LOWER PHY_REG(778, 28) 170#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 171#define HV_TNCRS_LOWER PHY_REG(778, 30) | 158#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 159#define HV_MUX_DATA_CTRL PHY_REG(776, 16) 160#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 161#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 162#define HV_STATS_PAGE 778 163#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ 164#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 165#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ 166#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 167#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ 168#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 169#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ 170#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 171#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ 172#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 173#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 174#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 175#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ 176#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) |
| 172 | 177 |
| 173#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ | 178#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ |
| 174 | 179 |
| 175#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 176#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ | 180/* 181 * For ICH, the name used for NVM word 17h is LED1 Config. 182 * For PCH, the word was re-named to OEM Config. 183 */ 184#define E1000_NVM_LED1_CONFIG 0x17 /* NVM LED1/LPLU Config Word */ 185#define E1000_NVM_LED1_CONFIG_LPLU_NONDOA 0x0400 /* NVM LPLU in non-D0a Bit */ 186#define E1000_NVM_OEM_CONFIG E1000_NVM_LED1_CONFIG 187#define E1000_NVM_OEM_CONFIG_LPLU_NONDOA E1000_NVM_LED1_CONFIG_LPLU_NONDOA |
| 177 | 188 |
| 189#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 190#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 191 |
|
| 178/* SMBus Address Phy Register */ | 192/* SMBus Address Phy Register */ |
| 179#define HV_SMB_ADDR PHY_REG(768, 26) 180#define HV_SMB_ADDR_MASK 0x007F 181#define HV_SMB_ADDR_PEC_EN 0x0200 182#define HV_SMB_ADDR_VALID 0x0080 | 193#define HV_SMB_ADDR PHY_REG(768, 26) 194#define HV_SMB_ADDR_MASK 0x007F 195#define HV_SMB_ADDR_PEC_EN 0x0200 196#define HV_SMB_ADDR_VALID 0x0080 |
| 183 184/* Strapping Option Register - RO */ | 197 198/* Strapping Option Register - RO */ |
| 185#define E1000_STRAP 0x0000C 186#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 187#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 | 199#define E1000_STRAP 0x0000C 200#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 201#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 |
| 188 189/* OEM Bits Phy Register */ | 202 203/* OEM Bits Phy Register */ |
| 190#define HV_OEM_BITS PHY_REG(768, 25) 191#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 192#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 193#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ | 204#define HV_OEM_BITS PHY_REG(768, 25) 205#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 206#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 207#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ |
| 194 | 208 |
| 195#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */ | 209#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy addr bit from LCD Config word */ |
| 196 197/* KMRN Mode Control */ | 210 211/* KMRN Mode Control */ |
| 198#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 199#define HV_KMRN_MDIO_SLOW 0x0400 | 212#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 213#define HV_KMRN_MDIO_SLOW 0x0400 |
| 200 | 214 |
| 215/* KMRN FIFO Control and Status */ 216#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 217#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 218#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 219 |
|
| 201/* PHY Power Management Control */ | 220/* PHY Power Management Control */ |
| 202#define HV_PM_CTRL PHY_REG(770, 17) | 221#define HV_PM_CTRL PHY_REG(770, 17) |
| 203 | 222 |
| 204#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ | 223#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ |
| 205 206/* PHY Low Power Idle Control */ | 224 225/* PHY Low Power Idle Control */ |
| 207#define I82579_LPI_CTRL PHY_REG(772, 20) 208#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 | 226#define I82579_LPI_CTRL PHY_REG(772, 20) 227#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 228#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 |
| 209 210/* EMI Registers */ | 229 230/* EMI Registers */ |
| 211#define I82579_EMI_ADDR 0x10 212#define I82579_EMI_DATA 0x11 213#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ | 231#define I82579_EMI_ADDR 0x10 232#define I82579_EMI_DATA 0x11 233#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 234#define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ 235#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ |
| 214 215/* 216 * Additional interrupts need to be handled for ICH family: 217 * DSW = The FW changed the status of the DISSW bit in FWSM 218 * PHYINT = The LAN connected device generates an interrupt 219 * EPRST = Manageability reset event 220 */ 221#define IMS_ICH_ENABLE_MASK (\ | 236 237/* 238 * Additional interrupts need to be handled for ICH family: 239 * DSW = The FW changed the status of the DISSW bit in FWSM 240 * PHYINT = The LAN connected device generates an interrupt 241 * EPRST = Manageability reset event 242 */ 243#define IMS_ICH_ENABLE_MASK (\ |
| 222 E1000_IMS_DSW | \ 223 E1000_IMS_PHYINT | \ 224 E1000_IMS_EPRST) | 244 E1000_IMS_DSW | \ 245 E1000_IMS_PHYINT | \ 246 E1000_IMS_EPRST) |
| 225 226/* Additional interrupt register bit definitions */ | 247 248/* Additional interrupt register bit definitions */ |
| 227#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */ 228#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ 229#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ | 249#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */ 250#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ 251#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ |
| 230 231/* Security Processing bit Indication */ | 252 253/* Security Processing bit Indication */ |
| 232#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 233#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 234#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 235#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 236#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 | 254#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 255#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 256#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 257#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 258#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 |
| 237 238/* Receive Address Initial CRC Calculation */ | 259 260/* Receive Address Initial CRC Calculation */ |
| 239#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) | 261#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) |
| 240 241void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | 262 263void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, |
| 242 bool state); | 264 bool state); |
| 243void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 244void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); | 265void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 266void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); |
| 245void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw); | 267void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 268void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); |
| 246s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); | 269s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); |
| 247s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config); 248s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); | |
| 249void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 250s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 251#endif | 270void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 271s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 272#endif |