| e1000_ich8lan.h (194865) | e1000_ich8lan.h (200243) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 194865 2009-06-24 17:41:29Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 200243 2009-12-08 01:07:44Z jfv $*/ |
| 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 --- 93 unchanged lines hidden (view full) --- 135#define HV_LATECOL_LOWER PHY_REG(778, 24) 136#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 137#define HV_COLC_LOWER PHY_REG(778, 26) 138#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 139#define HV_DC_LOWER PHY_REG(778, 28) 140#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 141#define HV_TNCRS_LOWER PHY_REG(778, 30) 142 | 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 --- 93 unchanged lines hidden (view full) --- 135#define HV_LATECOL_LOWER PHY_REG(778, 24) 136#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 137#define HV_COLC_LOWER PHY_REG(778, 26) 138#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 139#define HV_DC_LOWER PHY_REG(778, 28) 140#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 141#define HV_TNCRS_LOWER PHY_REG(778, 30) 142 |
| 143#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 144 145#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 146#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 147 148/* SMBus Address Phy Register */ 149#define HV_SMB_ADDR PHY_REG(768, 26) 150#define HV_SMB_ADDR_PEC_EN 0x0200 151#define HV_SMB_ADDR_VALID 0x0080 152 153/* Strapping Option Register - RO */ 154#define E1000_STRAP 0x0000C 155#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 156#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 157 158/* OEM Bits Phy Register */ 159#define HV_OEM_BITS PHY_REG(768, 25) 160#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 161#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 162#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 163 164#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */ 165 166#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ 167 |
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| 143/* 144 * Additional interrupts need to be handled for ICH family: 145 * DSW = The FW changed the status of the DISSW bit in FWSM 146 * PHYINT = The LAN connected device generates an interrupt 147 * EPRST = Manageability reset event 148 */ 149#define IMS_ICH_ENABLE_MASK (\ 150 E1000_IMS_DSW | \ --- 13 unchanged lines hidden (view full) --- 164#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 165 166 167void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 168 bool state); 169void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 170void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 171void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw); | 168/* 169 * Additional interrupts need to be handled for ICH family: 170 * DSW = The FW changed the status of the DISSW bit in FWSM 171 * PHYINT = The LAN connected device generates an interrupt 172 * EPRST = Manageability reset event 173 */ 174#define IMS_ICH_ENABLE_MASK (\ 175 E1000_IMS_DSW | \ --- 13 unchanged lines hidden (view full) --- 189#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 190 191 192void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 193 bool state); 194void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 195void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 196void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw); |
| 197s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 198s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config); |
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| 172s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); | 199s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); |
| 173 | |
| 174#endif | 200#endif |