| e1000_ich8lan.h (169589) | e1000_ich8lan.h (173788) |
|---|---|
| 1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ | 1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/em/e1000_ich8lan.h 169589 2007-05-16 00:14:23Z jfv $*/ | 33/* $FreeBSD: head/sys/dev/em/e1000_ich8lan.h 173788 2007-11-20 21:41:22Z jfv $ */ |
| 34 35 36#ifndef _E1000_ICH8LAN_H_ 37#define _E1000_ICH8LAN_H_ 38 39#define ICH_FLASH_GFPREG 0x0000 40#define ICH_FLASH_HSFSTS 0x0004 41#define ICH_FLASH_HSFCTL 0x0006 --- 20 unchanged lines hidden (view full) --- 62#define ICH_FLASH_SEG_SIZE_8K 8192 63#define ICH_FLASH_SEG_SIZE_64K 65536 64#define ICH_FLASH_SECTOR_SIZE 4096 65 66#define ICH_FLASH_REG_MAPSIZE 0x00A0 67 68#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 69#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ | 34 35 36#ifndef _E1000_ICH8LAN_H_ 37#define _E1000_ICH8LAN_H_ 38 39#define ICH_FLASH_GFPREG 0x0000 40#define ICH_FLASH_HSFSTS 0x0004 41#define ICH_FLASH_HSFCTL 0x0006 --- 20 unchanged lines hidden (view full) --- 62#define ICH_FLASH_SEG_SIZE_8K 8192 63#define ICH_FLASH_SEG_SIZE_64K 65536 64#define ICH_FLASH_SECTOR_SIZE 4096 65 66#define ICH_FLASH_REG_MAPSIZE 0x00A0 67 68#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 69#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ |
| 70#define E1000_ICH_FWSM_FW_VALID 0x00008000 /* FW established a valid 71 * mode. 72 */ | 70/* FW established a valid mode */ 71#define E1000_ICH_FWSM_FW_VALID 0x00008000 |
| 73 74#define E1000_ICH_MNG_IAMT_MODE 0x2 75 76#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 77 (ID_LED_DEF1_OFF2 << 8) | \ 78 (ID_LED_DEF1_ON2 << 4) | \ 79 (ID_LED_DEF1_DEF2)) 80 --- 17 unchanged lines hidden (view full) --- 98#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ 99#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ 100 101#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 102#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 103#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 104#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 105 | 72 73#define E1000_ICH_MNG_IAMT_MODE 0x2 74 75#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 76 (ID_LED_DEF1_OFF2 << 8) | \ 77 (ID_LED_DEF1_ON2 << 4) | \ 78 (ID_LED_DEF1_DEF2)) 79 --- 17 unchanged lines hidden (view full) --- 97#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ 98#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ 99 100#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 101#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 102#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 103#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 104 |
| 106/* Additional interrupts need to be handled for ICH family: 107 DSW = The FW changed the status of the DISSW bit in FWSM 108 PHYINT = The LAN connected device generates an interrupt 109 EPRST = Manageability reset event */ | 105/* 106 * Additional interrupts need to be handled for ICH family: 107 * DSW = The FW changed the status of the DISSW bit in FWSM 108 * PHYINT = The LAN connected device generates an interrupt 109 * EPRST = Manageability reset event 110 */ |
| 110#define IMS_ICH_ENABLE_MASK (\ 111 E1000_IMS_DSW | \ 112 E1000_IMS_PHYINT | \ 113 E1000_IMS_EPRST) 114 | 111#define IMS_ICH_ENABLE_MASK (\ 112 E1000_IMS_DSW | \ 113 E1000_IMS_PHYINT | \ 114 E1000_IMS_EPRST) 115 |
| 116 |
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| 115#endif | 117#endif |