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e1000_hw.h (218530) e1000_hw.h (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_hw.h 218530 2011-02-11 01:00:26Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_hw.h 228386 2011-12-10 06:55:02Z jfv $*/
34
35#ifndef _E1000_HW_H_
36#define _E1000_HW_H_
37
38#include "e1000_osdep.h"
39#include "e1000_regs.h"
40#include "e1000_defines.h"
41
42struct e1000_hw;
43
34
35#ifndef _E1000_HW_H_
36#define _E1000_HW_H_
37
38#include "e1000_osdep.h"
39#include "e1000_regs.h"
40#include "e1000_defines.h"
41
42struct e1000_hw;
43
44#define E1000_DEV_ID_82542 0x1000
45#define E1000_DEV_ID_82543GC_FIBER 0x1001
46#define E1000_DEV_ID_82543GC_COPPER 0x1004
47#define E1000_DEV_ID_82544EI_COPPER 0x1008
48#define E1000_DEV_ID_82544EI_FIBER 0x1009
49#define E1000_DEV_ID_82544GC_COPPER 0x100C
50#define E1000_DEV_ID_82544GC_LOM 0x100D
51#define E1000_DEV_ID_82540EM 0x100E
52#define E1000_DEV_ID_82540EM_LOM 0x1015
53#define E1000_DEV_ID_82540EP_LOM 0x1016
54#define E1000_DEV_ID_82540EP 0x1017
55#define E1000_DEV_ID_82540EP_LP 0x101E
56#define E1000_DEV_ID_82545EM_COPPER 0x100F
57#define E1000_DEV_ID_82545EM_FIBER 0x1011
58#define E1000_DEV_ID_82545GM_COPPER 0x1026
59#define E1000_DEV_ID_82545GM_FIBER 0x1027
60#define E1000_DEV_ID_82545GM_SERDES 0x1028
61#define E1000_DEV_ID_82546EB_COPPER 0x1010
62#define E1000_DEV_ID_82546EB_FIBER 0x1012
63#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64#define E1000_DEV_ID_82546GB_COPPER 0x1079
65#define E1000_DEV_ID_82546GB_FIBER 0x107A
66#define E1000_DEV_ID_82546GB_SERDES 0x107B
67#define E1000_DEV_ID_82546GB_PCIE 0x108A
68#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70#define E1000_DEV_ID_82541EI 0x1013
71#define E1000_DEV_ID_82541EI_MOBILE 0x1018
72#define E1000_DEV_ID_82541ER_LOM 0x1014
73#define E1000_DEV_ID_82541ER 0x1078
74#define E1000_DEV_ID_82541GI 0x1076
75#define E1000_DEV_ID_82541GI_LF 0x107C
76#define E1000_DEV_ID_82541GI_MOBILE 0x1077
77#define E1000_DEV_ID_82547EI 0x1019
78#define E1000_DEV_ID_82547EI_MOBILE 0x101A
79#define E1000_DEV_ID_82547GI 0x1075
80#define E1000_DEV_ID_82571EB_COPPER 0x105E
81#define E1000_DEV_ID_82571EB_FIBER 0x105F
82#define E1000_DEV_ID_82571EB_SERDES 0x1060
83#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89#define E1000_DEV_ID_82572EI_COPPER 0x107D
90#define E1000_DEV_ID_82572EI_FIBER 0x107E
91#define E1000_DEV_ID_82572EI_SERDES 0x107F
92#define E1000_DEV_ID_82572EI 0x10B9
93#define E1000_DEV_ID_82573E 0x108B
94#define E1000_DEV_ID_82573E_IAMT 0x108C
95#define E1000_DEV_ID_82573L 0x109A
96#define E1000_DEV_ID_82574L 0x10D3
97#define E1000_DEV_ID_82574LA 0x10F6
98#define E1000_DEV_ID_82583V 0x150C
99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103#define E1000_DEV_ID_ICH8_82567V_3 0x1501
104#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106#define E1000_DEV_ID_ICH8_IGP_C 0x104B
107#define E1000_DEV_ID_ICH8_IFE 0x104C
108#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110#define E1000_DEV_ID_ICH8_IGP_M 0x104D
111#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115#define E1000_DEV_ID_ICH9_BM 0x10E5
116#define E1000_DEV_ID_ICH9_IGP_C 0x294C
117#define E1000_DEV_ID_ICH9_IFE 0x10C0
118#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123#define E1000_DEV_ID_ICH10_HANKSVILLE 0xF0FE
124#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
125#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
126#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
44#define E1000_DEV_ID_82542 0x1000
45#define E1000_DEV_ID_82543GC_FIBER 0x1001
46#define E1000_DEV_ID_82543GC_COPPER 0x1004
47#define E1000_DEV_ID_82544EI_COPPER 0x1008
48#define E1000_DEV_ID_82544EI_FIBER 0x1009
49#define E1000_DEV_ID_82544GC_COPPER 0x100C
50#define E1000_DEV_ID_82544GC_LOM 0x100D
51#define E1000_DEV_ID_82540EM 0x100E
52#define E1000_DEV_ID_82540EM_LOM 0x1015
53#define E1000_DEV_ID_82540EP_LOM 0x1016
54#define E1000_DEV_ID_82540EP 0x1017
55#define E1000_DEV_ID_82540EP_LP 0x101E
56#define E1000_DEV_ID_82545EM_COPPER 0x100F
57#define E1000_DEV_ID_82545EM_FIBER 0x1011
58#define E1000_DEV_ID_82545GM_COPPER 0x1026
59#define E1000_DEV_ID_82545GM_FIBER 0x1027
60#define E1000_DEV_ID_82545GM_SERDES 0x1028
61#define E1000_DEV_ID_82546EB_COPPER 0x1010
62#define E1000_DEV_ID_82546EB_FIBER 0x1012
63#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64#define E1000_DEV_ID_82546GB_COPPER 0x1079
65#define E1000_DEV_ID_82546GB_FIBER 0x107A
66#define E1000_DEV_ID_82546GB_SERDES 0x107B
67#define E1000_DEV_ID_82546GB_PCIE 0x108A
68#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70#define E1000_DEV_ID_82541EI 0x1013
71#define E1000_DEV_ID_82541EI_MOBILE 0x1018
72#define E1000_DEV_ID_82541ER_LOM 0x1014
73#define E1000_DEV_ID_82541ER 0x1078
74#define E1000_DEV_ID_82541GI 0x1076
75#define E1000_DEV_ID_82541GI_LF 0x107C
76#define E1000_DEV_ID_82541GI_MOBILE 0x1077
77#define E1000_DEV_ID_82547EI 0x1019
78#define E1000_DEV_ID_82547EI_MOBILE 0x101A
79#define E1000_DEV_ID_82547GI 0x1075
80#define E1000_DEV_ID_82571EB_COPPER 0x105E
81#define E1000_DEV_ID_82571EB_FIBER 0x105F
82#define E1000_DEV_ID_82571EB_SERDES 0x1060
83#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89#define E1000_DEV_ID_82572EI_COPPER 0x107D
90#define E1000_DEV_ID_82572EI_FIBER 0x107E
91#define E1000_DEV_ID_82572EI_SERDES 0x107F
92#define E1000_DEV_ID_82572EI 0x10B9
93#define E1000_DEV_ID_82573E 0x108B
94#define E1000_DEV_ID_82573E_IAMT 0x108C
95#define E1000_DEV_ID_82573L 0x109A
96#define E1000_DEV_ID_82574L 0x10D3
97#define E1000_DEV_ID_82574LA 0x10F6
98#define E1000_DEV_ID_82583V 0x150C
99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103#define E1000_DEV_ID_ICH8_82567V_3 0x1501
104#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106#define E1000_DEV_ID_ICH8_IGP_C 0x104B
107#define E1000_DEV_ID_ICH8_IFE 0x104C
108#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110#define E1000_DEV_ID_ICH8_IGP_M 0x104D
111#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115#define E1000_DEV_ID_ICH9_BM 0x10E5
116#define E1000_DEV_ID_ICH9_IGP_C 0x294C
117#define E1000_DEV_ID_ICH9_IFE 0x10C0
118#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
125#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
127
126
128#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
129#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
130#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
131#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
132#define E1000_DEV_ID_PCH2_LV_LM 0x1502
133#define E1000_DEV_ID_PCH2_LV_V 0x1503
134#define E1000_DEV_ID_82576 0x10C9
135#define E1000_DEV_ID_82576_FIBER 0x10E6
136#define E1000_DEV_ID_82576_SERDES 0x10E7
137#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
138#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
139#define E1000_DEV_ID_82576_NS 0x150A
140#define E1000_DEV_ID_82576_NS_SERDES 0x1518
141#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
142#define E1000_DEV_ID_82576_VF 0x10CA
143#define E1000_DEV_ID_I350_VF 0x1520
144#define E1000_DEV_ID_82575EB_COPPER 0x10A7
145#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
146#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
147#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
148#define E1000_DEV_ID_82580_COPPER 0x150E
149#define E1000_DEV_ID_82580_FIBER 0x150F
150#define E1000_DEV_ID_82580_SERDES 0x1510
151#define E1000_DEV_ID_82580_SGMII 0x1511
152#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
153#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
154#define E1000_DEV_ID_I350_COPPER 0x1521
155#define E1000_DEV_ID_I350_FIBER 0x1522
156#define E1000_DEV_ID_I350_SERDES 0x1523
157#define E1000_DEV_ID_I350_SGMII 0x1524
158#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
159#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
160#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
161#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
162#define E1000_REVISION_0 0
163#define E1000_REVISION_1 1
164#define E1000_REVISION_2 2
165#define E1000_REVISION_3 3
166#define E1000_REVISION_4 4
127#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
128#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
129#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
130#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
131#define E1000_DEV_ID_PCH2_LV_LM 0x1502
132#define E1000_DEV_ID_PCH2_LV_V 0x1503
133#define E1000_DEV_ID_82576 0x10C9
134#define E1000_DEV_ID_82576_FIBER 0x10E6
135#define E1000_DEV_ID_82576_SERDES 0x10E7
136#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
137#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
138#define E1000_DEV_ID_82576_NS 0x150A
139#define E1000_DEV_ID_82576_NS_SERDES 0x1518
140#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
141#define E1000_DEV_ID_82576_VF 0x10CA
142#define E1000_DEV_ID_I350_VF 0x1520
143#define E1000_DEV_ID_82575EB_COPPER 0x10A7
144#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
145#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
146#define E1000_DEV_ID_82580_COPPER 0x150E
147#define E1000_DEV_ID_82580_FIBER 0x150F
148#define E1000_DEV_ID_82580_SERDES 0x1510
149#define E1000_DEV_ID_82580_SGMII 0x1511
150#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
151#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
152#define E1000_DEV_ID_I350_COPPER 0x1521
153#define E1000_DEV_ID_I350_FIBER 0x1522
154#define E1000_DEV_ID_I350_SERDES 0x1523
155#define E1000_DEV_ID_I350_SGMII 0x1524
156#define E1000_DEV_ID_I350_DA4 0x1546
157#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
158#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
159#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
160#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
161#define E1000_REVISION_0 0
162#define E1000_REVISION_1 1
163#define E1000_REVISION_2 2
164#define E1000_REVISION_3 3
165#define E1000_REVISION_4 4
167
166
168#define E1000_FUNC_0 0
169#define E1000_FUNC_1 1
170#define E1000_FUNC_2 2
171#define E1000_FUNC_3 3
167#define E1000_FUNC_0 0
168#define E1000_FUNC_1 1
169#define E1000_FUNC_2 2
170#define E1000_FUNC_3 3
172
171
173#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
174#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
175#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
176#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
172#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
173#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
174#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
175#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
177
178enum e1000_mac_type {
179 e1000_undefined = 0,
180 e1000_82542,
181 e1000_82543,
182 e1000_82544,
183 e1000_82540,
184 e1000_82545,

--- 152 unchanged lines hidden (view full) ---

337
338#define __le16 u16
339#define __le32 u32
340#define __le64 u64
341/* Receive Descriptor */
342struct e1000_rx_desc {
343 __le64 buffer_addr; /* Address of the descriptor's data buffer */
344 __le16 length; /* Length of data DMAed into data buffer */
176
177enum e1000_mac_type {
178 e1000_undefined = 0,
179 e1000_82542,
180 e1000_82543,
181 e1000_82544,
182 e1000_82540,
183 e1000_82545,

--- 152 unchanged lines hidden (view full) ---

336
337#define __le16 u16
338#define __le32 u32
339#define __le64 u64
340/* Receive Descriptor */
341struct e1000_rx_desc {
342 __le64 buffer_addr; /* Address of the descriptor's data buffer */
343 __le16 length; /* Length of data DMAed into data buffer */
345 __le16 csum; /* Packet checksum */
346 u8 status; /* Descriptor status */
347 u8 errors; /* Descriptor Errors */
344 __le16 csum; /* Packet checksum */
345 u8 status; /* Descriptor status */
346 u8 errors; /* Descriptor Errors */
348 __le16 special;
349};
350
351/* Receive Descriptor - Extended */
352union e1000_rx_desc_extended {
353 struct {
354 __le64 buffer_addr;
355 __le64 reserved;
356 } read;
357 struct {
358 struct {
347 __le16 special;
348};
349
350/* Receive Descriptor - Extended */
351union e1000_rx_desc_extended {
352 struct {
353 __le64 buffer_addr;
354 __le64 reserved;
355 } read;
356 struct {
357 struct {
359 __le32 mrq; /* Multiple Rx Queues */
358 __le32 mrq; /* Multiple Rx Queues */
360 union {
359 union {
361 __le32 rss; /* RSS Hash */
360 __le32 rss; /* RSS Hash */
362 struct {
363 __le16 ip_id; /* IP id */
364 __le16 csum; /* Packet Checksum */
365 } csum_ip;
366 } hi_dword;
367 } lower;
368 struct {
369 __le32 status_error; /* ext status/error */
370 __le16 length;
361 struct {
362 __le16 ip_id; /* IP id */
363 __le16 csum; /* Packet Checksum */
364 } csum_ip;
365 } hi_dword;
366 } lower;
367 struct {
368 __le32 status_error; /* ext status/error */
369 __le16 length;
371 __le16 vlan; /* VLAN tag */
370 __le16 vlan; /* VLAN tag */
372 } upper;
373 } wb; /* writeback */
374};
375
376#define MAX_PS_BUFFERS 4
377/* Receive Descriptor - Packet Split */
378union e1000_rx_desc_packet_split {
379 struct {
380 /* one buffer for protocol header(s), three data buffers */
381 __le64 buffer_addr[MAX_PS_BUFFERS];
382 } read;
383 struct {
384 struct {
371 } upper;
372 } wb; /* writeback */
373};
374
375#define MAX_PS_BUFFERS 4
376/* Receive Descriptor - Packet Split */
377union e1000_rx_desc_packet_split {
378 struct {
379 /* one buffer for protocol header(s), three data buffers */
380 __le64 buffer_addr[MAX_PS_BUFFERS];
381 } read;
382 struct {
383 struct {
385 __le32 mrq; /* Multiple Rx Queues */
384 __le32 mrq; /* Multiple Rx Queues */
386 union {
385 union {
387 __le32 rss; /* RSS Hash */
386 __le32 rss; /* RSS Hash */
388 struct {
389 __le16 ip_id; /* IP id */
390 __le16 csum; /* Packet Checksum */
391 } csum_ip;
392 } hi_dword;
393 } lower;
394 struct {
395 __le32 status_error; /* ext status/error */
387 struct {
388 __le16 ip_id; /* IP id */
389 __le16 csum; /* Packet Checksum */
390 } csum_ip;
391 } hi_dword;
392 } lower;
393 struct {
394 __le32 status_error; /* ext status/error */
396 __le16 length0; /* length of buffer 0 */
397 __le16 vlan; /* VLAN tag */
395 __le16 length0; /* length of buffer 0 */
396 __le16 vlan; /* VLAN tag */
398 } middle;
399 struct {
400 __le16 header_status;
401 __le16 length[3]; /* length of buffers 1-3 */
402 } upper;
403 __le64 reserved;
404 } wb; /* writeback */
405};
406
407/* Transmit Descriptor */
408struct e1000_tx_desc {
409 __le64 buffer_addr; /* Address of the descriptor's data buffer */
410 union {
411 __le32 data;
412 struct {
397 } middle;
398 struct {
399 __le16 header_status;
400 __le16 length[3]; /* length of buffers 1-3 */
401 } upper;
402 __le64 reserved;
403 } wb; /* writeback */
404};
405
406/* Transmit Descriptor */
407struct e1000_tx_desc {
408 __le64 buffer_addr; /* Address of the descriptor's data buffer */
409 union {
410 __le32 data;
411 struct {
413 __le16 length; /* Data buffer length */
414 u8 cso; /* Checksum offset */
415 u8 cmd; /* Descriptor control */
412 __le16 length; /* Data buffer length */
413 u8 cso; /* Checksum offset */
414 u8 cmd; /* Descriptor control */
416 } flags;
417 } lower;
418 union {
419 __le32 data;
420 struct {
415 } flags;
416 } lower;
417 union {
418 __le32 data;
419 struct {
421 u8 status; /* Descriptor status */
422 u8 css; /* Checksum start */
420 u8 status; /* Descriptor status */
421 u8 css; /* Checksum start */
423 __le16 special;
424 } fields;
425 } upper;
426};
427
428/* Offload Context Descriptor */
429struct e1000_context_desc {
430 union {
431 __le32 ip_config;
432 struct {
422 __le16 special;
423 } fields;
424 } upper;
425};
426
427/* Offload Context Descriptor */
428struct e1000_context_desc {
429 union {
430 __le32 ip_config;
431 struct {
433 u8 ipcss; /* IP checksum start */
434 u8 ipcso; /* IP checksum offset */
435 __le16 ipcse; /* IP checksum end */
432 u8 ipcss; /* IP checksum start */
433 u8 ipcso; /* IP checksum offset */
434 __le16 ipcse; /* IP checksum end */
436 } ip_fields;
437 } lower_setup;
438 union {
439 __le32 tcp_config;
440 struct {
435 } ip_fields;
436 } lower_setup;
437 union {
438 __le32 tcp_config;
439 struct {
441 u8 tucss; /* TCP checksum start */
442 u8 tucso; /* TCP checksum offset */
443 __le16 tucse; /* TCP checksum end */
440 u8 tucss; /* TCP checksum start */
441 u8 tucso; /* TCP checksum offset */
442 __le16 tucse; /* TCP checksum end */
444 } tcp_fields;
445 } upper_setup;
446 __le32 cmd_and_length;
447 union {
448 __le32 data;
449 struct {
443 } tcp_fields;
444 } upper_setup;
445 __le32 cmd_and_length;
446 union {
447 __le32 data;
448 struct {
450 u8 status; /* Descriptor status */
451 u8 hdr_len; /* Header length */
452 __le16 mss; /* Maximum segment size */
449 u8 status; /* Descriptor status */
450 u8 hdr_len; /* Header length */
451 __le16 mss; /* Maximum segment size */
453 } fields;
454 } tcp_seg_setup;
455};
456
457/* Offload data descriptor */
458struct e1000_data_desc {
452 } fields;
453 } tcp_seg_setup;
454};
455
456/* Offload data descriptor */
457struct e1000_data_desc {
459 __le64 buffer_addr; /* Address of the descriptor's buffer address */
458 __le64 buffer_addr; /* Address of the descriptor's buffer address */
460 union {
461 __le32 data;
462 struct {
459 union {
460 __le32 data;
461 struct {
463 __le16 length; /* Data buffer length */
462 __le16 length; /* Data buffer length */
464 u8 typ_len_ext;
465 u8 cmd;
466 } flags;
467 } lower;
468 union {
469 __le32 data;
470 struct {
463 u8 typ_len_ext;
464 u8 cmd;
465 } flags;
466 } lower;
467 union {
468 __le32 data;
469 struct {
471 u8 status; /* Descriptor status */
472 u8 popts; /* Packet Options */
470 u8 status; /* Descriptor status */
471 u8 popts; /* Packet Options */
473 __le16 special;
474 } fields;
475 } upper;
476};
477
478/* Statistics counters collected by the MAC */
479struct e1000_hw_stats {
480 u64 crcerrs;

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548 u64 hgptc;
549 u64 htcbdpc;
550 u64 hgorc;
551 u64 hgotc;
552 u64 lenerrs;
553 u64 scvpc;
554 u64 hrmpc;
555 u64 doosync;
472 __le16 special;
473 } fields;
474 } upper;
475};
476
477/* Statistics counters collected by the MAC */
478struct e1000_hw_stats {
479 u64 crcerrs;

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547 u64 hgptc;
548 u64 htcbdpc;
549 u64 hgorc;
550 u64 hgotc;
551 u64 lenerrs;
552 u64 scvpc;
553 u64 hrmpc;
554 u64 doosync;
555 u64 o2bgptc;
556 u64 o2bspc;
557 u64 b2ospc;
558 u64 b2ogprc;
556};
557
558struct e1000_vf_stats {
559 u64 base_gprc;
560 u64 base_gptc;
561 u64 base_gorc;
562 u64 base_gotc;
563 u64 base_mprc;

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606/* Host Interface "Rev 1" */
607struct e1000_host_command_header {
608 u8 command_id;
609 u8 command_length;
610 u8 command_options;
611 u8 checksum;
612};
613
559};
560
561struct e1000_vf_stats {
562 u64 base_gprc;
563 u64 base_gptc;
564 u64 base_gorc;
565 u64 base_gotc;
566 u64 base_mprc;

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609/* Host Interface "Rev 1" */
610struct e1000_host_command_header {
611 u8 command_id;
612 u8 command_length;
613 u8 command_options;
614 u8 checksum;
615};
616
614#define E1000_HI_MAX_DATA_LENGTH 252
617#define E1000_HI_MAX_DATA_LENGTH 252
615struct e1000_host_command_info {
616 struct e1000_host_command_header command_header;
617 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
618};
619
620/* Host Interface "Rev 2" */
621struct e1000_host_mng_command_header {
622 u8 command_id;
623 u8 checksum;
624 u16 reserved1;
625 u16 reserved2;
626 u16 command_length;
627};
628
618struct e1000_host_command_info {
619 struct e1000_host_command_header command_header;
620 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
621};
622
623/* Host Interface "Rev 2" */
624struct e1000_host_mng_command_header {
625 u8 command_id;
626 u8 checksum;
627 u16 reserved1;
628 u16 reserved2;
629 u16 command_length;
630};
631
629#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
632#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
630struct e1000_host_mng_command_info {
631 struct e1000_host_mng_command_header command_header;
632 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
633};
634
635#include "e1000_mac.h"
636#include "e1000_phy.h"
637#include "e1000_nvm.h"

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663 s32 (*setup_led)(struct e1000_hw *);
664 void (*write_vfta)(struct e1000_hw *, u32, u32);
665 void (*config_collision_dist)(struct e1000_hw *);
666 void (*rar_set)(struct e1000_hw *, u8*, u32);
667 s32 (*read_mac_addr)(struct e1000_hw *);
668 s32 (*validate_mdi_setting)(struct e1000_hw *);
669 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
670 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
633struct e1000_host_mng_command_info {
634 struct e1000_host_mng_command_header command_header;
635 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
636};
637
638#include "e1000_mac.h"
639#include "e1000_phy.h"
640#include "e1000_nvm.h"

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666 s32 (*setup_led)(struct e1000_hw *);
667 void (*write_vfta)(struct e1000_hw *, u32, u32);
668 void (*config_collision_dist)(struct e1000_hw *);
669 void (*rar_set)(struct e1000_hw *, u8*, u32);
670 s32 (*read_mac_addr)(struct e1000_hw *);
671 s32 (*validate_mdi_setting)(struct e1000_hw *);
672 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
673 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
671 struct e1000_host_mng_command_header*);
674 struct e1000_host_mng_command_header*);
672 s32 (*mng_enable_host_if)(struct e1000_hw *);
673 s32 (*wait_autoneg)(struct e1000_hw *);
674};
675
675 s32 (*mng_enable_host_if)(struct e1000_hw *);
676 s32 (*wait_autoneg)(struct e1000_hw *);
677};
678
679/*
680 * When to use various PHY register access functions:
681 *
682 * Func Caller
683 * Function Does Does When to use
684 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
685 * X_reg L,P,A n/a for simple PHY reg accesses
686 * X_reg_locked P,A L for multiple accesses of different regs
687 * on different pages
688 * X_reg_page A L,P for multiple accesses of different regs
689 * on the same page
690 *
691 * Where X=[read|write], L=locking, P=sets page, A=register access
692 *
693 */
676struct e1000_phy_operations {
677 s32 (*init_params)(struct e1000_hw *);
678 s32 (*acquire)(struct e1000_hw *);
679 s32 (*cfg_on_link_up)(struct e1000_hw *);
680 s32 (*check_polarity)(struct e1000_hw *);
681 s32 (*check_reset_block)(struct e1000_hw *);
682 s32 (*commit)(struct e1000_hw *);
683 s32 (*force_speed_duplex)(struct e1000_hw *);
684 s32 (*get_cfg_done)(struct e1000_hw *hw);
685 s32 (*get_cable_length)(struct e1000_hw *);
686 s32 (*get_info)(struct e1000_hw *);
694struct e1000_phy_operations {
695 s32 (*init_params)(struct e1000_hw *);
696 s32 (*acquire)(struct e1000_hw *);
697 s32 (*cfg_on_link_up)(struct e1000_hw *);
698 s32 (*check_polarity)(struct e1000_hw *);
699 s32 (*check_reset_block)(struct e1000_hw *);
700 s32 (*commit)(struct e1000_hw *);
701 s32 (*force_speed_duplex)(struct e1000_hw *);
702 s32 (*get_cfg_done)(struct e1000_hw *hw);
703 s32 (*get_cable_length)(struct e1000_hw *);
704 s32 (*get_info)(struct e1000_hw *);
705 s32 (*set_page)(struct e1000_hw *, u16);
687 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
688 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
706 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
707 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
708 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
689 void (*release)(struct e1000_hw *);
690 s32 (*reset)(struct e1000_hw *);
691 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
692 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
693 s32 (*write_reg)(struct e1000_hw *, u32, u16);
694 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
709 void (*release)(struct e1000_hw *);
710 s32 (*reset)(struct e1000_hw *);
711 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
712 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
713 s32 (*write_reg)(struct e1000_hw *, u32, u16);
714 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
715 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
695 void (*power_up)(struct e1000_hw *);
696 void (*power_down)(struct e1000_hw *);
716 void (*power_up)(struct e1000_hw *);
717 void (*power_down)(struct e1000_hw *);
718 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
719 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
697};
698
699struct e1000_nvm_operations {
700 s32 (*init_params)(struct e1000_hw *);
701 s32 (*acquire)(struct e1000_hw *);
702 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
703 void (*release)(struct e1000_hw *);
704 void (*reload)(struct e1000_hw *);

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776 u16 max_cable_length;
777 u16 min_cable_length;
778
779 u8 mdix;
780
781 bool disable_polarity_correction;
782 bool is_mdix;
783 bool polarity_correction;
720};
721
722struct e1000_nvm_operations {
723 s32 (*init_params)(struct e1000_hw *);
724 s32 (*acquire)(struct e1000_hw *);
725 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
726 void (*release)(struct e1000_hw *);
727 void (*reload)(struct e1000_hw *);

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799 u16 max_cable_length;
800 u16 min_cable_length;
801
802 u8 mdix;
803
804 bool disable_polarity_correction;
805 bool is_mdix;
806 bool polarity_correction;
784 bool reset_disable;
785 bool speed_downgraded;
786 bool autoneg_wait_to_complete;
787};
788
789struct e1000_nvm_info {
790 struct e1000_nvm_operations ops;
791 enum e1000_nvm_type type;
792 enum e1000_nvm_override override;

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806 enum e1000_bus_speed speed;
807 enum e1000_bus_width width;
808
809 u16 func;
810 u16 pci_cmd_word;
811};
812
813struct e1000_fc_info {
807 bool speed_downgraded;
808 bool autoneg_wait_to_complete;
809};
810
811struct e1000_nvm_info {
812 struct e1000_nvm_operations ops;
813 enum e1000_nvm_type type;
814 enum e1000_nvm_override override;

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828 enum e1000_bus_speed speed;
829 enum e1000_bus_width width;
830
831 u16 func;
832 u16 pci_cmd_word;
833};
834
835struct e1000_fc_info {
814 u32 high_water; /* Flow control high-water mark */
815 u32 low_water; /* Flow control low-water mark */
816 u16 pause_time; /* Flow control pause timer */
817 u16 refresh_time; /* Flow control refresh timer */
818 bool send_xon; /* Flow control send XON */
819 bool strict_ieee; /* Strict IEEE mode */
820 enum e1000_fc_mode current_mode; /* FC mode in effect */
821 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
836 u32 high_water; /* Flow control high-water mark */
837 u32 low_water; /* Flow control low-water mark */
838 u16 pause_time; /* Flow control pause timer */
839 u16 refresh_time; /* Flow control refresh timer */
840 bool send_xon; /* Flow control send XON */
841 bool strict_ieee; /* Strict IEEE mode */
842 enum e1000_fc_mode current_mode; /* FC mode in effect */
843 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
822};
823
824struct e1000_mbx_operations {
825 s32 (*init_params)(struct e1000_hw *hw);
826 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
827 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
828 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
829 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);

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891 bool nvm_k1_enabled;
892 bool eee_disable;
893};
894
895struct e1000_dev_spec_82575 {
896 bool sgmii_active;
897 bool global_device_reset;
898 bool eee_disable;
844};
845
846struct e1000_mbx_operations {
847 s32 (*init_params)(struct e1000_hw *hw);
848 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
849 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
850 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
851 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);

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913 bool nvm_k1_enabled;
914 bool eee_disable;
915};
916
917struct e1000_dev_spec_82575 {
918 bool sgmii_active;
919 bool global_device_reset;
920 bool eee_disable;
921 bool module_plugged;
922 u32 mtu;
899};
900
901struct e1000_dev_spec_vf {
902 u32 vf_number;
903 u32 v2p_mailbox;
904};
905
906struct e1000_hw {

--- 49 unchanged lines hidden --- 		923};
924
925struct e1000_dev_spec_vf {
926 u32 vf_number;
927 u32 v2p_mailbox;
928};
929
930struct e1000_hw {

--- 49 unchanged lines hidden ---