| e1000_defines.h (287990) | e1000_defines.h (295323) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 287990 2015-09-19 18:22:59Z sbruno $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 295323 2016-02-05 17:14:37Z erj $*/ |
| 34 35#ifndef _E1000_DEFINES_H_ 36#define _E1000_DEFINES_H_ 37 38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39#define REQ_TX_DESCRIPTOR_MULTIPLE 8 40#define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 --- 150 unchanged lines hidden (view full) --- 192#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 193#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 194#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 195#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 196#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 197#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 198#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 199#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ | 34 35#ifndef _E1000_DEFINES_H_ 36#define _E1000_DEFINES_H_ 37 38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39#define REQ_TX_DESCRIPTOR_MULTIPLE 8 40#define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 --- 150 unchanged lines hidden (view full) --- 192#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 193#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 194#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 195#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 196#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 197#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 198#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 199#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ |
| 200#define E1000_RCTL_RDMTS_HEX 0x00010000 201#define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX |
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| 200#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 201#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 202#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 203/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 204#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 205#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 206#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 207#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ --- 540 unchanged lines hidden (view full) --- 748#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 749#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 750#define E1000_RXCW_C 0x20000000 /* Receive config */ 751#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 752 753#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 754#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 755 | 202#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 203#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 204#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 205/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 206#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 207#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 208#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 209#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ --- 540 unchanged lines hidden (view full) --- 750#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 751#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 752#define E1000_RXCW_C 0x20000000 /* Receive config */ 753#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 754 755#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 756#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 757 |
| 758/* HH Time Sync */ 759#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 760#define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 761#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 762#define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 763 |
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| 756#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 757#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 758#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 759#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 760#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 761#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 762#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 763#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ --- 80 unchanged lines hidden (view full) --- 844/* EEE status */ 845#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 846#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 847#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 848#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 849#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 850#define E1000_M88E1543_EEE_CTRL_1 0x0 851#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ | 764#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 765#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 766#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 767#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 768#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 769#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 770#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 771#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ --- 80 unchanged lines hidden (view full) --- 852/* EEE status */ 853#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 854#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 855#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 856#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 857#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 858#define E1000_M88E1543_EEE_CTRL_1 0x0 859#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ |
| 860#define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ |
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| 852#define E1000_EEE_ADV_DEV_I354 7 853#define E1000_EEE_ADV_ADDR_I354 60 854#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 855#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 856#define E1000_PCS_STATUS_DEV_I354 3 857#define E1000_PCS_STATUS_ADDR_I354 1 858#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 859#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 --- 155 unchanged lines hidden (view full) --- 1015#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1016#define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 1017#define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 1018#define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 1019#define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 1020/* NVM Addressing bits based on type 0=small, 1=large */ 1021#define E1000_EECD_ADDR_BITS 0x00000400 1022#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ | 861#define E1000_EEE_ADV_DEV_I354 7 862#define E1000_EEE_ADV_ADDR_I354 60 863#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 864#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 865#define E1000_PCS_STATUS_DEV_I354 3 866#define E1000_PCS_STATUS_ADDR_I354 1 867#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 868#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 --- 155 unchanged lines hidden (view full) --- 1024#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1025#define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 1026#define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 1027#define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 1028#define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 1029/* NVM Addressing bits based on type 0=small, 1=large */ 1030#define E1000_EECD_ADDR_BITS 0x00000400 1031#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ |
| 1023#ifndef E1000_NVM_GRANT_ATTEMPTS | |
| 1024#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ | 1032#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ |
| 1025#endif | |
| 1026#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1027#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1028#define E1000_EECD_SIZE_EX_SHIFT 11 1029#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1030#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1031#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1032#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1033#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ --- 439 unchanged lines hidden --- | 1033#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1034#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1035#define E1000_EECD_SIZE_EX_SHIFT 11 1036#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1037#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1038#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1039#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1040#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ --- 439 unchanged lines hidden --- |