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e1000_defines.h (219753) e1000_defines.h (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 219753 2011-03-18 18:54:00Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 228386 2011-12-10 06:55:02Z jfv $*/
34
35#ifndef _E1000_DEFINES_H_
36#define _E1000_DEFINES_H_
37
38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
39#define REQ_TX_DESCRIPTOR_MULTIPLE 8
40#define REQ_RX_DESCRIPTOR_MULTIPLE 8
41
42/* Definitions for power management and wakeup registers */
43/* Wake Up Control */
34
35#ifndef _E1000_DEFINES_H_
36#define _E1000_DEFINES_H_
37
38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
39#define REQ_TX_DESCRIPTOR_MULTIPLE 8
40#define REQ_RX_DESCRIPTOR_MULTIPLE 8
41
42/* Definitions for power management and wakeup registers */
43/* Wake Up Control */
44#define E1000_WUC_APME 0x00000001 /* APM Enable */
45#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
49#define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */
50#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
51#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
52#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
53#define E1000_WUC_FLX6_PHY 0x4000 /* Flexible Filter 6 Enable */
54#define E1000_WUC_FLX7_PHY 0x8000 /* Flexible Filter 7 Enable */
44#define E1000_WUC_APME 0x00000001 /* APM Enable */
45#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
49#define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */
50#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
51#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
52#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
53#define E1000_WUC_FLX6_PHY 0x4000 /* Flexible Filter 6 Enable */
54#define E1000_WUC_FLX7_PHY 0x8000 /* Flexible Filter 7 Enable */
55
56/* Wake Up Filter Control */
55
56/* Wake Up Filter Control */
57#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
58#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
59#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
60#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
61#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
62#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
63#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
64#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
57#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
58#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
59#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
60#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
61#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
62#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
63#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
64#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
65#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
65#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
66#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */
67#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */
68#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */
69#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */
70#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */
71#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */
72#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
73#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
74#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
75#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
76#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
77#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
78#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
79#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */
80#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */
81#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */
82#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/
83#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
84#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/
85#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */
86#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/
87#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
88#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask for all 6 wakeup filters*/
89#define E1000_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask for all 8 wakeup filters*/
90#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
91#define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */
92#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flexible filters */
93#define E1000_WUFC_FLX_FILTERS_8 0x00FF0000 /* Mask for 8 flexible filters */
66#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */
67#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */
68#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */
69#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */
70#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */
71#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */
72#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
73#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
74#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
75#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
76#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
77#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
78#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
79#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */
80#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */
81#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */
82#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /* wakeup filters mask */
83#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Flexible Filters bits offset */
84#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /* 4 flexible filters mask */
85#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /* 6 wakeup filters mask */
86#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /* 6 flexible filters mask */
87#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* all wakeup filters mask */
88#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 wu filters */
89#define E1000_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 wu filters */
90#define E1000_WUFC_FLX_OFFSET 16 /* Flexible Filters bits offset */
91#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* 4 flexible filters mask */
92#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* 6 flexible filters mask */
93#define E1000_WUFC_FLX_FILTERS_8 0x00FF0000 /* 8 flexible filters mask */
94/*
95 * For 82576 to utilize Extended filter masks in addition to
96 * existing (filter) masks
97 */
94/*
95 * For 82576 to utilize Extended filter masks in addition to
96 * existing (filter) masks
97 */
98#define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */
98#define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */
99
100/* Wake Up Status */
99
100/* Wake Up Status */
101#define E1000_WUS_LNKC E1000_WUFC_LNKC
102#define E1000_WUS_MAG E1000_WUFC_MAG
103#define E1000_WUS_EX E1000_WUFC_EX
104#define E1000_WUS_MC E1000_WUFC_MC
105#define E1000_WUS_BC E1000_WUFC_BC
106#define E1000_WUS_ARP E1000_WUFC_ARP
107#define E1000_WUS_IPV4 E1000_WUFC_IPV4
108#define E1000_WUS_IPV6 E1000_WUFC_IPV6
109#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY
110#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY
111#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY
112#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY
113#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4
114#define E1000_WUS_FLX0 E1000_WUFC_FLX0
115#define E1000_WUS_FLX1 E1000_WUFC_FLX1
116#define E1000_WUS_FLX2 E1000_WUFC_FLX2
117#define E1000_WUS_FLX3 E1000_WUFC_FLX3
118#define E1000_WUS_FLX4 E1000_WUFC_FLX4
119#define E1000_WUS_FLX5 E1000_WUFC_FLX5
120#define E1000_WUS_FLX6 E1000_WUFC_FLX6
121#define E1000_WUS_FLX7 E1000_WUFC_FLX7
122#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY
123#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY
124#define E1000_WUS_FLX6_PHY 0x0400
125#define E1000_WUS_FLX7_PHY 0x0800
126#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
127#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6
128#define E1000_WUS_FLX_FILTERS_8 E1000_WUFC_FLX_FILTERS_8
129#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6
101#define E1000_WUS_LNKC E1000_WUFC_LNKC
102#define E1000_WUS_MAG E1000_WUFC_MAG
103#define E1000_WUS_EX E1000_WUFC_EX
104#define E1000_WUS_MC E1000_WUFC_MC
105#define E1000_WUS_BC E1000_WUFC_BC
106#define E1000_WUS_ARP E1000_WUFC_ARP
107#define E1000_WUS_IPV4 E1000_WUFC_IPV4
108#define E1000_WUS_IPV6 E1000_WUFC_IPV6
109#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY
110#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY
111#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY
112#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY
113#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4
114#define E1000_WUS_FLX0 E1000_WUFC_FLX0
115#define E1000_WUS_FLX1 E1000_WUFC_FLX1
116#define E1000_WUS_FLX2 E1000_WUFC_FLX2
117#define E1000_WUS_FLX3 E1000_WUFC_FLX3
118#define E1000_WUS_FLX4 E1000_WUFC_FLX4
119#define E1000_WUS_FLX5 E1000_WUFC_FLX5
120#define E1000_WUS_FLX6 E1000_WUFC_FLX6
121#define E1000_WUS_FLX7 E1000_WUFC_FLX7
122#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY
123#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY
124#define E1000_WUS_FLX6_PHY 0x0400
125#define E1000_WUS_FLX7_PHY 0x0800
126#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
127#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6
128#define E1000_WUS_FLX_FILTERS_8 E1000_WUFC_FLX_FILTERS_8
129#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6
130
131/* Wake Up Packet Length */
130
131/* Wake Up Packet Length */
132#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
132#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
133
134/* Four Flexible Filters are supported */
133
134/* Four Flexible Filters are supported */
135#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
135#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
136/* Six Flexible Filters are supported */
136/* Six Flexible Filters are supported */
137#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6
137#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6
138/* Eight Flexible Filters are supported */
138/* Eight Flexible Filters are supported */
139#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8 8
139#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8 8
140/* Two Extended Flexible Filters are supported (82576) */
140/* Two Extended Flexible Filters are supported (82576) */
141#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
142#define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
143#define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
141#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
142#define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
143#define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
144
145/* Each Flexible Filter is at most 128 (0x80) bytes in length */
144
145/* Each Flexible Filter is at most 128 (0x80) bytes in length */
146#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
146#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
147
147
148#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
149#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
150#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8
151#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
152#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
148#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
149#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
150#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8
151#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
152#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
153
154/* Extended Device Control */
153
154/* Extended Device Control */
155#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
156#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
157#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
158#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
159#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
155#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
156#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
157#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
158#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
159#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
160/* Reserved (bits 4,5) in >= 82575 */
160/* Reserved (bits 4,5) in >= 82575 */
161#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
162#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
163#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
164#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
165#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
161#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
162#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */
163#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
164#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
165#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
166/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
166/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
167#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
168#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
169#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
170#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
171#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
172#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
173#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
167#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
168#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
169#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
170#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
171#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
172#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
173#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
174/* Physical Func Reset Done Indication */
174/* Physical Func Reset Done Indication */
175#define E1000_CTRL_EXT_PFRSTD 0x00004000
176#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
177#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
178#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
179#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
180#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
181#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
182#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
183#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
184#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
185#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
186#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
187#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
188#define E1000_CTRL_EXT_EIAME 0x01000000
189#define E1000_CTRL_EXT_IRCA 0x00000001
190#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
191#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
192#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
193#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
194#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
195#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
196#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
175#define E1000_CTRL_EXT_PFRSTD 0x00004000
176#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
177#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
178#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
179#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
180/* Offset of the link mode field in Ctrl Ext register */
181#define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
182#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
183#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
184#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
185#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
186#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
187#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
188#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
189#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
190#define E1000_CTRL_EXT_EIAME 0x01000000
191#define E1000_CTRL_EXT_IRCA 0x00000001
192#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
193#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
194#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
195#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
196#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
197#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
198#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
197/* IAME enable bit (27) was removed in >= 82575 */
199/* IAME enable bit (27) was removed in >= 82575 */
198#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */
199#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error
200 * detection enabled */
201#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity
202 * error detection enable */
203#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
204#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
205#define E1000_CTRL_EXT_LSECCK 0x00001000
206#define E1000_CTRL_EXT_PHYPDEN 0x00100000
207#define E1000_I2CCMD_REG_ADDR_SHIFT 16
208#define E1000_I2CCMD_REG_ADDR 0x00FF0000
209#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
210#define E1000_I2CCMD_PHY_ADDR 0x07000000
211#define E1000_I2CCMD_OPCODE_READ 0x08000000
212#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
213#define E1000_I2CCMD_RESET 0x10000000
214#define E1000_I2CCMD_READY 0x20000000
215#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
216#define E1000_I2CCMD_ERROR 0x80000000
217#define E1000_MAX_SGMII_PHY_REG_ADDR 255
218#define E1000_I2CCMD_PHY_TIMEOUT 200
219#define E1000_IVAR_VALID 0x80
220#define E1000_GPIE_NSICR 0x00000001
221#define E1000_GPIE_MSIX_MODE 0x00000010
222#define E1000_GPIE_EIAME 0x40000000
223#define E1000_GPIE_PBA 0x80000000
200#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
201/* packet buffer parity error detection enabled */
202#define E1000_CRTL_EXT_PB_PAREN 0x01000000
203/* descriptor FIFO parity error detection enable */
204#define E1000_CTRL_EXT_DF_PAREN 0x02000000
205#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
206#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
207#define E1000_CTRL_EXT_LSECCK 0x00001000
208#define E1000_CTRL_EXT_PHYPDEN 0x00100000
209#define E1000_I2CCMD_REG_ADDR_SHIFT 16
210#define E1000_I2CCMD_REG_ADDR 0x00FF0000
211#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
212#define E1000_I2CCMD_PHY_ADDR 0x07000000
213#define E1000_I2CCMD_OPCODE_READ 0x08000000
214#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
215#define E1000_I2CCMD_RESET 0x10000000
216#define E1000_I2CCMD_READY 0x20000000
217#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
218#define E1000_I2CCMD_ERROR 0x80000000
219#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
220#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
221#define E1000_MAX_SGMII_PHY_REG_ADDR 255
222#define E1000_I2CCMD_PHY_TIMEOUT 200
223#define E1000_IVAR_VALID 0x80
224#define E1000_GPIE_NSICR 0x00000001
225#define E1000_GPIE_MSIX_MODE 0x00000010
226#define E1000_GPIE_EIAME 0x40000000
227#define E1000_GPIE_PBA 0x80000000
224
225/* Receive Descriptor bit definitions */
228
229/* Receive Descriptor bit definitions */
226#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
227#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
228#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
229#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
230#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
231#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
232#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
233#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
234#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
235#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
236#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
237#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
238#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
239#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
240#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
241#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
242#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
243#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
244#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
245#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
246#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
247#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
248#define E1000_RXD_SPC_PRI_SHIFT 13
249#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
250#define E1000_RXD_SPC_CFI_SHIFT 12
230#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
231#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
232#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
233#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
234#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
235#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
236#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
237#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
238#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
239#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
240#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
241#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
242#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
243#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
244#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
245#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
246#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
247#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
248#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
249#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
250#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
251#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
252#define E1000_RXD_SPC_PRI_SHIFT 13
253#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
254#define E1000_RXD_SPC_CFI_SHIFT 12
251
255
252#define E1000_RXDEXT_STATERR_LB 0x00040000
253#define E1000_RXDEXT_STATERR_CE 0x01000000
254#define E1000_RXDEXT_STATERR_SE 0x02000000
255#define E1000_RXDEXT_STATERR_SEQ 0x04000000
256#define E1000_RXDEXT_STATERR_CXE 0x10000000
257#define E1000_RXDEXT_STATERR_TCPE 0x20000000
258#define E1000_RXDEXT_STATERR_IPE 0x40000000
259#define E1000_RXDEXT_STATERR_RXE 0x80000000
256#define E1000_RXDEXT_STATERR_LB 0x00040000
257#define E1000_RXDEXT_STATERR_CE 0x01000000
258#define E1000_RXDEXT_STATERR_SE 0x02000000
259#define E1000_RXDEXT_STATERR_SEQ 0x04000000
260#define E1000_RXDEXT_STATERR_CXE 0x10000000
261#define E1000_RXDEXT_STATERR_TCPE 0x20000000
262#define E1000_RXDEXT_STATERR_IPE 0x40000000
263#define E1000_RXDEXT_STATERR_RXE 0x80000000
260
264
261#define E1000_RXDEXT_LSECH 0x01000000
262#define E1000_RXDEXT_LSECE_MASK 0x60000000
263#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000
264#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000
265#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
266#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000
265#define E1000_RXDEXT_LSECH 0x01000000
266#define E1000_RXDEXT_LSECE_MASK 0x60000000
267#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000
268#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000
269#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
270#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000
267
268/* mask to determine if packets should be dropped due to frame errors */
269#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
271
272/* mask to determine if packets should be dropped due to frame errors */
273#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
270 E1000_RXD_ERR_CE | \
271 E1000_RXD_ERR_SE | \
272 E1000_RXD_ERR_SEQ | \
273 E1000_RXD_ERR_CXE | \
274 E1000_RXD_ERR_RXE)
274 E1000_RXD_ERR_CE | \
275 E1000_RXD_ERR_SE | \
276 E1000_RXD_ERR_SEQ | \
277 E1000_RXD_ERR_CXE | \
278 E1000_RXD_ERR_RXE)
275
276/* Same mask, but for extended and packet split descriptors */
277#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
279
280/* Same mask, but for extended and packet split descriptors */
281#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
278 E1000_RXDEXT_STATERR_CE | \
279 E1000_RXDEXT_STATERR_SE | \
280 E1000_RXDEXT_STATERR_SEQ | \
281 E1000_RXDEXT_STATERR_CXE | \
282 E1000_RXDEXT_STATERR_RXE)
282 E1000_RXDEXT_STATERR_CE | \
283 E1000_RXDEXT_STATERR_SE | \
284 E1000_RXDEXT_STATERR_SEQ | \
285 E1000_RXDEXT_STATERR_CXE | \
286 E1000_RXDEXT_STATERR_RXE)
283
287
284#define E1000_MRQC_ENABLE_MASK 0x00000007
285#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
286#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
287#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
288#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
289#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
290#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
291#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
292#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
293#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
288#define E1000_MRQC_ENABLE_MASK 0x00000007
289#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
290#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
291#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
292#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
293#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
294#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
295#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
296#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
297#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
294
298
295#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
296#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
299#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
300#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
297
298/* Management Control */
301
302/* Management Control */
299#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
300#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
301#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
302#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
303#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
304#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
305#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
306#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
307#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
303#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
304#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
305#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
306#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
307#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
308#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
309#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
310#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
311#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
308/* Enable Neighbor Discovery Filtering */
312/* Enable Neighbor Discovery Filtering */
309#define E1000_MANC_NEIGHBOR_EN 0x00004000
310#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
311#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
312#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
313#define E1000_MANC_NEIGHBOR_EN 0x00004000
314#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
315#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
316#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
313#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
317#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
314#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
315#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
318#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
319#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
316/* Enable MAC address filtering */
320/* Enable MAC address filtering */
317#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
321#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
318/* Enable MNG packets to host memory */
322/* Enable MNG packets to host memory */
319#define E1000_MANC_EN_MNG2HOST 0x00200000
323#define E1000_MANC_EN_MNG2HOST 0x00200000
320/* Enable IP address filtering */
324/* Enable IP address filtering */
321#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
322#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
323#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
324#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
325#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
326#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
327#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
328#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
329#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
330#define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */
331#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabled or not */
325#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
326#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */
327#define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */
328#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
329#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
330#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
331#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
332#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
333#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
334#define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */
335#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */
332
336
333#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
334#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
337#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
338#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
335
339
336#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
337#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
338#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
339#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
340#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
341#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
342#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
343#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
340
341/* Receive Control */
344
345/* Receive Control */
342#define E1000_RCTL_RST 0x00000001 /* Software reset */
343#define E1000_RCTL_EN 0x00000002 /* enable */
344#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
345#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
346#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
347#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
348#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
349#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
350#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
351#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
352#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
353#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
354#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
355#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */
356#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */
357#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
358#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
359#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
360#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
361#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
362#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
363#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
346#define E1000_RCTL_RST 0x00000001 /* Software reset */
347#define E1000_RCTL_EN 0x00000002 /* enable */
348#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
349#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
350#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
351#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
352#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
353#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
354#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
355#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
356#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
357#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
358#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
359#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */
360#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */
361#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
362#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
363#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
364#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
365#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
366#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
367#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
364/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
368/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
365#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
366#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
367#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
368#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
369#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
370#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
371#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
372#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
369/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
373/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
370#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
371#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
372#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
373#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
374#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
375#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
376#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
377#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
378#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
379#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
380#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
381#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
374#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
375#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
376#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
377#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
378#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
379#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
380#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
381#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
382#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
383#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
384#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
385#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
382
383/*
384 * Use byte values for the following shift parameters
385 * Usage:
386 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
386
387/*
388 * Use byte values for the following shift parameters
389 * Usage:
390 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
387 * E1000_PSRCTL_BSIZE0_MASK) |
388 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
389 * E1000_PSRCTL_BSIZE1_MASK) |
390 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
391 * E1000_PSRCTL_BSIZE2_MASK) |
392 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
393 * E1000_PSRCTL_BSIZE3_MASK))
391 * E1000_PSRCTL_BSIZE0_MASK) |
392 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
393 * E1000_PSRCTL_BSIZE1_MASK) |
394 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
395 * E1000_PSRCTL_BSIZE2_MASK) |
396 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
397 * E1000_PSRCTL_BSIZE3_MASK))
394 * where value0 = [128..16256], default=256
395 * value1 = [1024..64512], default=4096
396 * value2 = [0..64512], default=4096
397 * value3 = [0..64512], default=0
398 */
399
398 * where value0 = [128..16256], default=256
399 * value1 = [1024..64512], default=4096
400 * value2 = [0..64512], default=4096
401 * value3 = [0..64512], default=0
402 */
403
400#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
401#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
402#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
403#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
404#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
405#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
406#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
407#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
404
408
405#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
406#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
407#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
408#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
409#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
410#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
411#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
412#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
409
410/* SWFW_SYNC Definitions */
413
414/* SWFW_SYNC Definitions */
411#define E1000_SWFW_EEP_SM 0x01
412#define E1000_SWFW_PHY0_SM 0x02
413#define E1000_SWFW_PHY1_SM 0x04
414#define E1000_SWFW_CSR_SM 0x08
415#define E1000_SWFW_PHY2_SM 0x20
416#define E1000_SWFW_PHY3_SM 0x40
417#define E1000_SWFW_SW_MNG_SM 0x400
415#define E1000_SWFW_EEP_SM 0x01
416#define E1000_SWFW_PHY0_SM 0x02
417#define E1000_SWFW_PHY1_SM 0x04
418#define E1000_SWFW_CSR_SM 0x08
419#define E1000_SWFW_PHY2_SM 0x20
420#define E1000_SWFW_PHY3_SM 0x40
421#define E1000_SWFW_SW_MNG_SM 0x400
418
419/* FACTPS Definitions */
422
423/* FACTPS Definitions */
420#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
424#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
421/* Device Control */
425/* Device Control */
422#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
423#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
424#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
426#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
427#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
428#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
425#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
429#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
426#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
427#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
428#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
429#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
430#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
431#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
432#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
433#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
434#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
435#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
436#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
437#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
438#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
439#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
440#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
441 * indication in SDP[0] */
442#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
443 * PHYRST_N pin */
444#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
445 * LINK_0 and LINK_1 pins */
446#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
447#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
448#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
449#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
450#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
451#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
452#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
453#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
454#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
455#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
456#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
457#define E1000_CTRL_RST 0x04000000 /* Global reset */
458#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
459#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
460#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
461#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
462#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
463#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
464#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
430#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
431#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
432#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
433#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
434#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
435#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
436#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
437#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
438#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
439#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
440#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
441#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
442#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
443#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
444/* Defined polarity of Dock/Undock indication in SDP[0] */
445#define E1000_CTRL_D_UD_POLARITY 0x00004000
446/* Reset both PHY ports, through PHYRST_N pin */
447#define E1000_CTRL_FORCE_PHY_RESET 0x00008000
448/* enable link status from external LINK_0 and LINK_1 pins */
449#define E1000_CTRL_EXT_LINK_EN 0x00010000
450#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
451#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
452#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
453#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
454#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
455#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
456#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
457#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
458#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
459#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
460#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
461#define E1000_CTRL_RST 0x04000000 /* Global reset */
462#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
463#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
464#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
465#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
466#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
467#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
468#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
465
466/*
467 * Bit definitions for the Management Data IO (MDIO) and Management Data
468 * Clock (MDC) pins in the Device Control Register.
469 */
469
470/*
471 * Bit definitions for the Management Data IO (MDIO) and Management Data
472 * Clock (MDC) pins in the Device Control Register.
473 */
470#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
471#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
472#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
473#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
474#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
475#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
476#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
477#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
474#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
475#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
476#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
477#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
478#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
479#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
480#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
481#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
478
482
479#define E1000_CONNSW_ENRGSRC 0x4
480#define E1000_PCS_CFG_PCS_EN 8
481#define E1000_PCS_LCTL_FLV_LINK_UP 1
482#define E1000_PCS_LCTL_FSV_10 0
483#define E1000_PCS_LCTL_FSV_100 2
484#define E1000_PCS_LCTL_FSV_1000 4
485#define E1000_PCS_LCTL_FDV_FULL 8
486#define E1000_PCS_LCTL_FSD 0x10
487#define E1000_PCS_LCTL_FORCE_LINK 0x20
488#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
489#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
490#define E1000_PCS_LCTL_AN_ENABLE 0x10000
491#define E1000_PCS_LCTL_AN_RESTART 0x20000
492#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
493#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
494#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
495#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
496#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
497#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
498#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
483#define E1000_CONNSW_ENRGSRC 0x4
484#define E1000_PCS_CFG_PCS_EN 8
485#define E1000_PCS_LCTL_FLV_LINK_UP 1
486#define E1000_PCS_LCTL_FSV_10 0
487#define E1000_PCS_LCTL_FSV_100 2
488#define E1000_PCS_LCTL_FSV_1000 4
489#define E1000_PCS_LCTL_FDV_FULL 8
490#define E1000_PCS_LCTL_FSD 0x10
491#define E1000_PCS_LCTL_FORCE_LINK 0x20
492#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
493#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
494#define E1000_PCS_LCTL_AN_ENABLE 0x10000
495#define E1000_PCS_LCTL_AN_RESTART 0x20000
496#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
497#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
498#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
499#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
500#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
501#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
502#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
499
503
500#define E1000_PCS_LSTS_LINK_OK 1
501#define E1000_PCS_LSTS_SPEED_10 0
502#define E1000_PCS_LSTS_SPEED_100 2
503#define E1000_PCS_LSTS_SPEED_1000 4
504#define E1000_PCS_LSTS_DUPLEX_FULL 8
505#define E1000_PCS_LSTS_SYNK_OK 0x10
506#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
507#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
508#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
509#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
510#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
504#define E1000_PCS_LSTS_LINK_OK 1
505#define E1000_PCS_LSTS_SPEED_10 0
506#define E1000_PCS_LSTS_SPEED_100 2
507#define E1000_PCS_LSTS_SPEED_1000 4
508#define E1000_PCS_LSTS_DUPLEX_FULL 8
509#define E1000_PCS_LSTS_SYNK_OK 0x10
510#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
511#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
512#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
513#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
514#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
511
512/* Device Status */
515
516/* Device Status */
513#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
514#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
515#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
516#define E1000_STATUS_FUNC_SHIFT 2
517#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
518#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
519#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
520#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
521#define E1000_STATUS_SPEED_MASK 0x000000C0
522#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
523#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
524#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
525#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
526#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
527#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
528#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state.
529 * Clear on write '0'. */
530#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
531#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
532#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
533#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
534#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
535#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
536#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
537#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
538#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
539#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
540#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution
541 * disabled */
542#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
543#define E1000_STATUS_FUSE_8 0x04000000
544#define E1000_STATUS_FUSE_9 0x08000000
545#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
546#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
517#define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
518#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
519#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
520#define E1000_STATUS_FUNC_SHIFT 2
521#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
522#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
523#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
524#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
525#define E1000_STATUS_SPEED_MASK 0x000000C0
526#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
527#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
528#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
529#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
530#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
531#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
532/* Change in Dock/Undock state clear on write '0'. */
533#define E1000_STATUS_DOCK_CI 0x00000800
534#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
535#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
536#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
537#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
538#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
539#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
540#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */
541#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
542#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
543#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
544/* BMC external code execution disabled */
545#define E1000_STATUS_BMC_LITE 0x01000000
546#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
547#define E1000_STATUS_FUSE_8 0x04000000
548#define E1000_STATUS_FUSE_9 0x08000000
549#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */
550#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */
547
548/* Constants used to interpret the masked PCI-X bus speed. */
551
552/* Constants used to interpret the masked PCI-X bus speed. */
549#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
550#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
551#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
553#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
554#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
555#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
552
556
553#define SPEED_10 10
554#define SPEED_100 100
555#define SPEED_1000 1000
556#define HALF_DUPLEX 1
557#define FULL_DUPLEX 2
557#define SPEED_10 10
558#define SPEED_100 100
559#define SPEED_1000 1000
560#define HALF_DUPLEX 1
561#define FULL_DUPLEX 2
558
562
559#define PHY_FORCE_TIME 20
563#define PHY_FORCE_TIME 20
560
564
561#define ADVERTISE_10_HALF 0x0001
562#define ADVERTISE_10_FULL 0x0002
563#define ADVERTISE_100_HALF 0x0004
564#define ADVERTISE_100_FULL 0x0008
565#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
566#define ADVERTISE_1000_FULL 0x0020
565#define ADVERTISE_10_HALF 0x0001
566#define ADVERTISE_10_FULL 0x0002
567#define ADVERTISE_100_HALF 0x0004
568#define ADVERTISE_100_FULL 0x0008
569#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
570#define ADVERTISE_1000_FULL 0x0020
567
568/* 1000/H is not supported, nor spec-compliant. */
571
572/* 1000/H is not supported, nor spec-compliant. */
569#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
570 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
571 ADVERTISE_1000_FULL)
572#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
573 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
574#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
575#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
576#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
577 ADVERTISE_1000_FULL)
578#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
573#define E1000_ALL_SPEED_DUPLEX ( \
574 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
575 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
576#define E1000_ALL_NOT_GIG ( \
577 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
578 ADVERTISE_100_FULL)
579#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
580#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
581#define E1000_ALL_FULL_DUPLEX ( \
582 ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
583#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
579
584
580#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
585#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
581
582/* LED Control */
586
587/* LED Control */
583#define E1000_PHY_LED0_MODE_MASK 0x00000007
584#define E1000_PHY_LED0_IVRT 0x00000008
585#define E1000_PHY_LED0_BLINK 0x00000010
586#define E1000_PHY_LED0_MASK 0x0000001F
588#define E1000_PHY_LED0_MODE_MASK 0x00000007
589#define E1000_PHY_LED0_IVRT 0x00000008
590#define E1000_PHY_LED0_BLINK 0x00000010
591#define E1000_PHY_LED0_MASK 0x0000001F
587
592
588#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
589#define E1000_LEDCTL_LED0_MODE_SHIFT 0
590#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
591#define E1000_LEDCTL_LED0_IVRT 0x00000040
592#define E1000_LEDCTL_LED0_BLINK 0x00000080
593#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
594#define E1000_LEDCTL_LED1_MODE_SHIFT 8
595#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
596#define E1000_LEDCTL_LED1_IVRT 0x00004000
597#define E1000_LEDCTL_LED1_BLINK 0x00008000
598#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
599#define E1000_LEDCTL_LED2_MODE_SHIFT 16
600#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
601#define E1000_LEDCTL_LED2_IVRT 0x00400000
602#define E1000_LEDCTL_LED2_BLINK 0x00800000
603#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
604#define E1000_LEDCTL_LED3_MODE_SHIFT 24
605#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
606#define E1000_LEDCTL_LED3_IVRT 0x40000000
607#define E1000_LEDCTL_LED3_BLINK 0x80000000
593#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
594#define E1000_LEDCTL_LED0_MODE_SHIFT 0
595#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
596#define E1000_LEDCTL_LED0_IVRT 0x00000040
597#define E1000_LEDCTL_LED0_BLINK 0x00000080
598#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
599#define E1000_LEDCTL_LED1_MODE_SHIFT 8
600#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
601#define E1000_LEDCTL_LED1_IVRT 0x00004000
602#define E1000_LEDCTL_LED1_BLINK 0x00008000
603#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
604#define E1000_LEDCTL_LED2_MODE_SHIFT 16
605#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
606#define E1000_LEDCTL_LED2_IVRT 0x00400000
607#define E1000_LEDCTL_LED2_BLINK 0x00800000
608#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
609#define E1000_LEDCTL_LED3_MODE_SHIFT 24
610#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
611#define E1000_LEDCTL_LED3_IVRT 0x40000000
612#define E1000_LEDCTL_LED3_BLINK 0x80000000
608
613
609#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
610#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
611#define E1000_LEDCTL_MODE_LINK_UP 0x2
612#define E1000_LEDCTL_MODE_ACTIVITY 0x3
613#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
614#define E1000_LEDCTL_MODE_LINK_10 0x5
615#define E1000_LEDCTL_MODE_LINK_100 0x6
616#define E1000_LEDCTL_MODE_LINK_1000 0x7
617#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
618#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
619#define E1000_LEDCTL_MODE_COLLISION 0xA
620#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
621#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
622#define E1000_LEDCTL_MODE_PAUSED 0xD
623#define E1000_LEDCTL_MODE_LED_ON 0xE
624#define E1000_LEDCTL_MODE_LED_OFF 0xF
614#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
615#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
616#define E1000_LEDCTL_MODE_LINK_UP 0x2
617#define E1000_LEDCTL_MODE_ACTIVITY 0x3
618#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
619#define E1000_LEDCTL_MODE_LINK_10 0x5
620#define E1000_LEDCTL_MODE_LINK_100 0x6
621#define E1000_LEDCTL_MODE_LINK_1000 0x7
622#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
623#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
624#define E1000_LEDCTL_MODE_COLLISION 0xA
625#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
626#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
627#define E1000_LEDCTL_MODE_PAUSED 0xD
628#define E1000_LEDCTL_MODE_LED_ON 0xE
629#define E1000_LEDCTL_MODE_LED_OFF 0xF
625
626/* Transmit Descriptor bit definitions */
630
631/* Transmit Descriptor bit definitions */
627#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
628#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
629#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
630#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
631#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
632#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
633#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
634#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
635#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
636#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
637#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
638#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
639#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
640#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
641#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
642#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
643#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
644#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
645#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
646#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
647#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
632#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
633#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
634#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
635#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
636#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
637#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
638#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
639#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
640#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
641#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
642#define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
643#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
644#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
645#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
646#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
647#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
648#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
649#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
650#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
651#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
652#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
648/* Extended desc bits for Linksec and timesync */
653/* Extended desc bits for Linksec and timesync */
649#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */
650#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
654#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */
655#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
651
652/* Transmit Control */
656
657/* Transmit Control */
653#define E1000_TCTL_RST 0x00000001 /* software reset */
654#define E1000_TCTL_EN 0x00000002 /* enable Tx */
655#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
656#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
657#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
658#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
659#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
660#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
661#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
662#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
663#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
658#define E1000_TCTL_RST 0x00000001 /* software reset */
659#define E1000_TCTL_EN 0x00000002 /* enable Tx */
660#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
661#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
662#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
663#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
664#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
665#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
666#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
667#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
668#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
664
665/* Transmit Arbitration Count */
669
670/* Transmit Arbitration Count */
666#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
671#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
667
668/* SerDes Control */
672
673/* SerDes Control */
669#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
674#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
670
671/* Receive Checksum Control */
675
676/* Receive Checksum Control */
672#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
673#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
674#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
675#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
676#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
677#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
678#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
677#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
678#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
679#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
680#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
681#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
682#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
683#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
679
680/* Header split receive */
684
685/* Header split receive */
681#define E1000_RFCTL_ISCSI_DIS 0x00000001
682#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
683#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
684#define E1000_RFCTL_NFSW_DIS 0x00000040
685#define E1000_RFCTL_NFSR_DIS 0x00000080
686#define E1000_RFCTL_NFS_VER_MASK 0x00000300
687#define E1000_RFCTL_NFS_VER_SHIFT 8
688#define E1000_RFCTL_IPV6_DIS 0x00000400
689#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
690#define E1000_RFCTL_ACK_DIS 0x00001000
691#define E1000_RFCTL_ACKD_DIS 0x00002000
692#define E1000_RFCTL_IPFRSP_DIS 0x00004000
693#define E1000_RFCTL_EXTEN 0x00008000
694#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
695#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
696#define E1000_RFCTL_LEF 0x00040000
686#define E1000_RFCTL_ISCSI_DIS 0x00000001
687#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
688#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
689#define E1000_RFCTL_NFSW_DIS 0x00000040
690#define E1000_RFCTL_NFSR_DIS 0x00000080
691#define E1000_RFCTL_NFS_VER_MASK 0x00000300
692#define E1000_RFCTL_NFS_VER_SHIFT 8
693#define E1000_RFCTL_IPV6_DIS 0x00000400
694#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
695#define E1000_RFCTL_ACK_DIS 0x00001000
696#define E1000_RFCTL_ACKD_DIS 0x00002000
697#define E1000_RFCTL_IPFRSP_DIS 0x00004000
698#define E1000_RFCTL_EXTEN 0x00008000
699#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
700#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
701#define E1000_RFCTL_LEF 0x00040000
697
698/* Collision related configuration parameters */
702
703/* Collision related configuration parameters */
699#define E1000_COLLISION_THRESHOLD 15
700#define E1000_CT_SHIFT 4
701#define E1000_COLLISION_DISTANCE 63
702#define E1000_COLD_SHIFT 12
704#define E1000_COLLISION_THRESHOLD 15
705#define E1000_CT_SHIFT 4
706#define E1000_COLLISION_DISTANCE 63
707#define E1000_COLD_SHIFT 12
703
704/* Default values for the transmit IPG register */
708
709/* Default values for the transmit IPG register */
705#define DEFAULT_82542_TIPG_IPGT 10
706#define DEFAULT_82543_TIPG_IPGT_FIBER 9
707#define DEFAULT_82543_TIPG_IPGT_COPPER 8
710#define DEFAULT_82542_TIPG_IPGT 10
711#define DEFAULT_82543_TIPG_IPGT_FIBER 9
712#define DEFAULT_82543_TIPG_IPGT_COPPER 8
708
713
709#define E1000_TIPG_IPGT_MASK 0x000003FF
710#define E1000_TIPG_IPGR1_MASK 0x000FFC00
711#define E1000_TIPG_IPGR2_MASK 0x3FF00000
714#define E1000_TIPG_IPGT_MASK 0x000003FF
715#define E1000_TIPG_IPGR1_MASK 0x000FFC00
716#define E1000_TIPG_IPGR2_MASK 0x3FF00000
712
717
713#define DEFAULT_82542_TIPG_IPGR1 2
714#define DEFAULT_82543_TIPG_IPGR1 8
715#define E1000_TIPG_IPGR1_SHIFT 10
718#define DEFAULT_82542_TIPG_IPGR1 2
719#define DEFAULT_82543_TIPG_IPGR1 8
720#define E1000_TIPG_IPGR1_SHIFT 10
716
721
717#define DEFAULT_82542_TIPG_IPGR2 10
718#define DEFAULT_82543_TIPG_IPGR2 6
719#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
720#define E1000_TIPG_IPGR2_SHIFT 20
722#define DEFAULT_82542_TIPG_IPGR2 10
723#define DEFAULT_82543_TIPG_IPGR2 6
724#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
725#define E1000_TIPG_IPGR2_SHIFT 20
721
722/* Ethertype field values */
726
727/* Ethertype field values */
723#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
728#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
724
729
725#define ETHERNET_FCS_SIZE 4
726#define MAX_JUMBO_FRAME_SIZE 0x3F00
730#define ETHERNET_FCS_SIZE 4
731#define MAX_JUMBO_FRAME_SIZE 0x3F00
727
728/* Extended Configuration Control and Size */
732
733/* Extended Configuration Control and Size */
729#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
730#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
731#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
732#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
733#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
734#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
735#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
736#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
737#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
734#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
735#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
736#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
737#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
738#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
739#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
740#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
741#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
742#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
738
743
739#define E1000_PHY_CTRL_SPD_EN 0x00000001
740#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
741#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
742#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
743#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
744#define E1000_PHY_CTRL_SPD_EN 0x00000001
745#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
746#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
747#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
748#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
744
749
745#define E1000_KABGTXD_BGSQLBIAS 0x00050000
750#define E1000_KABGTXD_BGSQLBIAS 0x00050000
746
747/* PBA constants */
751
752/* PBA constants */
748#define E1000_PBA_6K 0x0006 /* 6KB */
749#define E1000_PBA_8K 0x0008 /* 8KB */
750#define E1000_PBA_10K 0x000A /* 10KB */
751#define E1000_PBA_12K 0x000C /* 12KB */
752#define E1000_PBA_14K 0x000E /* 14KB */
753#define E1000_PBA_16K 0x0010 /* 16KB */
754#define E1000_PBA_18K 0x0012
755#define E1000_PBA_20K 0x0014
756#define E1000_PBA_22K 0x0016
757#define E1000_PBA_24K 0x0018
758#define E1000_PBA_26K 0x001A
759#define E1000_PBA_30K 0x001E
760#define E1000_PBA_32K 0x0020
761#define E1000_PBA_34K 0x0022
762#define E1000_PBA_35K 0x0023
763#define E1000_PBA_38K 0x0026
764#define E1000_PBA_40K 0x0028
765#define E1000_PBA_48K 0x0030 /* 48KB */
766#define E1000_PBA_64K 0x0040 /* 64KB */
753#define E1000_PBA_6K 0x0006 /* 6KB */
754#define E1000_PBA_8K 0x0008 /* 8KB */
755#define E1000_PBA_10K 0x000A /* 10KB */
756#define E1000_PBA_12K 0x000C /* 12KB */
757#define E1000_PBA_14K 0x000E /* 14KB */
758#define E1000_PBA_16K 0x0010 /* 16KB */
759#define E1000_PBA_18K 0x0012
760#define E1000_PBA_20K 0x0014
761#define E1000_PBA_22K 0x0016
762#define E1000_PBA_24K 0x0018
763#define E1000_PBA_26K 0x001A
764#define E1000_PBA_30K 0x001E
765#define E1000_PBA_32K 0x0020
766#define E1000_PBA_34K 0x0022
767#define E1000_PBA_35K 0x0023
768#define E1000_PBA_38K 0x0026
769#define E1000_PBA_40K 0x0028
770#define E1000_PBA_48K 0x0030 /* 48KB */
771#define E1000_PBA_64K 0x0040 /* 64KB */
767
772
768#define E1000_PBS_16K E1000_PBA_16K
769#define E1000_PBS_24K E1000_PBA_24K
773#define E1000_PBA_RXA_MASK 0xFFFF;
770
774
771#define IFS_MAX 80
772#define IFS_MIN 40
773#define IFS_RATIO 4
774#define IFS_STEP 10
775#define MIN_NUM_XMITS 1000
775#define E1000_PBS_16K E1000_PBA_16K
776#define E1000_PBS_24K E1000_PBA_24K
776
777
778#define IFS_MAX 80
779#define IFS_MIN 40
780#define IFS_RATIO 4
781#define IFS_STEP 10
782#define MIN_NUM_XMITS 1000
783
777/* SW Semaphore Register */
784/* SW Semaphore Register */
778#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
779#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
780#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
781#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
785#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
786#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
787#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
788#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
782
789
783#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
790#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
784
785/* Interrupt Cause Read */
791
792/* Interrupt Cause Read */
786#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
787#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
788#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
789#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
790#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
791#define E1000_ICR_RXO 0x00000040 /* Rx overrun */
792#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
793#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
794#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
795#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
796#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
797#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
798#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
799#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
800#define E1000_ICR_TXD_LOW 0x00008000
801#define E1000_ICR_SRPD 0x00010000
802#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
803#define E1000_ICR_MNG 0x00040000 /* Manageability event */
804#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
805#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
806#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver
807 * should claim the interrupt */
808#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
809#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
810#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
811#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
812#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
813#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
814#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
815#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW
816 * bit in the FWSM */
817#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates
818 * an interrupt */
819#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
820#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
821#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
822#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
823#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
824#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
825#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
826#define E1000_ICR_FER 0x00400000 /* Fatal Error */
793#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
794#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
795#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
796#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
797#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
798#define E1000_ICR_RXO 0x00000040 /* Rx overrun */
799#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
800#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
801#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
802#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
803#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
804#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
805#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
806#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
807#define E1000_ICR_TXD_LOW 0x00008000
808#define E1000_ICR_SRPD 0x00010000
809#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
810#define E1000_ICR_MNG 0x00040000 /* Manageability event */
811#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
812#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
813/* If this bit asserted, the driver should claim the interrupt */
814#define E1000_ICR_INT_ASSERTED 0x80000000
815#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
816#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
817#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
818#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
819#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
820#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
821#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
822/* FW changed the status of DISSW bit in the FWSM */
823#define E1000_ICR_DSW 0x00000020
824/* LAN connected device generates an interrupt */
825#define E1000_ICR_PHYINT 0x00001000
826#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
827#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
828#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
829#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
830#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
831#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
832#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
833#define E1000_ICR_FER 0x00400000 /* Fatal Error */
827
834
828#define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
829#define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
835#define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
836#define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
837
838#define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
839#define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */
840
830/* PBA ECC Register */
841/* PBA ECC Register */
831#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
832#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
833#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
834#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
835#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
842#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
843#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
844#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
845#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
846#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
836
837/* Extended Interrupt Cause Read */
847
848/* Extended Interrupt Cause Read */
838#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
839#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
840#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
841#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
842#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
843#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
844#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
845#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
846#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
847#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
849#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
850#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
851#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
852#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
853#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
854#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
855#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
856#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
857#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
858#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
848/* TCP Timer */
859/* TCP Timer */
849#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
850#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
851#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
852#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
860#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
861#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
862#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
863#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
853
854/*
855 * This defines the bits that are set in the Interrupt Mask
856 * Set/Read Register. Each bit is documented below:
857 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
858 * o RXSEQ = Receive Sequence Error
859 */
860#define POLL_IMS_ENABLE_MASK ( \
864
865/*
866 * This defines the bits that are set in the Interrupt Mask
867 * Set/Read Register. Each bit is documented below:
868 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
869 * o RXSEQ = Receive Sequence Error
870 */
871#define POLL_IMS_ENABLE_MASK ( \
861 E1000_IMS_RXDMT0 | \
862 E1000_IMS_RXSEQ)
872 E1000_IMS_RXDMT0 | \
873 E1000_IMS_RXSEQ)
863
864/*
865 * This defines the bits that are set in the Interrupt Mask
866 * Set/Read Register. Each bit is documented below:
867 * o RXT0 = Receiver Timer Interrupt (ring 0)
868 * o TXDW = Transmit Descriptor Written Back
869 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
870 * o RXSEQ = Receive Sequence Error
871 * o LSC = Link Status Change
872 */
873#define IMS_ENABLE_MASK ( \
874
875/*
876 * This defines the bits that are set in the Interrupt Mask
877 * Set/Read Register. Each bit is documented below:
878 * o RXT0 = Receiver Timer Interrupt (ring 0)
879 * o TXDW = Transmit Descriptor Written Back
880 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
881 * o RXSEQ = Receive Sequence Error
882 * o LSC = Link Status Change
883 */
884#define IMS_ENABLE_MASK ( \
874 E1000_IMS_RXT0 | \
875 E1000_IMS_TXDW | \
876 E1000_IMS_RXDMT0 | \
877 E1000_IMS_RXSEQ | \
878 E1000_IMS_LSC)
885 E1000_IMS_RXT0 | \
886 E1000_IMS_TXDW | \
887 E1000_IMS_RXDMT0 | \
888 E1000_IMS_RXSEQ | \
889 E1000_IMS_LSC)
879
880/* Interrupt Mask Set */
890
891/* Interrupt Mask Set */
881#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
882#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
883#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
884#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
885#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
886#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
887#define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
888#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
889#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
890#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
891#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
892#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
893#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
894#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
895#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
896#define E1000_IMS_SRPD E1000_ICR_SRPD
897#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
898#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
899#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
900#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
901#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
902 * parity error */
903#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
904 * parity error */
905#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer
906 * parity error */
907#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity
908 * error */
909#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
910 * parity error */
911#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
912 * parity error */
913#define E1000_IMS_DSW E1000_ICR_DSW
914#define E1000_IMS_PHYINT E1000_ICR_PHYINT
915#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
916#define E1000_IMS_EPRST E1000_ICR_EPRST
917#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
918#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
919#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
920#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
921#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
922#define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
892#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
893#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
894#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
895#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
896#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
897#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
898#define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
899#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
900#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
901#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
902#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
903#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
904#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
905#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
906#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
907#define E1000_IMS_SRPD E1000_ICR_SRPD
908#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
909#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
910#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
911#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
912/* Q0 Rx desc FIFO parity error */
913#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
914/* Q0 Tx desc FIFO parity error */
915#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
916/* host arb read buffer parity error */
917#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
918/* packet buffer parity error */
919#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR
920/* Q1 Rx desc FIFO parity error */
921#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
922/* Q1 Tx desc FIFO parity error */
923#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
924#define E1000_IMS_DSW E1000_ICR_DSW
925#define E1000_IMS_PHYINT E1000_ICR_PHYINT
926#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
927#define E1000_IMS_EPRST E1000_ICR_EPRST
928#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
929#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
930#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
931#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
932#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
933#define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
923
934
924#define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
925#define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
935#define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
936#define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
926/* Extended Interrupt Mask Set */
937/* Extended Interrupt Mask Set */
927#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
928#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
929#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
930#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
931#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
932#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
933#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
934#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
935#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
936#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
938#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
939#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
940#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
941#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
942#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
943#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
944#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
945#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
946#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
947#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
937
938/* Interrupt Cause Set */
948
949/* Interrupt Cause Set */
939#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */
940#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
941#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
942#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
943#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
944#define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */
945#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
946#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
947#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
948#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
949#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
950#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
951#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
952#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
953#define E1000_ICS_SRPD E1000_ICR_SRPD
954#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
955#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
956#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
957#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
958#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
959 * parity error */
960#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
961 * parity error */
962#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer
963 * parity error */
964#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity
965 * error */
966#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
967 * parity error */
968#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
969 * parity error */
970#define E1000_ICS_DSW E1000_ICR_DSW
971#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
972#define E1000_ICS_PHYINT E1000_ICR_PHYINT
973#define E1000_ICS_EPRST E1000_ICR_EPRST
950#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */
951#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
952#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
953#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
954#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
955#define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */
956#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
957#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
958#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
959#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
960#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
961#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
962#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
963#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
964#define E1000_ICS_SRPD E1000_ICR_SRPD
965#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
966#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
967#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
968#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
969/* Q0 Rx desc FIFO parity error */
970#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
971/* Q0 Tx desc FIFO parity error */
972#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
973/* host arb read buffer parity error */
974#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
975/* packet buffer parity error */
976#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR
977/* Q1 Rx desc FIFO parity error */
978#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
979/* Q1 Tx desc FIFO parity error */
980#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
981#define E1000_ICS_DSW E1000_ICR_DSW
982#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
983#define E1000_ICS_PHYINT E1000_ICR_PHYINT
984#define E1000_ICS_EPRST E1000_ICR_EPRST
974
975/* Extended Interrupt Cause Set */
985
986/* Extended Interrupt Cause Set */
976#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
977#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
978#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
979#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
980#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
981#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
982#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
983#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
984#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
985#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
987#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
988#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
989#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
990#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
991#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
992#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
993#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
994#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
995#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
996#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
986
997
987#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
998#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
988/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
999/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
989#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
1000#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
990
991/* Transmit Descriptor Control */
1001
1002/* Transmit Descriptor Control */
992#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
993#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
994#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
995#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
996#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
997#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1003#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1004#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1005#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1006#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1007#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1008#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
998#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
999/* Enable the counting of descriptors still to be processed. */
1009#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
1010/* Enable the counting of descriptors still to be processed. */
1000#define E1000_TXDCTL_COUNT_DESC 0x00400000
1011#define E1000_TXDCTL_COUNT_DESC 0x00400000
1001
1002/* Flow Control Constants */
1012
1013/* Flow Control Constants */
1003#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1004#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1005#define FLOW_CONTROL_TYPE 0x8808
1014#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1015#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1016#define FLOW_CONTROL_TYPE 0x8808
1006
1007/* 802.1q VLAN Packet Size */
1017
1018/* 802.1q VLAN Packet Size */
1008#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
1009#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
1019#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
1020#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
1010
1011/* Receive Address */
1012/*
1013 * Number of high/low register pairs in the RAR. The RAR (Receive Address
1014 * Registers) holds the directed and multicast addresses that we monitor.
1015 * Technically, we have 16 spots. However, we reserve one of these spots
1016 * (RAR[15]) for our directed address used by controllers with
1017 * manageability enabled, allowing us room for 15 multicast addresses.
1018 */
1021
1022/* Receive Address */
1023/*
1024 * Number of high/low register pairs in the RAR. The RAR (Receive Address
1025 * Registers) holds the directed and multicast addresses that we monitor.
1026 * Technically, we have 16 spots. However, we reserve one of these spots
1027 * (RAR[15]) for our directed address used by controllers with
1028 * manageability enabled, allowing us room for 15 multicast addresses.
1029 */
1019#define E1000_RAR_ENTRIES 15
1020#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1021#define E1000_RAL_MAC_ADDR_LEN 4
1022#define E1000_RAH_MAC_ADDR_LEN 2
1023#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
1024#define E1000_RAH_POOL_MASK 0x03FC0000
1025#define E1000_RAH_POOL_SHIFT 18
1026#define E1000_RAH_POOL_1 0x00040000
1030#define E1000_RAR_ENTRIES 15
1031#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1032#define E1000_RAL_MAC_ADDR_LEN 4
1033#define E1000_RAH_MAC_ADDR_LEN 2
1034#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
1035#define E1000_RAH_POOL_MASK 0x03FC0000
1036#define E1000_RAH_POOL_SHIFT 18
1037#define E1000_RAH_POOL_1 0x00040000
1027
1028/* Error Codes */
1038
1039/* Error Codes */
1029#define E1000_SUCCESS 0
1030#define E1000_ERR_NVM 1
1031#define E1000_ERR_PHY 2
1032#define E1000_ERR_CONFIG 3
1033#define E1000_ERR_PARAM 4
1034#define E1000_ERR_MAC_INIT 5
1035#define E1000_ERR_PHY_TYPE 6
1036#define E1000_ERR_RESET 9
1037#define E1000_ERR_MASTER_REQUESTS_PENDING 10
1038#define E1000_ERR_HOST_INTERFACE_COMMAND 11
1039#define E1000_BLK_PHY_RESET 12
1040#define E1000_ERR_SWFW_SYNC 13
1041#define E1000_NOT_IMPLEMENTED 14
1042#define E1000_ERR_MBX 15
1043#define E1000_ERR_INVALID_ARGUMENT 16
1044#define E1000_ERR_NO_SPACE 17
1045#define E1000_ERR_NVM_PBA_SECTION 18
1040#define E1000_SUCCESS 0
1041#define E1000_ERR_NVM 1
1042#define E1000_ERR_PHY 2
1043#define E1000_ERR_CONFIG 3
1044#define E1000_ERR_PARAM 4
1045#define E1000_ERR_MAC_INIT 5
1046#define E1000_ERR_PHY_TYPE 6
1047#define E1000_ERR_RESET 9
1048#define E1000_ERR_MASTER_REQUESTS_PENDING 10
1049#define E1000_ERR_HOST_INTERFACE_COMMAND 11
1050#define E1000_BLK_PHY_RESET 12
1051#define E1000_ERR_SWFW_SYNC 13
1052#define E1000_NOT_IMPLEMENTED 14
1053#define E1000_ERR_MBX 15
1054#define E1000_ERR_INVALID_ARGUMENT 16
1055#define E1000_ERR_NO_SPACE 17
1056#define E1000_ERR_NVM_PBA_SECTION 18
1057#define E1000_ERR_I2C 19
1058#define E1000_ERR_INVM_VALUE_NOT_FOUND 20
1046
1047/* Loop limit on how long we wait for auto-negotiation to complete */
1059
1060/* Loop limit on how long we wait for auto-negotiation to complete */
1048#define FIBER_LINK_UP_LIMIT 50
1049#define COPPER_LINK_UP_LIMIT 10
1050#define PHY_AUTO_NEG_LIMIT 45
1051#define PHY_FORCE_LIMIT 20
1061#define FIBER_LINK_UP_LIMIT 50
1062#define COPPER_LINK_UP_LIMIT 10
1063#define PHY_AUTO_NEG_LIMIT 45
1064#define PHY_FORCE_LIMIT 20
1052/* Number of 100 microseconds we wait for PCI Express master disable */
1065/* Number of 100 microseconds we wait for PCI Express master disable */
1053#define MASTER_DISABLE_TIMEOUT 800
1066#define MASTER_DISABLE_TIMEOUT 800
1054/* Number of milliseconds we wait for PHY configuration done after MAC reset */
1067/* Number of milliseconds we wait for PHY configuration done after MAC reset */
1055#define PHY_CFG_TIMEOUT 100
1068#define PHY_CFG_TIMEOUT 100
1056/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
1069/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
1057#define MDIO_OWNERSHIP_TIMEOUT 10
1070#define MDIO_OWNERSHIP_TIMEOUT 10
1058/* Number of milliseconds for NVM auto read done after MAC reset. */
1071/* Number of milliseconds for NVM auto read done after MAC reset. */
1059#define AUTO_READ_DONE_TIMEOUT 10
1072#define AUTO_READ_DONE_TIMEOUT 10
1060
1061/* Flow Control */
1073
1074/* Flow Control */
1062#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1063#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1064#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1065#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1075#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1076#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1077#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1078#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1066
1067/* Transmit Configuration Word */
1079
1080/* Transmit Configuration Word */
1068#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1069#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1070#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1071#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1072#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1073#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1074#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1075#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1076#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1077#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1081#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1082#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1083#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1084#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1085#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1086#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1087#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1088#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1089#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1090#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1078
1079/* Receive Configuration Word */
1091
1092/* Receive Configuration Word */
1080#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1081#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1082#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1083#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1084#define E1000_RXCW_C 0x20000000 /* Receive config */
1085#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1086#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1093#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1094#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1095#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1096#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1097#define E1000_RXCW_C 0x20000000 /* Receive config */
1098#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1099#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1087
1100
1088#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1089#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
1101#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1102#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
1090
1103
1091#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1092#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1093#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
1094#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
1095#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
1096#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
1097#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
1098#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
1104#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1105#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1106#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
1107#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
1108#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
1109#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
1110#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
1111#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
1099
1112
1100#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
1101#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
1102#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
1103#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
1104#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
1105#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
1113#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
1114#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
1115#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
1116#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
1117#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
1118#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
1106
1119
1107#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
1108#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
1109#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
1110#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
1111#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
1112#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
1113#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
1114#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
1115#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
1116#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
1117#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
1120#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
1121#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
1122#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
1123#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
1124#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
1125#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
1126#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
1127#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
1128#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
1129#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
1130#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
1118
1131
1119#define E1000_TIMINCA_16NS_SHIFT 24
1132#define E1000_TIMINCA_16NS_SHIFT 24
1120/* TUPLE Filtering Configuration */
1133/* TUPLE Filtering Configuration */
1121#define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
1122#define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
1123#define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
1134#define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
1135#define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
1136#define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
1124/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
1137/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
1125#define E1000_TTQF_PROTOCOL_TCP 0x0
1138#define E1000_TTQF_PROTOCOL_TCP 0x0
1126/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1139/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1127#define E1000_TTQF_PROTOCOL_UDP 0x1
1140#define E1000_TTQF_PROTOCOL_UDP 0x1
1128/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1141/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1129#define E1000_TTQF_PROTOCOL_SCTP 0x2
1130#define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
1131#define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
1132#define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
1133#define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
1134#define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
1135#define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
1136#define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
1137#define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
1142#define E1000_TTQF_PROTOCOL_SCTP 0x2
1143#define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
1144#define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
1145#define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
1146#define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
1147#define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
1148#define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
1149#define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
1150#define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
1138
1151
1139#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
1140#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
1141#define E1000_MDICNFG_PHY_MASK 0x03E00000
1142#define E1000_MDICNFG_PHY_SHIFT 21
1152#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
1153#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
1154#define E1000_MDICNFG_PHY_MASK 0x03E00000
1155#define E1000_MDICNFG_PHY_SHIFT 21
1143
1156
1144#define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
1145#define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
1146#define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
1147#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
1148#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */
1157#define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
1158#define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
1159#define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
1160#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
1161#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
1149
1162
1150/* Powerville EEE defines */
1151#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Enable 1G AN */
1152#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Enable 100M AN */
1153#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
1154#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
1155#define E1000_EEER_LPI_FC 0x00040000 /* EEER Enable on Flow Control*/
1163/* I350 EEE defines */
1164#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
1165#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
1166#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
1167#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
1168#define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
1156/* EEE status */
1169/* EEE status */
1157#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability negotiated */
1158#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
1159#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
1170#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
1171#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
1172#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
1160
1161/* PCI Express Control */
1173
1174/* PCI Express Control */
1162#define E1000_GCR_RXD_NO_SNOOP 0x00000001
1163#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1164#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1165#define E1000_GCR_TXD_NO_SNOOP 0x00000008
1166#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1167#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1168#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
1169#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
1170#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
1171#define E1000_GCR_CAP_VER2 0x00040000
1175#define E1000_GCR_RXD_NO_SNOOP 0x00000001
1176#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1177#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1178#define E1000_GCR_TXD_NO_SNOOP 0x00000008
1179#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1180#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1181#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
1182#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
1183#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
1184#define E1000_GCR_CAP_VER2 0x00040000
1172
1185
1173#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1174 E1000_GCR_RXDSCW_NO_SNOOP | \
1175 E1000_GCR_RXDSCR_NO_SNOOP | \
1176 E1000_GCR_TXD_NO_SNOOP | \
1177 E1000_GCR_TXDSCW_NO_SNOOP | \
1178 E1000_GCR_TXDSCR_NO_SNOOP)
1186#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1187 E1000_GCR_RXDSCW_NO_SNOOP | \
1188 E1000_GCR_RXDSCR_NO_SNOOP | \
1189 E1000_GCR_TXD_NO_SNOOP | \
1190 E1000_GCR_TXDSCW_NO_SNOOP | \
1191 E1000_GCR_TXDSCR_NO_SNOOP)
1179
1192
1193/* mPHY address control and data registers */
1194#define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
1195#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
1196#define E1000_MPHY_DATA 0x0E10 /* Data Register */
1197
1198/* AFE CSR Offset for PCS CLK */
1199#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
1200/* Override for near end digital loopback. */
1201#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
1202
1180/* PHY Control Register */
1203/* PHY Control Register */
1181#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1182#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1183#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1184#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1185#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1186#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1187#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1188#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1189#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1190#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1191#define MII_CR_SPEED_1000 0x0040
1192#define MII_CR_SPEED_100 0x2000
1193#define MII_CR_SPEED_10 0x0000
1204#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1205#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1206#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1207#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1208#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1209#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1210#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1211#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1212#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1213#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1214#define MII_CR_SPEED_1000 0x0040
1215#define MII_CR_SPEED_100 0x2000
1216#define MII_CR_SPEED_10 0x0000
1194
1195/* PHY Status Register */
1217
1218/* PHY Status Register */
1196#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1197#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1198#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1199#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1200#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1201#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1219#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1220#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1221#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1222#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1223#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1224#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1202#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1225#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1203#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1204#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1205#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1206#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1207#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1208#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1209#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1210#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1226#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1227#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1228#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1229#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1230#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1231#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1232#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1233#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1211
1212/* Autoneg Advertisement Register */
1234
1235/* Autoneg Advertisement Register */
1213#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1214#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1215#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1216#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1217#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1218#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1219#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1220#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1221#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1222#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1236#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1237#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1238#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1239#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1240#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1241#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1242#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1243#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1244#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1245#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1223
1224/* Link Partner Ability Register (Base Page) */
1246
1247/* Link Partner Ability Register (Base Page) */
1225#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1226#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1227#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1228#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1229#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1230#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1231#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1232#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1233#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1234#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1235#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1248#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1249#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
1250#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
1251#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
1252#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
1253#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1254#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1255#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
1256#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
1257#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
1258#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1236
1237/* Autoneg Expansion Register */
1259
1260/* Autoneg Expansion Register */
1238#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1239#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1240#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1241#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1242#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1261#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1262#define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
1263#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
1264#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
1265#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
1243
1244/* 1000BASE-T Control Register */
1266
1267/* 1000BASE-T Control Register */
1245#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1246#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1247#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1248#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1249 /* 0=DTE device */
1250#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1251 /* 0=Configure PHY as Slave */
1252#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1253 /* 0=Automatic Master/Slave config */
1268#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1269#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1270#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1271/* 1=Repeater/switch device port 0=DTE device */
1272#define CR_1000T_REPEATER_DTE 0x0400
1273/* 1=Configure PHY as Master 0=Configure PHY as Slave */
1274#define CR_1000T_MS_VALUE 0x0800
1275/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
1276#define CR_1000T_MS_ENABLE 0x1000
1254#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1277#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1255#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1256#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1257#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1258#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1278#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1279#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1280#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1281#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1259
1260/* 1000BASE-T Status Register */
1282
1283/* 1000BASE-T Status Register */
1261#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1262#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1263#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1264#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1265#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1266#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1267#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
1268#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1284#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
1285#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
1286#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1287#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1288#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1289#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1290#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
1291#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1269
1292
1270#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1293#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1271
1272/* PHY 1000 MII Register/Bit Definitions */
1273/* PHY Registers defined by IEEE */
1294
1295/* PHY 1000 MII Register/Bit Definitions */
1296/* PHY Registers defined by IEEE */
1274#define PHY_CONTROL 0x00 /* Control Register */
1275#define PHY_STATUS 0x01 /* Status Register */
1276#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1277#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1278#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1279#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1280#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1281#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1282#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1283#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1284#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1285#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1297#define PHY_CONTROL 0x00 /* Control Register */
1298#define PHY_STATUS 0x01 /* Status Register */
1299#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1300#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1301#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1302#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1303#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1304#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1305#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1306#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1307#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1308#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1286
1309
1287#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1310#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1288
1289/* NVM Control */
1311
1312/* NVM Control */
1290#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1291#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1292#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1293#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1294#define E1000_EECD_FWE_MASK 0x00000030
1295#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1296#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1297#define E1000_EECD_FWE_SHIFT 4
1298#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1299#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1300#define E1000_EECD_PRES 0x00000100 /* NVM Present */
1301#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1313#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1314#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1315#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1316#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1317#define E1000_EECD_FWE_MASK 0x00000030
1318#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1319#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1320#define E1000_EECD_FWE_SHIFT 4
1321#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1322#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1323#define E1000_EECD_PRES 0x00000100 /* NVM Present */
1324#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1325#define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1326#define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1327#define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1328#define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1302/* NVM Addressing bits based on type 0=small, 1=large */
1329/* NVM Addressing bits based on type 0=small, 1=large */
1303#define E1000_EECD_ADDR_BITS 0x00000400
1304#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1330#define E1000_EECD_ADDR_BITS 0x00000400
1331#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1305#ifndef E1000_NVM_GRANT_ATTEMPTS
1332#ifndef E1000_NVM_GRANT_ATTEMPTS
1306#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1333#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1307#endif
1334#endif
1308#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1309#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1310#define E1000_EECD_SIZE_EX_SHIFT 11
1311#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1312#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1313#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1314#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1315#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1316#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1317#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1318#define E1000_EECD_SECVAL_SHIFT 22
1319#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1335#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1336#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1337#define E1000_EECD_SIZE_EX_SHIFT 11
1338#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1339#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1340#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1341#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1342#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
1343#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1344#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1345#define E1000_EECD_SECVAL_SHIFT 22
1346#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1320
1347
1321#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1322#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
1323#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1324#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1325#define E1000_NVM_RW_REG_START 1 /* Start operation */
1326#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1327#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1328#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1329#define E1000_FLASH_UPDATES 2000
1348#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1349#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
1350#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1351#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1352#define E1000_NVM_RW_REG_START 1 /* Start operation */
1353#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1354#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1355#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1356#define E1000_FLASH_UPDATES 2000
1330
1331/* NVM Word Offsets */
1357
1358/* NVM Word Offsets */
1332#define NVM_COMPAT 0x0003
1333#define NVM_ID_LED_SETTINGS 0x0004
1334#define NVM_VERSION 0x0005
1335#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1336#define NVM_PHY_CLASS_WORD 0x0007
1337#define NVM_INIT_CONTROL1_REG 0x000A
1338#define NVM_INIT_CONTROL2_REG 0x000F
1339#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1340#define NVM_INIT_CONTROL3_PORT_B 0x0014
1341#define NVM_INIT_3GIO_3 0x001A
1342#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1343#define NVM_INIT_CONTROL3_PORT_A 0x0024
1344#define NVM_CFG 0x0012
1345#define NVM_FLASH_VERSION 0x0032
1346#define NVM_ALT_MAC_ADDR_PTR 0x0037
1347#define NVM_CHECKSUM_REG 0x003F
1348#define NVM_COMPATIBILITY_REG_3 0x0003
1349#define NVM_COMPATIBILITY_BIT_MASK 0x8000
1359#define NVM_COMPAT 0x0003
1360#define NVM_ID_LED_SETTINGS 0x0004
1361#define NVM_VERSION 0x0005
1362#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1363#define NVM_PHY_CLASS_WORD 0x0007
1364#define NVM_INIT_CONTROL1_REG 0x000A
1365#define NVM_INIT_CONTROL2_REG 0x000F
1366#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1367#define NVM_INIT_CONTROL3_PORT_B 0x0014
1368#define NVM_INIT_3GIO_3 0x001A
1369#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1370#define NVM_INIT_CONTROL3_PORT_A 0x0024
1371#define NVM_CFG 0x0012
1372#define NVM_FLASH_VERSION 0x0032
1373#define NVM_ALT_MAC_ADDR_PTR 0x0037
1374#define NVM_CHECKSUM_REG 0x003F
1375#define NVM_COMPATIBILITY_REG_3 0x0003
1376#define NVM_COMPATIBILITY_BIT_MASK 0x8000
1350
1377
1351#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1352#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1353#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1354#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1378#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1379#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1380#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1381#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1355
1382
1356#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
1383#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
1357
1358/* Mask bits for fields in Word 0x24 of the NVM */
1384
1385/* Mask bits for fields in Word 0x24 of the NVM */
1359#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1360#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */
1386#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1387#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1388/* Offset of Link Mode bits for 82575 up to Kawela */
1389#define NVM_WORD24_LNK_MODE_OFFSET 8
1390/* Offset of Link Mode bits for 82580 up */
1391#define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1361
1392
1393
1362/* Mask bits for fields in Word 0x0f of the NVM */
1394/* Mask bits for fields in Word 0x0f of the NVM */
1363#define NVM_WORD0F_PAUSE_MASK 0x3000
1364#define NVM_WORD0F_PAUSE 0x1000
1365#define NVM_WORD0F_ASM_DIR 0x2000
1366#define NVM_WORD0F_ANE 0x0800
1367#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1368#define NVM_WORD0F_LPLU 0x0001
1395#define NVM_WORD0F_PAUSE_MASK 0x3000
1396#define NVM_WORD0F_PAUSE 0x1000
1397#define NVM_WORD0F_ASM_DIR 0x2000
1398#define NVM_WORD0F_ANE 0x0800
1399#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1400#define NVM_WORD0F_LPLU 0x0001
1369
1370/* Mask bits for fields in Word 0x1a of the NVM */
1401
1402/* Mask bits for fields in Word 0x1a of the NVM */
1371#define NVM_WORD1A_ASPM_MASK 0x000C
1403#define NVM_WORD1A_ASPM_MASK 0x000C
1372
1373/* Mask bits for fields in Word 0x03 of the EEPROM */
1404
1405/* Mask bits for fields in Word 0x03 of the EEPROM */
1374#define NVM_COMPAT_LOM 0x0800
1406#define NVM_COMPAT_LOM 0x0800
1375
1376/* length of string needed to store PBA number */
1407
1408/* length of string needed to store PBA number */
1377#define E1000_PBANUM_LENGTH 11
1409#define E1000_PBANUM_LENGTH 11
1378
1379/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1410
1411/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1380#define NVM_SUM 0xBABA
1412#define NVM_SUM 0xBABA
1381
1413
1382#define NVM_MAC_ADDR_OFFSET 0
1383#define NVM_PBA_OFFSET_0 8
1384#define NVM_PBA_OFFSET_1 9
1385#define NVM_PBA_PTR_GUARD 0xFAFA
1386#define NVM_RESERVED_WORD 0xFFFF
1387#define NVM_PHY_CLASS_A 0x8000
1388#define NVM_SERDES_AMPLITUDE_MASK 0x000F
1389#define NVM_SIZE_MASK 0x1C00
1390#define NVM_SIZE_SHIFT 10
1391#define NVM_WORD_SIZE_BASE_SHIFT 6
1392#define NVM_SWDPIO_EXT_SHIFT 4
1414#define NVM_MAC_ADDR_OFFSET 0
1415#define NVM_PBA_OFFSET_0 8
1416#define NVM_PBA_OFFSET_1 9
1417#define NVM_PBA_PTR_GUARD 0xFAFA
1418#define NVM_RESERVED_WORD 0xFFFF
1419#define NVM_PHY_CLASS_A 0x8000
1420#define NVM_SERDES_AMPLITUDE_MASK 0x000F
1421#define NVM_SIZE_MASK 0x1C00
1422#define NVM_SIZE_SHIFT 10
1423#define NVM_WORD_SIZE_BASE_SHIFT 6
1424#define NVM_SWDPIO_EXT_SHIFT 4
1393
1394/* NVM Commands - Microwire */
1425
1426/* NVM Commands - Microwire */
1395#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1396#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1397#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1398#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1399#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1427#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1428#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1429#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1430#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1431#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1400
1401/* NVM Commands - SPI */
1432
1433/* NVM Commands - SPI */
1402#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1403#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1404#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1405#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1406#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1407#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
1408#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1409#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
1434#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1435#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1436#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1437#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1438#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1439#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
1440#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1441#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
1410
1411/* SPI NVM Status Register */
1442
1443/* SPI NVM Status Register */
1412#define NVM_STATUS_RDY_SPI 0x01
1413#define NVM_STATUS_WEN_SPI 0x02
1414#define NVM_STATUS_BP0_SPI 0x04
1415#define NVM_STATUS_BP1_SPI 0x08
1416#define NVM_STATUS_WPEN_SPI 0x80
1444#define NVM_STATUS_RDY_SPI 0x01
1445#define NVM_STATUS_WEN_SPI 0x02
1446#define NVM_STATUS_BP0_SPI 0x04
1447#define NVM_STATUS_BP1_SPI 0x08
1448#define NVM_STATUS_WPEN_SPI 0x80
1417
1418/* Word definitions for ID LED Settings */
1449
1450/* Word definitions for ID LED Settings */
1419#define ID_LED_RESERVED_0000 0x0000
1420#define ID_LED_RESERVED_FFFF 0xFFFF
1421#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1422 (ID_LED_OFF1_OFF2 << 8) | \
1423 (ID_LED_DEF1_DEF2 << 4) | \
1424 (ID_LED_DEF1_DEF2))
1425#define ID_LED_DEF1_DEF2 0x1
1426#define ID_LED_DEF1_ON2 0x2
1427#define ID_LED_DEF1_OFF2 0x3
1428#define ID_LED_ON1_DEF2 0x4
1429#define ID_LED_ON1_ON2 0x5
1430#define ID_LED_ON1_OFF2 0x6
1431#define ID_LED_OFF1_DEF2 0x7
1432#define ID_LED_OFF1_ON2 0x8
1433#define ID_LED_OFF1_OFF2 0x9
1451#define ID_LED_RESERVED_0000 0x0000
1452#define ID_LED_RESERVED_FFFF 0xFFFF
1453#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1454 (ID_LED_OFF1_OFF2 << 8) | \
1455 (ID_LED_DEF1_DEF2 << 4) | \
1456 (ID_LED_DEF1_DEF2))
1457#define ID_LED_DEF1_DEF2 0x1
1458#define ID_LED_DEF1_ON2 0x2
1459#define ID_LED_DEF1_OFF2 0x3
1460#define ID_LED_ON1_DEF2 0x4
1461#define ID_LED_ON1_ON2 0x5
1462#define ID_LED_ON1_OFF2 0x6
1463#define ID_LED_OFF1_DEF2 0x7
1464#define ID_LED_OFF1_ON2 0x8
1465#define ID_LED_OFF1_OFF2 0x9
1434
1466
1435#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1436#define IGP_ACTIVITY_LED_ENABLE 0x0300
1437#define IGP_LED3_MODE 0x07000000
1467#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1468#define IGP_ACTIVITY_LED_ENABLE 0x0300
1469#define IGP_LED3_MODE 0x07000000
1438
1439/* PCI/PCI-X/PCI-EX Config space */
1470
1471/* PCI/PCI-X/PCI-EX Config space */
1440#define PCIX_COMMAND_REGISTER 0xE6
1441#define PCIX_STATUS_REGISTER_LO 0xE8
1442#define PCIX_STATUS_REGISTER_HI 0xEA
1443#define PCI_HEADER_TYPE_REGISTER 0x0E
1444#define PCIE_LINK_STATUS 0x12
1445#define PCIE_DEVICE_CONTROL2 0x28
1472#define PCIX_COMMAND_REGISTER 0xE6
1473#define PCIX_STATUS_REGISTER_LO 0xE8
1474#define PCIX_STATUS_REGISTER_HI 0xEA
1475#define PCI_HEADER_TYPE_REGISTER 0x0E
1476#define PCIE_LINK_STATUS 0x12
1477#define PCIE_DEVICE_CONTROL2 0x28
1446
1478
1447#define PCIX_COMMAND_MMRBC_MASK 0x000C
1448#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1449#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1450#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1451#define PCIX_STATUS_HI_MMRBC_4K 0x3
1452#define PCIX_STATUS_HI_MMRBC_2K 0x2
1453#define PCIX_STATUS_LO_FUNC_MASK 0x7
1454#define PCI_HEADER_TYPE_MULTIFUNC 0x80
1455#define PCIE_LINK_WIDTH_MASK 0x3F0
1456#define PCIE_LINK_WIDTH_SHIFT 4
1457#define PCIE_LINK_SPEED_MASK 0x0F
1458#define PCIE_LINK_SPEED_2500 0x01
1459#define PCIE_LINK_SPEED_5000 0x02
1460#define PCIE_DEVICE_CONTROL2_16ms 0x0005
1479#define PCIX_COMMAND_MMRBC_MASK 0x000C
1480#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1481#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1482#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1483#define PCIX_STATUS_HI_MMRBC_4K 0x3
1484#define PCIX_STATUS_HI_MMRBC_2K 0x2
1485#define PCIX_STATUS_LO_FUNC_MASK 0x7
1486#define PCI_HEADER_TYPE_MULTIFUNC 0x80
1487#define PCIE_LINK_WIDTH_MASK 0x3F0
1488#define PCIE_LINK_WIDTH_SHIFT 4
1489#define PCIE_LINK_SPEED_MASK 0x0F
1490#define PCIE_LINK_SPEED_2500 0x01
1491#define PCIE_LINK_SPEED_5000 0x02
1492#define PCIE_DEVICE_CONTROL2_16ms 0x0005
1461
1462#ifndef ETH_ADDR_LEN
1493
1494#ifndef ETH_ADDR_LEN
1463#define ETH_ADDR_LEN 6
1495#define ETH_ADDR_LEN 6
1464#endif
1465
1496#endif
1497
1466#define PHY_REVISION_MASK 0xFFFFFFF0
1467#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1468#define MAX_PHY_MULTI_PAGE_REG 0xF
1498#define PHY_REVISION_MASK 0xFFFFFFF0
1499#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1500#define MAX_PHY_MULTI_PAGE_REG 0xF
1469
1470/* Bit definitions for valid PHY IDs. */
1471/*
1472 * I = Integrated
1473 * E = External
1474 */
1501
1502/* Bit definitions for valid PHY IDs. */
1503/*
1504 * I = Integrated
1505 * E = External
1506 */
1475#define M88E1000_E_PHY_ID 0x01410C50
1476#define M88E1000_I_PHY_ID 0x01410C30
1477#define M88E1011_I_PHY_ID 0x01410C20
1478#define IGP01E1000_I_PHY_ID 0x02A80380
1479#define M88E1011_I_REV_4 0x04
1480#define M88E1111_I_PHY_ID 0x01410CC0
1481#define M88E1112_E_PHY_ID 0x01410C90
1482#define I347AT4_E_PHY_ID 0x01410DC0
1483#define M88E1340M_E_PHY_ID 0x01410DF0
1484#define GG82563_E_PHY_ID 0x01410CA0
1485#define IGP03E1000_E_PHY_ID 0x02A80390
1486#define IFE_E_PHY_ID 0x02A80330
1487#define IFE_PLUS_E_PHY_ID 0x02A80320
1488#define IFE_C_E_PHY_ID 0x02A80310
1489#define BME1000_E_PHY_ID 0x01410CB0
1490#define BME1000_E_PHY_ID_R2 0x01410CB1
1491#define I82577_E_PHY_ID 0x01540050
1492#define I82578_E_PHY_ID 0x004DD040
1493#define I82579_E_PHY_ID 0x01540090
1494#define I82580_I_PHY_ID 0x015403A0
1495#define I350_I_PHY_ID 0x015403B0
1496#define IGP04E1000_E_PHY_ID 0x02A80391
1497#define M88_VENDOR 0x0141
1507#define M88E1000_E_PHY_ID 0x01410C50
1508#define M88E1000_I_PHY_ID 0x01410C30
1509#define M88E1011_I_PHY_ID 0x01410C20
1510#define IGP01E1000_I_PHY_ID 0x02A80380
1511#define M88E1011_I_REV_4 0x04
1512#define M88E1111_I_PHY_ID 0x01410CC0
1513#define M88E1112_E_PHY_ID 0x01410C90
1514#define I347AT4_E_PHY_ID 0x01410DC0
1515#define M88E1340M_E_PHY_ID 0x01410DF0
1516#define GG82563_E_PHY_ID 0x01410CA0
1517#define IGP03E1000_E_PHY_ID 0x02A80390
1518#define IFE_E_PHY_ID 0x02A80330
1519#define IFE_PLUS_E_PHY_ID 0x02A80320
1520#define IFE_C_E_PHY_ID 0x02A80310
1521#define BME1000_E_PHY_ID 0x01410CB0
1522#define BME1000_E_PHY_ID_R2 0x01410CB1
1523#define I82577_E_PHY_ID 0x01540050
1524#define I82578_E_PHY_ID 0x004DD040
1525#define I82579_E_PHY_ID 0x01540090
1526#define I82580_I_PHY_ID 0x015403A0
1527#define I350_I_PHY_ID 0x015403B0
1528#define IGP04E1000_E_PHY_ID 0x02A80391
1529#define M88_VENDOR 0x0141
1498
1499/* M88E1000 Specific Registers */
1530
1531/* M88E1000 Specific Registers */
1500#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1501#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1502#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1503#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1504#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1505#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1532#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1533#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1534#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */
1535#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */
1536#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1537#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1506
1538
1507#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1508#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1509#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1510#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1511#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1539#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1540#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1541#define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1542#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1543#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1512
1513/* M88E1000 PHY Specific Control Register */
1544
1545/* M88E1000 PHY Specific Control Register */
1514#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1515#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1516#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1546#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1547#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1548#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1517/* 1=CLK125 low, 0=CLK125 toggling */
1549/* 1=CLK125 low, 0=CLK125 toggling */
1518#define M88E1000_PSCR_CLK125_DISABLE 0x0010
1519#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1520 /* Manual MDI configuration */
1521#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1550#define M88E1000_PSCR_CLK125_DISABLE 0x0010
1551/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1552#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1553#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1522/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1554/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1523#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1555#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1524/* Auto crossover enabled all speeds */
1556/* Auto crossover enabled all speeds */
1525#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1557#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1526/*
1527 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1528 * 0=Normal 10BASE-T Rx Threshold
1529 */
1558/*
1559 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1560 * 0=Normal 10BASE-T Rx Threshold
1561 */
1530#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1562#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1531/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1563/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1532#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1533#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1534#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1535#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1564#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1565#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1566#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1567#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1536
1537/* M88E1000 PHY Specific Status Register */
1568
1569/* M88E1000 PHY Specific Status Register */
1538#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1539#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1540#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1541#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1570#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1571#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1572#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1573#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1542/*
1543 * 0 = <50M
1544 * 1 = 50-80M
1545 * 2 = 80-110M
1546 * 3 = 110-140M
1547 * 4 = >140M
1548 */
1574/*
1575 * 0 = <50M
1576 * 1 = 50-80M
1577 * 2 = 80-110M
1578 * 3 = 110-140M
1579 * 4 = >140M
1580 */
1549#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1550#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1551#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1552#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1553#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1554#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1555#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1556#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1557#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1581#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1582#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1583#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1584#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1585#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1586#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1587#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1588#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1589#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1558
1590
1559#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1591#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1560
1561/* M88E1000 Extended PHY Specific Control Register */
1592
1593/* M88E1000 Extended PHY Specific Control Register */
1562#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1594#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1563/*
1564 * 1 = Lost lock detect enabled.
1565 * Will assert lost lock and bring
1566 * link down if idle not seen
1567 * within 1ms in 1000BASE-T
1568 */
1595/*
1596 * 1 = Lost lock detect enabled.
1597 * Will assert lost lock and bring
1598 * link down if idle not seen
1599 * within 1ms in 1000BASE-T
1600 */
1569#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1601#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1570/*
1571 * Number of times we will attempt to autonegotiate before downshifting if we
1572 * are the master
1573 */
1602/*
1603 * Number of times we will attempt to autonegotiate before downshifting if we
1604 * are the master
1605 */
1574#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1575#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1576#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1577#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1578#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1606#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1607#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1608#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1609#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1610#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1579/*
1580 * Number of times we will attempt to autonegotiate before downshifting if we
1581 * are the slave
1582 */
1611/*
1612 * Number of times we will attempt to autonegotiate before downshifting if we
1613 * are the slave
1614 */
1583#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1584#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1585#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1586#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1587#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1588#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1589#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1590#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1615#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1616#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1617#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1618#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1619#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1620#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1621#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1622#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1591
1592/* M88E1111 Specific Registers */
1623
1624/* M88E1111 Specific Registers */
1593#define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */
1594#define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */
1625#define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */
1626#define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */
1595
1596/* M88E1111 page select register mask */
1627
1628/* M88E1111 page select register mask */
1597#define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF
1598#define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F
1629#define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF
1630#define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F
1599
1600/* Intel I347AT4 Registers */
1601
1631
1632/* Intel I347AT4 Registers */
1633
1602#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1603#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1604#define I347AT4_PAGE_SELECT 0x16
1634#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1635#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1636#define I347AT4_PAGE_SELECT 0x16
1605
1606/* I347AT4 Extended PHY Specific Control Register */
1607
1608/*
1609 * Number of times we will attempt to autonegotiate before downshifting if we
1610 * are the master
1611 */
1637
1638/* I347AT4 Extended PHY Specific Control Register */
1639
1640/*
1641 * Number of times we will attempt to autonegotiate before downshifting if we
1642 * are the master
1643 */
1612#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1613#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1614#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1615#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1616#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1617#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1618#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1619#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1620#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1621#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1644#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1645#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1646#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1647#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1648#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1649#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1650#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1651#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1652#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1653#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1622
1623/* I347AT4 PHY Cable Diagnostics Control */
1654
1655/* I347AT4 PHY Cable Diagnostics Control */
1624#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1656#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1625
1626/* M88E1112 only registers */
1657
1658/* M88E1112 only registers */
1627#define M88E1112_VCT_DSP_DISTANCE 0x001A
1659#define M88E1112_VCT_DSP_DISTANCE 0x001A
1628
1629/* M88EC018 Rev 2 specific DownShift settings */
1660
1661/* M88EC018 Rev 2 specific DownShift settings */
1630#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1631#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1632#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1633#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1634#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1635#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1636#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1637#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1638#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1662#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1663#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1664#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1665#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1666#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1667#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1668#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1669#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1670#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1639
1671
1640#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1641#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1672#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1673#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1642
1643/* BME1000 PHY Specific Control Register */
1674
1675/* BME1000 PHY Specific Control Register */
1644#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1676#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1645
1646/*
1647 * Bits...
1648 * 15-5: page
1649 * 4-0: register offset
1650 */
1677
1678/*
1679 * Bits...
1680 * 15-5: page
1681 * 4-0: register offset
1682 */
1651#define GG82563_PAGE_SHIFT 5
1652#define GG82563_REG(page, reg) \
1653 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1654#define GG82563_MIN_ALT_REG 30
1683#define GG82563_PAGE_SHIFT 5
1684#define GG82563_REG(page, reg) \
1685 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1686#define GG82563_MIN_ALT_REG 30
1655
1656/* GG82563 Specific Registers */
1687
1688/* GG82563 Specific Registers */
1657#define GG82563_PHY_SPEC_CTRL \
1658 GG82563_REG(0, 16) /* PHY Specific Control */
1659#define GG82563_PHY_SPEC_STATUS \
1660 GG82563_REG(0, 17) /* PHY Specific Status */
1661#define GG82563_PHY_INT_ENABLE \
1662 GG82563_REG(0, 18) /* Interrupt Enable */
1663#define GG82563_PHY_SPEC_STATUS_2 \
1664 GG82563_REG(0, 19) /* PHY Specific Status 2 */
1665#define GG82563_PHY_RX_ERR_CNTR \
1666 GG82563_REG(0, 21) /* Receive Error Counter */
1667#define GG82563_PHY_PAGE_SELECT \
1668 GG82563_REG(0, 22) /* Page Select */
1669#define GG82563_PHY_SPEC_CTRL_2 \
1670 GG82563_REG(0, 26) /* PHY Specific Control 2 */
1671#define GG82563_PHY_PAGE_SELECT_ALT \
1672 GG82563_REG(0, 29) /* Alternate Page Select */
1673#define GG82563_PHY_TEST_CLK_CTRL \
1674 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
1689#define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1690#define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */
1691#define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */
1692#define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */
1693#define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */
1694#define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1695#define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1696#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1697/* Test Clock Control (use reg. 29 to select) */
1698#define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30)
1675
1699
1676#define GG82563_PHY_MAC_SPEC_CTRL \
1677 GG82563_REG(2, 21) /* MAC Specific Control Register */
1678#define GG82563_PHY_MAC_SPEC_CTRL_2 \
1679 GG82563_REG(2, 26) /* MAC Specific Control 2 */
1700/* MAC Specific Control Register */
1701#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1702#define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */
1680
1703
1681#define GG82563_PHY_DSP_DISTANCE \
1682 GG82563_REG(5, 26) /* DSP Distance */
1704#define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1683
1684/* Page 193 - Port Control Registers */
1705
1706/* Page 193 - Port Control Registers */
1685#define GG82563_PHY_KMRN_MODE_CTRL \
1686 GG82563_REG(193, 16) /* Kumeran Mode Control */
1687#define GG82563_PHY_PORT_RESET \
1688 GG82563_REG(193, 17) /* Port Reset */
1689#define GG82563_PHY_REVISION_ID \
1690 GG82563_REG(193, 18) /* Revision ID */
1691#define GG82563_PHY_DEVICE_ID \
1692 GG82563_REG(193, 19) /* Device ID */
1693#define GG82563_PHY_PWR_MGMT_CTRL \
1694 GG82563_REG(193, 20) /* Power Management Control */
1695#define GG82563_PHY_RATE_ADAPT_CTRL \
1696 GG82563_REG(193, 25) /* Rate Adaptation Control */
1707/* Kumeran Mode Control */
1708#define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1709#define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */
1710#define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */
1711#define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */
1712#define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1713/* Rate Adaptation Control */
1714#define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25)
1697
1698/* Page 194 - KMRN Registers */
1715
1716/* Page 194 - KMRN Registers */
1699#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1700 GG82563_REG(194, 16) /* FIFO's Control/Status */
1701#define GG82563_PHY_KMRN_CTRL \
1702 GG82563_REG(194, 17) /* Control */
1703#define GG82563_PHY_INBAND_CTRL \
1704 GG82563_REG(194, 18) /* Inband Control */
1705#define GG82563_PHY_KMRN_DIAGNOSTIC \
1706 GG82563_REG(194, 19) /* Diagnostic */
1707#define GG82563_PHY_ACK_TIMEOUTS \
1708 GG82563_REG(194, 20) /* Acknowledge Timeouts */
1709#define GG82563_PHY_ADV_ABILITY \
1710 GG82563_REG(194, 21) /* Advertised Ability */
1711#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1712 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
1713#define GG82563_PHY_ADV_NEXT_PAGE \
1714 GG82563_REG(194, 24) /* Advertised Next Page */
1715#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1716 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
1717#define GG82563_PHY_KMRN_MISC \
1718 GG82563_REG(194, 26) /* Misc. */
1717/* FIFO's Control/Status */
1718#define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16)
1719#define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */
1720#define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
1721#define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */
1722#define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */
1723#define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */
1724/* Link Partner Advertised Ability */
1725#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23)
1726#define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */
1727/* Link Partner Advertised Next page */
1728#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25)
1729#define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */
1719
1720/* MDI Control */
1730
1731/* MDI Control */
1721#define E1000_MDIC_DATA_MASK 0x0000FFFF
1722#define E1000_MDIC_REG_MASK 0x001F0000
1723#define E1000_MDIC_REG_SHIFT 16
1724#define E1000_MDIC_PHY_MASK 0x03E00000
1725#define E1000_MDIC_PHY_SHIFT 21
1726#define E1000_MDIC_OP_WRITE 0x04000000
1727#define E1000_MDIC_OP_READ 0x08000000
1728#define E1000_MDIC_READY 0x10000000
1729#define E1000_MDIC_INT_EN 0x20000000
1730#define E1000_MDIC_ERROR 0x40000000
1731#define E1000_MDIC_DEST 0x80000000
1732#define E1000_MDIC_DATA_MASK 0x0000FFFF
1733#define E1000_MDIC_REG_MASK 0x001F0000
1734#define E1000_MDIC_REG_SHIFT 16
1735#define E1000_MDIC_PHY_MASK 0x03E00000
1736#define E1000_MDIC_PHY_SHIFT 21
1737#define E1000_MDIC_OP_WRITE 0x04000000
1738#define E1000_MDIC_OP_READ 0x08000000
1739#define E1000_MDIC_READY 0x10000000
1740#define E1000_MDIC_INT_EN 0x20000000
1741#define E1000_MDIC_ERROR 0x40000000
1742#define E1000_MDIC_DEST 0x80000000
1732
1733/* SerDes Control */
1743
1744/* SerDes Control */
1734#define E1000_GEN_CTL_READY 0x80000000
1735#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1736#define E1000_GEN_POLL_TIMEOUT 640
1745#define E1000_GEN_CTL_READY 0x80000000
1746#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1747#define E1000_GEN_POLL_TIMEOUT 640
1737
1738/* LinkSec register fields */
1748
1749/* LinkSec register fields */
1739#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1740#define E1000_LSECTXCAP_SUM_SHIFT 16
1741#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1742#define E1000_LSECRXCAP_SUM_SHIFT 16
1750#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1751#define E1000_LSECTXCAP_SUM_SHIFT 16
1752#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1753#define E1000_LSECRXCAP_SUM_SHIFT 16
1743
1754
1744#define E1000_LSECTXCTRL_EN_MASK 0x00000003
1745#define E1000_LSECTXCTRL_DISABLE 0x0
1746#define E1000_LSECTXCTRL_AUTH 0x1
1747#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1748#define E1000_LSECTXCTRL_AISCI 0x00000020
1749#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1750#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1755#define E1000_LSECTXCTRL_EN_MASK 0x00000003
1756#define E1000_LSECTXCTRL_DISABLE 0x0
1757#define E1000_LSECTXCTRL_AUTH 0x1
1758#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1759#define E1000_LSECTXCTRL_AISCI 0x00000020
1760#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1761#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1751
1762
1752#define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1753#define E1000_LSECRXCTRL_EN_SHIFT 2
1754#define E1000_LSECRXCTRL_DISABLE 0x0
1755#define E1000_LSECRXCTRL_CHECK 0x1
1756#define E1000_LSECRXCTRL_STRICT 0x2
1757#define E1000_LSECRXCTRL_DROP 0x3
1758#define E1000_LSECRXCTRL_PLSH 0x00000040
1759#define E1000_LSECRXCTRL_RP 0x00000080
1760#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1763#define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1764#define E1000_LSECRXCTRL_EN_SHIFT 2
1765#define E1000_LSECRXCTRL_DISABLE 0x0
1766#define E1000_LSECRXCTRL_CHECK 0x1
1767#define E1000_LSECRXCTRL_STRICT 0x2
1768#define E1000_LSECRXCTRL_DROP 0x3
1769#define E1000_LSECRXCTRL_PLSH 0x00000040
1770#define E1000_LSECRXCTRL_RP 0x00000080
1771#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1761
1762/* Tx Rate-Scheduler Config fields */
1763#define E1000_RTTBCNRC_RS_ENA 0x80000000
1764#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1772
1773/* Tx Rate-Scheduler Config fields */
1774#define E1000_RTTBCNRC_RS_ENA 0x80000000
1775#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1765#define E1000_RTTBCNRC_RF_INT_SHIFT 14
1776#define E1000_RTTBCNRC_RF_INT_SHIFT 14
1766#define E1000_RTTBCNRC_RF_INT_MASK \
1767 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1768
1769/* DMA Coalescing register fields */
1777#define E1000_RTTBCNRC_RF_INT_MASK \
1778 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1779
1780/* DMA Coalescing register fields */
1770#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing
1771 * Watchdog Timer */
1772#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Rx
1773 * Threshold */
1774#define E1000_DMACR_DMACTHR_SHIFT 16
1775#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe
1776 * transactions */
1777#define E1000_DMACR_DMAC_LX_SHIFT 28
1778#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1781/* DMA Coalescing Watchdog Timer */
1782#define E1000_DMACR_DMACWT_MASK 0x00003FFF
1783/* DMA Coalescing Rx Threshold */
1784#define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1785#define E1000_DMACR_DMACTHR_SHIFT 16
1786/* Lx when no PCIe transactions */
1787#define E1000_DMACR_DMAC_LX_MASK 0x30000000
1788#define E1000_DMACR_DMAC_LX_SHIFT 28
1789#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1779
1790
1780#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit
1781 * Threshold */
1791/* DMA Coalescing Transmit Threshold */
1792#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1782
1793
1783#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1794#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1784
1795
1785#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate
1786 * Threshold */
1787#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx packet rate in
1788 * current window */
1796/* Rx Traffic Rate Threshold */
1797#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1798/* Rx packet rate in current window */
1799#define E1000_DMCRTRH_LRPRCW 0x80000000
1789
1800
1790#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Traffic
1791 * Current Cnt */
1801/* DMA Coal Rx Traffic Current Count */
1802#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1792
1803
1793#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rx Threshold
1794 * High val */
1795#define E1000_FCRTC_RTH_COAL_SHIFT 4
1796#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based
1797 on DMA coal */
1804/* Flow ctrl Rx Threshold High val */
1805#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1806#define E1000_FCRTC_RTH_COAL_SHIFT 4
1807/* Lx power decision based on DMA coal */
1808#define E1000_PCIEMISC_LX_DECISION 0x00000080
1798
1809
1810#define E1000_LTRC_EEEMS_EN 0x00000005 /* Enable EEE LTR max send */
1811#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1812/* Minimum time for 1000BASE-T where no data will be transmit following move out
1813 * of EEE LPI Tx state
1814 */
1815#define E1000_TW_SYSTEM_1000_MASK 0x000000FF
1816/* Minimum time for 100BASE-T where no data will be transmit following move out
1817 * of EEE LPI Tx state
1818 */
1819#define E1000_TW_SYSTEM_100_MASK 0x0000FF00
1820#define E1000_TW_SYSTEM_100_SHIFT 8
1821#define E1000_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */
1822#define E1000_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */
1823#define E1000_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */
1824#define E1000_LTRMINV_SCALE_SHIFT 10
1825/* Reg val to set scale to 1024 nsec */
1826#define E1000_LTRMINV_SCALE_1024 2
1827/* Reg val to set scale to 32768 nsec */
1828#define E1000_LTRMINV_SCALE_32768 3
1829#define E1000_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */
1830#define E1000_LTRMAXV_SCALE_SHIFT 10
1831/* Reg val to set scale to 1024 nsec */
1832#define E1000_LTRMAXV_SCALE_1024 2
1833/* Reg val to set scale to 32768 nsec */
1834#define E1000_LTRMAXV_SCALE_32768 3
1835#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
1836#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
1837
1799/* Proxy Filer Control */
1838/* Proxy Filer Control */
1800#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1801#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1802#define E1000_PROXYFC_MC 0x00000008 /* Directed Multicast
1803 * Proxy */
1804#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1805#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy
1806 * Enable */
1807#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1808#define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1809#define E1000_PROXYFC_NS 0x00000200 /* IPv4 Neighborhood
1810 * Solicitation */
1811#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy
1812 * Enable */
1839#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1840#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1841#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1842#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1843#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1844#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1845#define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1846#define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */
1847#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1813/* Proxy Status */
1848/* Proxy Status */
1814#define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1849#define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1815
1816/* Firmware Status */
1850
1851/* Firmware Status */
1817#define E1000_FWSTS_FWRI 0x80000000 /* Firmware Reset
1818 * Indication */
1852#define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1853/* VF Control */
1854#define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1819
1855
1820
1856#define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1857/* Lan ID bit field offset in status register */
1858#define E1000_STATUS_LAN_ID_OFFSET 2
1859#define E1000_VFTA_ENTRIES 128
1821#endif /* _E1000_DEFINES_H_ */
1860#endif /* _E1000_DEFINES_H_ */