Deleted Added
sdiff udiff text old ( 169589 ) new ( 173788 )
full compact
e1000_defines.h (169589) e1000_defines.h (173788)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_defines.h 169589 2007-05-16 00:14:23Z jfv $*/
33/* $FreeBSD: head/sys/dev/em/e1000_defines.h 173788 2007-11-20 21:41:22Z jfv $ */
34
35
36#ifndef _E1000_DEFINES_H_
37#define _E1000_DEFINES_H_
38
34
35
36#ifndef _E1000_DEFINES_H_
37#define _E1000_DEFINES_H_
38
39#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
40#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
41#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
42#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
43#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
44#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
45#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
46#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
47#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
48#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
49#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
50#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
51#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
52#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
53#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
54#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
55#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
56#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
57/* Extended desc bits for Linksec and timesync */
58/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
59#define REQ_TX_DESCRIPTOR_MULTIPLE 8
60#define REQ_RX_DESCRIPTOR_MULTIPLE 8
61
62/* Definitions for power management and wakeup registers */
63/* Wake Up Control */
64#define E1000_WUC_APME 0x00000001 /* APM Enable */
65#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */

--- 172 unchanged lines hidden (view full) ---

238#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
239#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
240#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
241#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
242#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
243#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
244#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
245#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
39/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
40#define REQ_TX_DESCRIPTOR_MULTIPLE 8
41#define REQ_RX_DESCRIPTOR_MULTIPLE 8
42
43/* Definitions for power management and wakeup registers */
44/* Wake Up Control */
45#define E1000_WUC_APME 0x00000001 /* APM Enable */
46#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */

--- 172 unchanged lines hidden (view full) ---

219#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
220#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
221#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
222#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
223#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
224#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
225#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
226#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
246#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
247 * Filtering */
227/* Enable Neighbor Discovery Filtering */
228#define E1000_MANC_NEIGHBOR_EN 0x00004000
248#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
249#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
250#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
251#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
252#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
253#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
229#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
230#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
231#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
232#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
233#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
234#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
254#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
255 * filtering */
256#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
257 * memory */
258#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
259 * filtering */
235/* Enable MAC address filtering */
236#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
237/* Enable MNG packets to host memory */
238#define E1000_MANC_EN_MNG2HOST 0x00200000
239/* Enable IP address filtering */
240#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
260#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
261#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
262#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
263#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
264#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
265#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
266#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
267#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */

--- 38 unchanged lines hidden (view full) ---

306#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
307#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
308#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
309#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
310#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
311#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
312#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
313
241#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
242#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
243#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
244#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
245#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
246#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
247#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
248#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */

--- 38 unchanged lines hidden (view full) ---

287#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
288#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
289#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
290#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
291#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
292#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
293#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
294
314/* Use byte values for the following shift parameters
295/*
296 * Use byte values for the following shift parameters
315 * Usage:
316 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
317 * E1000_PSRCTL_BSIZE0_MASK) |
318 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
319 * E1000_PSRCTL_BSIZE1_MASK) |
320 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
321 * E1000_PSRCTL_BSIZE2_MASK) |
322 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;

--- 14 unchanged lines hidden (view full) ---

337#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
338#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
339
340/* SWFW_SYNC Definitions */
341#define E1000_SWFW_EEP_SM 0x1
342#define E1000_SWFW_PHY0_SM 0x2
343#define E1000_SWFW_PHY1_SM 0x4
344
297 * Usage:
298 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
299 * E1000_PSRCTL_BSIZE0_MASK) |
300 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
301 * E1000_PSRCTL_BSIZE1_MASK) |
302 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
303 * E1000_PSRCTL_BSIZE2_MASK) |
304 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;

--- 14 unchanged lines hidden (view full) ---

319#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
320#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
321
322/* SWFW_SYNC Definitions */
323#define E1000_SWFW_EEP_SM 0x1
324#define E1000_SWFW_PHY0_SM 0x2
325#define E1000_SWFW_PHY1_SM 0x4
326
327/* FACTPS Definitions */
328#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
345/* Device Control */
346#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
347#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
348#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
349#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
350#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
351#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
352#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */

--- 175 unchanged lines hidden (view full) ---

528#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
529#define E1000_LEDCTL_MODE_PAUSED 0xD
530#define E1000_LEDCTL_MODE_LED_ON 0xE
531#define E1000_LEDCTL_MODE_LED_OFF 0xF
532
533/* Transmit Descriptor bit definitions */
534#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
535#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
329/* Device Control */
330#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
331#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
332#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
333#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
334#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
335#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
336#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */

--- 175 unchanged lines hidden (view full) ---

512#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
513#define E1000_LEDCTL_MODE_PAUSED 0xD
514#define E1000_LEDCTL_MODE_LED_ON 0xE
515#define E1000_LEDCTL_MODE_LED_OFF 0xF
516
517/* Transmit Descriptor bit definitions */
518#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
519#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
520#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
536#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
537#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
538#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
539#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
540#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
541#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
542#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
543#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
544#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
545#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
546#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
547#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
548#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
549#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
550#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
551#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
552#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
553#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
521#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
522#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
523#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
524#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
525#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
526#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
527#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
528#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
529#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
530#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
531#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
532#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
533#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
534#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
535#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
536#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
537#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
538#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
539/* Extended desc bits for Linksec and timesync */
554
555/* Transmit Control */
556#define E1000_TCTL_RST 0x00000001 /* software reset */
557#define E1000_TCTL_EN 0x00000002 /* enable tx */
558#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
559#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
560#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
561#define E1000_TCTL_COLD 0x003ff000 /* collision distance */

--- 84 unchanged lines hidden (view full) ---

646#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
647#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
648#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
649#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
650
651#define E1000_KABGTXD_BGSQLBIAS 0x00050000
652
653/* PBA constants */
540
541/* Transmit Control */
542#define E1000_TCTL_RST 0x00000001 /* software reset */
543#define E1000_TCTL_EN 0x00000002 /* enable tx */
544#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
545#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
546#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
547#define E1000_TCTL_COLD 0x003ff000 /* collision distance */

--- 84 unchanged lines hidden (view full) ---

632#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
633#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
634#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
635#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
636
637#define E1000_KABGTXD_BGSQLBIAS 0x00050000
638
639/* PBA constants */
654#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
655#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
656#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
640#define E1000_PBA_8K 0x0008 /* 8KB */
641#define E1000_PBA_12K 0x000C /* 12KB */
642#define E1000_PBA_16K 0x0010 /* 16KB */
657#define E1000_PBA_20K 0x0014
658#define E1000_PBA_22K 0x0016
659#define E1000_PBA_24K 0x0018
660#define E1000_PBA_30K 0x001E
661#define E1000_PBA_32K 0x0020
662#define E1000_PBA_34K 0x0022
663#define E1000_PBA_38K 0x0026
664#define E1000_PBA_40K 0x0028
643#define E1000_PBA_20K 0x0014
644#define E1000_PBA_22K 0x0016
645#define E1000_PBA_24K 0x0018
646#define E1000_PBA_30K 0x001E
647#define E1000_PBA_32K 0x0020
648#define E1000_PBA_34K 0x0022
649#define E1000_PBA_38K 0x0026
650#define E1000_PBA_40K 0x0028
665#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
651#define E1000_PBA_48K 0x0030 /* 48KB */
652#define E1000_PBA_64K 0x0040 /* 64KB */
666
667#define E1000_PBS_16K E1000_PBA_16K
668#define E1000_PBS_24K E1000_PBA_24K
669
670#define IFS_MAX 80
671#define IFS_MIN 40
672#define IFS_RATIO 4
673#define IFS_STEP 10

--- 9 unchanged lines hidden (view full) ---

683#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
684#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
685#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
686#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
687#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
688#define E1000_ICR_RXO 0x00000040 /* rx overrun */
689#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
690#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
653
654#define E1000_PBS_16K E1000_PBA_16K
655#define E1000_PBS_24K E1000_PBA_24K
656
657#define IFS_MAX 80
658#define IFS_MIN 40
659#define IFS_RATIO 4
660#define IFS_STEP 10

--- 9 unchanged lines hidden (view full) ---

670#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
671#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
672#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
673#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
674#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
675#define E1000_ICR_RXO 0x00000040 /* rx overrun */
676#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
677#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
691#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
678#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
692#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
693#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
694#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
695#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
696#define E1000_ICR_TXD_LOW 0x00008000
697#define E1000_ICR_SRPD 0x00010000
698#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
699#define E1000_ICR_MNG 0x00040000 /* Manageability event */

--- 22 unchanged lines hidden (view full) ---

722#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
723#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
724/* TCP Timer */
725#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
726#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
727#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
728#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
729
679#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
680#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
681#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
682#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
683#define E1000_ICR_TXD_LOW 0x00008000
684#define E1000_ICR_SRPD 0x00010000
685#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
686#define E1000_ICR_MNG 0x00040000 /* Manageability event */

--- 22 unchanged lines hidden (view full) ---

709#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
710#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
711/* TCP Timer */
712#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
713#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
714#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
715#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
716
730/* This defines the bits that are set in the Interrupt Mask
717/*
718 * This defines the bits that are set in the Interrupt Mask
731 * Set/Read Register. Each bit is documented below:
732 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
733 * o RXSEQ = Receive Sequence Error
734 */
735#define POLL_IMS_ENABLE_MASK ( \
736 E1000_IMS_RXDMT0 | \
737 E1000_IMS_RXSEQ)
738
719 * Set/Read Register. Each bit is documented below:
720 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
721 * o RXSEQ = Receive Sequence Error
722 */
723#define POLL_IMS_ENABLE_MASK ( \
724 E1000_IMS_RXDMT0 | \
725 E1000_IMS_RXSEQ)
726
739/* This defines the bits that are set in the Interrupt Mask
727/*
728 * This defines the bits that are set in the Interrupt Mask
740 * Set/Read Register. Each bit is documented below:
741 * o RXT0 = Receiver Timer Interrupt (ring 0)
742 * o TXDW = Transmit Descriptor Written Back
743 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
744 * o RXSEQ = Receive Sequence Error
745 * o LSC = Link Status Change
746 */
747#define IMS_ENABLE_MASK ( \

--- 7 unchanged lines hidden (view full) ---

755#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
756#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
757#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
758#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
759#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
760#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
761#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
762#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
729 * Set/Read Register. Each bit is documented below:
730 * o RXT0 = Receiver Timer Interrupt (ring 0)
731 * o TXDW = Transmit Descriptor Written Back
732 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
733 * o RXSEQ = Receive Sequence Error
734 * o LSC = Link Status Change
735 */
736#define IMS_ENABLE_MASK ( \

--- 7 unchanged lines hidden (view full) ---

744#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
745#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
746#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
747#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
748#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
749#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
750#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
751#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
763#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
752#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
764#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
765#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
766#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
767#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
768#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
769#define E1000_IMS_SRPD E1000_ICR_SRPD
770#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
771#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */

--- 24 unchanged lines hidden (view full) ---

796#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
797#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
798#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
799#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
800#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
801#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
802#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
803#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
753#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
754#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
755#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
756#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
757#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
758#define E1000_IMS_SRPD E1000_ICR_SRPD
759#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
760#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */

--- 24 unchanged lines hidden (view full) ---

785#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
786#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
787#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
788#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
789#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
790#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
791#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
792#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
804#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
793#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
805#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
806#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
807#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
808#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
809#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
810#define E1000_ICS_SRPD E1000_ICR_SRPD
811#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
812#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */

--- 23 unchanged lines hidden (view full) ---

836/* Transmit Descriptor Control */
837#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
838#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
839#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
840#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
841#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
842#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
843#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
794#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
795#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
796#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
797#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
798#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
799#define E1000_ICS_SRPD E1000_ICR_SRPD
800#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
801#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */

--- 23 unchanged lines hidden (view full) ---

825/* Transmit Descriptor Control */
826#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
827#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
828#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
829#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
830#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
831#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
832#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
844#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
845 still to be processed. */
833/* Enable the counting of descriptors still to be processed. */
834#define E1000_TXDCTL_COUNT_DESC 0x00400000
846
847/* Flow Control Constants */
848#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
849#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
850#define FLOW_CONTROL_TYPE 0x8808
851
852/* 802.1q VLAN Packet Size */
853#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
854#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
855
856/* Receive Address */
835
836/* Flow Control Constants */
837#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
838#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
839#define FLOW_CONTROL_TYPE 0x8808
840
841/* 802.1q VLAN Packet Size */
842#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
843#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
844
845/* Receive Address */
857/* Number of high/low register pairs in the RAR. The RAR (Receive Address
846/*
847 * Number of high/low register pairs in the RAR. The RAR (Receive Address
858 * Registers) holds the directed and multicast addresses that we monitor.
859 * Technically, we have 16 spots. However, we reserve one of these spots
860 * (RAR[15]) for our directed address used by controllers with
861 * manageability enabled, allowing us room for 15 multicast addresses.
862 */
863#define E1000_RAR_ENTRIES 15
864#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
865

--- 150 unchanged lines hidden (view full) ---

1016
1017/* 1000BASE-T Status Register */
1018#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1019#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1020#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1021#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1022#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1023#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
848 * Registers) holds the directed and multicast addresses that we monitor.
849 * Technically, we have 16 spots. However, we reserve one of these spots
850 * (RAR[15]) for our directed address used by controllers with
851 * manageability enabled, allowing us room for 15 multicast addresses.
852 */
853#define E1000_RAR_ENTRIES 15
854#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
855

--- 150 unchanged lines hidden (view full) ---

1006
1007/* 1000BASE-T Status Register */
1008#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1009#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1010#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1011#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1012#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1013#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1024#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
1014#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
1025#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1026
1027#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1028
1029/* PHY 1000 MII Register/Bit Definitions */
1030/* PHY Registers defined by IEEE */
1031#define PHY_CONTROL 0x00 /* Control Register */
1032#define PHY_STATUS 0x01 /* Status Regiser */
1033#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1034#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1035#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1036#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1037#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1015#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1016
1017#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1018
1019/* PHY 1000 MII Register/Bit Definitions */
1020/* PHY Registers defined by IEEE */
1021#define PHY_CONTROL 0x00 /* Control Register */
1022#define PHY_STATUS 0x01 /* Status Regiser */
1023#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1024#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1025#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1026#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1027#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1038#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1028#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1039#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1040#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1041#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1042#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1043
1044/* NVM Control */
1045#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1046#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1047#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1048#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1049#define E1000_EECD_FWE_MASK 0x00000030
1050#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1051#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1052#define E1000_EECD_FWE_SHIFT 4
1053#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1054#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1055#define E1000_EECD_PRES 0x00000100 /* NVM Present */
1056#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1029#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1030#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1031#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1032#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1033
1034/* NVM Control */
1035#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1036#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1037#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1038#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1039#define E1000_EECD_FWE_MASK 0x00000030
1040#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1041#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1042#define E1000_EECD_FWE_SHIFT 4
1043#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1044#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1045#define E1000_EECD_PRES 0x00000100 /* NVM Present */
1046#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1057#define E1000_EECD_ADDR_BITS 0x00000400 /* NVM Addressing bits based on type
1058 * (0-small, 1-large) */
1047/* NVM Addressing bits based on type 0=small, 1=large */
1048#define E1000_EECD_ADDR_BITS 0x00000400
1059#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1060#ifndef E1000_NVM_GRANT_ATTEMPTS
1061#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1062#endif
1063#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1064#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1065#define E1000_EECD_SIZE_EX_SHIFT 11
1066#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */

--- 25 unchanged lines hidden (view full) ---

1092#define NVM_INIT_CONTROL2_REG 0x000F
1093#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1094#define NVM_INIT_CONTROL3_PORT_B 0x0014
1095#define NVM_INIT_3GIO_3 0x001A
1096#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1097#define NVM_INIT_CONTROL3_PORT_A 0x0024
1098#define NVM_CFG 0x0012
1099#define NVM_FLASH_VERSION 0x0032
1049#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1050#ifndef E1000_NVM_GRANT_ATTEMPTS
1051#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1052#endif
1053#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1054#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1055#define E1000_EECD_SIZE_EX_SHIFT 11
1056#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */

--- 25 unchanged lines hidden (view full) ---

1082#define NVM_INIT_CONTROL2_REG 0x000F
1083#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1084#define NVM_INIT_CONTROL3_PORT_B 0x0014
1085#define NVM_INIT_3GIO_3 0x001A
1086#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1087#define NVM_INIT_CONTROL3_PORT_A 0x0024
1088#define NVM_CFG 0x0012
1089#define NVM_FLASH_VERSION 0x0032
1090#define NVM_ALT_MAC_ADDR_PTR 0x0037
1100#define NVM_CHECKSUM_REG 0x003F
1101
1102#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
1103#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
1104
1105/* Mask bits for fields in Word 0x0f of the NVM */
1106#define NVM_WORD0F_PAUSE_MASK 0x3000
1107#define NVM_WORD0F_PAUSE 0x1000

--- 86 unchanged lines hidden (view full) ---

1194#define ETH_ADDR_LEN 6
1195#endif
1196
1197#define PHY_REVISION_MASK 0xFFFFFFF0
1198#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1199#define MAX_PHY_MULTI_PAGE_REG 0xF
1200
1201/* Bit definitions for valid PHY IDs. */
1091#define NVM_CHECKSUM_REG 0x003F
1092
1093#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
1094#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
1095
1096/* Mask bits for fields in Word 0x0f of the NVM */
1097#define NVM_WORD0F_PAUSE_MASK 0x3000
1098#define NVM_WORD0F_PAUSE 0x1000

--- 86 unchanged lines hidden (view full) ---

1185#define ETH_ADDR_LEN 6
1186#endif
1187
1188#define PHY_REVISION_MASK 0xFFFFFFF0
1189#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1190#define MAX_PHY_MULTI_PAGE_REG 0xF
1191
1192/* Bit definitions for valid PHY IDs. */
1202/* I = Integrated
1193/*
1194 * I = Integrated
1203 * E = External
1204 */
1205#define M88E1000_E_PHY_ID 0x01410C50
1206#define M88E1000_I_PHY_ID 0x01410C30
1207#define M88E1011_I_PHY_ID 0x01410C20
1208#define IGP01E1000_I_PHY_ID 0x02A80380
1209#define M88E1011_I_REV_4 0x04
1210#define M88E1111_I_PHY_ID 0x01410CC0

--- 17 unchanged lines hidden (view full) ---

1228#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1229#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1230#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1231
1232/* M88E1000 PHY Specific Control Register */
1233#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1234#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1235#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1195 * E = External
1196 */
1197#define M88E1000_E_PHY_ID 0x01410C50
1198#define M88E1000_I_PHY_ID 0x01410C30
1199#define M88E1011_I_PHY_ID 0x01410C20
1200#define IGP01E1000_I_PHY_ID 0x02A80380
1201#define M88E1011_I_REV_4 0x04
1202#define M88E1111_I_PHY_ID 0x01410CC0

--- 17 unchanged lines hidden (view full) ---

1220#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1221#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1222#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1223
1224/* M88E1000 PHY Specific Control Register */
1225#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1226#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1227#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1236#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
1237 * 0=CLK125 toggling
1238 */
1228/* 1=CLK125 low, 0=CLK125 toggling */
1229#define M88E1000_PSCR_CLK125_DISABLE 0x0010
1239#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1240 /* Manual MDI configuration */
1241#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1230#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1231 /* Manual MDI configuration */
1232#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1242#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1243 * 100BASE-TX/10BASE-T:
1244 * MDI Mode
1245 */
1246#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1247 * all speeds.
1248 */
1233/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1234#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1235/* Auto crossover enabled all speeds */
1236#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1237/*
1238 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1239 * 0=Normal 10BASE-T Rx Threshold
1240 */
1249#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1241#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1250 /* 1=Enable Extended 10BASE-T distance
1251 * (Lower 10BASE-T RX Threshold)
1252 * 0=Normal 10BASE-T RX Threshold */
1242/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1253#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1243#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1254 /* 1=5-Bit interface in 100BASE-TX
1255 * 0=MII interface in 100BASE-TX */
1256#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1257#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1258#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1259
1260/* M88E1000 PHY Specific Status Register */
1261#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1262#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1263#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1264#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1244#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1245#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1246#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1247
1248/* M88E1000 PHY Specific Status Register */
1249#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1250#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1251#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1252#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1265#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1266 * 3=110-140M;4=>140M */
1253/*
1254 * 0 = <50M
1255 * 1 = 50-80M
1256 * 2 = 80-110M
1257 * 3 = 110-140M
1258 * 4 = >140M
1259 */
1260#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1267#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1268#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1269#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1270#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1271#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1272#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1273#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1274#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1275
1276#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1277
1278/* M88E1000 Extended PHY Specific Control Register */
1279#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1261#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1262#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1263#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1264#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1265#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1266#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1267#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1268#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1269
1270#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1271
1272/* M88E1000 Extended PHY Specific Control Register */
1273#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1280#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
1281 * Will assert lost lock and bring
1282 * link down if idle not seen
1283 * within 1ms in 1000BASE-T
1284 */
1285/* Number of times we will attempt to autonegotiate before downshifting if we
1286 * are the master */
1274/*
1275 * 1 = Lost lock detect enabled.
1276 * Will assert lost lock and bring
1277 * link down if idle not seen
1278 * within 1ms in 1000BASE-T
1279 */
1280#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1281/*
1282 * Number of times we will attempt to autonegotiate before downshifting if we
1283 * are the master
1284 */
1287#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1288#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1289#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1290#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1291#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1285#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1286#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1287#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1288#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1289#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1292/* Number of times we will attempt to autonegotiate before downshifting if we
1293 * are the slave */
1290/*
1291 * Number of times we will attempt to autonegotiate before downshifting if we
1292 * are the slave
1293 */
1294#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1295#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1296#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1297#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1298#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1299#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1300#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1301#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */

--- 4 unchanged lines hidden (view full) ---

1306#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1307#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1308#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1309#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1310#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1311#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1312#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1313
1294#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1295#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1296#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1297#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1298#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1299#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1300#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1301#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */

--- 4 unchanged lines hidden (view full) ---

1306#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1307#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1308#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1309#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1310#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1311#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1312#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1313
1314/* Bits...
1314/*
1315 * Bits...
1315 * 15-5: page
1316 * 4-0: register offset
1317 */
1318#define GG82563_PAGE_SHIFT 5
1319#define GG82563_REG(page, reg) \
1320 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1321#define GG82563_MIN_ALT_REG 30
1322

--- 72 unchanged lines hidden (view full) ---

1395#define E1000_MDIC_READY 0x10000000
1396#define E1000_MDIC_INT_EN 0x20000000
1397#define E1000_MDIC_ERROR 0x40000000
1398
1399/* SerDes Control */
1400#define E1000_GEN_CTL_READY 0x80000000
1401#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1402#define E1000_GEN_POLL_TIMEOUT 640
1316 * 15-5: page
1317 * 4-0: register offset
1318 */
1319#define GG82563_PAGE_SHIFT 5
1320#define GG82563_REG(page, reg) \
1321 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1322#define GG82563_MIN_ALT_REG 30
1323

--- 72 unchanged lines hidden (view full) ---

1396#define E1000_MDIC_READY 0x10000000
1397#define E1000_MDIC_INT_EN 0x20000000
1398#define E1000_MDIC_ERROR 0x40000000
1399
1400/* SerDes Control */
1401#define E1000_GEN_CTL_READY 0x80000000
1402#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1403#define E1000_GEN_POLL_TIMEOUT 640
1404
1405/* LinkSec register fields */
1406#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1407#define E1000_LSECTXCAP_SUM_SHIFT 16
1408#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1409#define E1000_LSECRXCAP_SUM_SHIFT 16
1410
1411#define E1000_LSECTXCTRL_EN_MASK 0x00000003
1412#define E1000_LSECTXCTRL_DISABLE 0x0
1413#define E1000_LSECTXCTRL_AUTH 0x1
1414#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1415#define E1000_LSECTXCTRL_AISCI 0x00000020
1416#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1417#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1418
1419#define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1420#define E1000_LSECRXCTRL_EN_SHIFT 2
1421#define E1000_LSECRXCTRL_DISABLE 0x0
1422#define E1000_LSECRXCTRL_CHECK 0x1
1423#define E1000_LSECRXCTRL_STRICT 0x2
1424#define E1000_LSECRXCTRL_DROP 0x3
1425#define E1000_LSECRXCTRL_PLSH 0x00000040
1426#define E1000_LSECRXCTRL_RP 0x00000080
1427#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1428
1429#define UNREFERENCED_PARAMETER(_p)
1403#endif
1430#endif