| e1000_defines.h (169248) | e1000_defines.h (169589) |
|---|---|
| 1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ | 1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/em/e1000_defines.h 169589 2007-05-16 00:14:23Z jfv $*/ |
|
| 33 | 34 |
| 34/* 35 * $FreeBSD: head/sys/dev/em/e1000_defines.h 169248 2007-05-04 13:30:44Z rwatson $ 36 */ | |
| 37 | 35 |
| 38 | |
| 39#ifndef _E1000_DEFINES_H_ 40#define _E1000_DEFINES_H_ 41 42#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 43#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 44#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 45#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 46#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ --- 5 unchanged lines hidden (view full) --- 52#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 53#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 54#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 55#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 56#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 57#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 58#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 59#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | 36#ifndef _E1000_DEFINES_H_ 37#define _E1000_DEFINES_H_ 38 39#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 40#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 41#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 42#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 43#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ --- 5 unchanged lines hidden (view full) --- 49#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 50#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 51#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 52#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 53#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 54#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 55#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 56#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ |
| 60 | 57/* Extended desc bits for Linksec and timesync */ |
| 61/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 62#define REQ_TX_DESCRIPTOR_MULTIPLE 8 63#define REQ_RX_DESCRIPTOR_MULTIPLE 8 64 65/* Definitions for power management and wakeup registers */ 66/* Wake Up Control */ 67#define E1000_WUC_APME 0x00000001 /* APM Enable */ 68#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ --- 76 unchanged lines hidden (view full) --- 145#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 146#define E1000_CTRL_EXT_EIAME 0x01000000 147#define E1000_CTRL_EXT_IRCA 0x00000001 148#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 149#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 150#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 151#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 152#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 | 58/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 59#define REQ_TX_DESCRIPTOR_MULTIPLE 8 60#define REQ_RX_DESCRIPTOR_MULTIPLE 8 61 62/* Definitions for power management and wakeup registers */ 63/* Wake Up Control */ 64#define E1000_WUC_APME 0x00000001 /* APM Enable */ 65#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ --- 76 unchanged lines hidden (view full) --- 142#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 143#define E1000_CTRL_EXT_EIAME 0x01000000 144#define E1000_CTRL_EXT_IRCA 0x00000001 145#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 146#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 147#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 148#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 149#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 |
| 153#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */ 154#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 155#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 156#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | 150#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */ 151#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 152#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 153#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ |
| 157#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 158#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 159#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 160#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 161#define E1000_I2CCMD_REG_ADDR_SHIFT 16 162#define E1000_I2CCMD_REG_ADDR 0x00FF0000 163#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 164#define E1000_I2CCMD_PHY_ADDR 0x07000000 --- 1242 unchanged lines hidden --- | 154#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 155#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 156#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 157#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 158#define E1000_I2CCMD_REG_ADDR_SHIFT 16 159#define E1000_I2CCMD_REG_ADDR 0x00FF0000 160#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 161#define E1000_I2CCMD_PHY_ADDR 0x07000000 --- 1242 unchanged lines hidden --- |