1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
| 1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
|
33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 287990 2015-09-19 18:22:59Z sbruno $*/
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 295323 2016-02-05 17:14:37Z erj $*/
|
34
35#ifndef _E1000_DEFINES_H_
36#define _E1000_DEFINES_H_
37
38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
39#define REQ_TX_DESCRIPTOR_MULTIPLE 8
40#define REQ_RX_DESCRIPTOR_MULTIPLE 8
41
42/* Definitions for power management and wakeup registers */
43/* Wake Up Control */
44#define E1000_WUC_APME 0x00000001 /* APM Enable */
45#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
49
50/* Wake Up Filter Control */
51#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
57#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
58#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
59
60/* Wake Up Status */
61#define E1000_WUS_LNKC E1000_WUFC_LNKC
62#define E1000_WUS_MAG E1000_WUFC_MAG
63#define E1000_WUS_EX E1000_WUFC_EX
64#define E1000_WUS_MC E1000_WUFC_MC
65#define E1000_WUS_BC E1000_WUFC_BC
66
67/* Extended Device Control */
68#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
69#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
70#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
71#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
72/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
73#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
74#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
75#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
76#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
77#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
78/* Physical Func Reset Done Indication */
79#define E1000_CTRL_EXT_PFRSTD 0x00004000
80#define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
81#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
82#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
83#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
84#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
85/* Offset of the link mode field in Ctrl Ext register */
86#define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
87#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
88#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
89#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
90#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
91#define E1000_CTRL_EXT_EIAME 0x01000000
92#define E1000_CTRL_EXT_IRCA 0x00000001
93#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
94#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
95#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
96#define E1000_CTRL_EXT_LSECCK 0x00001000
97#define E1000_CTRL_EXT_PHYPDEN 0x00100000
98#define E1000_I2CCMD_REG_ADDR_SHIFT 16
99#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
100#define E1000_I2CCMD_OPCODE_READ 0x08000000
101#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
102#define E1000_I2CCMD_READY 0x20000000
103#define E1000_I2CCMD_ERROR 0x80000000
104#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
105#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
106#define E1000_MAX_SGMII_PHY_REG_ADDR 255
107#define E1000_I2CCMD_PHY_TIMEOUT 200
108#define E1000_IVAR_VALID 0x80
109#define E1000_GPIE_NSICR 0x00000001
110#define E1000_GPIE_MSIX_MODE 0x00000010
111#define E1000_GPIE_EIAME 0x40000000
112#define E1000_GPIE_PBA 0x80000000
113
114/* Receive Descriptor bit definitions */
115#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
116#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
117#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
118#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
119#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
120#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
121#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
122#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
123#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
124#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
125#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
126#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
127#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
128#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
129#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
130#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
131#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
132#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
133#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
134
135#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
136#define E1000_RXDEXT_STATERR_LB 0x00040000
137#define E1000_RXDEXT_STATERR_CE 0x01000000
138#define E1000_RXDEXT_STATERR_SE 0x02000000
139#define E1000_RXDEXT_STATERR_SEQ 0x04000000
140#define E1000_RXDEXT_STATERR_CXE 0x10000000
141#define E1000_RXDEXT_STATERR_TCPE 0x20000000
142#define E1000_RXDEXT_STATERR_IPE 0x40000000
143#define E1000_RXDEXT_STATERR_RXE 0x80000000
144
145/* mask to determine if packets should be dropped due to frame errors */
146#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
147 E1000_RXD_ERR_CE | \
148 E1000_RXD_ERR_SE | \
149 E1000_RXD_ERR_SEQ | \
150 E1000_RXD_ERR_CXE | \
151 E1000_RXD_ERR_RXE)
152
153/* Same mask, but for extended and packet split descriptors */
154#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
155 E1000_RXDEXT_STATERR_CE | \
156 E1000_RXDEXT_STATERR_SE | \
157 E1000_RXDEXT_STATERR_SEQ | \
158 E1000_RXDEXT_STATERR_CXE | \
159 E1000_RXDEXT_STATERR_RXE)
160
161#define E1000_MRQC_RSS_ENABLE_2Q 0x00000001
162#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
163#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
164#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
165#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
166#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
167#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
168#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
169
170#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
171
172/* Management Control */
173#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
175#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
176#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
177#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
178/* Enable MAC address filtering */
179#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
180/* Enable MNG packets to host memory */
181#define E1000_MANC_EN_MNG2HOST 0x00200000
182
183#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
184#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
185#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
186#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
187
188/* Receive Control */
189#define E1000_RCTL_RST 0x00000001 /* Software reset */
190#define E1000_RCTL_EN 0x00000002 /* enable */
191#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
192#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
193#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
194#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
195#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
196#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
197#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
198#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
199#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
| 34
35#ifndef _E1000_DEFINES_H_
36#define _E1000_DEFINES_H_
37
38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
39#define REQ_TX_DESCRIPTOR_MULTIPLE 8
40#define REQ_RX_DESCRIPTOR_MULTIPLE 8
41
42/* Definitions for power management and wakeup registers */
43/* Wake Up Control */
44#define E1000_WUC_APME 0x00000001 /* APM Enable */
45#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
49
50/* Wake Up Filter Control */
51#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
57#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
58#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
59
60/* Wake Up Status */
61#define E1000_WUS_LNKC E1000_WUFC_LNKC
62#define E1000_WUS_MAG E1000_WUFC_MAG
63#define E1000_WUS_EX E1000_WUFC_EX
64#define E1000_WUS_MC E1000_WUFC_MC
65#define E1000_WUS_BC E1000_WUFC_BC
66
67/* Extended Device Control */
68#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
69#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
70#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
71#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
72/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
73#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
74#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
75#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
76#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
77#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
78/* Physical Func Reset Done Indication */
79#define E1000_CTRL_EXT_PFRSTD 0x00004000
80#define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
81#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
82#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
83#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
84#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
85/* Offset of the link mode field in Ctrl Ext register */
86#define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
87#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
88#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
89#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
90#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
91#define E1000_CTRL_EXT_EIAME 0x01000000
92#define E1000_CTRL_EXT_IRCA 0x00000001
93#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
94#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
95#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
96#define E1000_CTRL_EXT_LSECCK 0x00001000
97#define E1000_CTRL_EXT_PHYPDEN 0x00100000
98#define E1000_I2CCMD_REG_ADDR_SHIFT 16
99#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
100#define E1000_I2CCMD_OPCODE_READ 0x08000000
101#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
102#define E1000_I2CCMD_READY 0x20000000
103#define E1000_I2CCMD_ERROR 0x80000000
104#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
105#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
106#define E1000_MAX_SGMII_PHY_REG_ADDR 255
107#define E1000_I2CCMD_PHY_TIMEOUT 200
108#define E1000_IVAR_VALID 0x80
109#define E1000_GPIE_NSICR 0x00000001
110#define E1000_GPIE_MSIX_MODE 0x00000010
111#define E1000_GPIE_EIAME 0x40000000
112#define E1000_GPIE_PBA 0x80000000
113
114/* Receive Descriptor bit definitions */
115#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
116#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
117#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
118#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
119#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
120#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
121#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
122#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
123#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
124#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
125#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
126#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
127#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
128#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
129#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
130#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
131#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
132#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
133#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
134
135#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
136#define E1000_RXDEXT_STATERR_LB 0x00040000
137#define E1000_RXDEXT_STATERR_CE 0x01000000
138#define E1000_RXDEXT_STATERR_SE 0x02000000
139#define E1000_RXDEXT_STATERR_SEQ 0x04000000
140#define E1000_RXDEXT_STATERR_CXE 0x10000000
141#define E1000_RXDEXT_STATERR_TCPE 0x20000000
142#define E1000_RXDEXT_STATERR_IPE 0x40000000
143#define E1000_RXDEXT_STATERR_RXE 0x80000000
144
145/* mask to determine if packets should be dropped due to frame errors */
146#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
147 E1000_RXD_ERR_CE | \
148 E1000_RXD_ERR_SE | \
149 E1000_RXD_ERR_SEQ | \
150 E1000_RXD_ERR_CXE | \
151 E1000_RXD_ERR_RXE)
152
153/* Same mask, but for extended and packet split descriptors */
154#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
155 E1000_RXDEXT_STATERR_CE | \
156 E1000_RXDEXT_STATERR_SE | \
157 E1000_RXDEXT_STATERR_SEQ | \
158 E1000_RXDEXT_STATERR_CXE | \
159 E1000_RXDEXT_STATERR_RXE)
160
161#define E1000_MRQC_RSS_ENABLE_2Q 0x00000001
162#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
163#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
164#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
165#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
166#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
167#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
168#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
169
170#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
171
172/* Management Control */
173#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
175#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
176#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
177#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
178/* Enable MAC address filtering */
179#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
180/* Enable MNG packets to host memory */
181#define E1000_MANC_EN_MNG2HOST 0x00200000
182
183#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
184#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
185#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
186#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
187
188/* Receive Control */
189#define E1000_RCTL_RST 0x00000001 /* Software reset */
190#define E1000_RCTL_EN 0x00000002 /* enable */
191#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
192#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
193#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
194#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
195#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
196#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
197#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
198#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
199#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
|
| 200#define E1000_RCTL_RDMTS_HEX 0x00010000
201#define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX
|
200#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
201#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
202#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
203/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
204#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
205#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
206#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
207#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
208/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
209#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
210#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
211#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
212#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
213#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
214#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
215#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
216#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
217#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
218#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
219
220/* Use byte values for the following shift parameters
221 * Usage:
222 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
223 * E1000_PSRCTL_BSIZE0_MASK) |
224 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
225 * E1000_PSRCTL_BSIZE1_MASK) |
226 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
227 * E1000_PSRCTL_BSIZE2_MASK) |
228 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
229 * E1000_PSRCTL_BSIZE3_MASK))
230 * where value0 = [128..16256], default=256
231 * value1 = [1024..64512], default=4096
232 * value2 = [0..64512], default=4096
233 * value3 = [0..64512], default=0
234 */
235
236#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
237#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
238#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
239#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
240
241#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
242#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
243#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
244#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
245
246/* SWFW_SYNC Definitions */
247#define E1000_SWFW_EEP_SM 0x01
248#define E1000_SWFW_PHY0_SM 0x02
249#define E1000_SWFW_PHY1_SM 0x04
250#define E1000_SWFW_CSR_SM 0x08
251#define E1000_SWFW_PHY2_SM 0x20
252#define E1000_SWFW_PHY3_SM 0x40
253#define E1000_SWFW_SW_MNG_SM 0x400
254
255/* Device Control */
256#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
257#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
258#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
259#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
260#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
261#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
262#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
263#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
264#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
265#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
266#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
267#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
268#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
269#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
270#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
271#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
272#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
273#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
274#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
275#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
276#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
277#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
278#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
279#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
280#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
281#define E1000_CTRL_RST 0x04000000 /* Global reset */
282#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
283#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
284#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
285#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
286#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
287
288#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
289#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
290#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
291#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
292
293#define E1000_CONNSW_ENRGSRC 0x4
294#define E1000_CONNSW_PHYSD 0x400
295#define E1000_CONNSW_PHY_PDN 0x800
296#define E1000_CONNSW_SERDESD 0x200
297#define E1000_CONNSW_AUTOSENSE_CONF 0x2
298#define E1000_CONNSW_AUTOSENSE_EN 0x1
299#define E1000_PCS_CFG_PCS_EN 8
300#define E1000_PCS_LCTL_FLV_LINK_UP 1
301#define E1000_PCS_LCTL_FSV_10 0
302#define E1000_PCS_LCTL_FSV_100 2
303#define E1000_PCS_LCTL_FSV_1000 4
304#define E1000_PCS_LCTL_FDV_FULL 8
305#define E1000_PCS_LCTL_FSD 0x10
306#define E1000_PCS_LCTL_FORCE_LINK 0x20
307#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
308#define E1000_PCS_LCTL_AN_ENABLE 0x10000
309#define E1000_PCS_LCTL_AN_RESTART 0x20000
310#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
311#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
312
313#define E1000_PCS_LSTS_LINK_OK 1
314#define E1000_PCS_LSTS_SPEED_100 2
315#define E1000_PCS_LSTS_SPEED_1000 4
316#define E1000_PCS_LSTS_DUPLEX_FULL 8
317#define E1000_PCS_LSTS_SYNK_OK 0x10
318#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
319
320/* Device Status */
321#define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
322#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
323#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
324#define E1000_STATUS_FUNC_SHIFT 2
325#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
326#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
327#define E1000_STATUS_SPEED_MASK 0x000000C0
328#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
329#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
330#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
331#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
332#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
333#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
334#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
335#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
336#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
337#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
338#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
339#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
340
341/* Constants used to interpret the masked PCI-X bus speed. */
342#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
343#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
344#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
345
346#define SPEED_10 10
347#define SPEED_100 100
348#define SPEED_1000 1000
349#define SPEED_2500 2500
350#define HALF_DUPLEX 1
351#define FULL_DUPLEX 2
352
353#define PHY_FORCE_TIME 20
354
355#define ADVERTISE_10_HALF 0x0001
356#define ADVERTISE_10_FULL 0x0002
357#define ADVERTISE_100_HALF 0x0004
358#define ADVERTISE_100_FULL 0x0008
359#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
360#define ADVERTISE_1000_FULL 0x0020
361
362/* 1000/H is not supported, nor spec-compliant. */
363#define E1000_ALL_SPEED_DUPLEX ( \
364 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
365 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
366#define E1000_ALL_NOT_GIG ( \
367 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
368 ADVERTISE_100_FULL)
369#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
370#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
371#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
372
373#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
374
375/* LED Control */
376#define E1000_PHY_LED0_MODE_MASK 0x00000007
377#define E1000_PHY_LED0_IVRT 0x00000008
378#define E1000_PHY_LED0_MASK 0x0000001F
379
380#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
381#define E1000_LEDCTL_LED0_MODE_SHIFT 0
382#define E1000_LEDCTL_LED0_IVRT 0x00000040
383#define E1000_LEDCTL_LED0_BLINK 0x00000080
384
385#define E1000_LEDCTL_MODE_LINK_UP 0x2
386#define E1000_LEDCTL_MODE_LED_ON 0xE
387#define E1000_LEDCTL_MODE_LED_OFF 0xF
388
389/* Transmit Descriptor bit definitions */
390#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
391#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
392#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
393#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
394#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
395#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
396#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
397#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
398#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
399#define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
400#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
401#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
402#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
403#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
404#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
405#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
406#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
407#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
408#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
409#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
410#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
411
412/* Transmit Control */
413#define E1000_TCTL_EN 0x00000002 /* enable Tx */
414#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
415#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
416#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
417#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
418#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
419
420/* Transmit Arbitration Count */
421#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
422
423/* SerDes Control */
424#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
425#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
426
427/* Receive Checksum Control */
428#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
429#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
430#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
431#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
432#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
433
434/* Header split receive */
435#define E1000_RFCTL_NFSW_DIS 0x00000040
436#define E1000_RFCTL_NFSR_DIS 0x00000080
437#define E1000_RFCTL_ACK_DIS 0x00001000
438#define E1000_RFCTL_EXTEN 0x00008000
439#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
440#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
441#define E1000_RFCTL_LEF 0x00040000
442
443/* Collision related configuration parameters */
444#define E1000_COLLISION_THRESHOLD 15
445#define E1000_CT_SHIFT 4
446#define E1000_COLLISION_DISTANCE 63
447#define E1000_COLD_SHIFT 12
448
449/* Default values for the transmit IPG register */
450#define DEFAULT_82542_TIPG_IPGT 10
451#define DEFAULT_82543_TIPG_IPGT_FIBER 9
452#define DEFAULT_82543_TIPG_IPGT_COPPER 8
453
454#define E1000_TIPG_IPGT_MASK 0x000003FF
455
456#define DEFAULT_82542_TIPG_IPGR1 2
457#define DEFAULT_82543_TIPG_IPGR1 8
458#define E1000_TIPG_IPGR1_SHIFT 10
459
460#define DEFAULT_82542_TIPG_IPGR2 10
461#define DEFAULT_82543_TIPG_IPGR2 6
462#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
463#define E1000_TIPG_IPGR2_SHIFT 20
464
465/* Ethertype field values */
466#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
467
468#define ETHERNET_FCS_SIZE 4
469#define MAX_JUMBO_FRAME_SIZE 0x3F00
470#define E1000_TX_PTR_GAP 0x1F
471
472/* Extended Configuration Control and Size */
473#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
474#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
475#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
476#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
477#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
478#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
479#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
480#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
481#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
482
483#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
484#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
485#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
486#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
487
488#define E1000_KABGTXD_BGSQLBIAS 0x00050000
489
490/* Low Power IDLE Control */
491#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */
492
493/* PBA constants */
494#define E1000_PBA_8K 0x0008 /* 8KB */
495#define E1000_PBA_10K 0x000A /* 10KB */
496#define E1000_PBA_12K 0x000C /* 12KB */
497#define E1000_PBA_14K 0x000E /* 14KB */
498#define E1000_PBA_16K 0x0010 /* 16KB */
499#define E1000_PBA_18K 0x0012
500#define E1000_PBA_20K 0x0014
501#define E1000_PBA_22K 0x0016
502#define E1000_PBA_24K 0x0018
503#define E1000_PBA_26K 0x001A
504#define E1000_PBA_30K 0x001E
505#define E1000_PBA_32K 0x0020
506#define E1000_PBA_34K 0x0022
507#define E1000_PBA_35K 0x0023
508#define E1000_PBA_38K 0x0026
509#define E1000_PBA_40K 0x0028
510#define E1000_PBA_48K 0x0030 /* 48KB */
511#define E1000_PBA_64K 0x0040 /* 64KB */
512
513#define E1000_PBA_RXA_MASK 0xFFFF
514
515#define E1000_PBS_16K E1000_PBA_16K
516
517/* Uncorrectable/correctable ECC Error counts and enable bits */
518#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
519#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
520#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
521#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
522
523#define IFS_MAX 80
524#define IFS_MIN 40
525#define IFS_RATIO 4
526#define IFS_STEP 10
527#define MIN_NUM_XMITS 1000
528
529/* SW Semaphore Register */
530#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
531#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
532#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
533
534#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
535
536/* Interrupt Cause Read */
537#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
538#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
539#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
540#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
541#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
542#define E1000_ICR_RXO 0x00000040 /* Rx overrun */
543#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
544#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
545#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
546#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
547#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
548#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
549#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
550#define E1000_ICR_TXD_LOW 0x00008000
551#define E1000_ICR_MNG 0x00040000 /* Manageability event */
552#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
553#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
554#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
555/* If this bit asserted, the driver should claim the interrupt */
556#define E1000_ICR_INT_ASSERTED 0x80000000
557#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
558#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
559#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
560#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
561#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
562#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
563#define E1000_ICR_FER 0x00400000 /* Fatal Error */
564
565#define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
566#define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
567
568#define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
569#define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */
570
571/* PBA ECC Register */
572#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
573#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
574#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
575#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
576#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
577
578/* Extended Interrupt Cause Read */
579#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
580#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
581#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
582#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
583#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
584#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
585#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
586#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
587#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
588#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
589/* TCP Timer */
590#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
591#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
592#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
593#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
594
595/* This defines the bits that are set in the Interrupt Mask
596 * Set/Read Register. Each bit is documented below:
597 * o RXT0 = Receiver Timer Interrupt (ring 0)
598 * o TXDW = Transmit Descriptor Written Back
599 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
600 * o RXSEQ = Receive Sequence Error
601 * o LSC = Link Status Change
602 */
603#define IMS_ENABLE_MASK ( \
604 E1000_IMS_RXT0 | \
605 E1000_IMS_TXDW | \
606 E1000_IMS_RXDMT0 | \
607 E1000_IMS_RXSEQ | \
608 E1000_IMS_LSC)
609
610/* Interrupt Mask Set */
611#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
612#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
613#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
614#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
615#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
616#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
617#define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
618#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
619#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
620#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
621#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
622#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
623#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
624#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
625#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
626#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
627#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
628#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
629#define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
630
631#define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
632#define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
633/* Extended Interrupt Mask Set */
634#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
635#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
636#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
637#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
638#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
639#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
640#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
641#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
642#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
643#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
644
645/* Interrupt Cause Set */
646#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
647#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
648#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
649
650/* Extended Interrupt Cause Set */
651#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
652#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
653#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
654#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
655#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
656#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
657#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
658#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
659#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
660#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
661
662#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
663/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
664#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
665#define E1000_EITR_INTERVAL 0x00007FFC
666
667/* Transmit Descriptor Control */
668#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
669#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
670#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
671#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
672#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
673#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
674/* Enable the counting of descriptors still to be processed. */
675#define E1000_TXDCTL_COUNT_DESC 0x00400000
676
677/* Flow Control Constants */
678#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
679#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
680#define FLOW_CONTROL_TYPE 0x8808
681
682/* 802.1q VLAN Packet Size */
683#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
684#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
685
686/* Receive Address
687 * Number of high/low register pairs in the RAR. The RAR (Receive Address
688 * Registers) holds the directed and multicast addresses that we monitor.
689 * Technically, we have 16 spots. However, we reserve one of these spots
690 * (RAR[15]) for our directed address used by controllers with
691 * manageability enabled, allowing us room for 15 multicast addresses.
692 */
693#define E1000_RAR_ENTRIES 15
694#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
695#define E1000_RAL_MAC_ADDR_LEN 4
696#define E1000_RAH_MAC_ADDR_LEN 2
697#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
698#define E1000_RAH_POOL_1 0x00040000
699
700/* Error Codes */
701#define E1000_SUCCESS 0
702#define E1000_ERR_NVM 1
703#define E1000_ERR_PHY 2
704#define E1000_ERR_CONFIG 3
705#define E1000_ERR_PARAM 4
706#define E1000_ERR_MAC_INIT 5
707#define E1000_ERR_PHY_TYPE 6
708#define E1000_ERR_RESET 9
709#define E1000_ERR_MASTER_REQUESTS_PENDING 10
710#define E1000_ERR_HOST_INTERFACE_COMMAND 11
711#define E1000_BLK_PHY_RESET 12
712#define E1000_ERR_SWFW_SYNC 13
713#define E1000_NOT_IMPLEMENTED 14
714#define E1000_ERR_MBX 15
715#define E1000_ERR_INVALID_ARGUMENT 16
716#define E1000_ERR_NO_SPACE 17
717#define E1000_ERR_NVM_PBA_SECTION 18
718#define E1000_ERR_I2C 19
719#define E1000_ERR_INVM_VALUE_NOT_FOUND 20
720
721/* Loop limit on how long we wait for auto-negotiation to complete */
722#define FIBER_LINK_UP_LIMIT 50
723#define COPPER_LINK_UP_LIMIT 10
724#define PHY_AUTO_NEG_LIMIT 45
725#define PHY_FORCE_LIMIT 20
726/* Number of 100 microseconds we wait for PCI Express master disable */
727#define MASTER_DISABLE_TIMEOUT 800
728/* Number of milliseconds we wait for PHY configuration done after MAC reset */
729#define PHY_CFG_TIMEOUT 100
730/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
731#define MDIO_OWNERSHIP_TIMEOUT 10
732/* Number of milliseconds for NVM auto read done after MAC reset. */
733#define AUTO_READ_DONE_TIMEOUT 10
734
735/* Flow Control */
736#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
737#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
738#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
739
740/* Transmit Configuration Word */
741#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
742#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
743#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
744#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
745#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
746
747/* Receive Configuration Word */
748#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
749#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
750#define E1000_RXCW_C 0x20000000 /* Receive config */
751#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
752
753#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
754#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
755
| 202#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
203#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
204#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
205/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
206#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
207#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
208#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
209#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
210/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
211#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
212#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
213#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
214#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
215#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
216#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
217#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
218#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
219#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
220#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
221
222/* Use byte values for the following shift parameters
223 * Usage:
224 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
225 * E1000_PSRCTL_BSIZE0_MASK) |
226 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
227 * E1000_PSRCTL_BSIZE1_MASK) |
228 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
229 * E1000_PSRCTL_BSIZE2_MASK) |
230 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
231 * E1000_PSRCTL_BSIZE3_MASK))
232 * where value0 = [128..16256], default=256
233 * value1 = [1024..64512], default=4096
234 * value2 = [0..64512], default=4096
235 * value3 = [0..64512], default=0
236 */
237
238#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
239#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
240#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
241#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
242
243#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
244#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
245#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
246#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
247
248/* SWFW_SYNC Definitions */
249#define E1000_SWFW_EEP_SM 0x01
250#define E1000_SWFW_PHY0_SM 0x02
251#define E1000_SWFW_PHY1_SM 0x04
252#define E1000_SWFW_CSR_SM 0x08
253#define E1000_SWFW_PHY2_SM 0x20
254#define E1000_SWFW_PHY3_SM 0x40
255#define E1000_SWFW_SW_MNG_SM 0x400
256
257/* Device Control */
258#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
259#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
260#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
261#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
262#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
264#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
265#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
266#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
267#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
268#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
269#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
270#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
271#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
272#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
273#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
274#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
275#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
276#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
277#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
278#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
279#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
280#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
281#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
282#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
283#define E1000_CTRL_RST 0x04000000 /* Global reset */
284#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
285#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
286#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
287#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
288#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
289
290#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
291#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
292#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
293#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
294
295#define E1000_CONNSW_ENRGSRC 0x4
296#define E1000_CONNSW_PHYSD 0x400
297#define E1000_CONNSW_PHY_PDN 0x800
298#define E1000_CONNSW_SERDESD 0x200
299#define E1000_CONNSW_AUTOSENSE_CONF 0x2
300#define E1000_CONNSW_AUTOSENSE_EN 0x1
301#define E1000_PCS_CFG_PCS_EN 8
302#define E1000_PCS_LCTL_FLV_LINK_UP 1
303#define E1000_PCS_LCTL_FSV_10 0
304#define E1000_PCS_LCTL_FSV_100 2
305#define E1000_PCS_LCTL_FSV_1000 4
306#define E1000_PCS_LCTL_FDV_FULL 8
307#define E1000_PCS_LCTL_FSD 0x10
308#define E1000_PCS_LCTL_FORCE_LINK 0x20
309#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
310#define E1000_PCS_LCTL_AN_ENABLE 0x10000
311#define E1000_PCS_LCTL_AN_RESTART 0x20000
312#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
313#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
314
315#define E1000_PCS_LSTS_LINK_OK 1
316#define E1000_PCS_LSTS_SPEED_100 2
317#define E1000_PCS_LSTS_SPEED_1000 4
318#define E1000_PCS_LSTS_DUPLEX_FULL 8
319#define E1000_PCS_LSTS_SYNK_OK 0x10
320#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
321
322/* Device Status */
323#define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
324#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
325#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
326#define E1000_STATUS_FUNC_SHIFT 2
327#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
328#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
329#define E1000_STATUS_SPEED_MASK 0x000000C0
330#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
331#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
332#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
333#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
334#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
335#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
336#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
337#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
338#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
339#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
340#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
342
343/* Constants used to interpret the masked PCI-X bus speed. */
344#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
347
348#define SPEED_10 10
349#define SPEED_100 100
350#define SPEED_1000 1000
351#define SPEED_2500 2500
352#define HALF_DUPLEX 1
353#define FULL_DUPLEX 2
354
355#define PHY_FORCE_TIME 20
356
357#define ADVERTISE_10_HALF 0x0001
358#define ADVERTISE_10_FULL 0x0002
359#define ADVERTISE_100_HALF 0x0004
360#define ADVERTISE_100_FULL 0x0008
361#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
362#define ADVERTISE_1000_FULL 0x0020
363
364/* 1000/H is not supported, nor spec-compliant. */
365#define E1000_ALL_SPEED_DUPLEX ( \
366 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
367 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
368#define E1000_ALL_NOT_GIG ( \
369 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
370 ADVERTISE_100_FULL)
371#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
372#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
373#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
374
375#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
376
377/* LED Control */
378#define E1000_PHY_LED0_MODE_MASK 0x00000007
379#define E1000_PHY_LED0_IVRT 0x00000008
380#define E1000_PHY_LED0_MASK 0x0000001F
381
382#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
383#define E1000_LEDCTL_LED0_MODE_SHIFT 0
384#define E1000_LEDCTL_LED0_IVRT 0x00000040
385#define E1000_LEDCTL_LED0_BLINK 0x00000080
386
387#define E1000_LEDCTL_MODE_LINK_UP 0x2
388#define E1000_LEDCTL_MODE_LED_ON 0xE
389#define E1000_LEDCTL_MODE_LED_OFF 0xF
390
391/* Transmit Descriptor bit definitions */
392#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
393#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
394#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
395#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
396#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
397#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
398#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
399#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
400#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
401#define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
402#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
403#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
404#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
405#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
406#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
407#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
408#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
409#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
410#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
411#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
412#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
413
414/* Transmit Control */
415#define E1000_TCTL_EN 0x00000002 /* enable Tx */
416#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
417#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
418#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
419#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
420#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
421
422/* Transmit Arbitration Count */
423#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
424
425/* SerDes Control */
426#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
427#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
428
429/* Receive Checksum Control */
430#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
431#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
432#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
433#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
434#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
435
436/* Header split receive */
437#define E1000_RFCTL_NFSW_DIS 0x00000040
438#define E1000_RFCTL_NFSR_DIS 0x00000080
439#define E1000_RFCTL_ACK_DIS 0x00001000
440#define E1000_RFCTL_EXTEN 0x00008000
441#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
442#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
443#define E1000_RFCTL_LEF 0x00040000
444
445/* Collision related configuration parameters */
446#define E1000_COLLISION_THRESHOLD 15
447#define E1000_CT_SHIFT 4
448#define E1000_COLLISION_DISTANCE 63
449#define E1000_COLD_SHIFT 12
450
451/* Default values for the transmit IPG register */
452#define DEFAULT_82542_TIPG_IPGT 10
453#define DEFAULT_82543_TIPG_IPGT_FIBER 9
454#define DEFAULT_82543_TIPG_IPGT_COPPER 8
455
456#define E1000_TIPG_IPGT_MASK 0x000003FF
457
458#define DEFAULT_82542_TIPG_IPGR1 2
459#define DEFAULT_82543_TIPG_IPGR1 8
460#define E1000_TIPG_IPGR1_SHIFT 10
461
462#define DEFAULT_82542_TIPG_IPGR2 10
463#define DEFAULT_82543_TIPG_IPGR2 6
464#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
465#define E1000_TIPG_IPGR2_SHIFT 20
466
467/* Ethertype field values */
468#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
469
470#define ETHERNET_FCS_SIZE 4
471#define MAX_JUMBO_FRAME_SIZE 0x3F00
472#define E1000_TX_PTR_GAP 0x1F
473
474/* Extended Configuration Control and Size */
475#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
476#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
477#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
478#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
479#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
480#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
481#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
482#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
483#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
484
485#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
486#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
487#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
488#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
489
490#define E1000_KABGTXD_BGSQLBIAS 0x00050000
491
492/* Low Power IDLE Control */
493#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */
494
495/* PBA constants */
496#define E1000_PBA_8K 0x0008 /* 8KB */
497#define E1000_PBA_10K 0x000A /* 10KB */
498#define E1000_PBA_12K 0x000C /* 12KB */
499#define E1000_PBA_14K 0x000E /* 14KB */
500#define E1000_PBA_16K 0x0010 /* 16KB */
501#define E1000_PBA_18K 0x0012
502#define E1000_PBA_20K 0x0014
503#define E1000_PBA_22K 0x0016
504#define E1000_PBA_24K 0x0018
505#define E1000_PBA_26K 0x001A
506#define E1000_PBA_30K 0x001E
507#define E1000_PBA_32K 0x0020
508#define E1000_PBA_34K 0x0022
509#define E1000_PBA_35K 0x0023
510#define E1000_PBA_38K 0x0026
511#define E1000_PBA_40K 0x0028
512#define E1000_PBA_48K 0x0030 /* 48KB */
513#define E1000_PBA_64K 0x0040 /* 64KB */
514
515#define E1000_PBA_RXA_MASK 0xFFFF
516
517#define E1000_PBS_16K E1000_PBA_16K
518
519/* Uncorrectable/correctable ECC Error counts and enable bits */
520#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
521#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
522#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
523#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
524
525#define IFS_MAX 80
526#define IFS_MIN 40
527#define IFS_RATIO 4
528#define IFS_STEP 10
529#define MIN_NUM_XMITS 1000
530
531/* SW Semaphore Register */
532#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
533#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
534#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
535
536#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
537
538/* Interrupt Cause Read */
539#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
540#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
541#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
542#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
543#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
544#define E1000_ICR_RXO 0x00000040 /* Rx overrun */
545#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
546#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
547#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
548#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
549#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
550#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
551#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
552#define E1000_ICR_TXD_LOW 0x00008000
553#define E1000_ICR_MNG 0x00040000 /* Manageability event */
554#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
555#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
556#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
557/* If this bit asserted, the driver should claim the interrupt */
558#define E1000_ICR_INT_ASSERTED 0x80000000
559#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
560#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
561#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
562#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
563#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
564#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
565#define E1000_ICR_FER 0x00400000 /* Fatal Error */
566
567#define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
568#define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
569
570#define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
571#define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */
572
573/* PBA ECC Register */
574#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
575#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
576#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
577#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
578#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
579
580/* Extended Interrupt Cause Read */
581#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
582#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
583#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
584#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
585#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
586#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
587#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
588#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
589#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
590#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
591/* TCP Timer */
592#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
593#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
594#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
595#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
596
597/* This defines the bits that are set in the Interrupt Mask
598 * Set/Read Register. Each bit is documented below:
599 * o RXT0 = Receiver Timer Interrupt (ring 0)
600 * o TXDW = Transmit Descriptor Written Back
601 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
602 * o RXSEQ = Receive Sequence Error
603 * o LSC = Link Status Change
604 */
605#define IMS_ENABLE_MASK ( \
606 E1000_IMS_RXT0 | \
607 E1000_IMS_TXDW | \
608 E1000_IMS_RXDMT0 | \
609 E1000_IMS_RXSEQ | \
610 E1000_IMS_LSC)
611
612/* Interrupt Mask Set */
613#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
614#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
615#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
616#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
617#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
618#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
619#define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
620#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
621#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
622#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
623#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
624#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
625#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
626#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
627#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
628#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
629#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
630#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
631#define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
632
633#define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
634#define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
635/* Extended Interrupt Mask Set */
636#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
637#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
638#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
639#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
640#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
641#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
642#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
643#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
644#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
645#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
646
647/* Interrupt Cause Set */
648#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
649#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
650#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
651
652/* Extended Interrupt Cause Set */
653#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
654#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
655#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
656#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
657#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
658#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
659#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
660#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
661#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
662#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
663
664#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
665/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
666#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
667#define E1000_EITR_INTERVAL 0x00007FFC
668
669/* Transmit Descriptor Control */
670#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
671#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
672#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
673#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
674#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
675#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
676/* Enable the counting of descriptors still to be processed. */
677#define E1000_TXDCTL_COUNT_DESC 0x00400000
678
679/* Flow Control Constants */
680#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
681#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
682#define FLOW_CONTROL_TYPE 0x8808
683
684/* 802.1q VLAN Packet Size */
685#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
686#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
687
688/* Receive Address
689 * Number of high/low register pairs in the RAR. The RAR (Receive Address
690 * Registers) holds the directed and multicast addresses that we monitor.
691 * Technically, we have 16 spots. However, we reserve one of these spots
692 * (RAR[15]) for our directed address used by controllers with
693 * manageability enabled, allowing us room for 15 multicast addresses.
694 */
695#define E1000_RAR_ENTRIES 15
696#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
697#define E1000_RAL_MAC_ADDR_LEN 4
698#define E1000_RAH_MAC_ADDR_LEN 2
699#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
700#define E1000_RAH_POOL_1 0x00040000
701
702/* Error Codes */
703#define E1000_SUCCESS 0
704#define E1000_ERR_NVM 1
705#define E1000_ERR_PHY 2
706#define E1000_ERR_CONFIG 3
707#define E1000_ERR_PARAM 4
708#define E1000_ERR_MAC_INIT 5
709#define E1000_ERR_PHY_TYPE 6
710#define E1000_ERR_RESET 9
711#define E1000_ERR_MASTER_REQUESTS_PENDING 10
712#define E1000_ERR_HOST_INTERFACE_COMMAND 11
713#define E1000_BLK_PHY_RESET 12
714#define E1000_ERR_SWFW_SYNC 13
715#define E1000_NOT_IMPLEMENTED 14
716#define E1000_ERR_MBX 15
717#define E1000_ERR_INVALID_ARGUMENT 16
718#define E1000_ERR_NO_SPACE 17
719#define E1000_ERR_NVM_PBA_SECTION 18
720#define E1000_ERR_I2C 19
721#define E1000_ERR_INVM_VALUE_NOT_FOUND 20
722
723/* Loop limit on how long we wait for auto-negotiation to complete */
724#define FIBER_LINK_UP_LIMIT 50
725#define COPPER_LINK_UP_LIMIT 10
726#define PHY_AUTO_NEG_LIMIT 45
727#define PHY_FORCE_LIMIT 20
728/* Number of 100 microseconds we wait for PCI Express master disable */
729#define MASTER_DISABLE_TIMEOUT 800
730/* Number of milliseconds we wait for PHY configuration done after MAC reset */
731#define PHY_CFG_TIMEOUT 100
732/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
733#define MDIO_OWNERSHIP_TIMEOUT 10
734/* Number of milliseconds for NVM auto read done after MAC reset. */
735#define AUTO_READ_DONE_TIMEOUT 10
736
737/* Flow Control */
738#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
739#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
740#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
741
742/* Transmit Configuration Word */
743#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
744#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
745#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
746#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
747#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
748
749/* Receive Configuration Word */
750#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
751#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
752#define E1000_RXCW_C 0x20000000 /* Receive config */
753#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
754
755#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
756#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
757
|
| 758/* HH Time Sync */
759#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
760#define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
761#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
762#define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
763
|
756#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
757#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
758#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
759#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
760#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
761#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
762#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
763#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
764#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
765
766#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
767#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
768
769#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
770#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
771
772#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
773#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
774#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
775#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
776#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
777#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
778
779#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
780#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
781#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
782#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
783#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
784#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
785#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
786#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
787#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
788#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
789#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
790
791#define E1000_TIMINCA_16NS_SHIFT 24
792#define E1000_TIMINCA_INCPERIOD_SHIFT 24
793#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
794
795#define E1000_TSICR_TXTS 0x00000002
796#define E1000_TSIM_TXTS 0x00000002
797/* TUPLE Filtering Configuration */
798#define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
799#define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
800#define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
801/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
802#define E1000_TTQF_PROTOCOL_TCP 0x0
803/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
804#define E1000_TTQF_PROTOCOL_UDP 0x1
805/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
806#define E1000_TTQF_PROTOCOL_SCTP 0x2
807#define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
808#define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
809#define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
810#define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
811#define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
812#define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
813#define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
814#define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
815
816#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
817#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
818#define E1000_MDICNFG_PHY_MASK 0x03E00000
819#define E1000_MDICNFG_PHY_SHIFT 21
820
821#define E1000_MEDIA_PORT_COPPER 1
822#define E1000_MEDIA_PORT_OTHER 2
823#define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
824#define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
825#define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
826#define E1000_M88E1112_MAC_CTRL_1 0x10
827#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
828#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
829#define E1000_M88E1112_PAGE_ADDR 0x16
830#define E1000_M88E1112_STATUS 0x01
831
832#define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
833#define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
834#define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
835#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
836#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
837
838/* I350 EEE defines */
839#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
840#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
841#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
842#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
843#define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
844/* EEE status */
845#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
846#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
847#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
848#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
849#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
850#define E1000_M88E1543_EEE_CTRL_1 0x0
851#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
| 764#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
765#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
766#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
767#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
768#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
769#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
770#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
771#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
772#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
773
774#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
775#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
776
777#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
778#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
779
780#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
781#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
782#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
783#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
784#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
785#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
786
787#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
788#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
789#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
790#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
791#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
792#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
793#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
794#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
795#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
796#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
797#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
798
799#define E1000_TIMINCA_16NS_SHIFT 24
800#define E1000_TIMINCA_INCPERIOD_SHIFT 24
801#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
802
803#define E1000_TSICR_TXTS 0x00000002
804#define E1000_TSIM_TXTS 0x00000002
805/* TUPLE Filtering Configuration */
806#define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
807#define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
808#define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
809/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
810#define E1000_TTQF_PROTOCOL_TCP 0x0
811/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
812#define E1000_TTQF_PROTOCOL_UDP 0x1
813/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
814#define E1000_TTQF_PROTOCOL_SCTP 0x2
815#define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
816#define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
817#define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
818#define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
819#define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
820#define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
821#define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
822#define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
823
824#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
825#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
826#define E1000_MDICNFG_PHY_MASK 0x03E00000
827#define E1000_MDICNFG_PHY_SHIFT 21
828
829#define E1000_MEDIA_PORT_COPPER 1
830#define E1000_MEDIA_PORT_OTHER 2
831#define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
832#define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
833#define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
834#define E1000_M88E1112_MAC_CTRL_1 0x10
835#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
836#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
837#define E1000_M88E1112_PAGE_ADDR 0x16
838#define E1000_M88E1112_STATUS 0x01
839
840#define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
841#define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
842#define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
843#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
844#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
845
846/* I350 EEE defines */
847#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
848#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
849#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
850#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
851#define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
852/* EEE status */
853#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
854#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
855#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
856#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
857#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
858#define E1000_M88E1543_EEE_CTRL_1 0x0
859#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
|
| 860#define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */
|
852#define E1000_EEE_ADV_DEV_I354 7
853#define E1000_EEE_ADV_ADDR_I354 60
854#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
855#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
856#define E1000_PCS_STATUS_DEV_I354 3
857#define E1000_PCS_STATUS_ADDR_I354 1
858#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
859#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
860#define E1000_M88E1512_CFG_REG_1 0x0010
861#define E1000_M88E1512_CFG_REG_2 0x0011
862#define E1000_M88E1512_CFG_REG_3 0x0007
863#define E1000_M88E1512_MODE 0x0014
864#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
865#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
866#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
867/* PCI Express Control */
868#define E1000_GCR_RXD_NO_SNOOP 0x00000001
869#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
870#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
871#define E1000_GCR_TXD_NO_SNOOP 0x00000008
872#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
873#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
874#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
875#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
876#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
877#define E1000_GCR_CAP_VER2 0x00040000
878
879#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
880 E1000_GCR_RXDSCW_NO_SNOOP | \
881 E1000_GCR_RXDSCR_NO_SNOOP | \
882 E1000_GCR_TXD_NO_SNOOP | \
883 E1000_GCR_TXDSCW_NO_SNOOP | \
884 E1000_GCR_TXDSCR_NO_SNOOP)
885
886#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
887
888/* mPHY address control and data registers */
889#define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
890#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
891#define E1000_MPHY_DATA 0x0E10 /* Data Register */
892
893/* AFE CSR Offset for PCS CLK */
894#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
895/* Override for near end digital loopback. */
896#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
897
898/* PHY Control Register */
899#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
900#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
901#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
902#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
903#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
904#define MII_CR_POWER_DOWN 0x0800 /* Power down */
905#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
906#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
907#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
908#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
909#define MII_CR_SPEED_1000 0x0040
910#define MII_CR_SPEED_100 0x2000
911#define MII_CR_SPEED_10 0x0000
912
913/* PHY Status Register */
914#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
915#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
916#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
917#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
918#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
919#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
920#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
921#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
922#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
923#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
924#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
925#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
926#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
927#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
928#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
929
930/* Autoneg Advertisement Register */
931#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
932#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
933#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
934#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
935#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
936#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
937#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
938#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
939#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
940#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
941
942/* Link Partner Ability Register (Base Page) */
943#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
944#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
945#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
946#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
947#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
948#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
949#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
950#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
951#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
952#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
953#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
954
955/* Autoneg Expansion Register */
956#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
957#define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
958#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
959#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
960#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
961
962/* 1000BASE-T Control Register */
963#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
964#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
965#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
966/* 1=Repeater/switch device port 0=DTE device */
967#define CR_1000T_REPEATER_DTE 0x0400
968/* 1=Configure PHY as Master 0=Configure PHY as Slave */
969#define CR_1000T_MS_VALUE 0x0800
970/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
971#define CR_1000T_MS_ENABLE 0x1000
972#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
973#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
974#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
975#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
976#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
977
978/* 1000BASE-T Status Register */
979#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
980#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
981#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
982#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
983#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
984#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
985#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
986#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
987
988#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
989
990/* PHY 1000 MII Register/Bit Definitions */
991/* PHY Registers defined by IEEE */
992#define PHY_CONTROL 0x00 /* Control Register */
993#define PHY_STATUS 0x01 /* Status Register */
994#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
995#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
996#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
997#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
998#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
999#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1000#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1001#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1002#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1003#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1004
1005#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1006
1007/* NVM Control */
1008#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1009#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1010#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1011#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1012#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1013#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1014#define E1000_EECD_PRES 0x00000100 /* NVM Present */
1015#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1016#define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1017#define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1018#define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1019#define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1020/* NVM Addressing bits based on type 0=small, 1=large */
1021#define E1000_EECD_ADDR_BITS 0x00000400
1022#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
| 861#define E1000_EEE_ADV_DEV_I354 7
862#define E1000_EEE_ADV_ADDR_I354 60
863#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
864#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
865#define E1000_PCS_STATUS_DEV_I354 3
866#define E1000_PCS_STATUS_ADDR_I354 1
867#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
868#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
869#define E1000_M88E1512_CFG_REG_1 0x0010
870#define E1000_M88E1512_CFG_REG_2 0x0011
871#define E1000_M88E1512_CFG_REG_3 0x0007
872#define E1000_M88E1512_MODE 0x0014
873#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
874#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
875#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
876/* PCI Express Control */
877#define E1000_GCR_RXD_NO_SNOOP 0x00000001
878#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
879#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
880#define E1000_GCR_TXD_NO_SNOOP 0x00000008
881#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
882#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
883#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
884#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
885#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
886#define E1000_GCR_CAP_VER2 0x00040000
887
888#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
889 E1000_GCR_RXDSCW_NO_SNOOP | \
890 E1000_GCR_RXDSCR_NO_SNOOP | \
891 E1000_GCR_TXD_NO_SNOOP | \
892 E1000_GCR_TXDSCW_NO_SNOOP | \
893 E1000_GCR_TXDSCR_NO_SNOOP)
894
895#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
896
897/* mPHY address control and data registers */
898#define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
899#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
900#define E1000_MPHY_DATA 0x0E10 /* Data Register */
901
902/* AFE CSR Offset for PCS CLK */
903#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
904/* Override for near end digital loopback. */
905#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
906
907/* PHY Control Register */
908#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
909#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
910#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
911#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
912#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
913#define MII_CR_POWER_DOWN 0x0800 /* Power down */
914#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
915#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
916#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
917#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
918#define MII_CR_SPEED_1000 0x0040
919#define MII_CR_SPEED_100 0x2000
920#define MII_CR_SPEED_10 0x0000
921
922/* PHY Status Register */
923#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
924#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
925#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
926#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
927#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
928#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
929#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
930#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
931#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
932#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
933#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
934#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
935#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
936#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
937#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
938
939/* Autoneg Advertisement Register */
940#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
941#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
942#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
943#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
944#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
945#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
946#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
947#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
948#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
949#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
950
951/* Link Partner Ability Register (Base Page) */
952#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
953#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
954#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
955#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
956#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
957#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
958#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
959#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
960#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
961#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
962#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
963
964/* Autoneg Expansion Register */
965#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
966#define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
967#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
968#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
969#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
970
971/* 1000BASE-T Control Register */
972#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
973#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
974#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
975/* 1=Repeater/switch device port 0=DTE device */
976#define CR_1000T_REPEATER_DTE 0x0400
977/* 1=Configure PHY as Master 0=Configure PHY as Slave */
978#define CR_1000T_MS_VALUE 0x0800
979/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
980#define CR_1000T_MS_ENABLE 0x1000
981#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
982#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
983#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
984#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
985#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
986
987/* 1000BASE-T Status Register */
988#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
989#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
990#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
991#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
992#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
993#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
994#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
995#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
996
997#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
998
999/* PHY 1000 MII Register/Bit Definitions */
1000/* PHY Registers defined by IEEE */
1001#define PHY_CONTROL 0x00 /* Control Register */
1002#define PHY_STATUS 0x01 /* Status Register */
1003#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1004#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1005#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1006#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1007#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1008#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1009#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1010#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1011#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1012#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1013
1014#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1015
1016/* NVM Control */
1017#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1018#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1019#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1020#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1021#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1022#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1023#define E1000_EECD_PRES 0x00000100 /* NVM Present */
1024#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1025#define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1026#define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1027#define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1028#define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1029/* NVM Addressing bits based on type 0=small, 1=large */
1030#define E1000_EECD_ADDR_BITS 0x00000400
1031#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
|
1023#ifndef E1000_NVM_GRANT_ATTEMPTS
| |
1024#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
| 1032#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
|
1025#endif
| |
1026#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1027#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1028#define E1000_EECD_SIZE_EX_SHIFT 11
1029#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1030#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
1031#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1032#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1033#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
1034#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
1035#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
1036#define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */
1037#define E1000_FLUDONE_ATTEMPTS 20000
1038#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
1039#define E1000_I210_FIFO_SEL_RX 0x00
1040#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
1041#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
1042#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
1043#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
1044
1045#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
1046/* Secure FLASH mode requires removing MSb */
1047#define E1000_I210_FW_PTR_MASK 0x7FFF
1048/* Firmware code revision field word offset*/
1049#define E1000_I210_FW_VER_OFFSET 328
1050
1051#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1052#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1053#define E1000_NVM_RW_REG_START 1 /* Start operation */
1054#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1055#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1056#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1057#define E1000_FLASH_UPDATES 2000
1058
1059/* NVM Word Offsets */
1060#define NVM_COMPAT 0x0003
1061#define NVM_ID_LED_SETTINGS 0x0004
1062#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1063#define NVM_PHY_CLASS_WORD 0x0007
1064#define E1000_I210_NVM_FW_MODULE_PTR 0x0010
1065#define E1000_I350_NVM_FW_MODULE_PTR 0x0051
1066#define NVM_FUTURE_INIT_WORD1 0x0019
1067#define NVM_MAC_ADDR 0x0000
1068#define NVM_SUB_DEV_ID 0x000B
1069#define NVM_SUB_VEN_ID 0x000C
1070#define NVM_DEV_ID 0x000D
1071#define NVM_VEN_ID 0x000E
1072#define NVM_INIT_CTRL_2 0x000F
1073#define NVM_INIT_CTRL_4 0x0013
1074#define NVM_LED_1_CFG 0x001C
1075#define NVM_LED_0_2_CFG 0x001F
1076
1077#define NVM_COMPAT_VALID_CSUM 0x0001
1078#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
1079
1080#define NVM_INIT_CONTROL2_REG 0x000F
1081#define NVM_INIT_CONTROL3_PORT_B 0x0014
1082#define NVM_INIT_3GIO_3 0x001A
1083#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1084#define NVM_INIT_CONTROL3_PORT_A 0x0024
1085#define NVM_CFG 0x0012
1086#define NVM_ALT_MAC_ADDR_PTR 0x0037
1087#define NVM_CHECKSUM_REG 0x003F
1088#define NVM_COMPATIBILITY_REG_3 0x0003
1089#define NVM_COMPATIBILITY_BIT_MASK 0x8000
1090
1091#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1092#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1093#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1094#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1095
1096#define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1097
1098/* Mask bits for fields in Word 0x24 of the NVM */
1099#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1100#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1101/* Offset of Link Mode bits for 82575/82576 */
1102#define NVM_WORD24_LNK_MODE_OFFSET 8
1103/* Offset of Link Mode bits for 82580 up */
1104#define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1105
1106
1107/* Mask bits for fields in Word 0x0f of the NVM */
1108#define NVM_WORD0F_PAUSE_MASK 0x3000
1109#define NVM_WORD0F_PAUSE 0x1000
1110#define NVM_WORD0F_ASM_DIR 0x2000
1111#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1112
1113/* Mask bits for fields in Word 0x1a of the NVM */
1114#define NVM_WORD1A_ASPM_MASK 0x000C
1115
1116/* Mask bits for fields in Word 0x03 of the EEPROM */
1117#define NVM_COMPAT_LOM 0x0800
1118
1119/* length of string needed to store PBA number */
1120#define E1000_PBANUM_LENGTH 11
1121
1122/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1123#define NVM_SUM 0xBABA
1124
1125/* PBA (printed board assembly) number words */
1126#define NVM_PBA_OFFSET_0 8
1127#define NVM_PBA_OFFSET_1 9
1128#define NVM_PBA_PTR_GUARD 0xFAFA
1129#define NVM_RESERVED_WORD 0xFFFF
1130#define NVM_PHY_CLASS_A 0x8000
1131#define NVM_SERDES_AMPLITUDE_MASK 0x000F
1132#define NVM_SIZE_MASK 0x1C00
1133#define NVM_SIZE_SHIFT 10
1134#define NVM_WORD_SIZE_BASE_SHIFT 6
1135#define NVM_SWDPIO_EXT_SHIFT 4
1136
1137/* NVM Commands - Microwire */
1138#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1139#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1140#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1141#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1142#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1143
1144/* NVM Commands - SPI */
1145#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1146#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1147#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1148#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1149#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1150#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1151
1152/* SPI NVM Status Register */
1153#define NVM_STATUS_RDY_SPI 0x01
1154
1155/* Word definitions for ID LED Settings */
1156#define ID_LED_RESERVED_0000 0x0000
1157#define ID_LED_RESERVED_FFFF 0xFFFF
1158#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1159 (ID_LED_OFF1_OFF2 << 8) | \
1160 (ID_LED_DEF1_DEF2 << 4) | \
1161 (ID_LED_DEF1_DEF2))
1162#define ID_LED_DEF1_DEF2 0x1
1163#define ID_LED_DEF1_ON2 0x2
1164#define ID_LED_DEF1_OFF2 0x3
1165#define ID_LED_ON1_DEF2 0x4
1166#define ID_LED_ON1_ON2 0x5
1167#define ID_LED_ON1_OFF2 0x6
1168#define ID_LED_OFF1_DEF2 0x7
1169#define ID_LED_OFF1_ON2 0x8
1170#define ID_LED_OFF1_OFF2 0x9
1171
1172#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1173#define IGP_ACTIVITY_LED_ENABLE 0x0300
1174#define IGP_LED3_MODE 0x07000000
1175
1176/* PCI/PCI-X/PCI-EX Config space */
1177#define PCIX_COMMAND_REGISTER 0xE6
1178#define PCIX_STATUS_REGISTER_LO 0xE8
1179#define PCIX_STATUS_REGISTER_HI 0xEA
1180#define PCI_HEADER_TYPE_REGISTER 0x0E
1181#define PCIE_LINK_STATUS 0x12
1182#define PCIE_DEVICE_CONTROL2 0x28
1183
1184#define PCIX_COMMAND_MMRBC_MASK 0x000C
1185#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1186#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1187#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1188#define PCIX_STATUS_HI_MMRBC_4K 0x3
1189#define PCIX_STATUS_HI_MMRBC_2K 0x2
1190#define PCIX_STATUS_LO_FUNC_MASK 0x7
1191#define PCI_HEADER_TYPE_MULTIFUNC 0x80
1192#define PCIE_LINK_WIDTH_MASK 0x3F0
1193#define PCIE_LINK_WIDTH_SHIFT 4
1194#define PCIE_LINK_SPEED_MASK 0x0F
1195#define PCIE_LINK_SPEED_2500 0x01
1196#define PCIE_LINK_SPEED_5000 0x02
1197#define PCIE_DEVICE_CONTROL2_16ms 0x0005
1198
1199#ifndef ETH_ADDR_LEN
1200#define ETH_ADDR_LEN 6
1201#endif
1202
1203#define PHY_REVISION_MASK 0xFFFFFFF0
1204#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1205#define MAX_PHY_MULTI_PAGE_REG 0xF
1206
1207/* Bit definitions for valid PHY IDs.
1208 * I = Integrated
1209 * E = External
1210 */
1211#define M88E1000_E_PHY_ID 0x01410C50
1212#define M88E1000_I_PHY_ID 0x01410C30
1213#define M88E1011_I_PHY_ID 0x01410C20
1214#define IGP01E1000_I_PHY_ID 0x02A80380
1215#define M88E1111_I_PHY_ID 0x01410CC0
1216#define M88E1543_E_PHY_ID 0x01410EA0
1217#define M88E1512_E_PHY_ID 0x01410DD0
1218#define M88E1112_E_PHY_ID 0x01410C90
1219#define I347AT4_E_PHY_ID 0x01410DC0
1220#define M88E1340M_E_PHY_ID 0x01410DF0
1221#define GG82563_E_PHY_ID 0x01410CA0
1222#define IGP03E1000_E_PHY_ID 0x02A80390
1223#define IFE_E_PHY_ID 0x02A80330
1224#define IFE_PLUS_E_PHY_ID 0x02A80320
1225#define IFE_C_E_PHY_ID 0x02A80310
1226#define BME1000_E_PHY_ID 0x01410CB0
1227#define BME1000_E_PHY_ID_R2 0x01410CB1
1228#define I82577_E_PHY_ID 0x01540050
1229#define I82578_E_PHY_ID 0x004DD040
1230#define I82579_E_PHY_ID 0x01540090
1231#define I217_E_PHY_ID 0x015400A0
1232#define I82580_I_PHY_ID 0x015403A0
1233#define I350_I_PHY_ID 0x015403B0
1234#define I210_I_PHY_ID 0x01410C00
1235#define IGP04E1000_E_PHY_ID 0x02A80391
1236#define M88_VENDOR 0x0141
1237
1238/* M88E1000 Specific Registers */
1239#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1240#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1241#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1242#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1243
1244#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1245#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1246#define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1247#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1248#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1249
1250/* M88E1000 PHY Specific Control Register */
1251#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1252/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1253#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1254#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1255/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1256#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1257/* Auto crossover enabled all speeds */
1258#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1259#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1260
1261/* M88E1000 PHY Specific Status Register */
1262#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1263#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1264#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1265/* 0 = <50M
1266 * 1 = 50-80M
1267 * 2 = 80-110M
1268 * 3 = 110-140M
1269 * 4 = >140M
1270 */
1271#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1272#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1273#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1274#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1275#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1276#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1277#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1278
1279#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1280
1281/* Number of times we will attempt to autonegotiate before downshifting if we
1282 * are the master
1283 */
1284#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1285#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1286/* Number of times we will attempt to autonegotiate before downshifting if we
1287 * are the slave
1288 */
1289#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1290#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1291#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1292
1293/* Intel I347AT4 Registers */
1294#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1295#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1296#define I347AT4_PAGE_SELECT 0x16
1297
1298/* I347AT4 Extended PHY Specific Control Register */
1299
1300/* Number of times we will attempt to autonegotiate before downshifting if we
1301 * are the master
1302 */
1303#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1304#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1305#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1306#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1307#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1308#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1309#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1310#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1311#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1312#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1313
1314/* I347AT4 PHY Cable Diagnostics Control */
1315#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1316
1317/* M88E1112 only registers */
1318#define M88E1112_VCT_DSP_DISTANCE 0x001A
1319
1320/* M88EC018 Rev 2 specific DownShift settings */
1321#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1322#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1323
1324#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1325#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1326
1327/* BME1000 PHY Specific Control Register */
1328#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1329
1330/* Bits...
1331 * 15-5: page
1332 * 4-0: register offset
1333 */
1334#define GG82563_PAGE_SHIFT 5
1335#define GG82563_REG(page, reg) \
1336 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1337#define GG82563_MIN_ALT_REG 30
1338
1339/* GG82563 Specific Registers */
1340#define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1341#define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1342#define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1343#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1344
1345/* MAC Specific Control Register */
1346#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1347
1348#define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1349
1350/* Page 193 - Port Control Registers */
1351/* Kumeran Mode Control */
1352#define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1353#define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1354
1355/* Page 194 - KMRN Registers */
1356#define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
1357
1358/* MDI Control */
1359#define E1000_MDIC_REG_MASK 0x001F0000
1360#define E1000_MDIC_REG_SHIFT 16
1361#define E1000_MDIC_PHY_MASK 0x03E00000
1362#define E1000_MDIC_PHY_SHIFT 21
1363#define E1000_MDIC_OP_WRITE 0x04000000
1364#define E1000_MDIC_OP_READ 0x08000000
1365#define E1000_MDIC_READY 0x10000000
1366#define E1000_MDIC_ERROR 0x40000000
1367#define E1000_MDIC_DEST 0x80000000
1368
1369/* SerDes Control */
1370#define E1000_GEN_CTL_READY 0x80000000
1371#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1372#define E1000_GEN_POLL_TIMEOUT 640
1373
1374/* LinkSec register fields */
1375#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1376#define E1000_LSECTXCAP_SUM_SHIFT 16
1377#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1378#define E1000_LSECRXCAP_SUM_SHIFT 16
1379
1380#define E1000_LSECTXCTRL_EN_MASK 0x00000003
1381#define E1000_LSECTXCTRL_DISABLE 0x0
1382#define E1000_LSECTXCTRL_AUTH 0x1
1383#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1384#define E1000_LSECTXCTRL_AISCI 0x00000020
1385#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1386#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1387
1388#define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1389#define E1000_LSECRXCTRL_EN_SHIFT 2
1390#define E1000_LSECRXCTRL_DISABLE 0x0
1391#define E1000_LSECRXCTRL_CHECK 0x1
1392#define E1000_LSECRXCTRL_STRICT 0x2
1393#define E1000_LSECRXCTRL_DROP 0x3
1394#define E1000_LSECRXCTRL_PLSH 0x00000040
1395#define E1000_LSECRXCTRL_RP 0x00000080
1396#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1397
1398/* Tx Rate-Scheduler Config fields */
1399#define E1000_RTTBCNRC_RS_ENA 0x80000000
1400#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1401#define E1000_RTTBCNRC_RF_INT_SHIFT 14
1402#define E1000_RTTBCNRC_RF_INT_MASK \
1403 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1404
1405/* DMA Coalescing register fields */
1406/* DMA Coalescing Watchdog Timer */
1407#define E1000_DMACR_DMACWT_MASK 0x00003FFF
1408/* DMA Coalescing Rx Threshold */
1409#define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1410#define E1000_DMACR_DMACTHR_SHIFT 16
1411/* Lx when no PCIe transactions */
1412#define E1000_DMACR_DMAC_LX_MASK 0x30000000
1413#define E1000_DMACR_DMAC_LX_SHIFT 28
1414#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1415/* DMA Coalescing BMC-to-OS Watchdog Enable */
1416#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1417
1418/* DMA Coalescing Transmit Threshold */
1419#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1420
1421#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1422
1423/* Rx Traffic Rate Threshold */
1424#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1425/* Rx packet rate in current window */
1426#define E1000_DMCRTRH_LRPRCW 0x80000000
1427
1428/* DMA Coal Rx Traffic Current Count */
1429#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1430
1431/* Flow ctrl Rx Threshold High val */
1432#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1433#define E1000_FCRTC_RTH_COAL_SHIFT 4
1434/* Lx power decision based on DMA coal */
1435#define E1000_PCIEMISC_LX_DECISION 0x00000080
1436
1437#define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1438#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1439#define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1440#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
1441#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
1442
1443#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
1444#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
1445
1446/* Proxy Filter Control */
1447#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1448#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1449#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1450#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1451#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1452#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1453#define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1454#define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
1455#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1456/* Proxy Status */
1457#define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1458
1459/* Firmware Status */
1460#define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1461/* VF Control */
1462#define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1463
1464#define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1465/* Lan ID bit field offset in status register */
1466#define E1000_STATUS_LAN_ID_OFFSET 2
1467#define E1000_VFTA_ENTRIES 128
1468#define E1000_UNUSEDARG
1469#ifndef ERROR_REPORT
1470#define ERROR_REPORT(fmt) do { } while (0)
1471#endif /* ERROR_REPORT */
1472#endif /* _E1000_DEFINES_H_ */
| 1033#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1034#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1035#define E1000_EECD_SIZE_EX_SHIFT 11
1036#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1037#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
1038#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1039#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1040#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
1041#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
1042#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
1043#define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */
1044#define E1000_FLUDONE_ATTEMPTS 20000
1045#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
1046#define E1000_I210_FIFO_SEL_RX 0x00
1047#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
1048#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
1049#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
1050#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
1051
1052#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
1053/* Secure FLASH mode requires removing MSb */
1054#define E1000_I210_FW_PTR_MASK 0x7FFF
1055/* Firmware code revision field word offset*/
1056#define E1000_I210_FW_VER_OFFSET 328
1057
1058#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1059#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1060#define E1000_NVM_RW_REG_START 1 /* Start operation */
1061#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1062#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1063#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1064#define E1000_FLASH_UPDATES 2000
1065
1066/* NVM Word Offsets */
1067#define NVM_COMPAT 0x0003
1068#define NVM_ID_LED_SETTINGS 0x0004
1069#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1070#define NVM_PHY_CLASS_WORD 0x0007
1071#define E1000_I210_NVM_FW_MODULE_PTR 0x0010
1072#define E1000_I350_NVM_FW_MODULE_PTR 0x0051
1073#define NVM_FUTURE_INIT_WORD1 0x0019
1074#define NVM_MAC_ADDR 0x0000
1075#define NVM_SUB_DEV_ID 0x000B
1076#define NVM_SUB_VEN_ID 0x000C
1077#define NVM_DEV_ID 0x000D
1078#define NVM_VEN_ID 0x000E
1079#define NVM_INIT_CTRL_2 0x000F
1080#define NVM_INIT_CTRL_4 0x0013
1081#define NVM_LED_1_CFG 0x001C
1082#define NVM_LED_0_2_CFG 0x001F
1083
1084#define NVM_COMPAT_VALID_CSUM 0x0001
1085#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
1086
1087#define NVM_INIT_CONTROL2_REG 0x000F
1088#define NVM_INIT_CONTROL3_PORT_B 0x0014
1089#define NVM_INIT_3GIO_3 0x001A
1090#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1091#define NVM_INIT_CONTROL3_PORT_A 0x0024
1092#define NVM_CFG 0x0012
1093#define NVM_ALT_MAC_ADDR_PTR 0x0037
1094#define NVM_CHECKSUM_REG 0x003F
1095#define NVM_COMPATIBILITY_REG_3 0x0003
1096#define NVM_COMPATIBILITY_BIT_MASK 0x8000
1097
1098#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1099#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1100#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1101#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1102
1103#define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1104
1105/* Mask bits for fields in Word 0x24 of the NVM */
1106#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1107#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1108/* Offset of Link Mode bits for 82575/82576 */
1109#define NVM_WORD24_LNK_MODE_OFFSET 8
1110/* Offset of Link Mode bits for 82580 up */
1111#define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1112
1113
1114/* Mask bits for fields in Word 0x0f of the NVM */
1115#define NVM_WORD0F_PAUSE_MASK 0x3000
1116#define NVM_WORD0F_PAUSE 0x1000
1117#define NVM_WORD0F_ASM_DIR 0x2000
1118#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1119
1120/* Mask bits for fields in Word 0x1a of the NVM */
1121#define NVM_WORD1A_ASPM_MASK 0x000C
1122
1123/* Mask bits for fields in Word 0x03 of the EEPROM */
1124#define NVM_COMPAT_LOM 0x0800
1125
1126/* length of string needed to store PBA number */
1127#define E1000_PBANUM_LENGTH 11
1128
1129/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1130#define NVM_SUM 0xBABA
1131
1132/* PBA (printed board assembly) number words */
1133#define NVM_PBA_OFFSET_0 8
1134#define NVM_PBA_OFFSET_1 9
1135#define NVM_PBA_PTR_GUARD 0xFAFA
1136#define NVM_RESERVED_WORD 0xFFFF
1137#define NVM_PHY_CLASS_A 0x8000
1138#define NVM_SERDES_AMPLITUDE_MASK 0x000F
1139#define NVM_SIZE_MASK 0x1C00
1140#define NVM_SIZE_SHIFT 10
1141#define NVM_WORD_SIZE_BASE_SHIFT 6
1142#define NVM_SWDPIO_EXT_SHIFT 4
1143
1144/* NVM Commands - Microwire */
1145#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1146#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1147#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1148#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1149#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1150
1151/* NVM Commands - SPI */
1152#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1153#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1154#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1155#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1156#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1157#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1158
1159/* SPI NVM Status Register */
1160#define NVM_STATUS_RDY_SPI 0x01
1161
1162/* Word definitions for ID LED Settings */
1163#define ID_LED_RESERVED_0000 0x0000
1164#define ID_LED_RESERVED_FFFF 0xFFFF
1165#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1166 (ID_LED_OFF1_OFF2 << 8) | \
1167 (ID_LED_DEF1_DEF2 << 4) | \
1168 (ID_LED_DEF1_DEF2))
1169#define ID_LED_DEF1_DEF2 0x1
1170#define ID_LED_DEF1_ON2 0x2
1171#define ID_LED_DEF1_OFF2 0x3
1172#define ID_LED_ON1_DEF2 0x4
1173#define ID_LED_ON1_ON2 0x5
1174#define ID_LED_ON1_OFF2 0x6
1175#define ID_LED_OFF1_DEF2 0x7
1176#define ID_LED_OFF1_ON2 0x8
1177#define ID_LED_OFF1_OFF2 0x9
1178
1179#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1180#define IGP_ACTIVITY_LED_ENABLE 0x0300
1181#define IGP_LED3_MODE 0x07000000
1182
1183/* PCI/PCI-X/PCI-EX Config space */
1184#define PCIX_COMMAND_REGISTER 0xE6
1185#define PCIX_STATUS_REGISTER_LO 0xE8
1186#define PCIX_STATUS_REGISTER_HI 0xEA
1187#define PCI_HEADER_TYPE_REGISTER 0x0E
1188#define PCIE_LINK_STATUS 0x12
1189#define PCIE_DEVICE_CONTROL2 0x28
1190
1191#define PCIX_COMMAND_MMRBC_MASK 0x000C
1192#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1193#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1194#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1195#define PCIX_STATUS_HI_MMRBC_4K 0x3
1196#define PCIX_STATUS_HI_MMRBC_2K 0x2
1197#define PCIX_STATUS_LO_FUNC_MASK 0x7
1198#define PCI_HEADER_TYPE_MULTIFUNC 0x80
1199#define PCIE_LINK_WIDTH_MASK 0x3F0
1200#define PCIE_LINK_WIDTH_SHIFT 4
1201#define PCIE_LINK_SPEED_MASK 0x0F
1202#define PCIE_LINK_SPEED_2500 0x01
1203#define PCIE_LINK_SPEED_5000 0x02
1204#define PCIE_DEVICE_CONTROL2_16ms 0x0005
1205
1206#ifndef ETH_ADDR_LEN
1207#define ETH_ADDR_LEN 6
1208#endif
1209
1210#define PHY_REVISION_MASK 0xFFFFFFF0
1211#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1212#define MAX_PHY_MULTI_PAGE_REG 0xF
1213
1214/* Bit definitions for valid PHY IDs.
1215 * I = Integrated
1216 * E = External
1217 */
1218#define M88E1000_E_PHY_ID 0x01410C50
1219#define M88E1000_I_PHY_ID 0x01410C30
1220#define M88E1011_I_PHY_ID 0x01410C20
1221#define IGP01E1000_I_PHY_ID 0x02A80380
1222#define M88E1111_I_PHY_ID 0x01410CC0
1223#define M88E1543_E_PHY_ID 0x01410EA0
1224#define M88E1512_E_PHY_ID 0x01410DD0
1225#define M88E1112_E_PHY_ID 0x01410C90
1226#define I347AT4_E_PHY_ID 0x01410DC0
1227#define M88E1340M_E_PHY_ID 0x01410DF0
1228#define GG82563_E_PHY_ID 0x01410CA0
1229#define IGP03E1000_E_PHY_ID 0x02A80390
1230#define IFE_E_PHY_ID 0x02A80330
1231#define IFE_PLUS_E_PHY_ID 0x02A80320
1232#define IFE_C_E_PHY_ID 0x02A80310
1233#define BME1000_E_PHY_ID 0x01410CB0
1234#define BME1000_E_PHY_ID_R2 0x01410CB1
1235#define I82577_E_PHY_ID 0x01540050
1236#define I82578_E_PHY_ID 0x004DD040
1237#define I82579_E_PHY_ID 0x01540090
1238#define I217_E_PHY_ID 0x015400A0
1239#define I82580_I_PHY_ID 0x015403A0
1240#define I350_I_PHY_ID 0x015403B0
1241#define I210_I_PHY_ID 0x01410C00
1242#define IGP04E1000_E_PHY_ID 0x02A80391
1243#define M88_VENDOR 0x0141
1244
1245/* M88E1000 Specific Registers */
1246#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1247#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1248#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1249#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1250
1251#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1252#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1253#define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1254#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1255#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1256
1257/* M88E1000 PHY Specific Control Register */
1258#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1259/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1260#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1261#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1262/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1263#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1264/* Auto crossover enabled all speeds */
1265#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1266#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1267
1268/* M88E1000 PHY Specific Status Register */
1269#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1270#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1271#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1272/* 0 = <50M
1273 * 1 = 50-80M
1274 * 2 = 80-110M
1275 * 3 = 110-140M
1276 * 4 = >140M
1277 */
1278#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1279#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1280#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1281#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1282#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1283#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1284#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1285
1286#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1287
1288/* Number of times we will attempt to autonegotiate before downshifting if we
1289 * are the master
1290 */
1291#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1292#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1293/* Number of times we will attempt to autonegotiate before downshifting if we
1294 * are the slave
1295 */
1296#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1297#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1298#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1299
1300/* Intel I347AT4 Registers */
1301#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1302#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1303#define I347AT4_PAGE_SELECT 0x16
1304
1305/* I347AT4 Extended PHY Specific Control Register */
1306
1307/* Number of times we will attempt to autonegotiate before downshifting if we
1308 * are the master
1309 */
1310#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1311#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1312#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1313#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1314#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1315#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1316#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1317#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1318#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1319#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1320
1321/* I347AT4 PHY Cable Diagnostics Control */
1322#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1323
1324/* M88E1112 only registers */
1325#define M88E1112_VCT_DSP_DISTANCE 0x001A
1326
1327/* M88EC018 Rev 2 specific DownShift settings */
1328#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1329#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1330
1331#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1332#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1333
1334/* BME1000 PHY Specific Control Register */
1335#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1336
1337/* Bits...
1338 * 15-5: page
1339 * 4-0: register offset
1340 */
1341#define GG82563_PAGE_SHIFT 5
1342#define GG82563_REG(page, reg) \
1343 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1344#define GG82563_MIN_ALT_REG 30
1345
1346/* GG82563 Specific Registers */
1347#define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1348#define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1349#define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1350#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1351
1352/* MAC Specific Control Register */
1353#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1354
1355#define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1356
1357/* Page 193 - Port Control Registers */
1358/* Kumeran Mode Control */
1359#define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1360#define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1361
1362/* Page 194 - KMRN Registers */
1363#define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
1364
1365/* MDI Control */
1366#define E1000_MDIC_REG_MASK 0x001F0000
1367#define E1000_MDIC_REG_SHIFT 16
1368#define E1000_MDIC_PHY_MASK 0x03E00000
1369#define E1000_MDIC_PHY_SHIFT 21
1370#define E1000_MDIC_OP_WRITE 0x04000000
1371#define E1000_MDIC_OP_READ 0x08000000
1372#define E1000_MDIC_READY 0x10000000
1373#define E1000_MDIC_ERROR 0x40000000
1374#define E1000_MDIC_DEST 0x80000000
1375
1376/* SerDes Control */
1377#define E1000_GEN_CTL_READY 0x80000000
1378#define E1000_GEN_CTL_ADDRESS_SHIFT 8
1379#define E1000_GEN_POLL_TIMEOUT 640
1380
1381/* LinkSec register fields */
1382#define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1383#define E1000_LSECTXCAP_SUM_SHIFT 16
1384#define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1385#define E1000_LSECRXCAP_SUM_SHIFT 16
1386
1387#define E1000_LSECTXCTRL_EN_MASK 0x00000003
1388#define E1000_LSECTXCTRL_DISABLE 0x0
1389#define E1000_LSECTXCTRL_AUTH 0x1
1390#define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1391#define E1000_LSECTXCTRL_AISCI 0x00000020
1392#define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1393#define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1394
1395#define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1396#define E1000_LSECRXCTRL_EN_SHIFT 2
1397#define E1000_LSECRXCTRL_DISABLE 0x0
1398#define E1000_LSECRXCTRL_CHECK 0x1
1399#define E1000_LSECRXCTRL_STRICT 0x2
1400#define E1000_LSECRXCTRL_DROP 0x3
1401#define E1000_LSECRXCTRL_PLSH 0x00000040
1402#define E1000_LSECRXCTRL_RP 0x00000080
1403#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1404
1405/* Tx Rate-Scheduler Config fields */
1406#define E1000_RTTBCNRC_RS_ENA 0x80000000
1407#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1408#define E1000_RTTBCNRC_RF_INT_SHIFT 14
1409#define E1000_RTTBCNRC_RF_INT_MASK \
1410 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1411
1412/* DMA Coalescing register fields */
1413/* DMA Coalescing Watchdog Timer */
1414#define E1000_DMACR_DMACWT_MASK 0x00003FFF
1415/* DMA Coalescing Rx Threshold */
1416#define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1417#define E1000_DMACR_DMACTHR_SHIFT 16
1418/* Lx when no PCIe transactions */
1419#define E1000_DMACR_DMAC_LX_MASK 0x30000000
1420#define E1000_DMACR_DMAC_LX_SHIFT 28
1421#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1422/* DMA Coalescing BMC-to-OS Watchdog Enable */
1423#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1424
1425/* DMA Coalescing Transmit Threshold */
1426#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1427
1428#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1429
1430/* Rx Traffic Rate Threshold */
1431#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1432/* Rx packet rate in current window */
1433#define E1000_DMCRTRH_LRPRCW 0x80000000
1434
1435/* DMA Coal Rx Traffic Current Count */
1436#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1437
1438/* Flow ctrl Rx Threshold High val */
1439#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1440#define E1000_FCRTC_RTH_COAL_SHIFT 4
1441/* Lx power decision based on DMA coal */
1442#define E1000_PCIEMISC_LX_DECISION 0x00000080
1443
1444#define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1445#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1446#define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1447#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
1448#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
1449
1450#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
1451#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
1452
1453/* Proxy Filter Control */
1454#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1455#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1456#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1457#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1458#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1459#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1460#define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1461#define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
1462#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1463/* Proxy Status */
1464#define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1465
1466/* Firmware Status */
1467#define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1468/* VF Control */
1469#define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1470
1471#define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1472/* Lan ID bit field offset in status register */
1473#define E1000_STATUS_LAN_ID_OFFSET 2
1474#define E1000_VFTA_ENTRIES 128
1475#define E1000_UNUSEDARG
1476#ifndef ERROR_REPORT
1477#define ERROR_REPORT(fmt) do { } while (0)
1478#endif /* ERROR_REPORT */
1479#endif /* _E1000_DEFINES_H_ */
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