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e1000_82575.h (194865) e1000_82575.h (200243)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.h 194865 2009-06-24 17:41:29Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.h 200243 2009-12-08 01:07:44Z jfv $*/
34
35#ifndef _E1000_82575_H_
36#define _E1000_82575_H_
37
38#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
39 (ID_LED_DEF1_DEF2 << 8) | \
40 (ID_LED_DEF1_DEF2 << 4) | \
41 (ID_LED_OFF1_ON2))

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46 * These entries are also used for MAC-based filtering.
47 */
48/*
49 * For 82576, there are an additional set of RARs that begin at an offset
50 * separate from the first set of RARs.
51 */
52#define E1000_RAR_ENTRIES_82575 16
53#define E1000_RAR_ENTRIES_82576 24
34
35#ifndef _E1000_82575_H_
36#define _E1000_82575_H_
37
38#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
39 (ID_LED_DEF1_DEF2 << 8) | \
40 (ID_LED_DEF1_DEF2 << 4) | \
41 (ID_LED_OFF1_ON2))

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46 * These entries are also used for MAC-based filtering.
47 */
48/*
49 * For 82576, there are an additional set of RARs that begin at an offset
50 * separate from the first set of RARs.
51 */
52#define E1000_RAR_ENTRIES_82575 16
53#define E1000_RAR_ENTRIES_82576 24
54#define E1000_RAR_ENTRIES_82580 24
55#define E1000_SW_SYNCH_MB 0x00000100
56#define E1000_STAT_DEV_RST_SET 0x00100000
57#define E1000_CTRL_DEV_RST 0x20000000
54
55#ifdef E1000_BIT_FIELDS
56struct e1000_adv_data_desc {
58
59#ifdef E1000_BIT_FIELDS
60struct e1000_adv_data_desc {
57 u64 buffer_addr; /* Address of the descriptor's data buffer */
61 __le64 buffer_addr; /* Address of the descriptor's data buffer */
58 union {
59 u32 data;
60 struct {
61 u32 datalen :16; /* Data buffer length */
62 u32 rsvd :4;
63 u32 dtyp :4; /* Descriptor type */
64 u32 dcmd :8; /* Descriptor command */
65 } config;

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123#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
124#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
125#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
126#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
127#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
128#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
129#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
130#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
62 union {
63 u32 data;
64 struct {
65 u32 datalen :16; /* Data buffer length */
66 u32 rsvd :4;
67 u32 dtyp :4; /* Descriptor type */
68 u32 dcmd :8; /* Descriptor command */
69 } config;

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127#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
128#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
129#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
130#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
131#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
132#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
133#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
134#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
135#define E1000_SRRCTL_TIMESTAMP 0x40000000
131#define E1000_SRRCTL_DROP_EN 0x80000000
132
133#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
134#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
135
136#define E1000_TX_HEAD_WB_ENABLE 0x1
137#define E1000_TX_SEQNUM_WB_ENABLE 0x2
138
139#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
140#define E1000_MRQC_ENABLE_VMDQ 0x00000003
141#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
142#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
143#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
144#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
136#define E1000_SRRCTL_DROP_EN 0x80000000
137
138#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
139#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
140
141#define E1000_TX_HEAD_WB_ENABLE 0x1
142#define E1000_TX_SEQNUM_WB_ENABLE 0x2
143
144#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
145#define E1000_MRQC_ENABLE_VMDQ 0x00000003
146#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
147#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
148#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
149#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
150#define E1000_MRQC_ENABLE_RSS_8Q 0x00000002
145
146#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8
147#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
148#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
149#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1)
150#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
151
152#define E1000_EICR_TX_QUEUE ( \

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180#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
181#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
182#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
183#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
184
185/* Receive Descriptor - Advanced */
186union e1000_adv_rx_desc {
187 struct {
151
152#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8
153#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
154#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
155#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1)
156#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
157
158#define E1000_EICR_TX_QUEUE ( \

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186#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
187#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
188#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
189#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
190
191/* Receive Descriptor - Advanced */
192union e1000_adv_rx_desc {
193 struct {
188 u64 pkt_addr; /* Packet buffer address */
189 u64 hdr_addr; /* Header buffer address */
194 __le64 pkt_addr; /* Packet buffer address */
195 __le64 hdr_addr; /* Header buffer address */
190 } read;
191 struct {
192 struct {
193 union {
196 } read;
197 struct {
198 struct {
199 union {
194 u32 data;
200 __le32 data;
195 struct {
201 struct {
196 u16 pkt_info; /* RSS type, Packet type */
197 u16 hdr_info; /* Split Header,
198 * header buffer length */
202 __le16 pkt_info; /*RSS type, Pkt type*/
203 __le16 hdr_info; /* Split Header,
204 * header buffer len*/
199 } hs_rss;
200 } lo_dword;
201 union {
205 } hs_rss;
206 } lo_dword;
207 union {
202 u32 rss; /* RSS Hash */
208 __le32 rss; /* RSS Hash */
203 struct {
209 struct {
204 u16 ip_id; /* IP id */
205 u16 csum; /* Packet Checksum */
210 __le16 ip_id; /* IP id */
211 __le16 csum; /* Packet Checksum */
206 } csum_ip;
207 } hi_dword;
208 } lower;
209 struct {
212 } csum_ip;
213 } hi_dword;
214 } lower;
215 struct {
210 u32 status_error; /* ext status/error */
211 u16 length; /* Packet length */
212 u16 vlan; /* VLAN tag */
216 __le32 status_error; /* ext status/error */
217 __le16 length; /* Packet length */
218 __le16 vlan; /* VLAN tag */
213 } upper;
214 } wb; /* writeback */
215};
216
217#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
218#define E1000_RXDADV_RSSTYPE_SHIFT 12
219#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
220#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
221#define E1000_RXDADV_SPLITHEADER_EN 0x00001000
222#define E1000_RXDADV_SPH 0x8000
219 } upper;
220 } wb; /* writeback */
221};
222
223#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
224#define E1000_RXDADV_RSSTYPE_SHIFT 12
225#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
226#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
227#define E1000_RXDADV_SPLITHEADER_EN 0x00001000
228#define E1000_RXDADV_SPH 0x8000
229#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
230#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
223#define E1000_RXDADV_ERR_HBO 0x00800000
224
225/* RSS Hash results */
226#define E1000_RXDADV_RSSTYPE_NONE 0x00000000
227#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
228#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
229#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
230#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004

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264#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
265#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
266#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
267#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
268
269/* Transmit Descriptor - Advanced */
270union e1000_adv_tx_desc {
271 struct {
231#define E1000_RXDADV_ERR_HBO 0x00800000
232
233/* RSS Hash results */
234#define E1000_RXDADV_RSSTYPE_NONE 0x00000000
235#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
236#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
237#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
238#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004

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272#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
273#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
274#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
275#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
276
277/* Transmit Descriptor - Advanced */
278union e1000_adv_tx_desc {
279 struct {
272 u64 buffer_addr; /* Address of descriptor's data buf */
273 u32 cmd_type_len;
274 u32 olinfo_status;
280 __le64 buffer_addr; /* Address of descriptor's data buf */
281 __le32 cmd_type_len;
282 __le32 olinfo_status;
275 } read;
276 struct {
283 } read;
284 struct {
277 u64 rsvd; /* Reserved */
278 u32 nxtseq_seed;
279 u32 status;
285 __le64 rsvd; /* Reserved */
286 __le32 nxtseq_seed;
287 __le32 status;
280 } wb;
281};
282
283/* Adv Transmit Descriptor Config Masks */
284#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
285#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
286#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
287#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */

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298#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
299#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
300#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
301#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
302#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
303
304/* Context descriptors */
305struct e1000_adv_tx_context_desc {
288 } wb;
289};
290
291/* Adv Transmit Descriptor Config Masks */
292#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
293#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
294#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
295#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */

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306#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
307#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
308#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
309#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
310#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
311
312/* Context descriptors */
313struct e1000_adv_tx_context_desc {
306 u32 vlan_macip_lens;
307 u32 seqnum_seed;
308 u32 type_tucmd_mlhl;
309 u32 mss_l4len_idx;
314 __le32 vlan_macip_lens;
315 __le32 seqnum_seed;
316 __le32 type_tucmd_mlhl;
317 __le32 mss_l4len_idx;
310};
311
312#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
313#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
314#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
315#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
316#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
317#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */

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373 * to avoid filter collisions later. Add new filters
374 * here!!
375 *
376 * Current filters:
377 * EAPOL 802.1x (0x888e): Filter 0
378 */
379#define E1000_ETQF_FILTER_EAPOL 0
380
318};
319
320#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
321#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
322#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
323#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
324#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
325#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */

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381 * to avoid filter collisions later. Add new filters
382 * here!!
383 *
384 * Current filters:
385 * EAPOL 802.1x (0x888e): Filter 0
386 */
387#define E1000_ETQF_FILTER_EAPOL 0
388
389#define E1000_FTQF_VF_BP 0x00008000
390#define E1000_FTQF_1588_TIME_STAMP 0x08000000
391#define E1000_FTQF_MASK 0xF0000000
392#define E1000_FTQF_MASK_PROTO_BP 0x10000000
393#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
394#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
395#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
396
381#define E1000_NVM_APME_82575 0x0400
382#define MAX_NUM_VFS 8
383
384#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
385#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
386#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
387#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
388#define E1000_DTXSWC_LLE_SHIFT 16

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411
412#define E1000_VLVF_ARRAY_SIZE 32
413#define E1000_VLVF_VLANID_MASK 0x00000FFF
414#define E1000_VLVF_POOLSEL_SHIFT 12
415#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
416#define E1000_VLVF_LVLAN 0x00100000
417#define E1000_VLVF_VLANID_ENABLE 0x80000000
418
397#define E1000_NVM_APME_82575 0x0400
398#define MAX_NUM_VFS 8
399
400#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
401#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
402#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
403#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
404#define E1000_DTXSWC_LLE_SHIFT 16

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427
428#define E1000_VLVF_ARRAY_SIZE 32
429#define E1000_VLVF_VLANID_MASK 0x00000FFF
430#define E1000_VLVF_POOLSEL_SHIFT 12
431#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
432#define E1000_VLVF_LVLAN 0x00100000
433#define E1000_VLVF_VLANID_ENABLE 0x80000000
434
435#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
436#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
437
419#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
420
421#define E1000_IOVCTL 0x05BBC
422#define E1000_IOVCTL_REUSE_VFQ 0x00000001
423
424#define E1000_RPLOLR_STRVLAN 0x40000000
425#define E1000_RPLOLR_STRCRC 0x80000000
426
438#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
439
440#define E1000_IOVCTL 0x05BBC
441#define E1000_IOVCTL_REUSE_VFQ 0x00000001
442
443#define E1000_RPLOLR_STRVLAN 0x40000000
444#define E1000_RPLOLR_STRCRC 0x80000000
445
446#define E1000_DTXCTL_8023LL 0x0004
447#define E1000_DTXCTL_VLAN_ADDED 0x0008
448#define E1000_DTXCTL_OOS_ENABLE 0x0010
449#define E1000_DTXCTL_MDP_EN 0x0020
450#define E1000_DTXCTL_SPOOF_INT 0x0040
451
427#define ALL_QUEUES 0xFFFF
428
452#define ALL_QUEUES 0xFFFF
453
454/* RX packet buffer size defines */
455#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
429void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
430void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
456void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
457void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
458u16 e1000_rxpbs_adjust_82580(u32 data);
459s32 e1000_erfuse_check_82580(struct e1000_hw *);
431#endif /* _E1000_82575_H_ */
460#endif /* _E1000_82575_H_ */