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e1000_82575.c (226436) e1000_82575.c (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 226436 2011-10-16 14:30:28Z eadler $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 */

--- 4 unchanged lines hidden (view full) ---

46static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
47static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
48static void e1000_release_phy_82575(struct e1000_hw *hw);
49static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
50static void e1000_release_nvm_82575(struct e1000_hw *hw);
51static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
52static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
53static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 */

--- 4 unchanged lines hidden (view full) ---

46static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
47static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
48static void e1000_release_phy_82575(struct e1000_hw *hw);
49static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
50static void e1000_release_nvm_82575(struct e1000_hw *hw);
51static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
52static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
53static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
54 u16 *duplex);
54 u16 *duplex);
55static s32 e1000_init_hw_82575(struct e1000_hw *hw);
56static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
57static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
55static s32 e1000_init_hw_82575(struct e1000_hw *hw);
56static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
57static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
58 u16 *data);
58 u16 *data);
59static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
60static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
61static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
59static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
60static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
61static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
62 u32 offset, u16 *data);
62 u32 offset, u16 *data);
63static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
63static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 data);
64 u32 offset, u16 data);
65static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
65static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
66 bool active);
66 bool active);
67static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
67static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
68 bool active);
68 bool active);
69static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
69static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
70 bool active);
70 bool active);
71static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
72static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
71static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
72static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
73static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
74static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
73static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
74static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
75static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
76static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
75 u32 offset, u16 data);
77 u32 offset, u16 data);
76static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
77static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
78static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
78static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
79static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
80static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
79 u16 *speed, u16 *duplex);
81 u16 *speed, u16 *duplex);
80static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
81static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
83static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
84static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
85static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
86static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
87static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
88static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
89static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
90static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
91static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
92static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
93static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
82static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
83static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
84static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
85static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
86static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
87static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
88static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
89static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
90static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
91static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
92static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
93static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
94static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
95static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
94 u16 offset);
96 u16 offset);
95static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
97static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
96 u16 offset);
98 u16 offset);
97static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
98static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
99static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
100static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
101static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
102static void e1000_clear_vfta_i350(struct e1000_hw *hw);
99
103
100static const u16 e1000_82580_rxpbs_table[] =
101 { 36, 72, 144, 1, 2, 4, 8, 16,
102 35, 70, 140 };
104static void e1000_i2c_start(struct e1000_hw *hw);
105static void e1000_i2c_stop(struct e1000_hw *hw);
106static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
107static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
108static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
109static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
110static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
111static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
112static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
113static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
114static bool e1000_get_i2c_data(u32 *i2cctl);
115
116static const u16 e1000_82580_rxpbs_table[] = {
117 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
103#define E1000_82580_RXPBS_TABLE_SIZE \
104 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
105
106
107/**
108 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
109 * @hw: pointer to the HW structure
110 *

--- 39 unchanged lines hidden (view full) ---

150 if (hw->phy.media_type != e1000_media_type_copper) {
151 phy->type = e1000_phy_none;
152 goto out;
153 }
154
155 phy->ops.power_up = e1000_power_up_phy_copper;
156 phy->ops.power_down = e1000_power_down_phy_copper_82575;
157
118#define E1000_82580_RXPBS_TABLE_SIZE \
119 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
120
121
122/**
123 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
124 * @hw: pointer to the HW structure
125 *

--- 39 unchanged lines hidden (view full) ---

165 if (hw->phy.media_type != e1000_media_type_copper) {
166 phy->type = e1000_phy_none;
167 goto out;
168 }
169
170 phy->ops.power_up = e1000_power_up_phy_copper;
171 phy->ops.power_down = e1000_power_down_phy_copper_82575;
172
158 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
159 phy->reset_delay_us = 100;
173 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
174 phy->reset_delay_us = 100;
160
175
161 phy->ops.acquire = e1000_acquire_phy_82575;
162 phy->ops.check_reset_block = e1000_check_reset_block_generic;
163 phy->ops.commit = e1000_phy_sw_reset_generic;
164 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
165 phy->ops.release = e1000_release_phy_82575;
176 phy->ops.acquire = e1000_acquire_phy_82575;
177 phy->ops.check_reset_block = e1000_check_reset_block_generic;
178 phy->ops.commit = e1000_phy_sw_reset_generic;
179 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
180 phy->ops.release = e1000_release_phy_82575;
166
167 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
168
169 if (e1000_sgmii_active_82575(hw)) {
181
182 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
183
184 if (e1000_sgmii_active_82575(hw)) {
170 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
185 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
171 ctrl_ext |= E1000_CTRL_I2C_ENA;
172 } else {
186 ctrl_ext |= E1000_CTRL_I2C_ENA;
187 } else {
173 phy->ops.reset = e1000_phy_hw_reset_generic;
188 phy->ops.reset = e1000_phy_hw_reset_generic;
174 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
175 }
176
177 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
178 e1000_reset_mdicnfg_82580(hw);
179
180 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
189 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
190 }
191
192 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
193 e1000_reset_mdicnfg_82580(hw);
194
195 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
181 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
182 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
196 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
197 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
183 } else if (hw->mac.type >= e1000_82580) {
198 } else if (hw->mac.type >= e1000_82580) {
184 phy->ops.read_reg = e1000_read_phy_reg_82580;
185 phy->ops.write_reg = e1000_write_phy_reg_82580;
199 phy->ops.read_reg = e1000_read_phy_reg_82580;
200 phy->ops.write_reg = e1000_write_phy_reg_82580;
186 } else {
201 } else {
187 phy->ops.read_reg = e1000_read_phy_reg_igp;
188 phy->ops.write_reg = e1000_write_phy_reg_igp;
202 phy->ops.read_reg = e1000_read_phy_reg_igp;
203 phy->ops.write_reg = e1000_write_phy_reg_igp;
189 }
190
191 /* Set phy->phy_addr and phy->id. */
192 ret_val = e1000_get_phy_id_82575(hw);
193
194 /* Verify phy id and set remaining function pointers */
195 switch (phy->id) {
196 case I347AT4_E_PHY_ID:
197 case M88E1112_E_PHY_ID:
198 case M88E1340M_E_PHY_ID:
199 case M88E1111_I_PHY_ID:
204 }
205
206 /* Set phy->phy_addr and phy->id. */
207 ret_val = e1000_get_phy_id_82575(hw);
208
209 /* Verify phy id and set remaining function pointers */
210 switch (phy->id) {
211 case I347AT4_E_PHY_ID:
212 case M88E1112_E_PHY_ID:
213 case M88E1340M_E_PHY_ID:
214 case M88E1111_I_PHY_ID:
200 phy->type = e1000_phy_m88;
201 phy->ops.check_polarity = e1000_check_polarity_m88;
202 phy->ops.get_info = e1000_get_phy_info_m88;
215 phy->type = e1000_phy_m88;
216 phy->ops.check_polarity = e1000_check_polarity_m88;
217 phy->ops.get_info = e1000_get_phy_info_m88;
203 if (phy->id == I347AT4_E_PHY_ID ||
204 phy->id == M88E1112_E_PHY_ID ||
205 phy->id == M88E1340M_E_PHY_ID)
218 if (phy->id == I347AT4_E_PHY_ID ||
219 phy->id == M88E1112_E_PHY_ID ||
220 phy->id == M88E1340M_E_PHY_ID)
206 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
221 phy->ops.get_cable_length =
222 e1000_get_cable_length_m88_gen2;
207 else
208 phy->ops.get_cable_length = e1000_get_cable_length_m88;
209 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
210 break;
211 case IGP03E1000_E_PHY_ID:
212 case IGP04E1000_E_PHY_ID:
223 else
224 phy->ops.get_cable_length = e1000_get_cable_length_m88;
225 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
226 break;
227 case IGP03E1000_E_PHY_ID:
228 case IGP04E1000_E_PHY_ID:
213 phy->type = e1000_phy_igp_3;
214 phy->ops.check_polarity = e1000_check_polarity_igp;
215 phy->ops.get_info = e1000_get_phy_info_igp;
216 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
229 phy->type = e1000_phy_igp_3;
230 phy->ops.check_polarity = e1000_check_polarity_igp;
231 phy->ops.get_info = e1000_get_phy_info_igp;
232 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
217 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
233 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
218 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
219 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
234 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
235 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
220 break;
221 case I82580_I_PHY_ID:
222 case I350_I_PHY_ID:
236 break;
237 case I82580_I_PHY_ID:
238 case I350_I_PHY_ID:
223 phy->type = e1000_phy_82580;
224 phy->ops.check_polarity = e1000_check_polarity_82577;
225 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
226 phy->ops.get_cable_length = e1000_get_cable_length_82577;
227 phy->ops.get_info = e1000_get_phy_info_82577;
228 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
229 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
239 phy->type = e1000_phy_82580;
240 phy->ops.check_polarity = e1000_check_polarity_82577;
241 phy->ops.force_speed_duplex =
242 e1000_phy_force_speed_duplex_82577;
243 phy->ops.get_cable_length = e1000_get_cable_length_82577;
244 phy->ops.get_info = e1000_get_phy_info_82577;
245 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
246 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
230 break;
231 default:
232 ret_val = -E1000_ERR_PHY;
233 goto out;
234 }
235
236out:
237 return ret_val;

--- 7 unchanged lines hidden (view full) ---

245{
246 struct e1000_nvm_info *nvm = &hw->nvm;
247 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
248 u16 size;
249
250 DEBUGFUNC("e1000_init_nvm_params_82575");
251
252 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
247 break;
248 default:
249 ret_val = -E1000_ERR_PHY;
250 goto out;
251 }
252
253out:
254 return ret_val;

--- 7 unchanged lines hidden (view full) ---

262{
263 struct e1000_nvm_info *nvm = &hw->nvm;
264 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
265 u16 size;
266
267 DEBUGFUNC("e1000_init_nvm_params_82575");
268
269 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
253 E1000_EECD_SIZE_EX_SHIFT);
270 E1000_EECD_SIZE_EX_SHIFT);
254 /*
255 * Added to a constant, "size" becomes the left-shift value
256 * for setting word_size.
257 */
258 size += NVM_WORD_SIZE_BASE_SHIFT;
259
271 /*
272 * Added to a constant, "size" becomes the left-shift value
273 * for setting word_size.
274 */
275 size += NVM_WORD_SIZE_BASE_SHIFT;
276
277 /* Just in case size is out of range, cap it to the largest
278 * EEPROM size supported
279 */
280 if (size > 15)
281 size = 15;
282
260 nvm->word_size = 1 << size;
283 nvm->word_size = 1 << size;
261 nvm->opcode_bits = 8;
262 nvm->delay_usec = 1;
284 nvm->opcode_bits = 8;
285 nvm->delay_usec = 1;
263 switch (nvm->override) {
264 case e1000_nvm_override_spi_large:
286 switch (nvm->override) {
287 case e1000_nvm_override_spi_large:
265 nvm->page_size = 32;
288 nvm->page_size = 32;
266 nvm->address_bits = 16;
267 break;
268 case e1000_nvm_override_spi_small:
289 nvm->address_bits = 16;
290 break;
291 case e1000_nvm_override_spi_small:
269 nvm->page_size = 8;
292 nvm->page_size = 8;
270 nvm->address_bits = 8;
271 break;
272 default:
293 nvm->address_bits = 8;
294 break;
295 default:
273 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
296 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
274 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
275 break;
276 }
277
278 nvm->type = e1000_nvm_eeprom_spi;
279
280 if (nvm->word_size == (1 << 15))
281 nvm->page_size = 128;
282
283 /* Function Pointers */
297 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
298 break;
299 }
300
301 nvm->type = e1000_nvm_eeprom_spi;
302
303 if (nvm->word_size == (1 << 15))
304 nvm->page_size = 128;
305
306 /* Function Pointers */
284 nvm->ops.acquire = e1000_acquire_nvm_82575;
285 nvm->ops.release = e1000_release_nvm_82575;
307 nvm->ops.acquire = e1000_acquire_nvm_82575;
308 nvm->ops.release = e1000_release_nvm_82575;
286 if (nvm->word_size < (1 << 15))
309 if (nvm->word_size < (1 << 15))
287 nvm->ops.read = e1000_read_nvm_eerd;
310 nvm->ops.read = e1000_read_nvm_eerd;
288 else
311 else
289 nvm->ops.read = e1000_read_nvm_spi;
312 nvm->ops.read = e1000_read_nvm_spi;
290
313
291 nvm->ops.write = e1000_write_nvm_spi;
292 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
293 nvm->ops.update = e1000_update_nvm_checksum_generic;
294 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
314 nvm->ops.write = e1000_write_nvm_spi;
315 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
316 nvm->ops.update = e1000_update_nvm_checksum_generic;
317 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
295
296 /* override genric family function pointers for specific descendants */
297 switch (hw->mac.type) {
298 case e1000_82580:
299 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
300 nvm->ops.update = e1000_update_nvm_checksum_82580;
301 break;
302 case e1000_i350:

--- 10 unchanged lines hidden (view full) ---

313/**
314 * e1000_init_mac_params_82575 - Init MAC func ptrs.
315 * @hw: pointer to the HW structure
316 **/
317static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
318{
319 struct e1000_mac_info *mac = &hw->mac;
320 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
318
319 /* override genric family function pointers for specific descendants */
320 switch (hw->mac.type) {
321 case e1000_82580:
322 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
323 nvm->ops.update = e1000_update_nvm_checksum_82580;
324 break;
325 case e1000_i350:

--- 10 unchanged lines hidden (view full) ---

336/**
337 * e1000_init_mac_params_82575 - Init MAC func ptrs.
338 * @hw: pointer to the HW structure
339 **/
340static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
341{
342 struct e1000_mac_info *mac = &hw->mac;
343 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
321 u32 ctrl_ext = 0;
322
323 DEBUGFUNC("e1000_init_mac_params_82575");
324
344
345 DEBUGFUNC("e1000_init_mac_params_82575");
346
325 /* Set media type */
326 /*
327 * The 82575 uses bits 22:23 for link mode. The mode can be changed
328 * based on the EEPROM. We cannot rely upon device ID. There
329 * is no distinguishable difference between fiber and internal
330 * SerDes mode on the 82575. There can be an external PHY attached
331 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
332 */
333 hw->phy.media_type = e1000_media_type_copper;
334 dev_spec->sgmii_active = FALSE;
335
336 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
337 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
338 case E1000_CTRL_EXT_LINK_MODE_SGMII:
339 dev_spec->sgmii_active = TRUE;
340 break;
341 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
342 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
343 hw->phy.media_type = e1000_media_type_internal_serdes;
344 break;
345 default:
346 break;
347 }
348
347 /* Derives media type */
348 e1000_get_media_type_82575(hw);
349 /* Set mta register count */
350 mac->mta_reg_count = 128;
351 /* Set uta register count */
352 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
353 /* Set rar entry count */
354 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
355 if (mac->type == e1000_82576)
356 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;

--- 6 unchanged lines hidden (view full) ---

363 }
364
365 /* Set if part includes ASF firmware */
366 mac->asf_firmware_present = TRUE;
367 /* FWSM register */
368 mac->has_fwsm = TRUE;
369 /* ARC supported; valid only if manageability features are enabled. */
370 mac->arc_subsystem_valid =
349 /* Set mta register count */
350 mac->mta_reg_count = 128;
351 /* Set uta register count */
352 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
353 /* Set rar entry count */
354 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
355 if (mac->type == e1000_82576)
356 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;

--- 6 unchanged lines hidden (view full) ---

363 }
364
365 /* Set if part includes ASF firmware */
366 mac->asf_firmware_present = TRUE;
367 /* FWSM register */
368 mac->has_fwsm = TRUE;
369 /* ARC supported; valid only if manageability features are enabled. */
370 mac->arc_subsystem_valid =
371 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
372 ? TRUE : FALSE;
371 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
372 ? TRUE : FALSE;
373
374 /* Function pointers */
375
376 /* bus type/speed/width */
377 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
378 /* reset */
379 if (mac->type >= e1000_82580)
380 mac->ops.reset_hw = e1000_reset_hw_82580;
381 else
382 mac->ops.reset_hw = e1000_reset_hw_82575;
383 /* hw initialization */
384 mac->ops.init_hw = e1000_init_hw_82575;
385 /* link setup */
386 mac->ops.setup_link = e1000_setup_link_generic;
387 /* physical interface link setup */
388 mac->ops.setup_physical_interface =
373
374 /* Function pointers */
375
376 /* bus type/speed/width */
377 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
378 /* reset */
379 if (mac->type >= e1000_82580)
380 mac->ops.reset_hw = e1000_reset_hw_82580;
381 else
382 mac->ops.reset_hw = e1000_reset_hw_82575;
383 /* hw initialization */
384 mac->ops.init_hw = e1000_init_hw_82575;
385 /* link setup */
386 mac->ops.setup_link = e1000_setup_link_generic;
387 /* physical interface link setup */
388 mac->ops.setup_physical_interface =
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? e1000_setup_copper_link_82575
391 : e1000_setup_serdes_link_82575;
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
392 /* physical interface shutdown */
393 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
394 /* physical interface power up */
395 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
396 /* check for link */
397 mac->ops.check_for_link = e1000_check_for_link_82575;
398 /* receive address register setting */
399 mac->ops.rar_set = e1000_rar_set_generic;
400 /* read mac address */
401 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
402 /* configure collision distance */
403 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
404 /* multicast address update */
405 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
391 /* physical interface shutdown */
392 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
393 /* physical interface power up */
394 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
395 /* check for link */
396 mac->ops.check_for_link = e1000_check_for_link_82575;
397 /* receive address register setting */
398 mac->ops.rar_set = e1000_rar_set_generic;
399 /* read mac address */
400 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
401 /* configure collision distance */
402 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
403 /* multicast address update */
404 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
406 /* writing VFTA */
407 mac->ops.write_vfta = e1000_write_vfta_generic;
408 /* clearing VFTA */
409 mac->ops.clear_vfta = e1000_clear_vfta_generic;
405 if (hw->mac.type == e1000_i350) {
406 /* writing VFTA */
407 mac->ops.write_vfta = e1000_write_vfta_i350;
408 /* clearing VFTA */
409 mac->ops.clear_vfta = e1000_clear_vfta_i350;
410 } else {
411 /* writing VFTA */
412 mac->ops.write_vfta = e1000_write_vfta_generic;
413 /* clearing VFTA */
414 mac->ops.clear_vfta = e1000_clear_vfta_generic;
415 }
410 /* ID LED init */
411 mac->ops.id_led_init = e1000_id_led_init_generic;
412 /* blink LED */
413 mac->ops.blink_led = e1000_blink_led_generic;
414 /* setup LED */
415 mac->ops.setup_led = e1000_setup_led_generic;
416 /* cleanup LED */
417 mac->ops.cleanup_led = e1000_cleanup_led_generic;

--- 76 unchanged lines hidden (view full) ---

494 * @hw: pointer to the HW structure
495 * @offset: register offset to be read
496 * @data: pointer to the read data
497 *
498 * Reads the PHY register at offset using the serial gigabit media independent
499 * interface and stores the retrieved information in data.
500 **/
501static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
416 /* ID LED init */
417 mac->ops.id_led_init = e1000_id_led_init_generic;
418 /* blink LED */
419 mac->ops.blink_led = e1000_blink_led_generic;
420 /* setup LED */
421 mac->ops.setup_led = e1000_setup_led_generic;
422 /* cleanup LED */
423 mac->ops.cleanup_led = e1000_cleanup_led_generic;

--- 76 unchanged lines hidden (view full) ---

500 * @hw: pointer to the HW structure
501 * @offset: register offset to be read
502 * @data: pointer to the read data
503 *
504 * Reads the PHY register at offset using the serial gigabit media independent
505 * interface and stores the retrieved information in data.
506 **/
507static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
502 u16 *data)
508 u16 *data)
503{
504 s32 ret_val = -E1000_ERR_PARAM;
505
506 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
507
508 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
509 DEBUGOUT1("PHY Address %u is out of range\n", offset);
510 goto out;

--- 16 unchanged lines hidden (view full) ---

527 * @hw: pointer to the HW structure
528 * @offset: register offset to write to
529 * @data: data to write at register offset
530 *
531 * Writes the data to PHY register at the offset using the serial gigabit
532 * media independent interface.
533 **/
534static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
509{
510 s32 ret_val = -E1000_ERR_PARAM;
511
512 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
513
514 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
515 DEBUGOUT1("PHY Address %u is out of range\n", offset);
516 goto out;

--- 16 unchanged lines hidden (view full) ---

533 * @hw: pointer to the HW structure
534 * @offset: register offset to write to
535 * @data: data to write at register offset
536 *
537 * Writes the data to PHY register at the offset using the serial gigabit
538 * media independent interface.
539 **/
540static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
535 u16 data)
541 u16 data)
536{
537 s32 ret_val = -E1000_ERR_PARAM;
538
539 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
540
541 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
542 DEBUGOUT1("PHY Address %d is out of range\n", offset);
543 goto out;

--- 62 unchanged lines hidden (view full) ---

606 }
607 ret_val = e1000_get_phy_id(hw);
608 goto out;
609 }
610
611 /* Power on sgmii phy if it is disabled */
612 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
613 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
542{
543 s32 ret_val = -E1000_ERR_PARAM;
544
545 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
546
547 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
548 DEBUGOUT1("PHY Address %d is out of range\n", offset);
549 goto out;

--- 62 unchanged lines hidden (view full) ---

612 }
613 ret_val = e1000_get_phy_id(hw);
614 goto out;
615 }
616
617 /* Power on sgmii phy if it is disabled */
618 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
619 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
614 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
620 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
615 E1000_WRITE_FLUSH(hw);
616 msec_delay(300);
617
618 /*
619 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
620 * Therefore, we need to test 1-7
621 */
622 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
623 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
624 if (ret_val == E1000_SUCCESS) {
625 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
621 E1000_WRITE_FLUSH(hw);
622 msec_delay(300);
623
624 /*
625 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
626 * Therefore, we need to test 1-7
627 */
628 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
629 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
630 if (ret_val == E1000_SUCCESS) {
631 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
626 phy_id,
627 phy->addr);
632 phy_id, phy->addr);
628 /*
629 * At the time of this writing, The M88 part is
630 * the only supported SGMII PHY product.
631 */
632 if (phy_id == M88_VENDOR)
633 break;
634 } else {
635 DEBUGOUT1("PHY address %u was unreadable\n",
633 /*
634 * At the time of this writing, The M88 part is
635 * the only supported SGMII PHY product.
636 */
637 if (phy_id == M88_VENDOR)
638 break;
639 } else {
640 DEBUGOUT1("PHY address %u was unreadable\n",
636 phy->addr);
641 phy->addr);
637 }
638 }
639
640 /* A valid PHY type couldn't be found. */
641 if (phy->addr == 8) {
642 phy->addr = 0;
643 ret_val = -E1000_ERR_PHY;
644 } else {

--- 69 unchanged lines hidden (view full) ---

714
715 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
716 if (ret_val)
717 goto out;
718
719 if (active) {
720 data |= IGP02E1000_PM_D0_LPLU;
721 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
642 }
643 }
644
645 /* A valid PHY type couldn't be found. */
646 if (phy->addr == 8) {
647 phy->addr = 0;
648 ret_val = -E1000_ERR_PHY;
649 } else {

--- 69 unchanged lines hidden (view full) ---

719
720 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
721 if (ret_val)
722 goto out;
723
724 if (active) {
725 data |= IGP02E1000_PM_D0_LPLU;
726 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
722 data);
727 data);
723 if (ret_val)
724 goto out;
725
726 /* When LPLU is enabled, we should disable SmartSpeed */
727 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
728 if (ret_val)
729 goto out;
730
731 /* When LPLU is enabled, we should disable SmartSpeed */
732 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
728 &data);
733 &data);
729 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
730 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
734 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
735 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
731 data);
736 data);
732 if (ret_val)
733 goto out;
734 } else {
735 data &= ~IGP02E1000_PM_D0_LPLU;
736 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
737 if (ret_val)
738 goto out;
739 } else {
740 data &= ~IGP02E1000_PM_D0_LPLU;
741 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
737 data);
742 data);
738 /*
739 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
740 * during Dx states where the power conservation is most
741 * important. During driver activity we should enable
742 * SmartSpeed, so performance is maintained.
743 */
744 if (phy->smart_speed == e1000_smart_speed_on) {
745 ret_val = phy->ops.read_reg(hw,
743 /*
744 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
745 * during Dx states where the power conservation is most
746 * important. During driver activity we should enable
747 * SmartSpeed, so performance is maintained.
748 */
749 if (phy->smart_speed == e1000_smart_speed_on) {
750 ret_val = phy->ops.read_reg(hw,
746 IGP01E1000_PHY_PORT_CONFIG,
747 &data);
751 IGP01E1000_PHY_PORT_CONFIG,
752 &data);
748 if (ret_val)
749 goto out;
750
751 data |= IGP01E1000_PSCFR_SMART_SPEED;
752 ret_val = phy->ops.write_reg(hw,
753 if (ret_val)
754 goto out;
755
756 data |= IGP01E1000_PSCFR_SMART_SPEED;
757 ret_val = phy->ops.write_reg(hw,
753 IGP01E1000_PHY_PORT_CONFIG,
754 data);
758 IGP01E1000_PHY_PORT_CONFIG,
759 data);
755 if (ret_val)
756 goto out;
757 } else if (phy->smart_speed == e1000_smart_speed_off) {
758 ret_val = phy->ops.read_reg(hw,
760 if (ret_val)
761 goto out;
762 } else if (phy->smart_speed == e1000_smart_speed_off) {
763 ret_val = phy->ops.read_reg(hw,
759 IGP01E1000_PHY_PORT_CONFIG,
760 &data);
764 IGP01E1000_PHY_PORT_CONFIG,
765 &data);
761 if (ret_val)
762 goto out;
763
764 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
765 ret_val = phy->ops.write_reg(hw,
766 if (ret_val)
767 goto out;
768
769 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
770 ret_val = phy->ops.write_reg(hw,
766 IGP01E1000_PHY_PORT_CONFIG,
767 data);
771 IGP01E1000_PHY_PORT_CONFIG,
772 data);
768 if (ret_val)
769 goto out;
770 }
771 }
772
773out:
774 return ret_val;
775}

--- 30 unchanged lines hidden (view full) ---

806 data &= ~E1000_82580_PM_D0_LPLU;
807
808 /*
809 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
810 * during Dx states where the power conservation is most
811 * important. During driver activity we should enable
812 * SmartSpeed, so performance is maintained.
813 */
773 if (ret_val)
774 goto out;
775 }
776 }
777
778out:
779 return ret_val;
780}

--- 30 unchanged lines hidden (view full) ---

811 data &= ~E1000_82580_PM_D0_LPLU;
812
813 /*
814 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
815 * during Dx states where the power conservation is most
816 * important. During driver activity we should enable
817 * SmartSpeed, so performance is maintained.
818 */
814 if (phy->smart_speed == e1000_smart_speed_on) {
819 if (phy->smart_speed == e1000_smart_speed_on)
815 data |= E1000_82580_PM_SPD;
820 data |= E1000_82580_PM_SPD;
816 } else if (phy->smart_speed == e1000_smart_speed_off) {
821 else if (phy->smart_speed == e1000_smart_speed_off)
817 data &= ~E1000_82580_PM_SPD;
822 data &= ~E1000_82580_PM_SPD;
818 }
819 }
820
821 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
822 return ret_val;
823}
824
825/**
826 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3

--- 22 unchanged lines hidden (view full) ---

849 if (!active) {
850 data &= ~E1000_82580_PM_D3_LPLU;
851 /*
852 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
853 * during Dx states where the power conservation is most
854 * important. During driver activity we should enable
855 * SmartSpeed, so performance is maintained.
856 */
823 }
824
825 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
826 return ret_val;
827}
828
829/**
830 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3

--- 22 unchanged lines hidden (view full) ---

853 if (!active) {
854 data &= ~E1000_82580_PM_D3_LPLU;
855 /*
856 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
857 * during Dx states where the power conservation is most
858 * important. During driver activity we should enable
859 * SmartSpeed, so performance is maintained.
860 */
857 if (phy->smart_speed == e1000_smart_speed_on) {
861 if (phy->smart_speed == e1000_smart_speed_on)
858 data |= E1000_82580_PM_SPD;
862 data |= E1000_82580_PM_SPD;
859 } else if (phy->smart_speed == e1000_smart_speed_off) {
863 else if (phy->smart_speed == e1000_smart_speed_off)
860 data &= ~E1000_82580_PM_SPD;
864 data &= ~E1000_82580_PM_SPD;
861 }
862 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
865 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
863 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
864 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
866 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
867 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
865 data |= E1000_82580_PM_D3_LPLU;
866 /* When LPLU is enabled, we should disable SmartSpeed */
867 data &= ~E1000_82580_PM_SPD;
868 }
869
870 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
871 return ret_val;
872}

--- 11 unchanged lines hidden (view full) ---

884{
885 s32 ret_val;
886
887 DEBUGFUNC("e1000_acquire_nvm_82575");
888
889 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
890 if (ret_val)
891 goto out;
868 data |= E1000_82580_PM_D3_LPLU;
869 /* When LPLU is enabled, we should disable SmartSpeed */
870 data &= ~E1000_82580_PM_SPD;
871 }
872
873 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
874 return ret_val;
875}

--- 11 unchanged lines hidden (view full) ---

887{
888 s32 ret_val;
889
890 DEBUGFUNC("e1000_acquire_nvm_82575");
891
892 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
893 if (ret_val)
894 goto out;
892 ret_val = e1000_acquire_nvm_generic(hw);
895
896 /*
897 * Check if there is some access
898 * error this access may hook on
899 */
900 if (hw->mac.type == e1000_i350) {
901 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
902 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
903 E1000_EECD_TIMEOUT)) {
904 /* Clear all access error flags */
905 E1000_WRITE_REG(hw, E1000_EECD, eecd |
906 E1000_EECD_ERROR_CLR);
907 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
908 }
909 }
910 if (hw->mac.type == e1000_82580) {
911 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
912 if (eecd & E1000_EECD_BLOCKED) {
913 /* Clear access error flag */
914 E1000_WRITE_REG(hw, E1000_EECD, eecd |
915 E1000_EECD_BLOCKED);
916 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
917 }
918 }
919
920
921 switch (hw->mac.type) {
922 default:
923 ret_val = e1000_acquire_nvm_generic(hw);
924 }
925
893 if (ret_val)
894 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
895
896out:
897 return ret_val;
898}
899
900/**
901 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
902 * @hw: pointer to the HW structure
903 *
904 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
905 * then release the semaphores acquired.
906 **/
907static void e1000_release_nvm_82575(struct e1000_hw *hw)
908{
909 DEBUGFUNC("e1000_release_nvm_82575");
910
926 if (ret_val)
927 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
928
929out:
930 return ret_val;
931}
932
933/**
934 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
935 * @hw: pointer to the HW structure
936 *
937 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
938 * then release the semaphores acquired.
939 **/
940static void e1000_release_nvm_82575(struct e1000_hw *hw)
941{
942 DEBUGFUNC("e1000_release_nvm_82575");
943
944 switch (hw->mac.type) {
945 default:
946 e1000_release_nvm_generic(hw);
947 }
911 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
912}
913
914/**
915 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
916 * @hw: pointer to the HW structure
917 * @mask: specifies which semaphore to acquire
918 *

--- 53 unchanged lines hidden (view full) ---

972 * will also specify which port we're releasing the lock for.
973 **/
974static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
975{
976 u32 swfw_sync;
977
978 DEBUGFUNC("e1000_release_swfw_sync_82575");
979
948 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
949}
950
951/**
952 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
953 * @hw: pointer to the HW structure
954 * @mask: specifies which semaphore to acquire
955 *

--- 53 unchanged lines hidden (view full) ---

1009 * will also specify which port we're releasing the lock for.
1010 **/
1011static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1012{
1013 u32 swfw_sync;
1014
1015 DEBUGFUNC("e1000_release_swfw_sync_82575");
1016
980 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
981 /* Empty */
1017 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1018 ; /* Empty */
982
983 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
984 swfw_sync &= ~mask;
985 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
986
987 e1000_put_hw_semaphore_generic(hw);
988}
989

--- 44 unchanged lines hidden (view full) ---

1034 * @speed: stores the current speed
1035 * @duplex: stores the current duplex
1036 *
1037 * This is a wrapper function, if using the serial gigabit media independent
1038 * interface, use PCS to retrieve the link speed and duplex information.
1039 * Otherwise, use the generic function to get the link speed and duplex info.
1040 **/
1041static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1019
1020 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1021 swfw_sync &= ~mask;
1022 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1023
1024 e1000_put_hw_semaphore_generic(hw);
1025}
1026

--- 44 unchanged lines hidden (view full) ---

1071 * @speed: stores the current speed
1072 * @duplex: stores the current duplex
1073 *
1074 * This is a wrapper function, if using the serial gigabit media independent
1075 * interface, use PCS to retrieve the link speed and duplex information.
1076 * Otherwise, use the generic function to get the link speed and duplex info.
1077 **/
1078static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1042 u16 *duplex)
1079 u16 *duplex)
1043{
1044 s32 ret_val;
1045
1046 DEBUGFUNC("e1000_get_link_up_info_82575");
1047
1048 if (hw->phy.media_type != e1000_media_type_copper)
1049 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1080{
1081 s32 ret_val;
1082
1083 DEBUGFUNC("e1000_get_link_up_info_82575");
1084
1085 if (hw->phy.media_type != e1000_media_type_copper)
1086 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1050 duplex);
1087 duplex);
1051 else
1052 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1088 else
1089 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1053 duplex);
1090 duplex);
1054
1055 return ret_val;
1056}
1057
1058/**
1059 * e1000_check_for_link_82575 - Check for link
1060 * @hw: pointer to the HW structure
1061 *

--- 4 unchanged lines hidden (view full) ---

1066{
1067 s32 ret_val;
1068 u16 speed, duplex;
1069
1070 DEBUGFUNC("e1000_check_for_link_82575");
1071
1072 if (hw->phy.media_type != e1000_media_type_copper) {
1073 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1091
1092 return ret_val;
1093}
1094
1095/**
1096 * e1000_check_for_link_82575 - Check for link
1097 * @hw: pointer to the HW structure
1098 *

--- 4 unchanged lines hidden (view full) ---

1103{
1104 s32 ret_val;
1105 u16 speed, duplex;
1106
1107 DEBUGFUNC("e1000_check_for_link_82575");
1108
1109 if (hw->phy.media_type != e1000_media_type_copper) {
1110 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1074 &duplex);
1111 &duplex);
1075 /*
1076 * Use this flag to determine if link needs to be checked or
1077 * not. If we have link clear the flag so that we do not
1078 * continue to check for link.
1079 */
1080 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1081 } else {
1082 ret_val = e1000_check_for_copper_link_generic(hw);

--- 36 unchanged lines hidden (view full) ---

1119 * @hw: pointer to the HW structure
1120 * @speed: stores the current speed
1121 * @duplex: stores the current duplex
1122 *
1123 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1124 * duplex, then store the values in the pointers provided.
1125 **/
1126static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1112 /*
1113 * Use this flag to determine if link needs to be checked or
1114 * not. If we have link clear the flag so that we do not
1115 * continue to check for link.
1116 */
1117 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1118 } else {
1119 ret_val = e1000_check_for_copper_link_generic(hw);

--- 36 unchanged lines hidden (view full) ---

1156 * @hw: pointer to the HW structure
1157 * @speed: stores the current speed
1158 * @duplex: stores the current duplex
1159 *
1160 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1161 * duplex, then store the values in the pointers provided.
1162 **/
1163static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1127 u16 *speed, u16 *duplex)
1164 u16 *speed, u16 *duplex)
1128{
1129 struct e1000_mac_info *mac = &hw->mac;
1130 u32 pcs;
1131
1132 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1133
1134 /* Set up defaults for the return values of this function */
1135 mac->serdes_has_link = FALSE;

--- 11 unchanged lines hidden (view full) ---

1147 * The link up bit determines when link is up on autoneg. The sync ok
1148 * gets set once both sides sync up and agree upon link. Stable link
1149 * can be determined by checking for both link up and link sync ok
1150 */
1151 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1152 mac->serdes_has_link = TRUE;
1153
1154 /* Detect and store PCS speed */
1165{
1166 struct e1000_mac_info *mac = &hw->mac;
1167 u32 pcs;
1168
1169 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1170
1171 /* Set up defaults for the return values of this function */
1172 mac->serdes_has_link = FALSE;

--- 11 unchanged lines hidden (view full) ---

1184 * The link up bit determines when link is up on autoneg. The sync ok
1185 * gets set once both sides sync up and agree upon link. Stable link
1186 * can be determined by checking for both link up and link sync ok
1187 */
1188 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1189 mac->serdes_has_link = TRUE;
1190
1191 /* Detect and store PCS speed */
1155 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1192 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1156 *speed = SPEED_1000;
1193 *speed = SPEED_1000;
1157 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1194 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1158 *speed = SPEED_100;
1195 *speed = SPEED_100;
1159 } else {
1196 else
1160 *speed = SPEED_10;
1197 *speed = SPEED_10;
1161 }
1162
1163 /* Detect and store PCS duplex */
1198
1199 /* Detect and store PCS duplex */
1164 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1200 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1165 *duplex = FULL_DUPLEX;
1201 *duplex = FULL_DUPLEX;
1166 } else {
1202 else
1167 *duplex = HALF_DUPLEX;
1203 *duplex = HALF_DUPLEX;
1168 }
1169 }
1170
1171 return E1000_SUCCESS;
1172}
1173
1174/**
1175 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1176 * @hw: pointer to the HW structure

--- 43 unchanged lines hidden (view full) ---

1220
1221 DEBUGFUNC("e1000_reset_hw_82575");
1222
1223 /*
1224 * Prevent the PCI-E bus from sticking if there is no TLP connection
1225 * on the last TLP read/write transaction when MAC is reset.
1226 */
1227 ret_val = e1000_disable_pcie_master_generic(hw);
1204 }
1205
1206 return E1000_SUCCESS;
1207}
1208
1209/**
1210 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1211 * @hw: pointer to the HW structure

--- 43 unchanged lines hidden (view full) ---

1255
1256 DEBUGFUNC("e1000_reset_hw_82575");
1257
1258 /*
1259 * Prevent the PCI-E bus from sticking if there is no TLP connection
1260 * on the last TLP read/write transaction when MAC is reset.
1261 */
1262 ret_val = e1000_disable_pcie_master_generic(hw);
1228 if (ret_val) {
1263 if (ret_val)
1229 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1264 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1230 }
1231
1232 /* set the completion timeout for interface */
1233 ret_val = e1000_set_pcie_completion_timeout(hw);
1265
1266 /* set the completion timeout for interface */
1267 ret_val = e1000_set_pcie_completion_timeout(hw);
1234 if (ret_val) {
1268 if (ret_val)
1235 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1269 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1236 }
1237
1238 DEBUGOUT("Masking off all interrupts\n");
1239 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1240
1241 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1242 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1243 E1000_WRITE_FLUSH(hw);
1244

--- 64 unchanged lines hidden (view full) ---

1309 /* Zero out the Unicast HASH table */
1310 DEBUGOUT("Zeroing the UTA\n");
1311 for (i = 0; i < mac->uta_reg_count; i++)
1312 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1313
1314 /* Setup link and flow control */
1315 ret_val = mac->ops.setup_link(hw);
1316
1270
1271 DEBUGOUT("Masking off all interrupts\n");
1272 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1273
1274 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1275 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1276 E1000_WRITE_FLUSH(hw);
1277

--- 64 unchanged lines hidden (view full) ---

1342 /* Zero out the Unicast HASH table */
1343 DEBUGOUT("Zeroing the UTA\n");
1344 for (i = 0; i < mac->uta_reg_count; i++)
1345 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1346
1347 /* Setup link and flow control */
1348 ret_val = mac->ops.setup_link(hw);
1349
1350 /* Set the default MTU size */
1351 hw->dev_spec._82575.mtu = 1500;
1352
1317 /*
1318 * Clear all of the statistics registers (clear on read). It is
1319 * important that we do this after we have tried to establish link
1320 * because the symbol error count will increment wildly if there
1321 * is no link.
1322 */
1323 e1000_clear_hw_cntrs_82575(hw);
1324

--- 19 unchanged lines hidden (view full) ---

1344 ctrl |= E1000_CTRL_SLU;
1345 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1346 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1347
1348 ret_val = e1000_setup_serdes_link_82575(hw);
1349 if (ret_val)
1350 goto out;
1351
1353 /*
1354 * Clear all of the statistics registers (clear on read). It is
1355 * important that we do this after we have tried to establish link
1356 * because the symbol error count will increment wildly if there
1357 * is no link.
1358 */
1359 e1000_clear_hw_cntrs_82575(hw);
1360

--- 19 unchanged lines hidden (view full) ---

1380 ctrl |= E1000_CTRL_SLU;
1381 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1382 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1383
1384 ret_val = e1000_setup_serdes_link_82575(hw);
1385 if (ret_val)
1386 goto out;
1387
1352 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1388 if (e1000_sgmii_active_82575(hw)) {
1353 /* allow time for SFP cage time to power up phy */
1354 msec_delay(300);
1355
1356 ret_val = hw->phy.ops.reset(hw);
1357 if (ret_val) {
1358 DEBUGOUT("Error resetting the PHY.\n");
1359 goto out;
1360 }

--- 34 unchanged lines hidden (view full) ---

1395 * used on copper connections where the serialized gigabit media independent
1396 * interface (sgmii), or serdes fiber is being used. Configures the link
1397 * for auto-negotiation or forces speed/duplex.
1398 **/
1399static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1400{
1401 u32 ctrl_ext, ctrl_reg, reg;
1402 bool pcs_autoneg;
1389 /* allow time for SFP cage time to power up phy */
1390 msec_delay(300);
1391
1392 ret_val = hw->phy.ops.reset(hw);
1393 if (ret_val) {
1394 DEBUGOUT("Error resetting the PHY.\n");
1395 goto out;
1396 }

--- 34 unchanged lines hidden (view full) ---

1431 * used on copper connections where the serialized gigabit media independent
1432 * interface (sgmii), or serdes fiber is being used. Configures the link
1433 * for auto-negotiation or forces speed/duplex.
1434 **/
1435static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1436{
1437 u32 ctrl_ext, ctrl_reg, reg;
1438 bool pcs_autoneg;
1439 s32 ret_val = E1000_SUCCESS;
1440 u16 data;
1403
1404 DEBUGFUNC("e1000_setup_serdes_link_82575");
1405
1406 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1407 !e1000_sgmii_active_82575(hw))
1441
1442 DEBUGFUNC("e1000_setup_serdes_link_82575");
1443
1444 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1445 !e1000_sgmii_active_82575(hw))
1408 return E1000_SUCCESS;
1446 return ret_val;
1409
1410 /*
1411 * On the 82575, SerDes loopback mode persists until it is
1412 * explicitly turned off or a power cycle is performed. A read to
1413 * the register does not indicate its status. Therefore, we ensure
1414 * loopback mode is disabled during initialization.
1415 */
1416 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);

--- 22 unchanged lines hidden (view full) ---

1439 /* autoneg time out should be disabled for SGMII mode */
1440 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1441 break;
1442 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1443 /* disable PCS autoneg and support parallel detect only */
1444 pcs_autoneg = FALSE;
1445 /* fall through to default case */
1446 default:
1447
1448 /*
1449 * On the 82575, SerDes loopback mode persists until it is
1450 * explicitly turned off or a power cycle is performed. A read to
1451 * the register does not indicate its status. Therefore, we ensure
1452 * loopback mode is disabled during initialization.
1453 */
1454 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);

--- 22 unchanged lines hidden (view full) ---

1477 /* autoneg time out should be disabled for SGMII mode */
1478 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1479 break;
1480 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1481 /* disable PCS autoneg and support parallel detect only */
1482 pcs_autoneg = FALSE;
1483 /* fall through to default case */
1484 default:
1485 if (hw->mac.type == e1000_82575 ||
1486 hw->mac.type == e1000_82576) {
1487 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1488 if (ret_val) {
1489 DEBUGOUT("NVM Read Error\n");
1490 return ret_val;
1491 }
1492
1493 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1494 pcs_autoneg = FALSE;
1495 }
1496
1447 /*
1448 * non-SGMII modes only supports a speed of 1000/Full for the
1449 * link so it is best to just force the MAC and let the pcs
1450 * link either autoneg or be forced to 1000/Full
1451 */
1452 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1497 /*
1498 * non-SGMII modes only supports a speed of 1000/Full for the
1499 * link so it is best to just force the MAC and let the pcs
1500 * link either autoneg or be forced to 1000/Full
1501 */
1502 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1453 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1503 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1454
1455 /* set speed of 1000/Full if speed/duplex is forced */
1456 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1457 break;
1458 }
1459
1460 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1461
1462 /*
1463 * New SerDes mode allows for forcing speed or autonegotiating speed
1464 * at 1gb. Autoneg should be default set by most drivers. This is the
1465 * mode that will be compatible with older link partners and switches.
1466 * However, both are supported by the hardware and some drivers/tools.
1467 */
1468 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1504
1505 /* set speed of 1000/Full if speed/duplex is forced */
1506 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1507 break;
1508 }
1509
1510 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1511
1512 /*
1513 * New SerDes mode allows for forcing speed or autonegotiating speed
1514 * at 1gb. Autoneg should be default set by most drivers. This is the
1515 * mode that will be compatible with older link partners and switches.
1516 * However, both are supported by the hardware and some drivers/tools.
1517 */
1518 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1469 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1519 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1470
1471 /*
1472 * We force flow control to prevent the CTRL register values from being
1473 * overwritten by the autonegotiated flow control values
1474 */
1475 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1476
1477 if (pcs_autoneg) {
1478 /* Set PCS register for autoneg */
1479 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1480 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1481 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1482 } else {
1483 /* Set PCS register for forced link */
1520
1521 /*
1522 * We force flow control to prevent the CTRL register values from being
1523 * overwritten by the autonegotiated flow control values
1524 */
1525 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1526
1527 if (pcs_autoneg) {
1528 /* Set PCS register for autoneg */
1529 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1530 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1531 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1532 } else {
1533 /* Set PCS register for forced link */
1484 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1534 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1485 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1486 }
1487
1488 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1489
1490 if (!e1000_sgmii_active_82575(hw))
1491 e1000_force_mac_fc_generic(hw);
1492
1535 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1536 }
1537
1538 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1539
1540 if (!e1000_sgmii_active_82575(hw))
1541 e1000_force_mac_fc_generic(hw);
1542
1493 return E1000_SUCCESS;
1543 return ret_val;
1494}
1495
1496/**
1544}
1545
1546/**
1547 * e1000_get_media_type_82575 - derives current media type.
1548 * @hw: pointer to the HW structure
1549 *
1550 * The media type is chosen reflecting few settings.
1551 * The following are taken into account:
1552 * - link mode set in the current port Init Control Word #3
1553 * - current link mode settings in CSR register
1554 * - MDIO vs. I2C PHY control interface chosen
1555 * - SFP module media type
1556 **/
1557static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1558{
1559 u32 lan_id = 0;
1560 s32 ret_val = E1000_ERR_CONFIG;
1561 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1562 u32 ctrl_ext = 0;
1563 u32 current_link_mode = 0;
1564 u16 init_ctrl_wd_3 = 0;
1565 u8 init_ctrl_wd_3_offset = 0;
1566 u8 init_ctrl_wd_3_bit_offset = 0;
1567
1568 /* Set internal phy as default */
1569 dev_spec->sgmii_active = FALSE;
1570 dev_spec->module_plugged = FALSE;
1571
1572 /*
1573 * Check if NVM access method is attached already.
1574 * If it is then Init Control Word #3 is considered
1575 * otherwise runtime CSR register content is taken.
1576 */
1577
1578 /* Get CSR setting */
1579 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1580
1581 /* Get link mode setting */
1582 if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
1583 /* Take link mode from EEPROM */
1584
1585 /*
1586 * Get LAN port ID to derive its
1587 * adequate Init Control Word #3
1588 */
1589 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
1590 E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
1591 /*
1592 * Derive Init Control Word #3 offset
1593 * and mask to pick up link mode setting.
1594 */
1595 if (hw->mac.type < e1000_82580) {
1596 init_ctrl_wd_3_offset = lan_id ?
1597 NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
1598 init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
1599 } else {
1600 init_ctrl_wd_3_offset =
1601 NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1602 NVM_INIT_CONTROL3_PORT_A;
1603 init_ctrl_wd_3_bit_offset =
1604 NVM_WORD24_82580_LNK_MODE_OFFSET;
1605 }
1606 /* Read Init Control Word #3*/
1607 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1608 current_link_mode = init_ctrl_wd_3;
1609 /*
1610 * Switch to CSR for all but internal PHY.
1611 */
1612 if ((init_ctrl_wd_3 << (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1613 init_ctrl_wd_3_bit_offset)) !=
1614 E1000_CTRL_EXT_LINK_MODE_GMII) {
1615 current_link_mode = ctrl_ext;
1616 init_ctrl_wd_3_bit_offset =
1617 E1000_CTRL_EXT_LINK_MODE_OFFSET;
1618 }
1619 } else {
1620 /* Take link mode from CSR */
1621 current_link_mode = ctrl_ext;
1622 init_ctrl_wd_3_bit_offset = E1000_CTRL_EXT_LINK_MODE_OFFSET;
1623 }
1624
1625 /*
1626 * Align link mode bits to
1627 * their CTRL_EXT location.
1628 */
1629 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1630 init_ctrl_wd_3_bit_offset);
1631 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1632
1633 switch (current_link_mode) {
1634
1635 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1636 hw->phy.media_type = e1000_media_type_internal_serdes;
1637 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1638 break;
1639 case E1000_CTRL_EXT_LINK_MODE_GMII:
1640 hw->phy.media_type = e1000_media_type_copper;
1641 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
1642 break;
1643 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1644 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1645 /* Get phy control interface type set (MDIO vs. I2C)*/
1646 if (e1000_sgmii_uses_mdio_82575(hw)) {
1647 hw->phy.media_type = e1000_media_type_copper;
1648 dev_spec->sgmii_active = TRUE;
1649 current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
1650 } else {
1651 ret_val = e1000_set_sfp_media_type_82575(hw);
1652 if (ret_val != E1000_SUCCESS)
1653 goto out;
1654 if (hw->phy.media_type ==
1655 e1000_media_type_internal_serdes) {
1656 current_link_mode =
1657 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1658 } else if (hw->phy.media_type ==
1659 e1000_media_type_copper) {
1660 current_link_mode =
1661 E1000_CTRL_EXT_LINK_MODE_SGMII;
1662 }
1663 }
1664 break;
1665 default:
1666 DEBUGOUT("Link mode mask doesn't fit bit field size\n");
1667 goto out;
1668 }
1669 /*
1670 * Do not change current link mode setting
1671 * if media type is fibre or has not been
1672 * recognized.
1673 */
1674 if ((hw->phy.media_type != e1000_media_type_unknown) &&
1675 (hw->phy.media_type != e1000_media_type_fiber)) {
1676 /* Update link mode */
1677 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1678 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
1679 current_link_mode);
1680 }
1681
1682 ret_val = E1000_SUCCESS;
1683out:
1684 /*
1685 * If media type was not identified then return media type
1686 * defined by the CTRL_EXT settings.
1687 */
1688 if (hw->phy.media_type == e1000_media_type_unknown) {
1689 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
1690 hw->phy.media_type = e1000_media_type_copper;
1691 else
1692 hw->phy.media_type = e1000_media_type_internal_serdes;
1693 }
1694
1695 return ret_val;
1696}
1697
1698/**
1699 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1700 * @hw: pointer to the HW structure
1701 *
1702 * The media type is chosen based on SFP module.
1703 * compatibility flags retrieved from SFP ID EEPROM.
1704 **/
1705static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1706{
1707 s32 ret_val = E1000_ERR_CONFIG;
1708 u32 ctrl_ext = 0;
1709 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1710 struct sfp_e1000_flags eth_flags = {0};
1711 u8 tranceiver_type = 0;
1712
1713 /* Turn I2C interface ON */
1714 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1715 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1716
1717 /* Read SFP module data */
1718 ret_val = e1000_read_sfp_data_byte(hw,
1719 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1720 &tranceiver_type);
1721 if (ret_val != E1000_SUCCESS)
1722 goto out;
1723 ret_val = e1000_read_sfp_data_byte(hw,
1724 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1725 (u8 *)&eth_flags);
1726 if (ret_val != E1000_SUCCESS)
1727 goto out;
1728 /*
1729 * Check if there is some SFP
1730 * module plugged and powered
1731 */
1732 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1733 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1734 dev_spec->module_plugged = TRUE;
1735 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
1736 hw->phy.media_type = e1000_media_type_internal_serdes;
1737 } else if (eth_flags.e1000_base_t) {
1738 dev_spec->sgmii_active = TRUE;
1739 hw->phy.media_type = e1000_media_type_copper;
1740 } else {
1741 hw->phy.media_type = e1000_media_type_unknown;
1742 DEBUGOUT("PHY module has not been recognized\n");
1743 goto out;
1744 }
1745 } else {
1746 hw->phy.media_type = e1000_media_type_unknown;
1747 }
1748 ret_val = E1000_SUCCESS;
1749out:
1750 /* Restore I2C interface setting */
1751 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1752 return ret_val;
1753}
1754
1755/**
1497 * e1000_valid_led_default_82575 - Verify a valid default LED config
1498 * @hw: pointer to the HW structure
1499 * @data: pointer to the NVM (EEPROM)
1500 *
1501 * Read the EEPROM for the current default LED configuration. If the
1502 * LED configuration is not valid, set to a valid LED configuration.
1503 **/
1504static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)

--- 4 unchanged lines hidden (view full) ---

1509
1510 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1511 if (ret_val) {
1512 DEBUGOUT("NVM Read Error\n");
1513 goto out;
1514 }
1515
1516 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1756 * e1000_valid_led_default_82575 - Verify a valid default LED config
1757 * @hw: pointer to the HW structure
1758 * @data: pointer to the NVM (EEPROM)
1759 *
1760 * Read the EEPROM for the current default LED configuration. If the
1761 * LED configuration is not valid, set to a valid LED configuration.
1762 **/
1763static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)

--- 4 unchanged lines hidden (view full) ---

1768
1769 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1770 if (ret_val) {
1771 DEBUGOUT("NVM Read Error\n");
1772 goto out;
1773 }
1774
1775 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1517 switch(hw->phy.media_type) {
1776 switch (hw->phy.media_type) {
1518 case e1000_media_type_internal_serdes:
1519 *data = ID_LED_DEFAULT_82575_SERDES;
1520 break;
1521 case e1000_media_type_copper:
1522 default:
1523 *data = ID_LED_DEFAULT;
1524 break;
1525 }

--- 18 unchanged lines hidden (view full) ---

1544
1545/**
1546 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1547 * @hw: pointer to the HW structure
1548 *
1549 * Inits recommended HW defaults after a reset when there is no EEPROM
1550 * detected. This is only for the 82575.
1551 **/
1777 case e1000_media_type_internal_serdes:
1778 *data = ID_LED_DEFAULT_82575_SERDES;
1779 break;
1780 case e1000_media_type_copper:
1781 default:
1782 *data = ID_LED_DEFAULT;
1783 break;
1784 }

--- 18 unchanged lines hidden (view full) ---

1803
1804/**
1805 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1806 * @hw: pointer to the HW structure
1807 *
1808 * Inits recommended HW defaults after a reset when there is no EEPROM
1809 * detected. This is only for the 82575.
1810 **/
1552static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1811static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1553{
1554 DEBUGFUNC("e1000_reset_init_script_82575");
1555
1556 if (hw->mac.type == e1000_82575) {
1557 DEBUGOUT("Running reset init script for 82575\n");
1558 /* SerDes configuration via SERDESCTRL */
1559 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1560 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);

--- 170 unchanged lines hidden (view full) ---

1731 if (hw->mac.type != e1000_82575 ||
1732 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1733 return;
1734
1735 /* Disable all Rx queues */
1736 for (i = 0; i < 4; i++) {
1737 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1738 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1812{
1813 DEBUGFUNC("e1000_reset_init_script_82575");
1814
1815 if (hw->mac.type == e1000_82575) {
1816 DEBUGOUT("Running reset init script for 82575\n");
1817 /* SerDes configuration via SERDESCTRL */
1818 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1819 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);

--- 170 unchanged lines hidden (view full) ---

1990 if (hw->mac.type != e1000_82575 ||
1991 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1992 return;
1993
1994 /* Disable all Rx queues */
1995 for (i = 0; i < 4; i++) {
1996 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1997 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1739 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1998 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1740 }
1741 /* Poll all queues to verify they have shut down */
1742 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1743 msec_delay(1);
1744 rx_enabled = 0;
1745 for (i = 0; i < 4; i++)
1746 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1747 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))

--- 69 unchanged lines hidden (view full) ---

1817 }
1818
1819 /*
1820 * for version 2 capabilities we need to write the config space
1821 * directly in order to set the completion timeout value for
1822 * 16ms to 55ms
1823 */
1824 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1999 }
2000 /* Poll all queues to verify they have shut down */
2001 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2002 msec_delay(1);
2003 rx_enabled = 0;
2004 for (i = 0; i < 4; i++)
2005 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2006 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))

--- 69 unchanged lines hidden (view full) ---

2076 }
2077
2078 /*
2079 * for version 2 capabilities we need to write the config space
2080 * directly in order to set the completion timeout value for
2081 * 16ms to 55ms
2082 */
2083 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1825 &pcie_devctl2);
2084 &pcie_devctl2);
1826 if (ret_val)
1827 goto out;
1828
1829 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1830
1831 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2085 if (ret_val)
2086 goto out;
2087
2088 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2089
2090 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1832 &pcie_devctl2);
2091 &pcie_devctl2);
1833out:
1834 /* disable completion timeout resend */
1835 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1836
1837 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1838 return ret_val;
1839}
1840

--- 6 unchanged lines hidden (view full) ---

1847 * enables/disables L2 switch anti-spoofing functionality.
1848 **/
1849void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1850{
1851 u32 dtxswc;
1852
1853 switch (hw->mac.type) {
1854 case e1000_82576:
2092out:
2093 /* disable completion timeout resend */
2094 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2095
2096 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2097 return ret_val;
2098}
2099

--- 6 unchanged lines hidden (view full) ---

2106 * enables/disables L2 switch anti-spoofing functionality.
2107 **/
2108void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2109{
2110 u32 dtxswc;
2111
2112 switch (hw->mac.type) {
2113 case e1000_82576:
1855 case e1000_i350:
1856 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1857 if (enable) {
1858 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1859 E1000_DTXSWC_VLAN_SPOOF_MASK);
1860 /* The PF can spoof - it has to in order to
1861 * support emulation mode NICs */
2114 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2115 if (enable) {
2116 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2117 E1000_DTXSWC_VLAN_SPOOF_MASK);
2118 /* The PF can spoof - it has to in order to
2119 * support emulation mode NICs */
1862 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2120 dtxswc ^= (1 << pf | 1 << (pf +
2121 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
1863 } else {
1864 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1865 E1000_DTXSWC_VLAN_SPOOF_MASK);
1866 }
1867 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1868 break;
2122 } else {
2123 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2124 E1000_DTXSWC_VLAN_SPOOF_MASK);
2125 }
2126 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2127 break;
2128 case e1000_i350:
2129 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2130 if (enable) {
2131 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2132 E1000_DTXSWC_VLAN_SPOOF_MASK);
2133 /* The PF can spoof - it has to in order to
2134 * support emulation mode NICs
2135 */
2136 dtxswc ^= (1 << pf | 1 << (pf +
2137 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2138 } else {
2139 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2140 E1000_DTXSWC_VLAN_SPOOF_MASK);
2141 }
2142 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
1869 default:
1870 break;
1871 }
1872}
1873
1874/**
1875 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
1876 * @hw: pointer to the hardware struct

--- 101 unchanged lines hidden (view full) ---

1978out:
1979 return ret_val;
1980}
1981
1982/**
1983 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1984 * @hw: pointer to the HW structure
1985 *
2143 default:
2144 break;
2145 }
2146}
2147
2148/**
2149 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2150 * @hw: pointer to the hardware struct

--- 101 unchanged lines hidden (view full) ---

2252out:
2253 return ret_val;
2254}
2255
2256/**
2257 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2258 * @hw: pointer to the HW structure
2259 *
1986 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2260 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1987 * the values found in the EEPROM. This addresses an issue in which these
1988 * bits are not restored from EEPROM after reset.
1989 **/
1990static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
1991{
1992 s32 ret_val = E1000_SUCCESS;
1993 u32 mdicnfg;
1994 u16 nvm_data = 0;
1995
1996 DEBUGFUNC("e1000_reset_mdicnfg_82580");
1997
1998 if (hw->mac.type != e1000_82580)
1999 goto out;
2000 if (!e1000_sgmii_active_82575(hw))
2001 goto out;
2002
2003 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2261 * the values found in the EEPROM. This addresses an issue in which these
2262 * bits are not restored from EEPROM after reset.
2263 **/
2264static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2265{
2266 s32 ret_val = E1000_SUCCESS;
2267 u32 mdicnfg;
2268 u16 nvm_data = 0;
2269
2270 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2271
2272 if (hw->mac.type != e1000_82580)
2273 goto out;
2274 if (!e1000_sgmii_active_82575(hw))
2275 goto out;
2276
2277 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2004 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2005 &nvm_data);
2278 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2279 &nvm_data);
2006 if (ret_val) {
2007 DEBUGOUT("NVM Read Error\n");
2008 goto out;
2009 }
2010
2011 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2012 if (nvm_data & NVM_WORD24_EXT_MDIO)
2013 mdicnfg |= E1000_MDICNFG_EXT_MDIO;

--- 38 unchanged lines hidden (view full) ---

2052 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2053 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2054 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2055 E1000_WRITE_FLUSH(hw);
2056
2057 msec_delay(10);
2058
2059 /* Determine whether or not a global dev reset is requested */
2280 if (ret_val) {
2281 DEBUGOUT("NVM Read Error\n");
2282 goto out;
2283 }
2284
2285 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2286 if (nvm_data & NVM_WORD24_EXT_MDIO)
2287 mdicnfg |= E1000_MDICNFG_EXT_MDIO;

--- 38 unchanged lines hidden (view full) ---

2326 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2327 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2328 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2329 E1000_WRITE_FLUSH(hw);
2330
2331 msec_delay(10);
2332
2333 /* Determine whether or not a global dev reset is requested */
2060 if (global_device_reset &&
2061 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
2334 if (global_device_reset && e1000_acquire_swfw_sync_82575(hw,
2335 swmbsw_mask))
2062 global_device_reset = FALSE;
2063
2336 global_device_reset = FALSE;
2337
2064 if (global_device_reset &&
2065 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2338 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2339 E1000_STAT_DEV_RST_SET))
2066 ctrl |= E1000_CTRL_DEV_RST;
2067 else
2068 ctrl |= E1000_CTRL_RST;
2069
2070 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2340 ctrl |= E1000_CTRL_DEV_RST;
2341 else
2342 ctrl |= E1000_CTRL_RST;
2343
2344 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2345 E1000_WRITE_FLUSH(hw);
2071
2072 /* Add delay to insure DEV_RST has time to complete */
2073 if (global_device_reset)
2074 msec_delay(5);
2075
2076 ret_val = e1000_get_auto_rd_done_generic(hw);
2077 if (ret_val) {
2078 /*

--- 108 unchanged lines hidden (view full) ---

2187 if (ret_val) {
2188 DEBUGOUT("NVM Read Error while updating checksum.\n");
2189 goto out;
2190 }
2191 checksum += nvm_data;
2192 }
2193 checksum = (u16) NVM_SUM - checksum;
2194 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2346
2347 /* Add delay to insure DEV_RST has time to complete */
2348 if (global_device_reset)
2349 msec_delay(5);
2350
2351 ret_val = e1000_get_auto_rd_done_generic(hw);
2352 if (ret_val) {
2353 /*

--- 108 unchanged lines hidden (view full) ---

2462 if (ret_val) {
2463 DEBUGOUT("NVM Read Error while updating checksum.\n");
2464 goto out;
2465 }
2466 checksum += nvm_data;
2467 }
2468 checksum = (u16) NVM_SUM - checksum;
2469 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2195 &checksum);
2470 &checksum);
2196 if (ret_val)
2197 DEBUGOUT("NVM Write Error while updating checksum.\n");
2198
2199out:
2200 return ret_val;
2201}
2202
2203/**

--- 23 unchanged lines hidden (view full) ---

2227 /* if chekcsums compatibility bit is set validate checksums
2228 * for all 4 ports. */
2229 eeprom_regions_count = 4;
2230 }
2231
2232 for (j = 0; j < eeprom_regions_count; j++) {
2233 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2234 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2471 if (ret_val)
2472 DEBUGOUT("NVM Write Error while updating checksum.\n");
2473
2474out:
2475 return ret_val;
2476}
2477
2478/**

--- 23 unchanged lines hidden (view full) ---

2502 /* if chekcsums compatibility bit is set validate checksums
2503 * for all 4 ports. */
2504 eeprom_regions_count = 4;
2505 }
2506
2507 for (j = 0; j < eeprom_regions_count; j++) {
2508 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2509 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2235 nvm_offset);
2510 nvm_offset);
2236 if (ret_val != E1000_SUCCESS)
2237 goto out;
2238 }
2239
2240out:
2241 return ret_val;
2242}
2243

--- 10 unchanged lines hidden (view full) ---

2254 s32 ret_val;
2255 u16 j, nvm_data;
2256 u16 nvm_offset;
2257
2258 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2259
2260 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2261 if (ret_val) {
2511 if (ret_val != E1000_SUCCESS)
2512 goto out;
2513 }
2514
2515out:
2516 return ret_val;
2517}
2518

--- 10 unchanged lines hidden (view full) ---

2529 s32 ret_val;
2530 u16 j, nvm_data;
2531 u16 nvm_offset;
2532
2533 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2534
2535 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2536 if (ret_val) {
2262 DEBUGOUT("NVM Read Error while updating checksum"
2263 " compatibility bit.\n");
2537 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2264 goto out;
2265 }
2266
2267 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2268 /* set compatibility bit to validate checksums appropriately */
2269 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2270 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2538 goto out;
2539 }
2540
2541 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2542 /* set compatibility bit to validate checksums appropriately */
2543 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2544 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2271 &nvm_data);
2545 &nvm_data);
2272 if (ret_val) {
2546 if (ret_val) {
2273 DEBUGOUT("NVM Write Error while updating checksum"
2274 " compatibility bit.\n");
2547 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2275 goto out;
2276 }
2277 }
2278
2279 for (j = 0; j < 4; j++) {
2280 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2281 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2548 goto out;
2549 }
2550 }
2551
2552 for (j = 0; j < 4; j++) {
2553 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2554 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2282 if (ret_val) {
2555 if (ret_val)
2283 goto out;
2556 goto out;
2284 }
2285 }
2286
2287out:
2288 return ret_val;
2289}
2290
2291/**
2292 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum

--- 9 unchanged lines hidden (view full) ---

2302 u16 j;
2303 u16 nvm_offset;
2304
2305 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2306
2307 for (j = 0; j < 4; j++) {
2308 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2309 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2557 }
2558
2559out:
2560 return ret_val;
2561}
2562
2563/**
2564 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum

--- 9 unchanged lines hidden (view full) ---

2574 u16 j;
2575 u16 nvm_offset;
2576
2577 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2578
2579 for (j = 0; j < 4; j++) {
2580 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2581 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2310 nvm_offset);
2582 nvm_offset);
2311 if (ret_val != E1000_SUCCESS)
2312 goto out;
2313 }
2314
2315out:
2316 return ret_val;
2317}
2318

--- 29 unchanged lines hidden (view full) ---

2348 * @hw: pointer to the HW structure
2349 *
2350 * Enable/disable EEE based on setting in dev_spec structure.
2351 *
2352 **/
2353s32 e1000_set_eee_i350(struct e1000_hw *hw)
2354{
2355 s32 ret_val = E1000_SUCCESS;
2583 if (ret_val != E1000_SUCCESS)
2584 goto out;
2585 }
2586
2587out:
2588 return ret_val;
2589}
2590

--- 29 unchanged lines hidden (view full) ---

2620 * @hw: pointer to the HW structure
2621 *
2622 * Enable/disable EEE based on setting in dev_spec structure.
2623 *
2624 **/
2625s32 e1000_set_eee_i350(struct e1000_hw *hw)
2626{
2627 s32 ret_val = E1000_SUCCESS;
2356 u32 ipcnfg, eeer, ctrl_ext;
2628 u32 ipcnfg, eeer;
2357
2358 DEBUGFUNC("e1000_set_eee_i350");
2359
2629
2630 DEBUGFUNC("e1000_set_eee_i350");
2631
2360 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2361 if ((hw->mac.type != e1000_i350) ||
2362 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2632 if ((hw->mac.type < e1000_i350) ||
2633 (hw->phy.media_type != e1000_media_type_copper))
2363 goto out;
2364 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2365 eeer = E1000_READ_REG(hw, E1000_EEER);
2366
2367 /* enable or disable per user setting */
2368 if (!(hw->dev_spec._82575.eee_disable)) {
2634 goto out;
2635 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2636 eeer = E1000_READ_REG(hw, E1000_EEER);
2637
2638 /* enable or disable per user setting */
2639 if (!(hw->dev_spec._82575.eee_disable)) {
2369 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2370 E1000_IPCNFG_EEE_100M_AN);
2371 eeer |= (E1000_EEER_TX_LPI_EN |
2372 E1000_EEER_RX_LPI_EN |
2373 E1000_EEER_LPI_FC);
2640 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2641 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2642 E1000_EEER_LPI_FC);
2374
2375 } else {
2643
2644 } else {
2376 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2377 E1000_IPCNFG_EEE_100M_AN);
2378 eeer &= ~(E1000_EEER_TX_LPI_EN |
2379 E1000_EEER_RX_LPI_EN |
2380 E1000_EEER_LPI_FC);
2645 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2646 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2647 E1000_EEER_LPI_FC);
2381 }
2382 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2383 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2648 }
2649 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2650 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2384 E1000_READ_REG(hw, E1000_IPCNFG);
2385 E1000_READ_REG(hw, E1000_EEER);
2651 E1000_READ_REG(hw, E1000_IPCNFG);
2652 E1000_READ_REG(hw, E1000_EEER);
2386out:
2387
2388 return ret_val;
2389}
2653out:
2654
2655 return ret_val;
2656}
2657
2658/* Due to a hw errata, if the host tries to configure the VFTA register
2659 * while performing queries from the BMC or DMA, then the VFTA in some
2660 * cases won't be written.
2661 */
2662
2663/**
2664 * e1000_clear_vfta_i350 - Clear VLAN filter table
2665 * @hw: pointer to the HW structure
2666 *
2667 * Clears the register array which contains the VLAN filter table by
2668 * setting all the values to 0.
2669 **/
2670void e1000_clear_vfta_i350(struct e1000_hw *hw)
2671{
2672 u32 offset;
2673 int i;
2674
2675 DEBUGFUNC("e1000_clear_vfta_350");
2676
2677 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2678 for (i = 0; i < 10; i++)
2679 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2680
2681 E1000_WRITE_FLUSH(hw);
2682 }
2683}
2684
2685/**
2686 * e1000_write_vfta_i350 - Write value to VLAN filter table
2687 * @hw: pointer to the HW structure
2688 * @offset: register offset in VLAN filter table
2689 * @value: register value written to VLAN filter table
2690 *
2691 * Writes value at the given offset in the register array which stores
2692 * the VLAN filter table.
2693 **/
2694void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2695{
2696 int i;
2697
2698 DEBUGFUNC("e1000_write_vfta_350");
2699
2700 for (i = 0; i < 10; i++)
2701 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2702
2703 E1000_WRITE_FLUSH(hw);
2704}
2705
2706
2707/**
2708 * e1000_set_i2c_bb - Enable I2C bit-bang
2709 * @hw: pointer to the HW structure
2710 *
2711 * Enable I2C bit-bang interface
2712 *
2713 **/
2714s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2715{
2716 s32 ret_val = E1000_SUCCESS;
2717 u32 ctrl_ext, i2cparams;
2718
2719 DEBUGFUNC("e1000_set_i2c_bb");
2720
2721 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2722 ctrl_ext |= E1000_CTRL_I2C_ENA;
2723 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2724 E1000_WRITE_FLUSH(hw);
2725
2726 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2727 i2cparams |= E1000_I2CBB_EN;
2728 i2cparams |= E1000_I2C_DATA_OE_N;
2729 i2cparams |= E1000_I2C_CLK_OE_N;
2730 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2731 E1000_WRITE_FLUSH(hw);
2732
2733 return ret_val;
2734}
2735
2736/**
2737 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2738 * @hw: pointer to hardware structure
2739 * @byte_offset: byte offset to read
2740 * @data: value read
2741 *
2742 * Performs byte read operation over I2C interface at
2743 * a specified device address.
2744 **/
2745s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2746 u8 dev_addr, u8 *data)
2747{
2748 s32 status = E1000_SUCCESS;
2749 u32 max_retry = 10;
2750 u32 retry = 1;
2751 u16 swfw_mask = 0;
2752
2753 bool nack = 1;
2754
2755 DEBUGFUNC("e1000_read_i2c_byte_generic");
2756
2757 swfw_mask = E1000_SWFW_PHY0_SM;
2758
2759 do {
2760 if (e1000_acquire_swfw_sync_82575(hw, swfw_mask)
2761 != E1000_SUCCESS) {
2762 status = E1000_ERR_SWFW_SYNC;
2763 goto read_byte_out;
2764 }
2765
2766 e1000_i2c_start(hw);
2767
2768 /* Device Address and write indication */
2769 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2770 if (status != E1000_SUCCESS)
2771 goto fail;
2772
2773 status = e1000_get_i2c_ack(hw);
2774 if (status != E1000_SUCCESS)
2775 goto fail;
2776
2777 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2778 if (status != E1000_SUCCESS)
2779 goto fail;
2780
2781 status = e1000_get_i2c_ack(hw);
2782 if (status != E1000_SUCCESS)
2783 goto fail;
2784
2785 e1000_i2c_start(hw);
2786
2787 /* Device Address and read indication */
2788 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2789 if (status != E1000_SUCCESS)
2790 goto fail;
2791
2792 status = e1000_get_i2c_ack(hw);
2793 if (status != E1000_SUCCESS)
2794 goto fail;
2795
2796 status = e1000_clock_in_i2c_byte(hw, data);
2797 if (status != E1000_SUCCESS)
2798 goto fail;
2799
2800 status = e1000_clock_out_i2c_bit(hw, nack);
2801 if (status != E1000_SUCCESS)
2802 goto fail;
2803
2804 e1000_i2c_stop(hw);
2805 break;
2806
2807fail:
2808 e1000_release_swfw_sync_82575(hw, swfw_mask);
2809 msec_delay(100);
2810 e1000_i2c_bus_clear(hw);
2811 retry++;
2812 if (retry < max_retry)
2813 DEBUGOUT("I2C byte read error - Retrying.\n");
2814 else
2815 DEBUGOUT("I2C byte read error.\n");
2816
2817 } while (retry < max_retry);
2818
2819 e1000_release_swfw_sync_82575(hw, swfw_mask);
2820
2821read_byte_out:
2822
2823 return status;
2824}
2825
2826/**
2827 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2828 * @hw: pointer to hardware structure
2829 * @byte_offset: byte offset to write
2830 * @data: value to write
2831 *
2832 * Performs byte write operation over I2C interface at
2833 * a specified device address.
2834 **/
2835s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2836 u8 dev_addr, u8 data)
2837{
2838 s32 status = E1000_SUCCESS;
2839 u32 max_retry = 1;
2840 u32 retry = 0;
2841 u16 swfw_mask = 0;
2842
2843 DEBUGFUNC("e1000_write_i2c_byte_generic");
2844
2845 swfw_mask = E1000_SWFW_PHY0_SM;
2846
2847 if (e1000_acquire_swfw_sync_82575(hw, swfw_mask) != E1000_SUCCESS) {
2848 status = E1000_ERR_SWFW_SYNC;
2849 goto write_byte_out;
2850 }
2851
2852 do {
2853 e1000_i2c_start(hw);
2854
2855 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2856 if (status != E1000_SUCCESS)
2857 goto fail;
2858
2859 status = e1000_get_i2c_ack(hw);
2860 if (status != E1000_SUCCESS)
2861 goto fail;
2862
2863 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2864 if (status != E1000_SUCCESS)
2865 goto fail;
2866
2867 status = e1000_get_i2c_ack(hw);
2868 if (status != E1000_SUCCESS)
2869 goto fail;
2870
2871 status = e1000_clock_out_i2c_byte(hw, data);
2872 if (status != E1000_SUCCESS)
2873 goto fail;
2874
2875 status = e1000_get_i2c_ack(hw);
2876 if (status != E1000_SUCCESS)
2877 goto fail;
2878
2879 e1000_i2c_stop(hw);
2880 break;
2881
2882fail:
2883 e1000_i2c_bus_clear(hw);
2884 retry++;
2885 if (retry < max_retry)
2886 DEBUGOUT("I2C byte write error - Retrying.\n");
2887 else
2888 DEBUGOUT("I2C byte write error.\n");
2889 } while (retry < max_retry);
2890
2891 e1000_release_swfw_sync_82575(hw, swfw_mask);
2892
2893write_byte_out:
2894
2895 return status;
2896}
2897
2898/**
2899 * e1000_i2c_start - Sets I2C start condition
2900 * @hw: pointer to hardware structure
2901 *
2902 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2903 **/
2904static void e1000_i2c_start(struct e1000_hw *hw)
2905{
2906 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2907
2908 DEBUGFUNC("e1000_i2c_start");
2909
2910 /* Start condition must begin with data and clock high */
2911 e1000_set_i2c_data(hw, &i2cctl, 1);
2912 e1000_raise_i2c_clk(hw, &i2cctl);
2913
2914 /* Setup time for start condition (4.7us) */
2915 usec_delay(E1000_I2C_T_SU_STA);
2916
2917 e1000_set_i2c_data(hw, &i2cctl, 0);
2918
2919 /* Hold time for start condition (4us) */
2920 usec_delay(E1000_I2C_T_HD_STA);
2921
2922 e1000_lower_i2c_clk(hw, &i2cctl);
2923
2924 /* Minimum low period of clock is 4.7 us */
2925 usec_delay(E1000_I2C_T_LOW);
2926
2927}
2928
2929/**
2930 * e1000_i2c_stop - Sets I2C stop condition
2931 * @hw: pointer to hardware structure
2932 *
2933 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2934 **/
2935static void e1000_i2c_stop(struct e1000_hw *hw)
2936{
2937 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2938
2939 DEBUGFUNC("e1000_i2c_stop");
2940
2941 /* Stop condition must begin with data low and clock high */
2942 e1000_set_i2c_data(hw, &i2cctl, 0);
2943 e1000_raise_i2c_clk(hw, &i2cctl);
2944
2945 /* Setup time for stop condition (4us) */
2946 usec_delay(E1000_I2C_T_SU_STO);
2947
2948 e1000_set_i2c_data(hw, &i2cctl, 1);
2949
2950 /* bus free time between stop and start (4.7us)*/
2951 usec_delay(E1000_I2C_T_BUF);
2952}
2953
2954/**
2955 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
2956 * @hw: pointer to hardware structure
2957 * @data: data byte to clock in
2958 *
2959 * Clocks in one byte data via I2C data/clock
2960 **/
2961static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
2962{
2963 s32 i;
2964 bool bit = 0;
2965
2966 DEBUGFUNC("e1000_clock_in_i2c_byte");
2967
2968 *data = 0;
2969 for (i = 7; i >= 0; i--) {
2970 e1000_clock_in_i2c_bit(hw, &bit);
2971 *data |= bit << i;
2972 }
2973
2974 return E1000_SUCCESS;
2975}
2976
2977/**
2978 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
2979 * @hw: pointer to hardware structure
2980 * @data: data byte clocked out
2981 *
2982 * Clocks out one byte data via I2C data/clock
2983 **/
2984static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
2985{
2986 s32 status = E1000_SUCCESS;
2987 s32 i;
2988 u32 i2cctl;
2989 bool bit = 0;
2990
2991 DEBUGFUNC("e1000_clock_out_i2c_byte");
2992
2993 for (i = 7; i >= 0; i--) {
2994 bit = (data >> i) & 0x1;
2995 status = e1000_clock_out_i2c_bit(hw, bit);
2996
2997 if (status != E1000_SUCCESS)
2998 break;
2999 }
3000
3001 /* Release SDA line (set high) */
3002 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3003
3004 i2cctl |= E1000_I2C_DATA_OE_N;
3005 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3006 E1000_WRITE_FLUSH(hw);
3007
3008 return status;
3009}
3010
3011/**
3012 * e1000_get_i2c_ack - Polls for I2C ACK
3013 * @hw: pointer to hardware structure
3014 *
3015 * Clocks in/out one bit via I2C data/clock
3016 **/
3017static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3018{
3019 s32 status = E1000_SUCCESS;
3020 u32 i = 0;
3021 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3022 u32 timeout = 10;
3023 bool ack = 1;
3024
3025 DEBUGFUNC("e1000_get_i2c_ack");
3026
3027 e1000_raise_i2c_clk(hw, &i2cctl);
3028
3029 /* Minimum high period of clock is 4us */
3030 usec_delay(E1000_I2C_T_HIGH);
3031
3032 /* Wait until SCL returns high */
3033 for (i = 0; i < timeout; i++) {
3034 usec_delay(1);
3035 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3036 if (i2cctl & E1000_I2C_CLK_IN)
3037 break;
3038 }
3039 if (!(i2cctl & E1000_I2C_CLK_IN))
3040 return E1000_ERR_I2C;
3041
3042 ack = e1000_get_i2c_data(&i2cctl);
3043 if (ack == 1) {
3044 DEBUGOUT("I2C ack was not received.\n");
3045 status = E1000_ERR_I2C;
3046 }
3047
3048 e1000_lower_i2c_clk(hw, &i2cctl);
3049
3050 /* Minimum low period of clock is 4.7 us */
3051 usec_delay(E1000_I2C_T_LOW);
3052
3053 return status;
3054}
3055
3056/**
3057 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3058 * @hw: pointer to hardware structure
3059 * @data: read data value
3060 *
3061 * Clocks in one bit via I2C data/clock
3062 **/
3063static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3064{
3065 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3066
3067 DEBUGFUNC("e1000_clock_in_i2c_bit");
3068
3069 e1000_raise_i2c_clk(hw, &i2cctl);
3070
3071 /* Minimum high period of clock is 4us */
3072 usec_delay(E1000_I2C_T_HIGH);
3073
3074 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3075 *data = e1000_get_i2c_data(&i2cctl);
3076
3077 e1000_lower_i2c_clk(hw, &i2cctl);
3078
3079 /* Minimum low period of clock is 4.7 us */
3080 usec_delay(E1000_I2C_T_LOW);
3081
3082 return E1000_SUCCESS;
3083}
3084
3085/**
3086 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3087 * @hw: pointer to hardware structure
3088 * @data: data value to write
3089 *
3090 * Clocks out one bit via I2C data/clock
3091 **/
3092static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3093{
3094 s32 status;
3095 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3096
3097 DEBUGFUNC("e1000_clock_out_i2c_bit");
3098
3099 status = e1000_set_i2c_data(hw, &i2cctl, data);
3100 if (status == E1000_SUCCESS) {
3101 e1000_raise_i2c_clk(hw, &i2cctl);
3102
3103 /* Minimum high period of clock is 4us */
3104 usec_delay(E1000_I2C_T_HIGH);
3105
3106 e1000_lower_i2c_clk(hw, &i2cctl);
3107
3108 /* Minimum low period of clock is 4.7 us.
3109 * This also takes care of the data hold time.
3110 */
3111 usec_delay(E1000_I2C_T_LOW);
3112 } else {
3113 status = E1000_ERR_I2C;
3114 DEBUGOUT1("I2C data was not set to %X\n", data);
3115 }
3116
3117 return status;
3118}
3119/**
3120 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3121 * @hw: pointer to hardware structure
3122 * @i2cctl: Current value of I2CCTL register
3123 *
3124 * Raises the I2C clock line '0'->'1'
3125 **/
3126static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3127{
3128 DEBUGFUNC("e1000_raise_i2c_clk");
3129
3130 *i2cctl |= E1000_I2C_CLK_OUT;
3131 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3132 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3133 E1000_WRITE_FLUSH(hw);
3134
3135 /* SCL rise time (1000ns) */
3136 usec_delay(E1000_I2C_T_RISE);
3137}
3138
3139/**
3140 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3141 * @hw: pointer to hardware structure
3142 * @i2cctl: Current value of I2CCTL register
3143 *
3144 * Lowers the I2C clock line '1'->'0'
3145 **/
3146static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3147{
3148
3149 DEBUGFUNC("e1000_lower_i2c_clk");
3150
3151 *i2cctl &= ~E1000_I2C_CLK_OUT;
3152 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3153 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3154 E1000_WRITE_FLUSH(hw);
3155
3156 /* SCL fall time (300ns) */
3157 usec_delay(E1000_I2C_T_FALL);
3158}
3159
3160/**
3161 * e1000_set_i2c_data - Sets the I2C data bit
3162 * @hw: pointer to hardware structure
3163 * @i2cctl: Current value of I2CCTL register
3164 * @data: I2C data value (0 or 1) to set
3165 *
3166 * Sets the I2C data bit
3167 **/
3168static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3169{
3170 s32 status = E1000_SUCCESS;
3171
3172 DEBUGFUNC("e1000_set_i2c_data");
3173
3174 if (data)
3175 *i2cctl |= E1000_I2C_DATA_OUT;
3176 else
3177 *i2cctl &= ~E1000_I2C_DATA_OUT;
3178
3179 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3180 *i2cctl |= E1000_I2C_CLK_OE_N;
3181 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3182 E1000_WRITE_FLUSH(hw);
3183
3184 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3185 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3186
3187 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3188 if (data != e1000_get_i2c_data(i2cctl)) {
3189 status = E1000_ERR_I2C;
3190 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3191 }
3192
3193 return status;
3194}
3195
3196/**
3197 * e1000_get_i2c_data - Reads the I2C SDA data bit
3198 * @hw: pointer to hardware structure
3199 * @i2cctl: Current value of I2CCTL register
3200 *
3201 * Returns the I2C data bit value
3202 **/
3203static bool e1000_get_i2c_data(u32 *i2cctl)
3204{
3205 bool data;
3206
3207 DEBUGFUNC("e1000_get_i2c_data");
3208
3209 if (*i2cctl & E1000_I2C_DATA_IN)
3210 data = 1;
3211 else
3212 data = 0;
3213
3214 return data;
3215}
3216
3217/**
3218 * e1000_i2c_bus_clear - Clears the I2C bus
3219 * @hw: pointer to hardware structure
3220 *
3221 * Clears the I2C bus by sending nine clock pulses.
3222 * Used when data line is stuck low.
3223 **/
3224void e1000_i2c_bus_clear(struct e1000_hw *hw)
3225{
3226 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3227 u32 i;
3228
3229 DEBUGFUNC("e1000_i2c_bus_clear");
3230
3231 e1000_i2c_start(hw);
3232
3233 e1000_set_i2c_data(hw, &i2cctl, 1);
3234
3235 for (i = 0; i < 9; i++) {
3236 e1000_raise_i2c_clk(hw, &i2cctl);
3237
3238 /* Min high period of clock is 4us */
3239 usec_delay(E1000_I2C_T_HIGH);
3240
3241 e1000_lower_i2c_clk(hw, &i2cctl);
3242
3243 /* Min low period of clock is 4.7us*/
3244 usec_delay(E1000_I2C_T_LOW);
3245 }
3246
3247 e1000_i2c_start(hw);
3248
3249 /* Put the i2c bus back to default state */
3250 e1000_i2c_stop(hw);
3251}
3252